From f497ab6b4bb813aca439b7f3a72a060b58b147c4 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 10 Jun 2019 16:51:44 -0700 Subject: ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron This enables wake up on Bluetooth activity when the device is suspended. The BT_HOST_WAKE signal is only connected on devices with BT module that are connected through UART. Signed-off-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 3257ca90f0e8..e2635ad574e7 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -23,6 +23,31 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + bt_activity: bt-activity { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake>; + + /* + * HACK: until we have an LPM driver, we'll use an + * ugly GPIO key to allow Bluetooth to wake from S3. + * This is expected to only be used by BT modules that + * use UART for comms. For BT modules that talk over + * SDIO we should use a wakeup mechanism related to SDIO. + * + * Use KEY_RESERVED here since that will work as a wakeup but + * doesn't get reported to higher levels (so doesn't confuse + * Chrome). + */ + bt-wake { + label = "BT Wakeup"; + gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + + }; + power_button: power-button { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -549,6 +574,10 @@ rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; + bt_host_wake: bt-host-wake { + rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + /* * We run sdio0 at max speed; bump up drive strength. * We also have external pulls, so disable the internal ones. -- cgit v1.2.3 From 4db11c378ab1e170c3a197ea3719ffe54cd06637 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 19 Jun 2019 11:34:25 -0700 Subject: ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron This is the other half of the hacky solution from commit f497ab6b4bb8 ("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on veyron"). Specifically the LPM driver that the Broadcom Bluetooth expects to have (but is missing in mainline) has two halves of the equation: BT_HOST_WAKE and BT_DEV_WAKE. The BT_HOST_WAKE (which was handled in the previous commit) is the one that lets the Bluetooth wake the system up. The BT_DEV_WAKE (this patch) tells the Bluetooth that it's OK to go into a low power mode. That means we were burning a bit of extra power in S3 without this patch. Measurements are a bit noisy, but it appears to be a few mA worth of difference. NOTE: Though these pins don't do much on systems with Marvell Bluetooth, downstream kernels set it on all veyron boards so we'll do the same. Signed-off-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 ++ arch/arm/boot/dts/rk3288-veyron.dtsi | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 5727017f34b2..1cadb522fd0d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -237,6 +237,7 @@ /* Wake only */ &suspend_l_wake + &bt_dev_wake_awake >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ @@ -246,6 +247,7 @@ /* Sleep only */ &suspend_l_sleep + &bt_dev_wake_sleep >; backlight { diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index e2635ad574e7..53d2f2452868 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -485,12 +485,18 @@ &ddr0_retention &ddrio_pwroff &global_pwroff + + /* Wake only */ + &bt_dev_wake_awake >; pinctrl-1 = < /* Common for sleep and wake, but no owners */ &ddr0_retention &ddrio_pwroff &global_pwroff + + /* Sleep only */ + &bt_dev_wake_sleep >; pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { @@ -596,6 +602,20 @@ sdio0_clk: sdio0-clk { rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>; }; + + /* + * These pins are only present on very new veyron boards; on + * older boards bt_dev_wake is simply always high. Note that + * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt + * to map this pin everywhere + */ + bt_dev_wake_sleep: bt-dev-wake-sleep { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + bt_dev_wake_awake: bt-dev-wake-awake { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; }; tpm { -- cgit v1.2.3 From fe32553c8704fe15effd6945afd5de893d417a80 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 18 Jun 2019 11:45:31 -0700 Subject: Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie" This reverts commit 288ceb85b505c19abe1895df068dda5ed20cf482. The commit assumes that the minnie panel is a AUO B101EAN01.1 (LVDS interface), however it is a AUO B101EAN01.8 (eDP interface). The eDP panel doesn't need the 200 ms delay. Signed-off-by: Matthias Kaehlcke Reviewed-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index b2cc70a08554..9008e703c07e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -106,8 +106,6 @@ 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; power-supply = <&backlight_regulator>; - post-pwm-on-delay-ms = <200>; - pwm-off-delay-ms = <200>; }; &i2c_tunnel { -- cgit v1.2.3 From 836e2abff0021b4c20ec31f743d95be2a3d5869f Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Fri, 14 Jun 2019 11:05:12 +0200 Subject: ARM: dts: rockchip: fix vop iommu-cells on rk322x iommu-cells obviously needs to start with a "#". Signed-off-by: Justin Swartz Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index da102fff96a2..b19e7939f3ea 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -579,7 +579,7 @@ interrupt-names = "vop_mmu"; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk", "iface"; - iommu-cells = <0>; + #iommu-cells = <0>; status = "disabled"; }; -- cgit v1.2.3 From 519574e3259c8d7e5d78366ef513cfaaf650784f Mon Sep 17 00:00:00 2001 From: Justin Swartz Date: Thu, 13 Jun 2019 10:13:04 +0000 Subject: ARM: dts: rockchip: add display nodes for rk322x Add display_subsystem, hdmi_phy, vop, and hdmi device nodes plus a few hdmi pinctrl entries to allow for HDMI output. Signed-off-by: Justin Swartz [added assigned-clock settings for hdmiphy output] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 83 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index b19e7939f3ea..340ed6ccb08f 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -143,6 +143,11 @@ #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + i2s1: i2s1@100b0000 { compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; reg = <0x100b0000 0x4000>; @@ -529,6 +534,17 @@ status = "disabled"; }; + hdmi_phy: hdmi-phy@12030000 { + compatible = "rockchip,rk3228-hdmi-phy"; + reg = <0x12030000 0x10000>; + clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + #clock-cells = <0>; + clock-output-names = "hdmiphy_phy"; + #phy-cells = <0>; + status = "disabled"; + }; + gpu: gpu@20000000 { compatible = "rockchip,rk3228-mali", "arm,mali-400"; reg = <0x20000000 0x10000>; @@ -572,6 +588,28 @@ status = "disabled"; }; + vop: vop@20050000 { + compatible = "rockchip,rk3228-vop"; + reg = <0x20050000 0x1ffc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + vop_mmu: iommu@20053f00 { compatible = "rockchip,iommu"; reg = <0x20053f00 0x100>; @@ -594,6 +632,36 @@ status = "disabled"; }; + hdmi: hdmi@200a0000 { + compatible = "rockchip,rk3228-dw-hdmi"; + reg = <0x200a0000 0x20000>; + reg-io-width = <4>; + interrupts = ; + assigned-clocks = <&cru SCLK_HDMI_PHY>; + assigned-clock-parents = <&hdmi_phy>; + clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; + clock-names = "isfr", "iahb", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; + resets = <&cru SRST_HDMI_P>; + reset-names = "hdmi"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + sdmmc: dwmmc@30000000 { compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x30000000 0x4000>; @@ -922,6 +990,21 @@ }; }; + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; + }; + + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, -- cgit v1.2.3