From a2730ed3e0f39c528014673cb96807bb16a8ce35 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 21 Jan 2018 23:14:12 +0100 Subject: ARM: dts: meson8b: grow the reset controller memory zone The reset controller in the Meson8b SoCs also supports level resets. These use the same defines (from dt-bindings/reset/amlogic,meson8b-reset.h) as the reset pulses. The reset-meson driver internally handles the difference if a consumer requests a reset pulse or a level reset. However, for this to work we must extend the memory zone of the reset controller. Suggested-by: Neil Armstrong Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 7cd03ed3742e..4c1ac3a44357 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -152,7 +152,7 @@ reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; - reg = <0x4404 0x20>; + reg = <0x4404 0x9c>; #reset-cells = <1>; }; -- cgit v1.2.3 From e3087187e5f18231e48450e602220eb65c409b59 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 21 Jan 2018 23:14:13 +0100 Subject: ARM: dts: meson8: add the reset controller Meson8 uses the same reset controller as Meson8b. Add the node along with the #include for the reset lines to meson8.dtsi so we can use it from there as well. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index d2e3eeaa1a5f..f48e89a7f7b4 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -46,6 +46,7 @@ #include #include #include +#include #include "meson.dtsi" / { @@ -187,6 +188,12 @@ reg = <0x8000 0x4>, <0x4000 0x460>; }; + reset: reset-controller@4404 { + compatible = "amlogic,meson8b-reset"; + reg = <0x4404 0x9c>; + #reset-cells = <1>; + }; + analog_top: analog-top@81a8 { compatible = "amlogic,meson8-analog-top", "syscon"; reg = <0x81a8 0x14>; -- cgit v1.2.3 From e1fa57dfd7e28b30d6419b7c309b4a890ff4410a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 21 Jan 2018 23:14:14 +0100 Subject: ARM: dts: meson8: add the USB reset line Now that we support the reset controller on Meson8 we can add the reset line to the USB PHYs (just like on Meson8b). Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index f48e89a7f7b4..dcc9292d2ffa 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -390,10 +390,12 @@ compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; }; &usb1_phy { compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; }; -- cgit v1.2.3 From b96446541d8390ec22e6dc579282770453ec98a4 Mon Sep 17 00:00:00 2001 From: Emiliano Ingrassia Date: Fri, 19 Jan 2018 02:48:00 +0100 Subject: ARM: dts: meson8b: extend ethernet controller description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable S805 (aka Meson8b) ethernet pin multiplexing and extend the controller description. The programmable ethernet (PRG_ETHERNET) register address value (0xc1108108), contained in meson.dtsi, is overridden according to the value found in S805 SoC manual. This also required to switch to "amlogic,meson8b-dwmac" compatible to correctly configure that register. The two clock sources "clkin0" and "clkin1" are both equals to MPLL2 because, as reported in bit 9-7 register description, that is the only Meson8b ethernet clock source. Signed-off-by: Emiliano Ingrassia Tested-by: Linus Lüssing Reviewed-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 4c1ac3a44357..1a7c16640ea5 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -185,6 +185,27 @@ #gpio-cells = <2>; gpio-ranges = <&pinctrl_cbus 0 0 130>; }; + + eth_rgmii_pins: eth-rgmii { + mux { + groups = "eth_tx_clk", + "eth_tx_en", + "eth_txd1_0", + "eth_txd1_1", + "eth_txd0_0", + "eth_txd0_1", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd1", + "eth_rxd0", + "eth_mdio_en", + "eth_mdc", + "eth_ref_clk", + "eth_txd2", + "eth_txd3"; + function = "ethernet"; + }; + }; }; }; @@ -203,8 +224,18 @@ }; ðmac { - clocks = <&clkc CLKID_ETH>; - clock-names = "stmmaceth"; + compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; + + reg = <0xc9410000 0x10000 + 0xc1108140 0x4>; + + clocks = <&clkc CLKID_ETH>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL2>; + clock-names = "stmmaceth", "clkin0", "clkin1"; + + resets = <&reset RESET_ETHERNET>; + reset-names = "stmmaceth"; }; &gpio_intc { -- cgit v1.2.3 From 9c15795a4f96cb4f82a0e1503b46621251644bc2 Mon Sep 17 00:00:00 2001 From: Emiliano Ingrassia Date: Fri, 19 Jan 2018 02:49:17 +0100 Subject: ARM: dts: meson8b-odroidc1: ethernet support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY which supports 10/100/1000 Mbps ethernet. The PHY reset and interrupt lines are controlled by the SoC via two GPIO lines (GPIOH_4 and GPIOH_3 respectively). The PHY energy efficient ethernet (eee) mode is marked as broken using "eee-broken-1000t" because, during tests, high packet losses were experienced without it. Signed-off-by: Emiliano Ingrassia Tested-by: Linus Lüssing Reviewed-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 9ff6ca4e20d0..d5e83051bb54 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -99,3 +99,33 @@ &usb1 { status = "okay"; }; + +ðmac { + status = "okay"; + + snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 30000>; + + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + phy-handle = <ð_phy>; + amlogic,tx-delay-ns = <4>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Realtek RTL8211F (0x001cc916) */ + eth_phy: ethernet-phy@0 { + reg = <0>; + eee-broken-1000t; + interrupt-parent = <&gpio_intc>; + /* GPIOH_3 */ + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; -- cgit v1.2.3 From 7a6cc8be3938c322964065312d57439a92584488 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 17 Feb 2018 17:06:50 +0100 Subject: ARM: dts: meson8b: add the I2C clocks Add the I2C clocks so the I2C busses can be used. The clock input is not device specific (the AO I2C bus uses clk81 as input, while the two I2C busses in CBUS have a separate "CLKID_I2C" gate, provided by the clock controller. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 1a7c16640ea5..5f7841b2d163 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -250,6 +250,18 @@ clock-names = "core"; }; +&i2c_AO { + clocks = <&clkc CLKID_CLK81>; +}; + +&i2c_A { + clocks = <&clkc CLKID_I2C>; +}; + +&i2c_B { + clocks = <&clkc CLKID_I2C>; +}; + &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; -- cgit v1.2.3 From e03efbce6bebf55111ec8e22e2f545f72aff6cfd Mon Sep 17 00:00:00 2001 From: Linus Lüssing Date: Sat, 17 Mar 2018 21:11:14 +0100 Subject: ARM: dts: meson8b-odroidc1: add microSD support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Odroid C1 features a microSD slot. This patch adds the necessary DT bindings to support it. Signed-off-by: Linus Lüssing Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b-odroidc1.dts | 58 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 8 +++++ 2 files changed, 66 insertions(+) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index d5e83051bb54..3a5603d95b70 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -54,6 +54,7 @@ aliases { serial0 = &uart_AO; + mmc0 = &sd_card_slot; }; memory { @@ -69,6 +70,37 @@ default-state = "off"; }; }; + + tflash_vdd: regulator-tflash_vdd { + /* + * signal name from schematics: TFLASH_VDD_EN + */ + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + /* + * signal name from schematics: TF_3V3N_1V8_EN + */ + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0 + 1800000 1>; + }; }; &uart_AO { @@ -100,6 +132,32 @@ status = "okay"; }; +&sdio { + status = "okay"; + + pinctrl-0 = <&sd_b_pins>; + pinctrl-names = "default"; + + /* SD card */ + sd_card_slot: slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + no-sdio; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; + }; +}; + ðmac { status = "okay"; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 5f7841b2d163..f9eceab4e3db 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -206,6 +206,14 @@ function = "ethernet"; }; }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; + }; }; }; -- cgit v1.2.3 From 4e461e62fc987ed5edb82e2a902fd93f4dccae8f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 12 Mar 2018 21:57:09 +0100 Subject: ARM: dts: meson8b: the CBUS GPIO controller only has 83 GPIOs Update the "gpio-ranges" property of the CBUS GPIO controller on Meson8b because it only provides 83 GPIOs. The GPIO definitions in include/dt-bindings/gpio/meson8b-gpio.h inherited all GPIOs from Meson8 until recently. However, Meson8b does not support all GPIOs which are supported by Meson8 (Meson8b doesn't have a GPIOZ bank, most of the pins from the GPIODV bank are missing on Meson8b - just to name a few differences). The actual number of GPIOs is only 83, instead of 120 from Meson8 plus the 10 GPIOs from the DIF bank on Meson8b. Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet Acked-by: Linus Walleij Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/boot/dts') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index f9eceab4e3db..553b82174604 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -183,7 +183,7 @@ reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 130>; + gpio-ranges = <&pinctrl_cbus 0 0 83>; }; eth_rgmii_pins: eth-rgmii { -- cgit v1.2.3