From 7d7db8db67003e4837bbc3f0402b76a225f4eed5 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 6 Feb 2014 17:28:49 +0200 Subject: ARM: dts: MSM8974: Add pinctrl node Add the pin control node and pin definitions of SPI8. Signed-off-by: Ivan T. Ivanov Reviewed-by: Bjorn Andersson Acked-by: Linus Walleij Signed-off-by: Kumar Gala --- arch/arm/boot/dts/qcom-msm8974.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm/boot/dts/qcom-msm8974.dtsi') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index f68723918b3f..23aa38745037 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -198,5 +198,34 @@ clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; + }; }; }; -- cgit v1.2.3 From 3e944c7693b7eaf0dfc35765e41e8c571fa64707 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Fri, 31 Jan 2014 16:21:56 +0200 Subject: ARM: dts: msm: Add SDHC controller nodes for MSM8974 and DB8074 board Add support for the 2 SDHC controllers on the DB8074 board. The first controller (at 0xf9824900) is connected to an on board soldered eMMC. The second controller (at 0xf98a4900) is connected to a uSD card slot. Signed-off-by: Georgi Djakov Signed-off-by: Kumar Gala --- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 13 +++++++++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'arch/arm/boot/dts/qcom-msm8974.dtsi') diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 13ac3e222495..92320c4a7668 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -3,4 +3,17 @@ / { model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; + + soc: soc { + sdhci@f9824900 { + bus-width = <8>; + non-removable; + status = "ok"; + }; + + sdhci@f98a4900 { + cd-gpios = <&msmgpio 62 0x1>; + bus-width = <4>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 23aa38745037..c530a33a10a0 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -192,6 +192,28 @@ clock-names = "core", "iface"; }; + sdhci@f9824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + rng@f9bff000 { compatible = "qcom,prng"; reg = <0xf9bff000 0x200>; -- cgit v1.2.3 From ba08220aa81e757491a3665c28df7eaa954128dc Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 28 May 2014 12:01:29 -0500 Subject: ARM: dts: qcom: Update msm8974/apq8074 device trees * Move SoC peripherals into an SoC container node * Move serial enabling into board file (qcom-apq8074-dragonboard.dts) * Move spi pinctrl into board file * Cleanup cpu node to match binding spec, enable-method and compatible should be per cpu, not part of the container * Drop interrupts property from l2-cache node as its not part of the binding spec * Move timer node out of SoC container Signed-off-by: Kumar Gala --- arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 ++++++++++++++- arch/arm/boot/dts/qcom-msm8974.dtsi | 49 ++++++++++---------------- 2 files changed, 45 insertions(+), 32 deletions(-) (limited to 'arch/arm/boot/dts/qcom-msm8974.dtsi') diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index 92320c4a7668..b4dfb01fe6fb 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -4,7 +4,11 @@ model = "Qualcomm APQ8074 Dragonboard"; compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; - soc: soc { + soc { + serial@f991e000 { + status = "ok"; + }; + sdhci@f9824900 { bus-width = <8>; non-removable; @@ -15,5 +19,27 @@ cd-gpios = <&msmgpio 62 0x1>; bus-width = <4>; }; + + + pinctrl@fd510000 { + spi8_default: spi8_default { + mosi { + pins = "gpio45"; + function = "blsp_spi8"; + }; + miso { + pins = "gpio46"; + function = "blsp_spi8"; + }; + cs { + pins = "gpio47"; + function = "blsp_spi8"; + }; + clk { + pins = "gpio48"; + function = "blsp_spi8"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c530a33a10a0..69dca2aca25a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -13,10 +13,10 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <1 9 0xf04>; - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; @@ -24,6 +24,8 @@ }; cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; @@ -31,6 +33,8 @@ }; cpu@2 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; @@ -38,6 +42,8 @@ }; cpu@3 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; @@ -47,7 +53,6 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; - interrupts = <0 2 0x4>; qcom,saw = <&saw_l2>; }; }; @@ -57,6 +62,15 @@ interrupts = <1 7 0xf04>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <19200000>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -71,15 +85,6 @@ <0xf9002000 0x1000>; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -190,6 +195,7 @@ interrupts = <0 108 0x0>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + status = "disabled"; }; sdhci@f9824900 { @@ -229,25 +235,6 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <0 208 0>; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; }; }; }; -- cgit v1.2.3