From bcc4d65abec2adb74157b34519e80331eb4427eb Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Thu, 4 Jun 2015 14:39:15 +0530 Subject: ARCv2: MMUv4: support aliasing icache config This is also default for AXS103 release Signed-off-by: Vineet Gupta --- arch/arc/include/asm/cache.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arc/include/asm') diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index e54977a7d006..d21c76d6b054 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void); #define ARC_REG_IC_IVIC 0x10 #define ARC_REG_IC_CTRL 0x11 #define ARC_REG_IC_IVIL 0x19 -#if defined(CONFIG_ARC_MMU_V3) +#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4) #define ARC_REG_IC_PTAG 0x1E #endif @@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void); #define ARC_REG_DC_IVDL 0x4A #define ARC_REG_DC_FLSH 0x4B #define ARC_REG_DC_FLDL 0x4C -#if defined(CONFIG_ARC_MMU_V3) #define ARC_REG_DC_PTAG 0x5C -#endif /* Bit val in DC_CTRL */ #define DC_CTRL_INV_MODE_FLUSH 0x40 -- cgit v1.2.3