From 3c8b5fb9983b7c7eb2e3557d687a3613288e0780 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Thu, 17 Sep 2020 14:37:02 -0500 Subject: MAINTAINERS: Remove Andrew F. Davis Andrews TI email is no longer valid and he indicated that it is OK to remove him from the MAINTAINERS file for the DMA HEAPS FRAMEWORK. For the BQ27xxx list I replaced Andrews email with mine. Signed-off-by: Dan Murphy Acked-by: Krzysztof Kozlowski Signed-off-by: Sebastian Reichel --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'MAINTAINERS') diff --git a/MAINTAINERS b/MAINTAINERS index deaafb617361..75b724181c7b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5195,7 +5195,6 @@ F: kernel/dma/ DMA-BUF HEAPS FRAMEWORK M: Sumit Semwal -R: Andrew F. Davis R: Benjamin Gaignard R: Liam Mark R: Laura Abbott @@ -17236,7 +17235,7 @@ S: Maintained F: drivers/thermal/ti-soc-thermal/ TI BQ27XXX POWER SUPPLY DRIVER -R: Andrew F. Davis +R: Dan Murphy F: drivers/power/supply/bq27xxx_battery.c F: drivers/power/supply/bq27xxx_battery_i2c.c F: include/linux/power/bq27xxx_battery.h -- cgit v1.2.3 From 312e95c6e92122fac0251a84efa1cf3914c877a6 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Tue, 6 Oct 2020 22:03:14 +0200 Subject: dt-bindings: reset: ocelot: Add Sparx5 support This adds the support for the Sparx5 SoC. Signed-off-by: Lars Povlsen Acked-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++-- MAINTAINERS | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'MAINTAINERS') diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 1b4213eb3473..4d530d815484 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -1,10 +1,13 @@ Microsemi Ocelot reset controller The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. +SoC core. + +The reset registers are both present in the MSCC vcoreiii MIPS and +microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" + - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { diff --git a/MAINTAINERS b/MAINTAINERS index 75b724181c7b..a733a80748ff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11515,6 +11515,7 @@ M: Microchip Linux Driver Support L: linux-mips@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt +F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c -- cgit v1.2.3