From 10003938a0c64c2f0d8934ef3f4f36ac5b4960dc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 19 Sep 2019 09:17:13 +0100 Subject: dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding Add binding documentation for the RZ/G2N (R8A774b1) Clock Pulse Generator driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/1568881036-4404-6-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index 916a601b76a7..b5edebeb12b4 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -19,6 +19,7 @@ Required Properties: - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E) - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C) - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M) + - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N) - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E) - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2) - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W) @@ -40,10 +41,11 @@ Required Properties: clock-names - clock-names: List of external parent clock names. Valid names are: - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, - r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, - r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990, - r8a77995) - - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) + r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, + r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, + r8a77990, r8a77995) + - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a7796, r8a77965, r8a77970, + r8a77980) - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, r8a7794) -- cgit v1.2.3 From 8511c9de1a31e2dd183573e9a91317e33948fa47 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 27 Jun 2019 14:52:44 +0200 Subject: dt-bindings: clk: armada3700: fix typo in SoC name This documentation is about Armada 3700 SoCs. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lkml.kernel.org/r/20190627125245.26788-4-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt index 1e3370ba189f..85972715e593 100644 --- a/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt +++ b/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt @@ -9,7 +9,7 @@ bridge. The peripheral clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. -The following is a list of provided IDs for Armada 370 North bridge clocks: +The following is a list of provided IDs for Armada 3700 North bridge clocks: ID Clock name Description ----------------------------------- 0 mmc MMC controller @@ -30,7 +30,7 @@ ID Clock name Description 15 eip97 EIP 97 16 cpu CPU -The following is a list of provided IDs for Armada 370 South bridge clocks: +The following is a list of provided IDs for Armada 3700 South bridge clocks: ID Clock name Description ----------------------------------- 0 gbe-50 50 MHz parent clock for Gigabit Ethernet -- cgit v1.2.3 From 06aeb3fb9f310f7e9dcdfc524bde8901d367019f Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Thu, 27 Jun 2019 14:52:45 +0200 Subject: dt-bindings: clk: armada3700: document the PCIe clock Add a reference to the missing PCIe clock managed by this IP. The clock resides in the south bridge. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Link: https://lkml.kernel.org/r/20190627125245.26788-5-miquel.raynal@bootlin.com Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt b/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt index 85972715e593..fbf58c443c04 100644 --- a/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt +++ b/Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt @@ -46,6 +46,7 @@ ID Clock name Description 10 sdio SDIO 11 usb32-sub2-sys USB 2 clock 12 usb32-ss-sys USB 3 clock +13 pcie PCIe controller Required properties: -- cgit v1.2.3 From 0ea0a188fdc5ace5afd0e25c87575c5fc1ae7e89 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 2 Oct 2019 11:15:23 +0200 Subject: dt-bindings: clk: axg-audio: add sm1 bindings Add the compatible and clock ids of the sm1 audio clock controller Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet --- .../devicetree/bindings/clock/amlogic,axg-audio-clkc.txt | 3 ++- include/dt-bindings/clock/axg-audio-clkc.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt index b3957d10d241..3a8948c04bc9 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt @@ -7,7 +7,8 @@ devices. Required Properties: - compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, - "amlogic,g12a-audio-clkc" for G12A. + "amlogic,g12a-audio-clkc" for G12A, + "amlogic,sm1-audio-clkc" for S905X3. - reg : physical base address of the clock controller and length of memory mapped region. - clocks : a list of phandle + clock-specifier pairs for the clocks listed diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h index 75901c636893..f561f5c5ef8f 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -80,5 +80,15 @@ #define AUD_CLKID_TDM_SCLK_PAD0 160 #define AUD_CLKID_TDM_SCLK_PAD1 161 #define AUD_CLKID_TDM_SCLK_PAD2 162 +#define AUD_CLKID_TOP 163 +#define AUD_CLKID_TORAM 164 +#define AUD_CLKID_EQDRC 165 +#define AUD_CLKID_RESAMPLE_B 166 +#define AUD_CLKID_TOVAD 167 +#define AUD_CLKID_LOCKER 168 +#define AUD_CLKID_SPDIFIN_LB 169 +#define AUD_CLKID_FRDDR_D 170 +#define AUD_CLKID_TODDR_D 171 +#define AUD_CLKID_LOOPBACK_B 172 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ -- cgit v1.2.3 From 8e7b71f8a9750be1ca15f0285142a6aa000755a0 Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Fri, 11 Oct 2019 18:59:27 +0530 Subject: dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings Add devicetree binding for the Q6SSTOP clock controller found in QCS404. Signed-off-by: Govind Singh Link: https://lkml.kernel.org/r/20191011132928.9388-2-govinds@codeaurora.org Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,q6sstopcc.yaml | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml new file mode 100644 index 000000000000..bbaaf1e2a203 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,q6sstopcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Q6SSTOP clock Controller + +maintainers: + - Govind Singh + +properties: + compatible: + const: "qcom,qcs404-q6sstopcc" + + reg: + items: + - description: Q6SSTOP clocks register region + - description: Q6SSTOP_TCSR register region + + clocks: + items: + - description: ahb clock for the q6sstopCC + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + q6sstopcc: clock-controller@7500000 { + compatible = "qcom,qcs404-q6sstopcc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x10000>; + clocks = <&gcc 141>; + #clock-cells = <1>; + }; -- cgit v1.2.3 From 72b2429d40d878bfdd066b9401c9a5cbb2a755d3 Mon Sep 17 00:00:00 2001 From: Fancy Fang Date: Mon, 28 Oct 2019 08:07:59 +0000 Subject: clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock The mipi pll clock comes from the MIPI PHY PLL output, so it should not be a fixed clock. MIPI PHY PLL is in the MIPI DSI space, and it is used as the bit clock for transferring the pixel data out and its output clock is configured according to the display mode. So it should be used only for MIPI DSI and not be exported out for other usages. Signed-off-by: Fancy Fang Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 - drivers/clk/imx/clk-imx7ulp.c | 3 +-- include/dt-bindings/clock/imx7ulp-clock.h | 1 + 3 files changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt index a4f8cd478f92..93d89adb7afe 100644 --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 { <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index c4b78a2d12b1..3fdf3d494f0a 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dumm static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dummy", }; static const char * const nic_sels[] = { "firc", "ddr_clk", }; static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; -static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; +static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", }; static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", }; /* used by sosc/sirc/firc/ddr/spll/apll dividers */ @@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); - clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll"); clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); /* SCG1 */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 6f66f9005c81..38145bdcd975 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -49,6 +49,7 @@ #define IMX7ULP_CLK_NIC1_DIV 36 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 #define IMX7ULP_CLK_NIC1_EXT_DIV 38 +/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ #define IMX7ULP_CLK_MIPI_PLL 39 #define IMX7ULP_CLK_SIRC 40 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 -- cgit v1.2.3 From c99b23eb5a983c02355f4e3f0234b6f92a69be7b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 16 Oct 2019 16:52:07 +0200 Subject: dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings As of commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files use the unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. Hence remove the old R-Car Gen2 DT bindings describing a hierarchical representation of the various CPG and MSTP clocks. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/20191016145207.29779-1-geert+renesas@glider.be --- .../clock/renesas,rcar-gen2-cpg-clocks.txt | 60 ---------------------- 1 file changed, 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt deleted file mode 100644 index f8c05bb4116e..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Renesas R-Car Gen2 Clock Pulse Generator (CPG) - -The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs -and several fixed ratio dividers. -The CPG also provides a Clock Domain for SoC devices, in combination with the -CPG Module Stop (MSTP) Clocks. - -Required Properties: - - - compatible: Must be one of - - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG - - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG - - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG - - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG - - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG - and "renesas,rcar-gen2-cpg-clocks" as a fallback. - - - reg: Base address and length of the memory resource used by the CPG - - - clocks: References to the parent clocks: first to the EXTAL clock, second - to the USB_EXTAL clock - - #clock-cells: Must be 1 - - clock-output-names: The names of the clocks. Supported clocks are "main", - "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and - "adsp" - - #power-domain-cells: Must be 0 - -SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed -through an MSTP clock should refer to the CPG device node in their -"power-domains" property, as documented by the generic PM domain bindings in -Documentation/devicetree/bindings/power/power_domain.txt. - - -Examples --------- - - - CPG device node: - - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7790-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0, "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", "z", - "rcan", "adsp"; - #power-domain-cells = <0>; - }; - - - - CPG/MSTP Clock Domain member device node: - - thermal@e61f0000 { - compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; - power-domains = <&cpg_clocks>; - }; -- cgit v1.2.3 From 830dbce7c76ea529decac7d23b808c1e7da3d891 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 16 Oct 2019 16:56:50 +0200 Subject: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example The documented compatible value for R-Car H3 is "renesas,r8a7795-rcar-usb2-clock-sel", not "renesas,r8a77950-rcar-usb2-clock-sel". Fixes: 311accb64570db45 ("clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY") Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Acked-by: Rob Herring Link: https://lore.kernel.org/r/20191016145650.30003-1-geert+renesas@glider.be --- Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt index e96e085271c1..83f6c6a7c41c 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt @@ -46,7 +46,7 @@ Required properties: Example (R-Car H3): usb2_clksel: clock-controller@e6590630 { - compatible = "renesas,r8a77950-rcar-usb2-clock-sel", + compatible = "renesas,r8a7795-rcar-usb2-clock-sel", "renesas,rcar-gen3-usb2-clock-sel"; reg = <0 0xe6590630 0 0x02>; clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>; -- cgit v1.2.3 From e751a25b4eecef0b1b305872027ae64d3b82569f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Oct 2019 14:29:38 +0200 Subject: dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support Add DT binding documentation for the Clock Pulse Generator / Module Standby and Software Reset block in the Renesas R-Car M3-W+ (R8A77961) SoC. Update all references to R-Car M3-W from "r8a7796" to "r8a77960", to avoid confusion between R-Car M3-W (R8A77960) and M3-W+. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20191023122941.12342-2-geert+renesas@glider.be --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index b5edebeb12b4..d67f57e0dfd2 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -27,7 +27,8 @@ Required Properties: - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N) - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) + - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W) + - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+) - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) @@ -42,10 +43,10 @@ Required Properties: - clock-names: List of external parent clock names. Valid names are: - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1, r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, - r8a7794, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, - r8a77990, r8a77995) - - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a7796, r8a77965, r8a77970, - r8a77980) + r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970, + r8a77980, r8a77990, r8a77995) + - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965, + r8a77970, r8a77980) - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793, r8a7794) -- cgit v1.2.3 From 9de7269e9703f32f742d8c88211320baaece58bc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 14 Oct 2019 15:53:06 +0530 Subject: dt-bindings: clock: Add YAML schemas for the QCOM GCC clock bindings The GCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Taniya Das Link: https://lkml.kernel.org/r/20191014102308.27441-4-tdas@codeaurora.org Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gcc.txt | 94 ----------- .../devicetree/bindings/clock/qcom,gcc.yaml | 174 +++++++++++++++++++++ 2 files changed, 174 insertions(+), 94 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt deleted file mode 100644 index d14362ad4132..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ /dev/null @@ -1,94 +0,0 @@ -Qualcomm Global Clock & Reset Controller Binding ------------------------------------------------- - -Required properties : -- compatible : shall contain only one of the following: - - "qcom,gcc-apq8064" - "qcom,gcc-apq8084" - "qcom,gcc-ipq8064" - "qcom,gcc-ipq4019" - "qcom,gcc-ipq8074" - "qcom,gcc-msm8660" - "qcom,gcc-msm8916" - "qcom,gcc-msm8960" - "qcom,gcc-msm8974" - "qcom,gcc-msm8974pro" - "qcom,gcc-msm8974pro-ac" - "qcom,gcc-msm8994" - "qcom,gcc-msm8996" - "qcom,gcc-msm8998" - "qcom,gcc-mdm9615" - "qcom,gcc-qcs404" - "qcom,gcc-sdm630" - "qcom,gcc-sdm660" - "qcom,gcc-sdm845" - "qcom,gcc-sm8150" - -- reg : shall contain base register location and length -- #clock-cells : shall contain 1 -- #reset-cells : shall contain 1 - -Optional properties : -- #power-domain-cells : shall contain 1 -- Qualcomm TSENS (thermal sensor device) on some devices can -be part of GCC and hence the TSENS properties can also be -part of the GCC/clock-controller node. -For more details on the TSENS properties please refer -Documentation/devicetree/bindings/thermal/qcom-tsens.txt -- protected-clocks : Protected clock specifier list as per common clock - binding. - -For SM8150 only: - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: "bi_tcxo" (required) - "sleep_clk" (optional) - "aud_ref_clock" (optional) - -Example: - clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - reg = <0x900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - -Example of GCC with TSENS properties: - clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; - #clock-cells = <1>; - #reset-cells = <1>; - #thermal-sensor-cells = <1>; - }; - -Example of GCC with protected-clocks properties: - clock-controller@100000 { - compatible = "qcom,gcc-sdm845"; - reg = <0x100000 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - protected-clocks = , - , - , - , - ; - }; - -Example of GCC with clocks - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x00100000 0x1f0000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&sleep_clk>; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file mode 100644 index 000000000000..b3ef1e24e91a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains. + +properties: + compatible : + enum: + - qcom,gcc-apq8064 + - qcom,gcc-apq8084 + - qcom,gcc-ipq8064 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq8074 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-msm8994 + - qcom,gcc-msm8996 + - qcom,gcc-msm8998 + - qcom,gcc-mdm9615 + - qcom,gcc-qcs404 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - qcom,gcc-sdm845 + - qcom,gcc-sm8150 + + clocks: + minItems: 1 + maxItems: 3 + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + clock-names: + minItems: 1 + maxItems: 3 + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + nvmem-cells: + minItems: 1 + maxItems: 2 + description: + Qualcomm TSENS (thermal sensor device) on some devices can + be part of GCC and hence the TSENS properties can also be part + of the GCC/clock-controller node. + For more details on the TSENS properties please refer + Documentation/devicetree/bindings/thermal/qcom-tsens.txt + + nvmem-cell-names: + minItems: 1 + maxItems: 2 + description: + Names for each nvmem-cells specified. + items: + - const: calib + - const: calib_backup + + 'thermal-sensor-cells': + const: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +if: + properties: + compatible: + contains: + const: qcom,gcc-apq8064 + +then: + required: + - nvmem-cells + - nvmem-cell-names + - '#thermal-sensor-cells' + +else: + if: + properties: + compatible: + contains: + enum: + - qcom,gcc-sm8150 + then: + required: + - clocks + - clock-names + + +examples: + # Example for GCC for MSM8960: + - | + clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + + # Example of GCC with TSENS properties: + - | + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + #thermal-sensor-cells = <1>; + }; + + # Example of GCC with protected-clocks properties: + - | + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + protected-clocks = <187>, <188>, <189>, <190>, <191>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + # Example of GCC with clock node properties for SM8150: + - | + clock-controller@100000 { + compatible = "qcom,gcc-sm8150"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc 0>, <&rpmhcc 1>, <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... -- cgit v1.2.3 From 8b9e0562f330ac20f0e77c0feb38cc7953274d7f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 14 Oct 2019 15:53:07 +0530 Subject: dt-bindings: clock: Add sc7180 GCC clock binding Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das Link: https://lkml.kernel.org/r/20191014102308.27441-5-tdas@codeaurora.org Reviewed-by: Rob Herring [sboyd@kernel.org: Reword subject to make sc7180 specific, sort compatible] Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gcc.yaml | 14 ++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index b3ef1e24e91a..e73a56fb60ca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -33,6 +33,7 @@ properties: - qcom,gcc-msm8998 - qcom,gcc-mdm9615 - qcom,gcc-qcs404 + - qcom,gcc-sc7180 - qcom,gcc-sdm630 - qcom,gcc-sdm660 - qcom,gcc-sdm845 @@ -118,6 +119,7 @@ else: contains: enum: - qcom,gcc-sm8150 + - qcom,gcc-sc7180 then: required: - clocks @@ -171,4 +173,16 @@ examples: #reset-cells = <1>; #power-domain-cells = <1>; }; + + # Example of GCC with clock nodes properties for SC7180: + - | + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc 0>, <&rpmhcc 1>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; ... diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h new file mode 100644 index 000000000000..e8029b2e92d7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H + +/* GCC clocks */ +#define GCC_GPLL0_MAIN_DIV_CDIV 0 +#define GPLL0 1 +#define GPLL0_OUT_EVEN 2 +#define GPLL1 3 +#define GPLL4 4 +#define GPLL6 5 +#define GPLL7 6 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CE1_AHB_CLK 14 +#define GCC_CE1_AXI_CLK 15 +#define GCC_CE1_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_CPUSS_AHB_CLK 18 +#define GCC_CPUSS_AHB_CLK_SRC 19 +#define GCC_CPUSS_GNOC_CLK 20 +#define GCC_CPUSS_RBCPR_CLK 21 +#define GCC_DDRSS_GPU_AXI_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_GPLL0_CLK_SRC 24 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 +#define GCC_DISP_HF_AXI_CLK 26 +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 +#define GCC_DISP_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_GPU_CFG_AHB_CLK 35 +#define GCC_GPU_GPLL0_CLK_SRC 36 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +#define GCC_GPU_MEMNOC_GFX_CLK 38 +#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +#define GCC_NPU_AXI_CLK 40 +#define GCC_NPU_BWMON_AXI_CLK 41 +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 +#define GCC_NPU_CFG_AHB_CLK 44 +#define GCC_NPU_DMA_CLK 45 +#define GCC_NPU_GPLL0_CLK_SRC 46 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 +#define GCC_PDM2_CLK 48 +#define GCC_PDM2_CLK_SRC 49 +#define GCC_PDM_AHB_CLK 50 +#define GCC_PDM_XO4_CLK 51 +#define GCC_PRNG_AHB_CLK 52 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 +#define GCC_QSPI_CORE_CLK 54 +#define GCC_QSPI_CORE_CLK_SRC 55 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 +#define GCC_QUPV3_WRAP0_CORE_CLK 57 +#define GCC_QUPV3_WRAP0_S0_CLK 58 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S1_CLK 60 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S2_CLK 62 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S3_CLK 64 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S4_CLK 66 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S5_CLK 68 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_CLK 71 +#define GCC_QUPV3_WRAP1_S0_CLK 72 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +#define GCC_QUPV3_WRAP1_S1_CLK 74 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S2_CLK 76 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S3_CLK 78 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S4_CLK 80 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S5_CLK 82 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 +#define GCC_SDCC1_AHB_CLK 88 +#define GCC_SDCC1_APPS_CLK 89 +#define GCC_SDCC1_APPS_CLK_SRC 90 +#define GCC_SDCC1_ICE_CORE_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_SDCC2_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_MEM_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_SLEEP_CLK 113 +#define GCC_USB3_PRIM_CLKREF_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 +#define GCC_VIDEO_THROTTLE_AXI_CLK 123 +#define GCC_VIDEO_XO_CLK 124 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB3_DP_PHY_PRIM_BCR 4 +#define GCC_USB3_DP_PHY_SEC_BCR 5 +#define GCC_USB3_PHY_PRIM_BCR 6 +#define GCC_USB3_PHY_SEC_BCR 7 +#define GCC_USB3PHY_PHY_PRIM_BCR 8 +#define GCC_USB3PHY_PHY_SEC_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 + +/* GCC GDSCRs */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 + +#endif -- cgit v1.2.3 From 681a6ad5c009e53f175db537f79314cbe6c7c816 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 29 Oct 2019 23:18:17 +0530 Subject: dt-bindings: clock: Add YAML schemas for the QCOM RPMHCC clock bindings The RPMHCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Taniya Das Link: https://lkml.kernel.org/r/1572371299-16774-2-git-send-email-tdas@codeaurora.org Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,rpmh-clk.txt | 27 ------------ .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 48 ++++++++++++++++++++++ 2 files changed, 48 insertions(+), 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt deleted file mode 100644 index 365bbde599b1..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt +++ /dev/null @@ -1,27 +0,0 @@ -Qualcomm Technologies, Inc. RPMh Clocks -------------------------------------------------------- - -Resource Power Manager Hardened (RPMh) manages shared resources on -some Qualcomm Technologies Inc. SoCs. It accepts clock requests from -other hardware subsystems via RSC to control clocks. - -Required properties : -- compatible : must be one of: - "qcom,sdm845-rpmh-clk" - "qcom,sm8150-rpmh-clk" - -- #clock-cells : must contain 1 -- clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. -- clock-names: Parent board clock: "xo". - -Example : - -#include - - &apps_rsc { - rpmhcc: clock-controller { - compatible = "qcom,sdm845-rpmh-clk"; - #clock-cells = <1>; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml new file mode 100644 index 000000000000..f25d76fc96ba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/qcom,rpmhcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. RPMh Clocks Bindings + +maintainers: + - Taniya Das + +description: | + Resource Power Manager Hardened (RPMh) manages shared resources on + some Qualcomm Technologies Inc. SoCs. It accepts clock requests from + other hardware subsystems via RSC to control clocks. + +properties: + compatible: + enum: + - qcom,sdm845-rpmh-clk + - qcom,sm8150-rpmh-clk + + clocks: + maxItems: 1 + + clock-names: + items: + - const: xo + + '#clock-cells': + const: 1 + +required: + - compatible + - '#clock-cells' + +examples: + # Example for GCC for SDM845: The below node should be defined inside + # &apps_rsc node. + - | + #include + rpmhcc: clock-controller { + compatible = "qcom,sdm845-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; +... -- cgit v1.2.3 From 36b355c84042d0d7d3bedbcdf7b92b3e5f187060 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 29 Oct 2019 23:18:18 +0530 Subject: dt-bindings: clock: Introduce RPMHCC bindings for SC7180 Add compatible for SC7180 RPMHCC. Signed-off-by: Taniya Das Acked-by: Rob Herring Link: https://lkml.kernel.org/r/1572371299-16774-3-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Sort compatible list] Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index f25d76fc96ba..94e2f14eb967 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - qcom,sc7180-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sm8150-rpmh-clk -- cgit v1.2.3 From 0b24748c3b26b9e55d195e11c7e9bed843ebff99 Mon Sep 17 00:00:00 2001 From: Zhou Yanjie Date: Sun, 10 Nov 2019 17:28:21 +0800 Subject: dt-bindings: clock: Add X1000 bindings. Add the clock bindings for the X1000 Soc from Ingenic. Signed-off-by: Zhou Yanjie Link: https://lkml.kernel.org/r/1573378102-72380-2-git-send-email-zhouyanjie@zoho.com Reviewed-by: Paul Cercueil Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/ingenic,cgu.txt | 1 + include/dt-bindings/clock/x1000-cgu.h | 44 ++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 include/dt-bindings/clock/x1000-cgu.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt index ba5a442026b7..75598e655067 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.txt +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.txt @@ -11,6 +11,7 @@ Required properties: * ingenic,jz4725b-cgu * ingenic,jz4770-cgu * ingenic,jz4780-cgu + * ingenic,x1000-cgu - reg : The address & length of the CGU registers. - clocks : List of phandle & clock specifiers for clocks external to the CGU. Two such external clocks should be specified - first the external crystal diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h new file mode 100644 index 000000000000..bbaebaf7adb9 --- /dev/null +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1000-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1000 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ + +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_SCLKA 4 +#define X1000_CLK_CPUMUX 5 +#define X1000_CLK_CPU 6 +#define X1000_CLK_L2CACHE 7 +#define X1000_CLK_AHB0 8 +#define X1000_CLK_AHB2PMUX 9 +#define X1000_CLK_AHB2 10 +#define X1000_CLK_PCLK 11 +#define X1000_CLK_DDR 12 +#define X1000_CLK_MAC 13 +#define X1000_CLK_MSCMUX 14 +#define X1000_CLK_MSC0 15 +#define X1000_CLK_MSC1 16 +#define X1000_CLK_SSIPLL 17 +#define X1000_CLK_SSIMUX 18 +#define X1000_CLK_SFC 19 +#define X1000_CLK_I2C0 20 +#define X1000_CLK_I2C1 21 +#define X1000_CLK_I2C2 22 +#define X1000_CLK_UART0 23 +#define X1000_CLK_UART1 24 +#define X1000_CLK_UART2 25 +#define X1000_CLK_SSI 26 +#define X1000_CLK_PDMA 27 + +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ -- cgit v1.2.3 From 7046c6b018912726947d75c4cacf03ca51267f59 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 15 Nov 2019 21:58:57 +0530 Subject: dt-bindings: clock: Add devicetree binding for BM1880 SoC Add YAML devicetree binding for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Link: https://lkml.kernel.org/r/20191115162901.17456-4-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd --- .../bindings/clock/bitmain,bm1880-clk.yaml | 76 ++++++++++++++++++++ include/dt-bindings/clock/bm1880-clock.h | 82 ++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 include/dt-bindings/clock/bm1880-clock.h (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml new file mode 100644 index 000000000000..e63827399c1a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Clock Controller + +maintainers: + - Manivannan Sadhasivam + +description: | + The Bitmain BM1880 clock controller generates and supplies clock to + various peripherals within the SoC. + + This binding uses common clock bindings + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +properties: + compatible: + const: bitmain,bm1880-clk + + reg: + items: + - description: pll registers + - description: system registers + + reg-names: + items: + - const: pll + - const: sys + + clocks: + maxItems: 1 + + clock-names: + const: osc + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + + # Example UART controller node that consumes clock generated by the clock controller: + - | + uart0: serial@58018000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk 45>, <&clk 46>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <0 9 4>; + reg-shift = <2>; + reg-io-width = <4>; + }; + +... diff --git a/include/dt-bindings/clock/bm1880-clock.h b/include/dt-bindings/clock/bm1880-clock.h new file mode 100644 index 000000000000..b46732361b25 --- /dev/null +++ b/include/dt-bindings/clock/bm1880-clock.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Device Tree binding constants for Bitmain BM1880 SoC + * + * Copyright (c) 2019 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_BM1880_H +#define __DT_BINDINGS_CLOCK_BM1880_H + +#define BM1880_CLK_OSC 0 +#define BM1880_CLK_MPLL 1 +#define BM1880_CLK_SPLL 2 +#define BM1880_CLK_FPLL 3 +#define BM1880_CLK_DDRPLL 4 +#define BM1880_CLK_A53 5 +#define BM1880_CLK_50M_A53 6 +#define BM1880_CLK_AHB_ROM 7 +#define BM1880_CLK_AXI_SRAM 8 +#define BM1880_CLK_DDR_AXI 9 +#define BM1880_CLK_EFUSE 10 +#define BM1880_CLK_APB_EFUSE 11 +#define BM1880_CLK_AXI5_EMMC 12 +#define BM1880_CLK_EMMC 13 +#define BM1880_CLK_100K_EMMC 14 +#define BM1880_CLK_AXI5_SD 15 +#define BM1880_CLK_SD 16 +#define BM1880_CLK_100K_SD 17 +#define BM1880_CLK_500M_ETH0 18 +#define BM1880_CLK_AXI4_ETH0 19 +#define BM1880_CLK_500M_ETH1 20 +#define BM1880_CLK_AXI4_ETH1 21 +#define BM1880_CLK_AXI1_GDMA 22 +#define BM1880_CLK_APB_GPIO 23 +#define BM1880_CLK_APB_GPIO_INTR 24 +#define BM1880_CLK_GPIO_DB 25 +#define BM1880_CLK_AXI1_MINER 26 +#define BM1880_CLK_AHB_SF 27 +#define BM1880_CLK_SDMA_AXI 28 +#define BM1880_CLK_SDMA_AUD 29 +#define BM1880_CLK_APB_I2C 30 +#define BM1880_CLK_APB_WDT 31 +#define BM1880_CLK_APB_JPEG 32 +#define BM1880_CLK_JPEG_AXI 33 +#define BM1880_CLK_AXI5_NF 34 +#define BM1880_CLK_APB_NF 35 +#define BM1880_CLK_NF 36 +#define BM1880_CLK_APB_PWM 37 +#define BM1880_CLK_DIV_0_RV 38 +#define BM1880_CLK_DIV_1_RV 39 +#define BM1880_CLK_MUX_RV 40 +#define BM1880_CLK_RV 41 +#define BM1880_CLK_APB_SPI 42 +#define BM1880_CLK_TPU_AXI 43 +#define BM1880_CLK_DIV_UART_500M 44 +#define BM1880_CLK_UART_500M 45 +#define BM1880_CLK_APB_UART 46 +#define BM1880_CLK_APB_I2S 47 +#define BM1880_CLK_AXI4_USB 48 +#define BM1880_CLK_APB_USB 49 +#define BM1880_CLK_125M_USB 50 +#define BM1880_CLK_33K_USB 51 +#define BM1880_CLK_DIV_12M_USB 52 +#define BM1880_CLK_12M_USB 53 +#define BM1880_CLK_APB_VIDEO 54 +#define BM1880_CLK_VIDEO_AXI 55 +#define BM1880_CLK_VPP_AXI 56 +#define BM1880_CLK_APB_VPP 57 +#define BM1880_CLK_DIV_0_AXI1 58 +#define BM1880_CLK_DIV_1_AXI1 59 +#define BM1880_CLK_AXI1 60 +#define BM1880_CLK_AXI2 61 +#define BM1880_CLK_AXI3 62 +#define BM1880_CLK_AXI4 63 +#define BM1880_CLK_AXI5 64 +#define BM1880_CLK_DIV_0_AXI6 65 +#define BM1880_CLK_DIV_1_AXI6 66 +#define BM1880_CLK_MUX_AXI6 67 +#define BM1880_CLK_AXI6 68 +#define BM1880_NR_CLKS 69 + +#endif /* __DT_BINDINGS_CLOCK_BM1880_H */ -- cgit v1.2.3