From 2ce6324eadb014136a4baaf7a174f47d771364a0 Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Tue, 15 Sep 2020 16:18:14 -0700 Subject: ACPI: DPTF: Add PCH FIVR participant driver This driver adds support for Dynamic Platform and Thermal Framework (DPTF) PCH (Platform Controller Hub) FIVR (Fully Integrated Voltage Regulator) participant support. This participant is responsible for exposing platform telemetry and control for: freq_mhz_high_clock freq_mhz_low_clock These attributes are used to get and set PCH FIVR switching frequency for thermal and radio frequency interference mitigation. Refer to Documentation/ABI/testing/sysfs-platform-dptf for ABI details. ACPI methods description used in this driver: RFC0: This ACPI method to set PCH FIVR switching frequency when FIVR clock is 19.2MHz or 24MHz. The ACPI method takes a DWORD value. GFC0: This ACPI method to get PCH FIVR switching frequency when FIVR clock is 19.2MHz or 24MHz. RFC1: This ACPI method to set PCH FIVR switching frequency when FIVR clock is 38.4MHz. The ACPI method takes a DWORD value. GFC1: This ACPI method to get PCH FIVR switching frequency when FIVR clock is 38.4MHz. Signed-off-by: Srinivas Pandruvada Signed-off-by: Rafael J. Wysocki --- Documentation/ABI/testing/sysfs-platform-dptf | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation') diff --git a/Documentation/ABI/testing/sysfs-platform-dptf b/Documentation/ABI/testing/sysfs-platform-dptf index eeed81ca6949..2cbc660d163b 100644 --- a/Documentation/ABI/testing/sysfs-platform-dptf +++ b/Documentation/ABI/testing/sysfs-platform-dptf @@ -92,3 +92,19 @@ Contact: linux-acpi@vger.kernel.org Description: (RO) The battery discharge current capability obtained from battery fuel gauge in milli Amps. + +What: /sys/bus/platform/devices/INTC1045:00/pch_fivr_switch_frequency/freq_mhz_low_clock +Date: November, 2020 +KernelVersion: v5.10 +Contact: linux-acpi@vger.kernel.org +Description: + (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz, + when FIVR clock is 19.2MHz or 24MHz. + +What: /sys/bus/platform/devices/INTC1045:00/pch_fivr_switch_frequency/freq_mhz_high_clock +Date: November, 2020 +KernelVersion: v5.10 +Contact: linux-acpi@vger.kernel.org +Description: + (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz, + when FIVR clock is 38.4MHz. -- cgit v1.2.3 From dc9e7860df91625fef04d7016182653e8f678f05 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Wed, 30 Sep 2020 22:05:47 +0800 Subject: docs: mm: numaperf.rst Add brief description for access class 1. Try to make minimal changes to the document which already describes access class 0 in a generic fashion (including IO initiatiors that are not CPUs). Signed-off-by: Jonathan Cameron Signed-off-by: Rafael J. Wysocki --- Documentation/admin-guide/mm/numaperf.rst | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/admin-guide/mm/numaperf.rst b/Documentation/admin-guide/mm/numaperf.rst index 4d69ef1de830..86f2a3c4b638 100644 --- a/Documentation/admin-guide/mm/numaperf.rst +++ b/Documentation/admin-guide/mm/numaperf.rst @@ -56,6 +56,11 @@ nodes' access characteristics share the same performance relative to other linked initiator nodes. Each target within an initiator's access class, though, do not necessarily perform the same as each other. +The access class "1" is used to allow differentiation between initiators +that are CPUs and hence suitable for generic task scheduling, and +IO initiators such as GPUs and NICs. Unlike access class 0, only +nodes containing CPUs are considered. + ================ NUMA Performance ================ @@ -88,6 +93,9 @@ The latency attributes are provided in nanoseconds. The values reported here correspond to the rated latency and bandwidth for the platform. +Access class 1 takes the same form but only includes values for CPU to +memory activity. + ========== NUMA Cache ========== -- cgit v1.2.3