From e51e597d9f692cd7d205e3b44bb35ea3b97e7329 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 28 Jun 2018 10:25:32 +0300 Subject: dt-bindings: serial: imx: clarify rs485 support usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX UART peripheral uses the RST_B signal as input, and CTS_B as output. This is just like the DCE role in RS-232. This is true regardless of the "DTE mode" setting of this peripheral. As a result, rs485 support hardware must use the CTS_B signal to control the RS-485 transceiver. This is in contrast to generic rs485 kernel code, documentation, and DT property names that consistently refer to the RTS as transceiver control signal. Add a note in the DT binding document about that, to reduce the confusion somewhat. Signed-off-by: Baruch Siach Acked-by: Uwe Kleine-König Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/fsl-imx-uart.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt index afcfbc34e243..35957cbf1571 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt @@ -9,7 +9,11 @@ Optional properties: - fsl,dte-mode : Indicate the uart works in DTE mode. The uart works in DCE mode by default. - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx, - linux,rs485-enabled-at-boot-time: see rs485.txt + linux,rs485-enabled-at-boot-time: see rs485.txt. Note that for RS485 + you must enable either the "uart-has-rtscts" or the "rts-gpios" + properties. In case you use "uart-has-rtscts" the signal that controls + the transceiver is actually CTS_B, not RTS_B. CTS_B is always output, + and RTS_B is input, regardless of dte-mode. Please check Documentation/devicetree/bindings/serial/serial.txt for the complete list of generic properties. -- cgit v1.2.3 From ccd8350d06c6df5dca868fefbd925af8ef55ac12 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 19 Jun 2018 14:44:49 -0500 Subject: dt-bindings: serial: 8250_omap: Add compatible for AM654 UART controller AM654 uses a UART controller that is only partially compatible with existing 8250 UART. UART DMA integration is substantially different and even a match against standard 8250 or omap4 would result in non-working UART once DMA is enabled by default. Introduce a specific compatible to help build up the differences in follow on patches. Cc: Sekhar Nori Cc: Vignesh R Signed-off-by: Nishanth Menon Acked-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/omap_serial.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt index 4b0f05adb228..c35d5ece1156 100644 --- a/Documentation/devicetree/bindings/serial/omap_serial.txt +++ b/Documentation/devicetree/bindings/serial/omap_serial.txt @@ -1,6 +1,7 @@ OMAP UART controller Required properties: +- compatible : should be "ti,am654-uart" for AM654 controllers - compatible : should be "ti,omap2-uart" for OMAP2 controllers - compatible : should be "ti,omap3-uart" for OMAP3 controllers - compatible : should be "ti,omap4-uart" for OMAP4 controllers -- cgit v1.2.3 From 2867443e3b6b35a0b8fafabe9090fa8c35f690e7 Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Wed, 4 Jul 2018 09:52:51 +0800 Subject: dt-bindings: mediatek: add support for mt6765 reference board Update binding document for mt6765 reference board Signed-off-by: Mars Cheng Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index 7d21ab37c19c..48fac4ec91fc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -11,6 +11,7 @@ compatible: Must contain one of "mediatek,mt6589" "mediatek,mt6592" "mediatek,mt6755" + "mediatek,mt6765" "mediatek,mt6795" "mediatek,mt6797" "mediatek,mt7622" @@ -41,6 +42,9 @@ Supported boards: - Evaluation phone for MT6755(Helio P10): Required root node properties: - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; +- Evaluation board for MT6765(Helio P22): + Required root node properties: + - compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; - Evaluation board for MT6795(Helio X10): Required root node properties: - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; -- cgit v1.2.3 From eb3c74c27d059234c58e40caefa3d64cbf998a45 Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Wed, 4 Jul 2018 09:52:52 +0800 Subject: dt-bindings: mtk-uart: add mt6765 uart bindings Add documentation for mt6765 uart dt-bindings Signed-off-by: Mars Cheng Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index f73abff3de43..742cb470595b 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -8,6 +8,7 @@ Required properties: * "mediatek,mt6582-uart" for MT6582 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6755-uart" for MT6755 compatible UARTS + * "mediatek,mt6765-uart" for MT6765 compatible UARTS * "mediatek,mt6795-uart" for MT6795 compatible UARTS * "mediatek,mt6797-uart" for MT6797 compatible UARTS * "mediatek,mt7622-uart" for MT7622 compatible UARTS -- cgit v1.2.3 From 447735fafe5f8779f07091f5d30cca6a44c0c1fd Mon Sep 17 00:00:00 2001 From: Mars Cheng Date: Wed, 4 Jul 2018 09:52:53 +0800 Subject: dt-bindings: interrupt-controller: add binding for mt6765 Update the dt-binding documentation of sysirq for mt6765 Signed-off-by: Mars Cheng Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 07bf0b9a5139..c8eda800f37e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -11,6 +11,7 @@ Required properties: "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 + "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755 "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592 "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589 -- cgit v1.2.3 From b819e4aba0f8456966dce137650b9421f5bf9be7 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Wed, 11 Jul 2018 09:41:31 -0500 Subject: serial: sh-sci: Document r7s9210 bindings Add R7S9210 (RZ/A2) support Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 106808b55b6d..5c002bce8f42 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -5,6 +5,7 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. + - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART. - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. -- cgit v1.2.3 From 8a8a66a1a18a1dbd213bee460bcedb1361abc7ff Mon Sep 17 00:00:00 2001 From: Girish Mahadevan Date: Fri, 13 Jul 2018 16:17:35 -0600 Subject: tty: serial: qcom_geni_serial: Add support for flow control Add support for flow control functionality in the GENI serial driver and also support for non-console higher baud rate(upto 4Mbps) usecases. Signed-off-by: Girish Mahadevan Signed-off-by: Mohammed Khajapasha Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 2 +- drivers/tty/serial/qcom_geni_serial.c | 261 ++++++++++++++++++--- 2 files changed, 231 insertions(+), 32 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt index d330c73de9a2..a9eeca28f03e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt @@ -46,7 +46,7 @@ Child nodes should conform to I2C bus binding as described in i2c.txt. Qualcomm Technologies Inc. GENI Serial Engine based UART Controller Required properties: -- compatible: Must be "qcom,geni-debug-uart". +- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart". - reg: Must contain UART register location and length. - interrupts: Must contain UART core interrupts. - clock-names: Must contain "se". diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index c62e17c85f57..29ec34387246 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -17,6 +17,7 @@ #include /* UART specific GENI registers */ +#define SE_UART_LOOPBACK_CFG 0x22c #define SE_UART_TX_TRANS_CFG 0x25c #define SE_UART_TX_WORD_LEN 0x268 #define SE_UART_TX_STOP_BIT_LEN 0x26c @@ -26,6 +27,7 @@ #define SE_UART_RX_STALE_CNT 0x294 #define SE_UART_TX_PARITY_CFG 0x2a4 #define SE_UART_RX_PARITY_CFG 0x2a8 +#define SE_UART_MANUAL_RFR 0x2ac /* SE_UART_TRANS_CFG */ #define UART_TX_PAR_EN BIT(0) @@ -62,6 +64,11 @@ #define PAR_SPACE 0x10 #define PAR_MARK 0x11 +/* SE_UART_MANUAL_RFR register fields */ +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) + /* UART M_CMD OP codes */ #define UART_START_TX 0x1 #define UART_START_BREAK 0x4 @@ -74,10 +81,12 @@ #define STALE_TIMEOUT 16 #define DEFAULT_BITS_PER_CHAR 10 #define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 #define DEF_FIFO_DEPTH_WORDS 16 #define DEF_TX_WM 2 #define DEF_FIFO_WIDTH_BITS 32 #define UART_CONSOLE_RX_WM 2 +#define MAX_LOOPBACK_CFG 3 #ifdef CONFIG_CONSOLE_POLL #define RX_BYTES_PW 1 @@ -101,22 +110,81 @@ struct qcom_geni_serial_port { unsigned int baud; unsigned int tx_bytes_pw; unsigned int rx_bytes_pw; + u32 *rx_fifo; + u32 loopback; bool brk; }; static const struct uart_ops qcom_geni_console_pops; +static const struct uart_ops qcom_geni_uart_pops; static struct uart_driver qcom_geni_console_driver; +static struct uart_driver qcom_geni_uart_driver; static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); +static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); static void qcom_geni_serial_stop_rx(struct uart_port *uport); static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, 32000000, 48000000, 64000000, 80000000, - 96000000, 100000000}; + 96000000, 100000000, 102400000, + 112000000, 120000000, 128000000}; #define to_dev_port(ptr, member) \ container_of(ptr, struct qcom_geni_serial_port, member) +static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { + [0] = { + .uport = { + .iotype = UPIO_MEM, + .ops = &qcom_geni_uart_pops, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, + }, + }, + [1] = { + .uport = { + .iotype = UPIO_MEM, + .ops = &qcom_geni_uart_pops, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, + }, + }, + [2] = { + .uport = { + .iotype = UPIO_MEM, + .ops = &qcom_geni_uart_pops, + .flags = UPF_BOOT_AUTOCONF, + .line = 2, + }, + }, +}; + +static ssize_t loopback_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); + + return snprintf(buf, sizeof(u32), "%d\n", port->loopback); +} + +static ssize_t loopback_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + struct platform_device *pdev = to_platform_device(dev); + struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); + u32 loopback; + + if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) { + dev_err(dev, "Invalid input\n"); + return -EINVAL; + } + port->loopback = loopback; + return size; +} +static DEVICE_ATTR_RW(loopback); + static struct qcom_geni_serial_port qcom_geni_console_port = { .uport = { .iotype = UPIO_MEM, @@ -148,14 +216,33 @@ static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) } } -static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport) +static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) { - return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS; + unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; + u32 geni_ios; + + if (uart_console(uport) || !uart_cts_enabled(uport)) { + mctrl |= TIOCM_CTS; + } else { + geni_ios = readl_relaxed(uport->membase + SE_GENI_IOS); + if (!(geni_ios & IO2_DATA_IN)) + mctrl |= TIOCM_CTS; + } + + return mctrl; } -static void qcom_geni_cons_set_mctrl(struct uart_port *uport, +static void qcom_geni_serial_set_mctrl(struct uart_port *uport, unsigned int mctrl) { + u32 uart_manual_rfr = 0; + + if (uart_console(uport) || !uart_cts_enabled(uport)) + return; + + if (!(mctrl & TIOCM_RTS)) + uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; + writel_relaxed(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); } static const char *qcom_geni_serial_get_type(struct uart_port *uport) @@ -163,11 +250,16 @@ static const char *qcom_geni_serial_get_type(struct uart_port *uport) return "MSM"; } -static struct qcom_geni_serial_port *get_port_from_line(int line) +static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) { - if (line < 0 || line >= GENI_UART_CONS_PORTS) + struct qcom_geni_serial_port *port; + int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; + + if (line < 0 || line >= nr_ports) return ERR_PTR(-ENXIO); - return &qcom_geni_console_port; + + port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; + return port; } static bool qcom_geni_serial_poll_bit(struct uart_port *uport, @@ -346,7 +438,7 @@ static void qcom_geni_serial_console_write(struct console *co, const char *s, WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); - port = get_port_from_line(co->index); + port = get_port_from_line(co->index, true); if (IS_ERR(port)) return; @@ -420,6 +512,32 @@ static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ +static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) +{ + unsigned char *buf; + struct tty_port *tport; + struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; + u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; + int ret; + + tport = &uport->state->port; + ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); + if (drop) + return 0; + + buf = (unsigned char *)port->rx_fifo; + ret = tty_insert_flip_string(tport, buf, bytes); + if (ret != bytes) { + dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", + __func__, ret, bytes); + WARN_ON_ONCE(1); + } + uport->icount.rx += ret; + tty_flip_buffer_push(tport); + return ret; +} + static void qcom_geni_serial_start_tx(struct uart_port *uport) { u32 irq_en; @@ -586,6 +704,7 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport) u32 status; unsigned int chunk; int tail; + u32 irq_en; chunk = uart_circ_chars_pending(xmit); status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS); @@ -595,6 +714,13 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport) goto out_write_wakeup; } + if (!uart_console(uport)) { + irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); + irq_en &= ~(M_TX_FIFO_WATERMARK_EN); + writel_relaxed(0, uport->membase + SE_GENI_TX_WATERMARK_REG); + writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); + } + avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw; tail = xmit->tail; chunk = min3((size_t)chunk, (size_t)(UART_XMIT_SIZE - tail), avail); @@ -623,7 +749,8 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport) } xmit->tail = tail & (UART_XMIT_SIZE - 1); - qcom_geni_serial_poll_tx_done(uport); + if (uart_console(uport)) + qcom_geni_serial_poll_tx_done(uport); out_write_wakeup: if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(uport); @@ -710,7 +837,8 @@ static void qcom_geni_serial_shutdown(struct uart_port *uport) unsigned long flags; /* Stop the console before stopping the current tx */ - console_stop(uport->cons); + if (uart_console(uport)) + console_stop(uport->cons); free_irq(uport->irq, uport); spin_lock_irqsave(&uport->lock, flags); @@ -731,13 +859,20 @@ static int qcom_geni_serial_port_setup(struct uart_port *uport) * it else we could end up in data loss scenarios. */ port->xfer_mode = GENI_SE_FIFO; - qcom_geni_serial_poll_tx_done(uport); + if (uart_console(uport)) + qcom_geni_serial_poll_tx_done(uport); geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw, false, true, false); geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw, false, false, true); geni_se_init(&port->se, port->rx_wm, port->rx_rfr); geni_se_select_mode(&port->se, port->xfer_mode); + if (!uart_console(uport)) { + port->rx_fifo = devm_kzalloc(uport->dev, + port->rx_fifo_depth * sizeof(u32), GFP_KERNEL); + if (!port->rx_fifo) + return -ENOMEM; + } port->setup = true; return 0; } @@ -749,8 +884,13 @@ static int qcom_geni_serial_startup(struct uart_port *uport) struct qcom_geni_serial_port *port = to_dev_port(uport, uport); scnprintf(port->name, sizeof(port->name), - "qcom_serial_geni%d", uport->line); + "qcom_serial_%s%d", + (uart_console(uport) ? "console" : "uart"), uport->line); + if (!uart_console(uport)) { + port->tx_bytes_pw = 4; + port->rx_bytes_pw = RX_BYTES_PW; + } proto = geni_se_read_proto(&port->se); if (proto != GENI_SE_UART) { dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); @@ -886,6 +1026,9 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, if (baud) uart_update_timeout(uport, termios->c_cflag, baud); + if (!uart_console(uport)) + writel_relaxed(port->loopback, + uport->membase + SE_UART_LOOPBACK_CFG); writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); @@ -917,7 +1060,7 @@ static int __init qcom_geni_console_setup(struct console *co, char *options) if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) return -ENXIO; - port = get_port_from_line(co->index); + port = get_port_from_line(co->index, true); if (IS_ERR(port)) { pr_err("Invalid line %d\n", co->index); return PTR_ERR(port); @@ -1048,16 +1191,23 @@ static void console_unregister(struct uart_driver *drv) } #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ -static void qcom_geni_serial_cons_pm(struct uart_port *uport, +static struct uart_driver qcom_geni_uart_driver = { + .owner = THIS_MODULE, + .driver_name = "qcom_geni_uart", + .dev_name = "ttyHS", + .nr = GENI_UART_PORTS, +}; + +static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { struct qcom_geni_serial_port *port = to_dev_port(uport, uport); - if (unlikely(!uart_console(uport))) - return; - if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) geni_se_resources_on(&port->se); + else if (!uart_console(uport) && (new_state == UART_PM_STATE_ON && + old_state == UART_PM_STATE_UNDEFINED)) + geni_se_resources_on(&port->se); else if (new_state == UART_PM_STATE_OFF && old_state == UART_PM_STATE_ON) geni_se_resources_off(&port->se); @@ -1074,13 +1224,29 @@ static const struct uart_ops qcom_geni_console_pops = { .config_port = qcom_geni_serial_config_port, .shutdown = qcom_geni_serial_shutdown, .type = qcom_geni_serial_get_type, - .set_mctrl = qcom_geni_cons_set_mctrl, - .get_mctrl = qcom_geni_cons_get_mctrl, + .set_mctrl = qcom_geni_serial_set_mctrl, + .get_mctrl = qcom_geni_serial_get_mctrl, #ifdef CONFIG_CONSOLE_POLL .poll_get_char = qcom_geni_serial_get_char, .poll_put_char = qcom_geni_serial_poll_put_char, #endif - .pm = qcom_geni_serial_cons_pm, + .pm = qcom_geni_serial_pm, +}; + +static const struct uart_ops qcom_geni_uart_pops = { + .tx_empty = qcom_geni_serial_tx_empty, + .stop_tx = qcom_geni_serial_stop_tx, + .start_tx = qcom_geni_serial_start_tx, + .stop_rx = qcom_geni_serial_stop_rx, + .set_termios = qcom_geni_serial_set_termios, + .startup = qcom_geni_serial_startup, + .request_port = qcom_geni_serial_request_port, + .config_port = qcom_geni_serial_config_port, + .shutdown = qcom_geni_serial_shutdown, + .type = qcom_geni_serial_get_type, + .set_mctrl = qcom_geni_serial_set_mctrl, + .get_mctrl = qcom_geni_serial_get_mctrl, + .pm = qcom_geni_serial_pm, }; static int qcom_geni_serial_probe(struct platform_device *pdev) @@ -1091,13 +1257,23 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) struct uart_port *uport; struct resource *res; int irq; + bool console = false; + struct uart_driver *drv; - if (pdev->dev.of_node) - line = of_alias_get_id(pdev->dev.of_node, "serial"); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) + console = true; - if (line < 0 || line >= GENI_UART_CONS_PORTS) - return -ENXIO; - port = get_port_from_line(line); + if (pdev->dev.of_node) { + if (console) { + drv = &qcom_geni_console_driver; + line = of_alias_get_id(pdev->dev.of_node, "serial"); + } else { + drv = &qcom_geni_uart_driver; + line = of_alias_get_id(pdev->dev.of_node, "hsuart"); + } + } + + port = get_port_from_line(line, console); if (IS_ERR(port)) { dev_err(&pdev->dev, "Invalid line %d\n", line); return PTR_ERR(port); @@ -1134,10 +1310,12 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) } uport->irq = irq; - uport->private_data = &qcom_geni_console_driver; + uport->private_data = drv; platform_set_drvdata(pdev, port); - port->handle_rx = handle_rx_console; - return uart_add_one_port(&qcom_geni_console_driver, uport); + port->handle_rx = console ? handle_rx_console : handle_rx_uart; + if (!console) + device_create_file(uport->dev, &dev_attr_loopback); + return uart_add_one_port(drv, uport); } static int qcom_geni_serial_remove(struct platform_device *pdev) @@ -1154,7 +1332,17 @@ static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev) struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; - uart_suspend_port(uport->private_data, uport); + if (uart_console(uport)) { + uart_suspend_port(uport->private_data, uport); + } else { + struct uart_state *state = uport->state; + /* + * If the port is open, deny system suspend. + */ + if (state->pm_state == UART_PM_STATE_ON) + return -EBUSY; + } + return 0; } @@ -1163,7 +1351,8 @@ static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev) struct qcom_geni_serial_port *port = dev_get_drvdata(dev); struct uart_port *uport = &port->uport; - if (console_suspend_enabled && uport->suspended) { + if (uart_console(uport) && + console_suspend_enabled && uport->suspended) { uart_resume_port(uport->private_data, uport); /* * uart_suspend_port() invokes port shutdown which in turn @@ -1185,6 +1374,7 @@ static const struct dev_pm_ops qcom_geni_serial_pm_ops = { static const struct of_device_id qcom_geni_serial_match_table[] = { { .compatible = "qcom,geni-debug-uart", }, + { .compatible = "qcom,geni-uart", }, {} }; MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); @@ -1207,9 +1397,17 @@ static int __init qcom_geni_serial_init(void) if (ret) return ret; + ret = uart_register_driver(&qcom_geni_uart_driver); + if (ret) { + console_unregister(&qcom_geni_console_driver); + return ret; + } + ret = platform_driver_register(&qcom_geni_serial_platform_driver); - if (ret) + if (ret) { console_unregister(&qcom_geni_console_driver); + uart_unregister_driver(&qcom_geni_uart_driver); + } return ret; } module_init(qcom_geni_serial_init); @@ -1218,6 +1416,7 @@ static void __exit qcom_geni_serial_exit(void) { platform_driver_unregister(&qcom_geni_serial_platform_driver); console_unregister(&qcom_geni_console_driver); + uart_unregister_driver(&qcom_geni_uart_driver); } module_exit(qcom_geni_serial_exit); -- cgit v1.2.3 From 72b0505f0830df9531cffa5e22cebb8a551f5ba8 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 13 Jul 2018 10:33:48 +0100 Subject: dt: serial: Add Renesas RZ/N1 binding documentation The RZ/N1 UART is a modified Synopsys DesignWare UART. The modifications only relate to DMA so you could actually use the controller with the Synopsys compatible string if you are not using DMA, but you should not do so. Signed-off-by: Phil Edworthy Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt new file mode 100644 index 000000000000..8b9e0d4dc2e4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rzn1-uart.txt @@ -0,0 +1,10 @@ +Renesas RZ/N1 UART + +This controller is based on the Synopsys DesignWare ABP UART and inherits all +properties defined in snps-dw-apb-uart.txt except for the compatible property. + +Required properties: +- compatible : The device specific string followed by the generic RZ/N1 string. + Therefore it must be one of: + "renesas,r9a06g032-uart", "renesas,rzn1-uart" + "renesas,r9a06g033-uart", "renesas,rzn1-uart" -- cgit v1.2.3 From 3bae8cea04c6db58e5e694e708bd33dac924bf30 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 Jul 2018 14:19:40 +0200 Subject: serial: sh-sci: Document that serial aliases became optional Serial aliases are optional since commit 7678f4c20fa7670f ("serial: sh-sci: Add support for dynamic instances"). Update the DT bindings to reflect this. Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 5c002bce8f42..a7cda6550100 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -90,7 +90,7 @@ Required properties: - "scif_clk" for the optional external clock source for the frequency divider (SCIF_CLK). -Note: Each enabled SCIx UART should have an alias correctly numbered in the +Note: Each enabled SCIx UART may have an optional "serialN" alias in the "aliases" node. Optional properties: -- cgit v1.2.3 From 13aa0a12183f804d95c4c5c4d09df19ea74eb424 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Tue, 17 Jul 2018 21:02:42 -0400 Subject: vt: add /dev/vcsu* to devices.txt Also mention that the traditional devices provide glyph values whereas /dev/vcsu* is unicode based. Suggested-by: Geert Uytterhoeven Signed-off-by: Nicolas Pitre Reviewed-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/devices.txt | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'Documentation') diff --git a/Documentation/admin-guide/devices.txt b/Documentation/admin-guide/devices.txt index 4ec843123cc3..1649117e6087 100644 --- a/Documentation/admin-guide/devices.txt +++ b/Documentation/admin-guide/devices.txt @@ -173,14 +173,18 @@ they are redirected through the parport multiplex layer. 7 char Virtual console capture devices - 0 = /dev/vcs Current vc text contents - 1 = /dev/vcs1 tty1 text contents + 0 = /dev/vcs Current vc text (glyph) contents + 1 = /dev/vcs1 tty1 text (glyph) contents ... - 63 = /dev/vcs63 tty63 text contents - 128 = /dev/vcsa Current vc text/attribute contents - 129 = /dev/vcsa1 tty1 text/attribute contents + 63 = /dev/vcs63 tty63 text (glyph) contents + 64 = /dev/vcsu Current vc text (unicode) contents + 65 = /dev/vcsu1 tty1 text (unicode) contents ... - 191 = /dev/vcsa63 tty63 text/attribute contents + 127 = /dev/vcsu63 tty63 text (unicode) contents + 128 = /dev/vcsa Current vc text/attribute (glyph) contents + 129 = /dev/vcsa1 tty1 text/attribute (glyph) contents + ... + 191 = /dev/vcsa63 tty63 text/attribute (glyph) contents NOTE: These devices permit both read and write access. -- cgit v1.2.3 From 70a15ff0ed1183a8879031d6014dd6dd159ea617 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Tue, 31 Jul 2018 05:41:36 -0500 Subject: serial: sh-sci: Improve interrupts description Describe interrupts property in more detail, especially when there are more than one interrupt. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/serial/renesas,sci-serial.txt | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index a7cda6550100..eaca9da79d83 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -73,7 +73,21 @@ Required properties: family-specific and/or generic versions. - reg: Base address and length of the I/O registers used by the UART. - - interrupts: Must contain an interrupt-specifier for the SCIx interrupt. + - interrupts: Must contain one or more interrupt-specifiers for the SCIx. + If a single interrupt is expressed, then all events are + multiplexed into this single interrupt. + + If multiple interrupts are provided by the hardware, the order + in which the interrupts are listed must match order below. Note + that some HW interrupt events may be muxed together resulting + in duplicate entries. + The interrupt order is as follows: + 1. Error (ERI) + 2. Receive buffer full (RXI) + 3. Transmit buffer empty (TXI) + 4. Break (BRI) + 5. Data Ready (DRI) + 6. Transmit End (TEI) - clocks: Must contain a phandle and clock-specifier pair for each entry in clock-names. -- cgit v1.2.3 From bfbf2de2c9f467219b472e99c303449634fc3186 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Sat, 21 Jul 2018 17:19:07 +0530 Subject: dt-bindings: serial: Add binding for uartlite The uartlite devicetree binding was missed out. Add the binding documentation for uartlite that is already in use. Signed-off-by: Shubhrajyoti Datta Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- .../bindings/serial/xlnx,opb-uartlite.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt new file mode 100644 index 000000000000..c37deb44dead --- /dev/null +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt @@ -0,0 +1,23 @@ +Xilinx Axi Uartlite controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Can be either of + "xlnx,xps-uartlite-1.00.a" + "xlnx,opb-uartlite-1.00.b" +- reg : Physical base address and size of the Axi Uartlite + registers map. +- interrupts : Should contain the UART controller interrupt. + +Optional properties: +- port-number : Set Uart port number +- clock-names : Should be "s_axi_aclk" +- clocks : Input clock specifier. Refer to common clock bindings. + +Example: +serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x0 0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; +}; -- cgit v1.2.3