From 2524257bce43610f5ec14feccbacf7a103cae94a Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 1 Apr 2022 12:57:42 -0700 Subject: dt-bindings: Fix phandle-array issues in the idle-states bindings As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the phandle-array bindings have been disambiguated. This fixes the new RISC-V idle-states bindings to comply with the schema. Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states") Reviewed-by: Rob Herring Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++-------- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 2 files changed, 10 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml index 5daa219ceb7b..fa4d4142ac93 100644 --- a/Documentation/devicetree/bindings/cpu/idle-states.yaml +++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml @@ -719,8 +719,8 @@ examples: reg = <0x0>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -735,8 +735,8 @@ examples: reg = <0x1>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0 - &CLUSTER_RET_0 &CLUSTER_NONRET_0>; + cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>, + <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>; cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -751,8 +751,8 @@ examples: reg = <0x10>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; cpu_intc10: interrupt-controller { #interrupt-cells = <1>; @@ -767,8 +767,8 @@ examples: reg = <0x11>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; - cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0 - &CLUSTER_RET_1 &CLUSTER_NONRET_1>; + cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>, + <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>; cpu_intc11: interrupt-controller { #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f62f646bc695..d632ac76532e 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -101,6 +101,8 @@ properties: cpu-idle-states: $ref: '/schemas/types.yaml#/definitions/phandle-array' + items: + maxItems: 1 description: | List of phandles to idle state nodes supported by this hart (see ./idle-states.yaml). -- cgit v1.2.3