From 27bfb201b2c03c8a033b60e5ad80cbf3aaa52b94 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 11 Jul 2022 17:30:40 +0200 Subject: dt-bindings: mtd: partitions: add binding for U-Boot bootloader MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Right now there is no (known) real reason for a custom binding for standard U-Boot partitions. Broadcom's U-Boot however requires extra handling - looking for environment variables subblocks. This commit adds Broadcom specific binding. Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220711153041.6036-1-zajec5@gmail.com --- .../devicetree/bindings/mtd/partitions/u-boot.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml b/Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml new file mode 100644 index 000000000000..8a88e7d16524 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/u-boot.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/u-boot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: U-Boot bootloader partition + +description: | + U-Boot is a bootlodaer commonly used in embedded devices. It's almost always + located on some kind of flash device. + + Device configuration is stored as a set of environment variables that are + located in a (usually standalone) block of data. + +maintainers: + - Rafał Miłecki + +allOf: + - $ref: partition.yaml# + +properties: + compatible: + oneOf: + - const: brcm,u-boot + description: | + Broadcom stores environment variables inside a U-Boot partition. They + can be identified by a custom header with magic value. + +unevaluatedProperties: false + +examples: + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "brcm,u-boot"; + reg = <0x0 0x100000>; + label = "u-boot"; + }; + + partition@100000 { + reg = <0x100000 0x1ff00000>; + label = "firmware"; + }; + }; -- cgit v1.2.3 From c6d7ce0a7e0562846431dc3c7c390dde7d0c0c42 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 3 Jul 2022 01:12:20 +0200 Subject: dt-bindings: mtd: intel: lgm-nand: Fix compatible string The driver which was added at the same time as the dt-bindings uses the compatible string "intel,lgm-ebunand". Use the same compatible string also in the dt-bindings and rename the bindings file accordingly. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-2-martin.blumenstingl@googlemail.com --- .../devicetree/bindings/mtd/intel,lgm-ebunand.yaml | 99 ++++++++++++++++++++++ .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 99 ---------------------- 2 files changed, 99 insertions(+), 99 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml new file mode 100644 index 000000000000..763ee3e1faf3 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel LGM SoC NAND Controller Device Tree Bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Ramuthevar Vadivel Murugan + +properties: + compatible: + const: intel,lgm-ebunand + + reg: + maxItems: 6 + + reg-names: + items: + - const: ebunand + - const: hsnand + - const: nand_cs0 + - const: nand_cs1 + - const: addr_sel0 + - const: addr_sel1 + + clocks: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^nand@[a-f0-9]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 7 + + nand-ecc-mode: true + + nand-ecc-algo: + const: hw + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - clocks + - dmas + - dma-names + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + nand-controller@e0f00000 { + compatible = "intel,lgm-ebunand"; + reg = <0xe0f00000 0x100>, + <0xe1000000 0x300>, + <0xe1400000 0x8000>, + <0xe1c00000 0x1000>, + <0x17400000 0x4>, + <0x17c00000 0x4>; + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", + "addr_sel0", "addr_sel1"; + clocks = <&cgu0 125>; + dmas = <&dma0 8>, <&dma0 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml deleted file mode 100644 index 30e0c66ab0eb..000000000000 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml +++ /dev/null @@ -1,99 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel LGM SoC NAND Controller Device Tree Bindings - -allOf: - - $ref: "nand-controller.yaml" - -maintainers: - - Ramuthevar Vadivel Murugan - -properties: - compatible: - const: intel,lgm-nand - - reg: - maxItems: 6 - - reg-names: - items: - - const: ebunand - - const: hsnand - - const: nand_cs0 - - const: nand_cs1 - - const: addr_sel0 - - const: addr_sel1 - - clocks: - maxItems: 1 - - dmas: - maxItems: 2 - - dma-names: - items: - - const: tx - - const: rx - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - -patternProperties: - "^nand@[a-f0-9]+$": - type: object - properties: - reg: - minimum: 0 - maximum: 7 - - nand-ecc-mode: true - - nand-ecc-algo: - const: hw - - additionalProperties: false - -required: - - compatible - - reg - - reg-names - - clocks - - dmas - - dma-names - - "#address-cells" - - "#size-cells" - -additionalProperties: false - -examples: - - | - nand-controller@e0f00000 { - compatible = "intel,lgm-nand"; - reg = <0xe0f00000 0x100>, - <0xe1000000 0x300>, - <0xe1400000 0x8000>, - <0xe1c00000 0x1000>, - <0x17400000 0x4>, - <0x17c00000 0x4>; - reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", - "addr_sel0", "addr_sel1"; - clocks = <&cgu0 125>; - dmas = <&dma0 8>, <&dma0 9>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - nand-ecc-mode = "hw"; - }; - }; - -... -- cgit v1.2.3 From 9fac2a193e4553d6ce093a626ef5920c362d0753 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 3 Jul 2022 01:12:21 +0200 Subject: dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value The Intel LGM NAND IP only supports two chip selects: There's only two CS and ADDR_SEL register sets. Fix the maximum allowed chip select value according to the dt-bindings. Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC") Acked-by: Rob Herring Signed-off-by: Martin Blumenstingl Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220702231227.1579176-3-martin.blumenstingl@googlemail.com --- Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml index 763ee3e1faf3..04f26196c4c1 100644 --- a/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-ebunand.yaml @@ -51,7 +51,7 @@ patternProperties: properties: reg: minimum: 0 - maximum: 7 + maximum: 1 nand-ecc-mode: true -- cgit v1.2.3 From c2807b38ab96b6eb6a9e6467a088b9785f4df9aa Mon Sep 17 00:00:00 2001 From: Liang Yang Date: Wed, 7 Sep 2022 16:04:01 +0800 Subject: dt-bindings: nand: meson: fix meson nfc clock EMMC and NAND have the same clock control register named 'SD_EMMC_CLOCK' which is defined in EMMC port internally. bit0~5 of 'SD_EMMC_CLOCK' is the divider and bit6~7 is the mux for fix pll and xtal. At the beginning, a common MMC and NAND sub-clock was discussed and planed to be implemented as NFC clock provider, but now this series of patches of a common MMC and NAND sub-clock are never being accepted and the current binding was never valid. the reasons for giving up are: 1. EMMC and NAND, which are mutually exclusive anyway 2. coupling the EMMC and NAND. 3. it seems that a common MMC and NAND sub-clock is over engineered. and let us see the link fot more information: https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com so The meson nfc can't work now, let us rework the clock. Acked-by: Rob Herring Signed-off-by: Liang Yang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220907080405.28240-2-liang.yang@amlogic.com --- .../devicetree/bindings/mtd/amlogic,meson-nand.txt | 29 +++++++++------------- 1 file changed, 12 insertions(+), 17 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt index 5794ab1147c1..5d5cdfef417f 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt @@ -7,18 +7,19 @@ Required properties: - compatible : contains one of: - "amlogic,meson-gxl-nfc" - "amlogic,meson-axg-nfc" + +- reg : Offset and length of the register set + +- reg-names : "nfc" is the register set for NFC controller and "emmc" + is the register set for MCI controller. + - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. - clock-names: Should contain the following: "core" - NFC module gate clock - "device" - device clock from eMMC sub clock controller - "rx" - rx clock phase - "tx" - tx clock phase - -- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC - controller port C + "device" - parent clock for internal NFC Optional children nodes: Children nodes represent the available nand chips. @@ -28,24 +29,18 @@ see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindi Example demonstrate on AXG SoC: - sd_emmc_c_clkc: mmc@7000 { - compatible = "amlogic,meson-axg-mmc-clkc", "syscon"; - reg = <0x0 0x7000 0x0 0x800>; - }; - nand-controller@7800 { compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>; + reg = <0x0 0x7800 0x0 0x100>, + <0x0 0x7000 0x0 0x800>; + reg-names = "nfc", "emmc"; #address-cells = <1>; #size-cells = <0>; interrupts = ; clocks = <&clkc CLKID_SD_EMMC_C>, - <&sd_emmc_c_clkc CLKID_MMC_DIV>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>, - <&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>; - clock-names = "core", "device", "rx", "tx"; - amlogic,mmc-syscon = <&sd_emmc_c_clkc>; + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; pinctrl-names = "default"; pinctrl-0 = <&nand_pins>; -- cgit v1.2.3 From fbc00b5e746f138aa647fa8ddca5ed032195d089 Mon Sep 17 00:00:00 2001 From: Liang Yang Date: Wed, 7 Sep 2022 16:04:04 +0800 Subject: dt-bindings: nand: meson: convert txt to yaml convert the amlogic,meson-name.txt to amlogic,meson-nand.yaml Signed-off-by: Liang Yang Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20220907080405.28240-5-liang.yang@amlogic.com --- .../devicetree/bindings/mtd/amlogic,meson-nand.txt | 55 ------------- .../bindings/mtd/amlogic,meson-nand.yaml | 93 ++++++++++++++++++++++ 2 files changed, 93 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt create mode 100644 Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt deleted file mode 100644 index 5d5cdfef417f..000000000000 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt +++ /dev/null @@ -1,55 +0,0 @@ -Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs - -This file documents the properties in addition to those available in -the MTD NAND bindings. - -Required properties: -- compatible : contains one of: - - "amlogic,meson-gxl-nfc" - - "amlogic,meson-axg-nfc" - -- reg : Offset and length of the register set - -- reg-names : "nfc" is the register set for NFC controller and "emmc" - is the register set for MCI controller. - -- clocks : - A list of phandle + clock-specifier pairs for the clocks listed - in clock-names. - -- clock-names: Should contain the following: - "core" - NFC module gate clock - "device" - parent clock for internal NFC - -Optional children nodes: -Children nodes represent the available nand chips. - -Other properties: -see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. - -Example demonstrate on AXG SoC: - - nand-controller@7800 { - compatible = "amlogic,meson-axg-nfc"; - reg = <0x0 0x7800 0x0 0x100>, - <0x0 0x7000 0x0 0x800>; - reg-names = "nfc", "emmc"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - - clocks = <&clkc CLKID_SD_EMMC_C>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "device"; - - pinctrl-names = "default"; - pinctrl-0 = <&nand_pins>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - nand-on-flash-bbt; - }; - }; diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml new file mode 100644 index 000000000000..28fb9a7dd70f --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs + +allOf: + - $ref: nand-controller.yaml + +maintainers: + - liang.yang@amlogic.com + +properties: + compatible: + enum: + - amlogic,meson-gxl-nfc + - amlogic,meson-axg-nfc + + reg: + maxItems: 2 + + reg-names: + items: + - const: nfc + - const: emmc + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: device + +patternProperties: + "^nand@[0-7]$": + type: object + properties: + reg: + minimum: 0 + maximum: 1 + + nand-ecc-mode: + const: hw + + nand-ecc-step-size: + const: 1024 + + nand-ecc-strength: + enum: [8, 16, 24, 30, 40, 50, 60] + description: | + The ECC configurations that can be supported are as follows. + meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60 + meson-axg-nfc 8 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + nand-controller@ffe07800 { + compatible = "amlogic,meson-axg-nfc"; + reg = <0xffe07800 0x100>, <0xffe07000 0x800>; + reg-names = "nfc", "emmc"; + interrupts = ; + clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "device"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + }; + }; + +... -- cgit v1.2.3