From 1f854536a8336c61c89ab040bbc874c75325d37c Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Thu, 31 Mar 2022 15:41:14 +0200 Subject: dmaengine: Clarify cyclic transfer residue documentation The current documentation for the residue reported in a cyclic transfer case mentions that the reported residue should be relative to the current period only. However the definition of DMA_RESIDUE_GRANULARITY_SEGMENT specifies that the residue should be updated after each period for a cyclic transfer, which is in direct contradiction. Moreover the pcm_dmaengine common code uses the residue relative to the whole cyclic buffer size, not one period. Correct the residue-related documentation to reflect this. Signed-off-by: Paul Kocialkowski Link: https://lore.kernel.org/r/20220331134114.703782-1-paul.kocialkowski@bootlin.com Signed-off-by: Vinod Koul --- Documentation/driver-api/dmaengine/provider.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index 0072c9c7efd3..d3fa80e333b1 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -457,7 +457,7 @@ supported. - Should use dma_set_residue to report it - In the case of a cyclic transfer, it should only take into - account the current period. + account the total size of the cyclic buffer. - Should return DMA_OUT_OF_ORDER if the device does not support in order completion and is completing the operation out of order. -- cgit v1.2.3 From fc44ff0ae9f2aa20b64c4e63ab4614156df80240 Mon Sep 17 00:00:00 2001 From: Ben Walker Date: Tue, 1 Mar 2022 11:25:48 -0700 Subject: dmaengine: Document dmaengine_prep_dma_memset Document this function to make clear the expected behavior of the 'value' parameter. It was intended to match the behavior of POSIX memset as laid out here: https://lore.kernel.org/dmaengine/YejrA5ZWZ3lTRO%2F1@matsya/ Signed-off-by: Ben Walker Link: https://lore.kernel.org/r/20220301182551.883474-2-benjamin.walker@intel.com Signed-off-by: Vinod Koul --- Documentation/driver-api/dmaengine/provider.rst | 6 ++++++ include/linux/dmaengine.h | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'Documentation/driver-api') diff --git a/Documentation/driver-api/dmaengine/provider.rst b/Documentation/driver-api/dmaengine/provider.rst index d3fa80e333b1..1e0f1f85d10e 100644 --- a/Documentation/driver-api/dmaengine/provider.rst +++ b/Documentation/driver-api/dmaengine/provider.rst @@ -206,6 +206,12 @@ Currently, the types available are: - The device is able to perform parity check using RAID6 P+Q algorithm against a memory buffer. +- DMA_MEMSET + + - The device is able to fill memory with the provided pattern + + - The pattern is treated as a single byte signed value. + - DMA_INTERRUPT - The device is able to trigger a dummy transfer that will diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 6db9e03afd0b..b46b88e6aa0d 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -1030,6 +1030,14 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( return chan->device->device_prep_interleaved_dma(chan, xt, flags); } +/** + * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor. + * @chan: The channel to be used for this descriptor + * @dest: Address of buffer to be set + * @value: Treated as a single byte value that fills the destination buffer + * @len: The total size of dest + * @flags: DMA engine flags + */ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( struct dma_chan *chan, dma_addr_t dest, int value, size_t len, unsigned long flags) -- cgit v1.2.3