From 22042a6e694db118cdb27e8a9ead21df046458df Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 15 Jan 2018 11:33:36 +0100 Subject: dt-bindings: iio: adc: add binding for X-Powers AXP PMICs ADC X-Powers PMICs have several ADC channels that can be used for different purposes, e.g. PMIC internal temperature, battery voltage or AC current. This is the documentation for AXP209, AXP221/223 and AXP813 ADC bindings. Signed-off-by: Quentin Schulz Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../devicetree/bindings/iio/adc/axp20x_adc.txt | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt b/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt new file mode 100644 index 000000000000..7a6313913923 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/axp20x_adc.txt @@ -0,0 +1,48 @@ +* X-Powers AXP ADC bindings + +Required properties: + - compatible: should be one of: + - "x-powers,axp209-adc", + - "x-powers,axp221-adc", + - "x-powers,axp813-adc", + - #io-channel-cells: should be 1, + +Example: + +&axp22x { + adc { + compatible = "x-powers,axp221-adc"; + #io-channel-cells = <1>; + }; +}; + +ADC channels and their indexes per variant: + +AXP209 +------ + 0 | acin_v + 1 | acin_i + 2 | vbus_v + 3 | vbus_i + 4 | pmic_temp + 5 | gpio0_v + 6 | gpio1_v + 7 | ipsout_v + 8 | batt_v + 9 | batt_chrg_i +10 | batt_dischrg_i + +AXP22x +------ + 0 | pmic_temp + 1 | batt_v + 2 | batt_chrg_i + 3 | batt_dischrg_i + +AXP813 +------ + 0 | pmic_temp + 1 | gpio0_v + 2 | batt_v + 3 | batt_chrg_i + 4 | batt_dischrg_i -- cgit v1.2.3 From a8062aa116aa6b25cbd4d1617162fa77f5414883 Mon Sep 17 00:00:00 2001 From: Crt Mori Date: Thu, 11 Jan 2018 11:20:10 +0100 Subject: dt-bindings: iio: temperature: add MLX90632 device bindings Add device tree bindings for MLX90632 IR temperature sensor. Signed-off-by: Crt Mori Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- .../bindings/iio/temperature/mlx90632.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/temperature/mlx90632.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt new file mode 100644 index 000000000000..0b05812001f8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/temperature/mlx90632.txt @@ -0,0 +1,28 @@ +* Melexis MLX90632 contactless Infra Red temperature sensor + +Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632 + +There are various applications for the Infra Red contactless temperature sensor +and MLX90632 is most suitable for consumer applications where measured object +temperature is in range between -20 to 200 degrees Celsius with relative error +of measurement below 1 degree Celsius in object temperature range for +industrial applications. Since it can operate and measure ambient temperature +in range of -20 to 85 degrees Celsius it is suitable also for outdoor use. + +Be aware that electronics surrounding the sensor can increase ambient +temperature. MLX90632 can be calibrated to reduce the housing effect via +already existing EEPROM parameters. + +Since measured object emissivity effects Infra Red energy emitted, emissivity +should be set before requesting the object temperature. + +Required properties: + - compatible: should be "melexis,mlx90632" + - reg: the I2C address of the sensor (default 0x3a) + +Example: + +mlx90632@3a { + compatible = "melexis,mlx90632"; + reg = <0x3a>; +}; -- cgit v1.2.3 From 8730e267a17a56e9aea8d8daa15da4f2fb98c8e4 Mon Sep 17 00:00:00 2001 From: Phil Reid Date: Fri, 9 Feb 2018 08:57:26 +0800 Subject: dt-bindings: ad5272: Add bindings for Analog Devices digital potentiometers Add binding documentation for Analog Devices AD5272 and AD5274 digital potentiometer devices. Signed-off-by: Phil Reid Signed-off-by: Jonathan Cameron --- .../bindings/iio/potentiometer/ad5272.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt b/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt new file mode 100644 index 000000000000..f9b2eef946aa --- /dev/null +++ b/Documentation/devicetree/bindings/iio/potentiometer/ad5272.txt @@ -0,0 +1,27 @@ +* Analog Devices AD5272 digital potentiometer + +The node for this device must be a child node of a I2C controller, hence +all mandatory properties for your controller must be specified. See directory: + + Documentation/devicetree/bindings/i2c + +for more details. + +Required properties: + - compatible: Must be one of the following, depending on the model: + adi,ad5272-020 + adi,ad5272-050 + adi,ad5272-100 + adi,ad5274-020 + adi,ad5274-100 + +Optional properties: + - reset-gpios: GPIO specification for the RESET input. This is an + active low signal to the AD5272. + +Example: +ad5272: potentiometer@2f { + reg = <0x2F>; + compatible = "adi,ad5272-020"; + reset-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From 9bfda6636edd5db9b3cdbb2df6483ceb7618ec6a Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 1 Feb 2018 22:09:25 +0300 Subject: DT: dmaengine: renesas,rcar-dmac: document R8A77980 support Renesas R-Car V3H SoC has the R-Car gen3 compatible DMA controllers. Document R-Car V3H (also known as R8A77980) SoC bindings. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 891db41e9420..2f5167da1afc 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -26,6 +26,7 @@ Required Properties: - "renesas,dmac-r8a7795" (R-Car H3) - "renesas,dmac-r8a7796" (R-Car M3-W) - "renesas,dmac-r8a77970" (R-Car V3M) + - "renesas,dmac-r8a77980" (R-Car V3H) - reg: base address and length of the registers block for the DMAC -- cgit v1.2.3 From 4760b6fa442276783aa4294e131b72fea8c5a18a Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Mon, 22 Jan 2018 06:04:09 +0100 Subject: dt-bindings: gpio: Add binding for Wii GPIO controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Nintendo Wii game console has a GPIO controller, which is used for the optical disk slot LED, buttons, poweroff, etc. This patch adds a binding for this GPIO controller. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/gpio/nintendo,hollywood-gpio.txt | 27 ++++++++++++++++++++++ .../devicetree/bindings/powerpc/nintendo/wii.txt | 9 +------- 2 files changed, 28 insertions(+), 8 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt b/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt new file mode 100644 index 000000000000..20fc72d9e61e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt @@ -0,0 +1,27 @@ +Nintendo Wii (Hollywood) GPIO controller + +Required properties: +- compatible: "nintendo,hollywood-gpio +- reg: Physical base address and length of the controller's registers. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be <2>. The first cell is the pin number and the + second cell is used to specify optional parameters: + - bit 0 specifies polarity (0 for normal, 1 for inverted). + +Optional properties: +- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- interrupts: Interrupt specifier for the controller's Broadway (PowerPC) + interrupt. +- interrupt-parent: phandle of the parent interrupt controller. + +Example: + + GPIO: gpio@d8000c0 { + #gpio-cells = <2>; + compatible = "nintendo,hollywood-gpio"; + reg = <0x0d8000c0 0x40>; + gpio-controller; + ngpios = <24>; + } diff --git a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt index 36afa322b04b..a3dc4b9fa11a 100644 --- a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt +++ b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt @@ -152,14 +152,7 @@ Nintendo Wii device tree 1.l) The General Purpose I/O (GPIO) controller node - Represents the dual access 32 GPIO controller interface. - - Required properties: - - - #gpio-cells : <2> - - compatible : should be "nintendo,hollywood-gpio" - - reg : should contain the IPC registers location and length - - gpio-controller + see Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt 1.m) The control node -- cgit v1.2.3 From 2171f4fdac060e05826f9972a19bfdb569f5dcfe Mon Sep 17 00:00:00 2001 From: Levin Du Date: Tue, 23 Jan 2018 10:10:17 +0800 Subject: arm64: dts: rockchip: add roc-rk3328-cc board The roc-rk3328-cc is a credit card size single board computer using the Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting up to 2GB 2133MHz LPDDR4 memory. It provides eMMC module socket, MicroSD Card slot, USB 2.0/3.0, Gigabit Ethernet, HDMI/CVBS, Infrared Receiver, SPDIF/I2S, and SPI/I2C/UART/PWM interfaces. The devicetree currently supports basic peripherals. Signed-off-by: Levin Du Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 267 +++++++++++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 326d24bca1a9..0f76a621015c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -50,6 +50,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; +- Firefly roc-rk3328-cc board: + Required root node properties: + - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + - ChipSPARK PopMetal-RK3288 board: Required root node properties: - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index ce2701e37d00..cf14b8679eac 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts new file mode 100644 index 000000000000..246c317f6a68 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Firefly roc-rk3328-cc"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x25>; + rx_delay = <0x11>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- cgit v1.2.3 From f51237829c8688cfc5af11ccaa1f90126870e3c6 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 10 Jan 2018 22:00:03 -0800 Subject: dt-bindings: pinctrl: Add Qualcomm SDM845 TLMM binding This adds the DeviceTree binding for the Qualcomm SDM845 TLMM block. Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 176 +++++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt new file mode 100644 index 000000000000..665aadb5ea28 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -0,0 +1,176 @@ +Qualcomm SDM845 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SDM845 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc2_clk, sdc2_cmd, sdc2_data + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + gpio, adsp_ext, agera_pll, atest_char, atest_tsens, + atest_tsens2, atest_usb1, atest_usb10, atest_usb11, + atest_usb12, atest_usb13, atest_usb2, atest_usb20, + atest_usb21, atest_usb22, atest_usb23, audio_ref, + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, + gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update, + lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator, + pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, + pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, + qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1, + qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4, + qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, + qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd, + sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0, + tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, + tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, + tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, + uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, + vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, + wlan2_adc1, + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup9_active: qup9-active { + mux { + pins = "gpio4", "gpio5"; + function = "qup9"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; -- cgit v1.2.3 From 5e195f120138a7ab8245a5e64296c16f8e48527f Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 16 Jan 2018 11:12:34 +0100 Subject: dt-bindings: power: reset: Document ocelot-reset binding Add binding documentation for the Microsemi Ocelot reset block. Cc: devicetree@vger.kernel.org Cc: linux-pm@vger.kernel.org Signed-off-by: Alexandre Belloni Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt new file mode 100644 index 000000000000..1b4213eb3473 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -0,0 +1,14 @@ +Microsemi Ocelot reset controller + +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the +SoC MIPS core. + +Required Properties: + - compatible: "mscc,ocelot-chip-reset" + +Example: + reset@1070008 { + compatible = "mscc,ocelot-chip-reset"; + reg = <0x1070008 0x4>; + }; + -- cgit v1.2.3 From 20ebbd2f89a9b2c61c4d432aa1156fc09e37f37c Mon Sep 17 00:00:00 2001 From: Bard Liao Date: Mon, 29 Jan 2018 19:15:38 +0800 Subject: ASoC: rt5665: remove rt5668 support Remove rt5668 support from rt5665 codec driver since rt5668 will not go into mass production. Signed-off-by: Bard Liao Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5665.txt | 4 ++-- sound/soc/codecs/rt5665.c | 5 ----- sound/soc/codecs/rt5665.h | 1 - 3 files changed, 2 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5665.txt b/Documentation/devicetree/bindings/sound/rt5665.txt index 419c89219681..8df170506986 100644 --- a/Documentation/devicetree/bindings/sound/rt5665.txt +++ b/Documentation/devicetree/bindings/sound/rt5665.txt @@ -1,10 +1,10 @@ -RT5665/RT5666/RT5668 audio CODEC +RT5665/RT5666 audio CODEC This device supports I2C only. Required properties: -- compatible : One of "realtek,rt5665", "realtek,rt5666" or "realtek,rt5668". +- compatible : One of "realtek,rt5665", "realtek,rt5666". - reg : The I2C address of the device. diff --git a/sound/soc/codecs/rt5665.c b/sound/soc/codecs/rt5665.c index 819df1a32dd4..6ba99f5ed3f4 100644 --- a/sound/soc/codecs/rt5665.c +++ b/sound/soc/codecs/rt5665.c @@ -4826,9 +4826,6 @@ static int rt5665_i2c_probe(struct i2c_client *i2c, case 0x0: rt5665->id = CODEC_5666; break; - case 0x6: - rt5665->id = CODEC_5668; - break; case 0x3: default: rt5665->id = CODEC_5665; @@ -4955,7 +4952,6 @@ static void rt5665_i2c_shutdown(struct i2c_client *client) static const struct of_device_id rt5665_of_match[] = { {.compatible = "realtek,rt5665"}, {.compatible = "realtek,rt5666"}, - {.compatible = "realtek,rt5668"}, {}, }; MODULE_DEVICE_TABLE(of, rt5665_of_match); @@ -4965,7 +4961,6 @@ MODULE_DEVICE_TABLE(of, rt5665_of_match); static const struct acpi_device_id rt5665_acpi_match[] = { {"10EC5665", 0,}, {"10EC5666", 0,}, - {"10EC5668", 0,}, {}, }; MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match); diff --git a/sound/soc/codecs/rt5665.h b/sound/soc/codecs/rt5665.h index b528e416b592..b0a98ca39c5b 100644 --- a/sound/soc/codecs/rt5665.h +++ b/sound/soc/codecs/rt5665.h @@ -1978,7 +1978,6 @@ enum { enum { CODEC_5665, CODEC_5666, - CODEC_5668, }; /* filter mask */ -- cgit v1.2.3 From 28fb53de064b24eed55540ddeccab517e4babca3 Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Fri, 19 Jan 2018 18:25:28 +0900 Subject: ASoC: uniphier: add DT bindings documentation for UniPhier AIO This patch adds DT binding documentation for UniPhier AIO audio subsystem. Acked-by: Rob Herring Signed-off-by: Katsuhiro Suzuki Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/uniphier,aio.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/uniphier,aio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/uniphier,aio.txt b/Documentation/devicetree/bindings/sound/uniphier,aio.txt new file mode 100644 index 000000000000..73f6c27ae4f7 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/uniphier,aio.txt @@ -0,0 +1,36 @@ +Socionext UniPhier SoC audio driver + +The Socionext UniPhier audio subsystem consists of I2S and S/PDIF blocks in +the same register space. + +Required properties: +- compatible : should be one of the following: + "socionext,uniphier-ld11-aio" + "socionext,uniphier-ld20-aio" +- reg : offset and length of the register set for the device. +- interrupts : should contain I2S or S/PDIF interrupt. +- pinctrl-names : should be "default". +- pinctrl-0 : defined I2S signal pins for an external codec chip. +- clock-names : should include following entries: + "aio" +- clocks : a list of phandle, should contain an entry for each + entry in clock-names. +- reset-names : should include following entries: + "aio" +- resets : a list of phandle, should contain an entry for each + entry in reset-names. +- #sound-dai-cells: should be 1. + +Example: + audio { + compatible = "socionext,uniphier-ld20-aio"; + reg = <0x56000000 0x80000>; + interrupts = <0 144 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aout>; + clock-names = "aio"; + clocks = <&sys_clk 40>; + reset-names = "aio"; + resets = <&sys_rst 40>; + #sound-dai-cells = <1>; + }; -- cgit v1.2.3 From 7d7b619e16d420b723d6618c60a0aaf0ba4e3666 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 2 Feb 2018 21:27:01 +0300 Subject: soc: renesas: rcar-rst: add R8A77980 support Add support for R-Car V3H (R8A77980) to the R-Car RST driver -- this driver is needed for the clock driver to work. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + drivers/soc/renesas/Kconfig | 2 +- drivers/soc/renesas/rcar-rst.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index a8014f3ab8ba..a55b88658446 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -27,6 +27,7 @@ Required properties: - "renesas,r8a7795-rst" (R-Car H3) - "renesas,r8a7796-rst" (R-Car M3-W) - "renesas,r8a77970-rst" (R-Car V3M) + - "renesas,r8a77980-rst" (R-Car V3H) - "renesas,r8a77995-rst" (R-Car D3) - reg: Address start and address range for the device. diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 09550b1da56d..6efd7bef8577 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -4,7 +4,7 @@ config SOC_RENESAS select SOC_BUS select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \ ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \ - ARCH_R8A77995 + ARCH_R8A77980 || ARCH_R8A77995 select SYSC_R8A7743 if ARCH_R8A7743 select SYSC_R8A7745 if ARCH_R8A7745 select SYSC_R8A7779 if ARCH_R8A7779 diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 3316b028f231..e2340eb9ea9c 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -42,6 +42,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen2 }, + { .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen2 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen2 }, { /* sentinel */ } }; -- cgit v1.2.3 From f15092f8482b63b91d7ca7f4bd7090da7f9f2f24 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 31 Jan 2018 22:56:47 +0300 Subject: dt-bindings: arm: document R8A77980 SoC bindings Document the R-Car V3H (R8A77980) SoC device tree bindings. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 5c3af7ef0761..3ccad353acfa 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -41,6 +41,8 @@ SoCs: compatible = "renesas,r8a7796" - R-Car V3M (R8A77970) compatible = "renesas,r8a77970" + - R-Car V3H (R8A77980) + compatible = "renesas,r8a77980" - R-Car D3 (R8A77995) compatible = "renesas,r8a77995" -- cgit v1.2.3 From dd5bdb797f0a6e0d3d2aa86af60f92b094705d24 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 25 Dec 2017 17:36:00 +0100 Subject: clk: rockchip: document hdmi_phy external input for rk3328 The hdmi-phy block inside the soc also loops its pll output back into the clock controller, so document that already used input clock. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt index e71c675ba5da..904ae682ea90 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt @@ -32,6 +32,7 @@ clock-output-names: - "clkin_i2s" - external I2S clock - optional, - "gmac_clkin" - external GMAC clock - optional - "phy_50m_out" - output clock of the pll in the mac phy + - "hdmi_phy" - output clock of the hdmi phy pll - optional Example: Clock controller node: -- cgit v1.2.3 From edc4e74d96982ef9304dc7239a294e3e0ac2144a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Dec 2017 15:38:12 +0100 Subject: dt-bindings: pinctrl: sh-pfc: Correct SoC family name for R8A7778 R8A7778 is R-Car (not R-Mobile) M1. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman --- Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index bb1790e0b176..dd64dbb4cb0e 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -15,7 +15,7 @@ Required Properties: - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. + - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. -- cgit v1.2.3 From 7353c54620732797dcc3b4b1fc6f3cc0c0d9b6ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 30 Jan 2018 22:18:16 +0100 Subject: soc: samsung: pmu: Populate children syscon nodes The syscon poweroff and restart nodes logically belong to the Power Management Unit so populate possible children. This also requires providing compatibles for Exynos5410 and Exynos7 so the PMU device and its children will be instantiated for them as well. Just like Exynos5433, these chipsets are not yet supported by the PMU driver. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Tested-by: Marek Szyprowski --- Documentation/devicetree/bindings/arm/samsung/pmu.txt | 6 ++++++ drivers/soc/samsung/exynos-pmu.c | 7 +++++++ 2 files changed, 13 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt index 779f5614bcee..16685787d2bd 100644 --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt @@ -43,6 +43,12 @@ following properties: - interrupt-parent: a phandle indicating which interrupt controller this PMU signals interrupts to. + +Optional nodes: + +- nodes defining the restart and poweroff syscon children + + Example : pmu_system_controller: system-controller@10040000 { compatible = "samsung,exynos5250-pmu", "syscon"; diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index f56adbd9fb8b..d34ca201b8b7 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -84,11 +84,15 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos5250-pmu", .data = exynos_pmu_data_arm_ptr(exynos5250_pmu_data), + }, { + .compatible = "samsung,exynos5410-pmu", }, { .compatible = "samsung,exynos5420-pmu", .data = exynos_pmu_data_arm_ptr(exynos5420_pmu_data), }, { .compatible = "samsung,exynos5433-pmu", + }, { + .compatible = "samsung,exynos7-pmu", }, { /*sentinel*/ }, }; @@ -126,6 +130,9 @@ static int exynos_pmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmu_context); + if (devm_of_platform_populate(dev)) + dev_err(dev, "Error populating children, reboot and poweroff might not work properly\n"); + dev_dbg(dev, "Exynos PMU Driver probe done\n"); return 0; } -- cgit v1.2.3 From bd010d6066ba3267909bf8a318e0d2f2eaf3fb53 Mon Sep 17 00:00:00 2001 From: Simon Shields Date: Thu, 8 Feb 2018 11:01:34 +1100 Subject: dt-bindings: samsung: Document bindings for Midas family boards Document GT-I9300, GT-I9305, GT-N7100, and GT-N7105 bindings, along with the shared "midas" binding. Signed-off-by: Simon Shields Reviewed-by: Rob Herring Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 469ac98ecf8f..14510b215480 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -9,7 +9,11 @@ Required root node properties: - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. - "samsung,trats" - for Exynos4210-based Tizen Reference board. - "samsung,universal_c210" - for Exynos4210-based Samsung board. + - "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board. + - "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board. + - "samsung,midas" - for Exynos4412-based Samsung Midas board. - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. + - "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board. - "samsung,trats2" - for Exynos4412-based Tizen Reference board. - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. - "samsung,xyref5260" - for Exynos5260-based Samsung board. -- cgit v1.2.3 From e2ce852a7464fe3caaf72f9f3da87d2bfcf3eb84 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Mon, 12 Feb 2018 17:15:32 +0100 Subject: ASoC: samsung: i2s: Update clock-output-names property documentation The clock-output-names property is marked as deprecated. While at it, and few typos are fixed. Signed-off-by: Sylwester Nawrocki Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/samsung-i2s.txt | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index bf100cd0d0f7..c1f508f18ac8 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt @@ -7,7 +7,7 @@ Required SoC Specific Properties: - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with secondary fifo, s/w reset control and internal mux for root clk src. - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for - playback, sterio channel capture, secondary fifo using internal + playback, stereo channel capture, secondary fifo using internal or external dma, s/w reset control, internal mux for root clk src and 7.1 channel TDM support for playback. TDM (Time division multiplexing) is to allow transfer of multiple channel audio data on single data line. @@ -25,7 +25,7 @@ Required SoC Specific Properties: These strings correspond 1:1 with the ordered pairs in dmas. - clocks: Handle to iis clock and RCLK source clk. - clock-names: - i2s0 uses some base clks from CMU and some are from audio subsystem internal + i2s0 uses some base clocks from CMU and some are from audio subsystem internal clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and "i2s_opclk1" as shown in the example below. i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should @@ -36,9 +36,9 @@ Required SoC Specific Properties: - #clock-cells: should be 1, this property must be present if the I2S device is a clock provider in terms of the common clock bindings, described in ../clock/clock-bindings.txt. -- clock-output-names: from the common clock bindings, names of the CDCLK - I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1", - "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively. +- clock-output-names (deprecated): from the common clock bindings, names of + the CDCLK I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1", + "i2s_cdclk3" for the I2S0, I2S1, I2S2 devices respectively. There are following clocks available at the I2S device nodes: CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock, @@ -49,9 +49,10 @@ There are following clocks available at the I2S device nodes: Refer to the SoC datasheet for availability of the above clocks. The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available -in the IIS Multi Audio Interface (I2S0). -Note: Old DTs may not have the #clock-cells, clock-output-names properties -and then not use the I2S node as a clock supplier. +in the IIS Multi Audio Interface. + +Note: Old DTs may not have the #clock-cells property and then not use the I2S +node as a clock supplier. Optional SoC Specific Properties: @@ -74,8 +75,7 @@ i2s0: i2s@3830000 { <&clock_audss EXYNOS_I2S_BUS>, <&clock_audss EXYNOS_SCLK_I2S>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; - #clock-cells; - clock-output-names = "i2s_cdclk0"; + #clock-cells = <1>; samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; -- cgit v1.2.3 From 3a3ac1ea898399f14748a358dd33262c97a9a86b Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Mon, 12 Feb 2018 17:15:36 +0100 Subject: ASoC: samsung,tm2-audio DT binding documentation update This patch documents additional entries of the audio-codec and i2s-controller properties required for the HDMI audio support. Signed-off-by: Sylwester Nawrocki Reviewed-by: Rob Herring Acked-by: Krzysztof Kozlowski Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/samsung,tm2-audio.txt | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt index 94442e5673b3..f5ccc12ddc00 100644 --- a/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt +++ b/Documentation/devicetree/bindings/sound/samsung,tm2-audio.txt @@ -4,9 +4,13 @@ Required properties: - compatible : "samsung,tm2-audio" - model : the user-visible name of this sound complex - - audio-codec : the phandle of the wm5110 audio codec node, - as described in ../mfd/arizona.txt - - i2s-controller : the phandle of the I2S controller + - audio-codec : the first entry should be phandle of the wm5110 audio + codec node, as described in ../mfd/arizona.txt; + the second entry should be phandle of the HDMI + transmitter node + - i2s-controller : the list of phandle and argument tuples pointing to + I2S controllers, the first entry should be I2S0 and + the second one I2S1 - audio-amplifier : the phandle of the MAX98504 amplifier - samsung,audio-routing : a list of the connections between audio components; each entry is a pair of strings, the first being the @@ -22,8 +26,8 @@ Example: sound { compatible = "samsung,tm2-audio"; - audio-codec = <&wm5110>; - i2s-controller = <&i2s0>; + audio-codec = <&wm5110>, <&hdmi>; + i2s-controller = <&i2s0 0>, <&i2s1 0>; audio-amplifier = <&max98504>; mic-bias-gpios = <&gpr3 2 0>; model = "wm5110"; -- cgit v1.2.3 From 3f0c43e60d19e1c126ddad47c77a5e1036e52378 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Mon, 12 Feb 2018 17:15:38 +0100 Subject: ASoC: samsung: Add missing #sound-dai-cells property documentation The #sound-dai-cells property might be helpful in selecting primary or secondary CPU DAI and it's already present in i2s nodes for some exynos SoCs so let's add it to the DT binding documentation. Signed-off-by: Sylwester Nawrocki Acked-by: Krzysztof Kozlowski Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/samsung-i2s.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index c1f508f18ac8..a88cb00fa096 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt @@ -60,6 +60,7 @@ Optional SoC Specific Properties: sub system(used in secondary sound source). - pinctrl-0: Should specify pin control groups used for this controller. - pinctrl-names: Should contain only one value - "default". +- #sound-dai-cells: should be 1. Example: @@ -79,4 +80,5 @@ i2s0: i2s@3830000 { samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + #sound-dai-cells = <1>; }; -- cgit v1.2.3 From 77a060533c0468069d0b4a5d1968a42259763f08 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 12 Feb 2018 13:45:32 +0100 Subject: spi: spi-gpio: Augment device tree bindings After we augmented the core to handle "gpio-sck"/"sck-gpios", "gpio-mosi"/"mosi-gpios", "gpio-miso"/"miso-gpios" alike, deprecate the old binding and put the strict modern and recommended binding practice into place as the default for GPIO-based SPI. This reflects the similar change in I2C: commit 7d29f509d2cf ("dt-bindings: i2c: i2c-gpio: Add support for named gpios") Signed-off-by: Linus Walleij Reviewed-by: Andy Shevchenko Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-gpio.txt | 24 ++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt index a95603bcf6ff..52db562f17a4 100644 --- a/Documentation/devicetree/bindings/spi/spi-gpio.txt +++ b/Documentation/devicetree/bindings/spi/spi-gpio.txt @@ -1,18 +1,30 @@ SPI-GPIO devicetree bindings +This represents a group of 3-n GPIO lines used for bit-banged SPI on dedicated +GPIO lines. + Required properties: - compatible: should be set to "spi-gpio" - #address-cells: should be set to <0x1> - ranges - - gpio-sck: GPIO spec for the SCK line to use - - gpio-miso: GPIO spec for the MISO line to use - - gpio-mosi: GPIO spec for the MOSI line to use + - sck-gpios: GPIO spec for the SCK line to use + - miso-gpios: GPIO spec for the MISO line to use + - mosi-gpios: GPIO spec for the MOSI line to use - cs-gpios: GPIOs to use for chipselect lines. Not needed if num-chipselects = <0>. - num-chipselects: Number of chipselect lines. Should be <0> if a single device with no chip select is connected. +Deprecated bindings: + +These legacy GPIO line bindings can alternatively be used to define the +GPIO lines used, they should not be used in new device trees. + + - gpio-sck: GPIO spec for the SCK line to use + - gpio-miso: GPIO spec for the MISO line to use + - gpio-mosi: GPIO spec for the MOSI line to use + Example: spi { @@ -20,9 +32,9 @@ Example: #address-cells = <0x1>; ranges; - gpio-sck = <&gpio 95 0>; - gpio-miso = <&gpio 98 0>; - gpio-mosi = <&gpio 97 0>; + sck-gpios = <&gpio 95 0>; + miso-gpios = <&gpio 98 0>; + mosi-gpios = <&gpio 97 0>; cs-gpios = <&gpio 125 0>; num-chipselects = <1>; -- cgit v1.2.3 From 4b75291621830acad2c66a1d21d7840a7ca169d3 Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Tue, 13 Feb 2018 14:43:08 +0000 Subject: regulator: dt: regulator-name is required property These two drivers fail to probe if no name is provided. For details see: https://www.spinics.net/lists/kernel/msg2457515.html Signed-off-by: Harald Geyer Acked-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/regulator/fixed-regulator.txt | 1 + Documentation/devicetree/bindings/regulator/gpio-regulator.txt | 2 ++ 2 files changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt index 4fae41d54798..0c2a6c8a1536 100644 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt @@ -2,6 +2,7 @@ Fixed Voltage regulators Required properties: - compatible: Must be "regulator-fixed"; +- regulator-name: Defined in regulator.txt as optional, but required here. Optional properties: - gpio: gpio to use for enable control diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt index dd1ed789728e..1f496159e2bb 100644 --- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt @@ -2,6 +2,8 @@ GPIO controlled regulators Required properties: - compatible : Must be "regulator-gpio". +- regulator-name : Defined in regulator.txt as optional, but required + here. - states : Selection of available voltages and GPIO configs. if there are no states, then use a fixed regulator -- cgit v1.2.3 From 0e47079b6cd7d26e2dab95398927b1184a9a733c Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Wed, 14 Feb 2018 17:07:12 +0100 Subject: net: phy: dp83867: Add documentation for CLK_OUT pin muxing Add documentation of ti,clk-output-sel which can be used to select a specific clock for CLK_OUT. Signed-off-by: Wadim Egorov Signed-off-by: Daniel Schultz Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/ti,dp83867.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index 02c4353b5cf2..9ef9338aaee1 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -25,6 +25,8 @@ Optional property: software needs to take when this pin is strapped in these modes. See data manual for details. + - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h + for applicable values. Note: ti,min-output-impedance and ti,max-output-impedance are mutually exclusive. When both properties are present ti,max-output-impedance -- cgit v1.2.3 From 17e2304f0ad31d3f9bba4285b7024bf3c3626600 Mon Sep 17 00:00:00 2001 From: Cosmin-Gabriel Samoila Date: Wed, 14 Feb 2018 15:21:07 +0200 Subject: ASoC: ak4458: Add bindings for AK4458 DAC Document the bindings for AK4458 DAC Signed-off-by: Cosmin-Gabriel Samoila Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/ak4458.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ak4458.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ak4458.txt b/Documentation/devicetree/bindings/sound/ak4458.txt new file mode 100644 index 000000000000..7839be78448d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak4458.txt @@ -0,0 +1,23 @@ +AK4458 audio DAC + +This device supports I2C mode. + +Required properties: + +- compatible : "asahi-kasei,ak4458" +- reg : The I2C address of the device for I2C + +Optional properties: +- reset-gpios: A GPIO specifier for the power down & reset pin +- mute-gpios: A GPIO specifier for the soft mute pin + +Example: + +&i2c { + ak4458: dac@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW> + mute-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH> + }; +}; -- cgit v1.2.3 From af0424e44c180d66c2ddfb0a99c52382de8f69f8 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Tue, 13 Feb 2018 16:29:34 +0200 Subject: ASoC: ak5558: Add bindings for AK5558 ADC Document the bindings for AK5558 ADC. Reviewed-by: Rob Herring Signed-off-by: Daniel Baluta Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/ak5558.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/ak5558.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/ak5558.txt b/Documentation/devicetree/bindings/sound/ak5558.txt new file mode 100644 index 000000000000..7d67ca6ced80 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ak5558.txt @@ -0,0 +1,22 @@ +AK5558 8 channel differential 32-bit delta-sigma ADC + +This device supports I2C mode only. + +Required properties: + +- compatible : "asahi-kasei,ak5558" +- reg : The I2C address of the device. + +Optional properties: + +- reset-gpios: A GPIO specifier for the power down & reset pin. + +Example: + +&i2c { + ak5558: adc@10 { + compatible = "asahi-kasei,ak5558"; + reg = <0x10>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; +}; -- cgit v1.2.3 From 1bdd335fa6a8ce27ee9bfe1e0c7a45fc0588156e Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 16 Feb 2018 18:05:44 +0100 Subject: dt-bindings: pinctrl: Add st,stm32f769-pinctrl compatible to stm32-pinctrl Add new compatible for stm32f769 MCU. Signed-off-by: Alexandre Torgue Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 2c46f30b62c5..9a06e1fdbc42 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -11,6 +11,7 @@ Required properies: "st,stm32f429-pinctrl" "st,stm32f469-pinctrl" "st,stm32f746-pinctrl" + "st,stm32f769-pinctrl" "st,stm32h743-pinctrl" "st,stm32mp157-pinctrl" "st,stm32mp157-z-pinctrl" -- cgit v1.2.3 From e493621390f9be06b51afe99d982cbd2b2eb81b1 Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Tue, 30 Jan 2018 13:39:28 +0100 Subject: dt-bindings: add RK3368-uQ7 SoM and EVK base board RK3368-uQ7 is a Qseven compatible system-on-module by Theobroma Systems. This adds the module and the EVK baseboard "Haikou" Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 0f76a621015c..9a3e98356b1e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -189,6 +189,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; +- Theobroma Systems RK3368-uQ7 Haikou Baseboard: + Required root node properties: + - compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368"; + - Theobroma Systems RK3399-Q7 Haikou Baseboard: Required root node properties: - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399"; -- cgit v1.2.3 From 05c9b302eda71083840392d74ce62dd1e1f30621 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 16 Feb 2018 09:53:12 -0800 Subject: ASoC: dmic: Add optional wakeup delay On some systems a delay is needed after switching on the clocks, to allow the output to stabilize and avoid a popping noise at the beginning of the recording. Add the optional device tree property 'wakeup-delay-ms' and apply the specified delay after enabling the mic. A blocking delay can't be applied in dmic_daiops_trigger() since the function is called in atomic context. Instead use a DAPM event handler to set the enable GPIO and apply the delay in the handler. Signed-off-by: Matthias Kaehlcke Reviewed-by: Peter Ujfalusi Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/dmic.txt | 2 + sound/soc/codecs/dmic.c | 63 +++++++++++++----------- 2 files changed, 37 insertions(+), 28 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/dmic.txt b/Documentation/devicetree/bindings/sound/dmic.txt index f7bf65611453..e957b4136716 100644 --- a/Documentation/devicetree/bindings/sound/dmic.txt +++ b/Documentation/devicetree/bindings/sound/dmic.txt @@ -8,6 +8,7 @@ Required properties: Optional properties: - dmicen-gpios: GPIO specifier for dmic to control start and stop - num-channels: Number of microphones on this DAI + - wakeup-delay-ms: Delay (in ms) after enabling the DMIC Example node: @@ -15,4 +16,5 @@ Example node: compatible = "dmic-codec"; dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; num-channels = <1>; + wakeup-delay-ms <50>; }; diff --git a/sound/soc/codecs/dmic.c b/sound/soc/codecs/dmic.c index 32a8f71d51f1..bac5bbb2dd59 100644 --- a/sound/soc/codecs/dmic.c +++ b/sound/soc/codecs/dmic.c @@ -19,6 +19,7 @@ * */ +#include #include #include #include @@ -29,34 +30,33 @@ #include #include -static int dmic_daiops_trigger(struct snd_pcm_substream *substream, - int cmd, struct snd_soc_dai *dai) -{ - struct gpio_desc *dmic_en = snd_soc_dai_get_drvdata(dai); +struct dmic { + struct gpio_desc *gpio_en; + int wakeup_delay; +}; - if (!dmic_en) - return 0; +static int dmic_aif_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) { + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct dmic *dmic = snd_soc_codec_get_drvdata(codec); - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - gpiod_set_value(dmic_en, 1); + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (dmic->gpio_en) + gpiod_set_value(dmic->gpio_en, 1); + + if (dmic->wakeup_delay) + msleep(dmic->wakeup_delay); break; - case SNDRV_PCM_TRIGGER_STOP: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - gpiod_set_value(dmic_en, 0); + case SND_SOC_DAPM_POST_PMD: + if (dmic->gpio_en) + gpiod_set_value(dmic->gpio_en, 0); break; } return 0; } -static const struct snd_soc_dai_ops dmic_dai_ops = { - .trigger = dmic_daiops_trigger, -}; - static struct snd_soc_dai_driver dmic_dai = { .name = "dmic-hifi", .capture = { @@ -68,26 +68,33 @@ static struct snd_soc_dai_driver dmic_dai = { | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE, }, - .ops = &dmic_dai_ops, }; static int dmic_component_probe(struct snd_soc_component *component) { - struct gpio_desc *dmic_en; + struct dmic *dmic; + + dmic = devm_kzalloc(component->dev, sizeof(*dmic), GFP_KERNEL); + if (!dmic) + return -ENOMEM; + + dmic->gpio_en = devm_gpiod_get_optional(component->dev, + "dmicen", GPIOD_OUT_LOW); + if (IS_ERR(dmic->gpio_en)) + return PTR_ERR(dmic->gpio_en); - dmic_en = devm_gpiod_get_optional(component->dev, - "dmicen", GPIOD_OUT_LOW); - if (IS_ERR(dmic_en)) - return PTR_ERR(dmic_en); + device_property_read_u32(component->dev, "wakeup-delay-ms", + &dmic->wakeup_delay); - snd_soc_component_set_drvdata(component, dmic_en); + snd_soc_component_set_drvdata(component, dmic); return 0; } static const struct snd_soc_dapm_widget dmic_dapm_widgets[] = { - SND_SOC_DAPM_AIF_OUT("DMIC AIF", "Capture", 0, - SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT_E("DMIC AIF", "Capture", 0, + SND_SOC_NOPM, 0, 0, dmic_aif_event, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_INPUT("DMic"), }; -- cgit v1.2.3 From 41d6d8bd8ae94ca9ee53720cd530168aca557db7 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 16 Feb 2018 21:28:02 +0300 Subject: soc: renesas: rcar-sysc: add R8A77980 support Add support for R-Car V3H (R8A77980) SoC power areas to the R-Car SYSC driver. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../bindings/power/renesas,rcar-sysc.txt | 1 + drivers/soc/renesas/Kconfig | 5 +++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a77980-sysc.c | 52 ++++++++++++++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 ++ drivers/soc/renesas/rcar-sysc.h | 1 + 6 files changed, 63 insertions(+) create mode 100644 drivers/soc/renesas/r8a77980-sysc.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 8690f10426a3..6284a9550b3c 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -18,6 +18,7 @@ Required properties: - "renesas,r8a7795-sysc" (R-Car H3) - "renesas,r8a7796-sysc" (R-Car M3-W) - "renesas,r8a77970-sysc" (R-Car V3M) + - "renesas,r8a77980-sysc" (R-Car V3H) - "renesas,r8a77995-sysc" (R-Car D3) - reg: Address start and address range for the device. - #power-domain-cells: Must be 1. diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 6efd7bef8577..6caa393e3a2d 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -15,6 +15,7 @@ config SOC_RENESAS select SYSC_R8A7795 if ARCH_R8A7795 select SYSC_R8A7796 if ARCH_R8A7796 select SYSC_R8A77970 if ARCH_R8A77970 + select SYSC_R8A77980 if ARCH_R8A77980 select SYSC_R8A77995 if ARCH_R8A77995 if SOC_RENESAS @@ -60,6 +61,10 @@ config SYSC_R8A77970 bool "R-Car V3M System Controller support" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A77980 + bool "R-Car V3H System Controller support" if COMPILE_TEST + select SYSC_RCAR + config SYSC_R8A77995 bool "R-Car D3 System Controller support" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 845d62a08ce1..d3b7bb3284c0 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o +obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o # Family diff --git a/drivers/soc/renesas/r8a77980-sysc.c b/drivers/soc/renesas/r8a77980-sysc.c new file mode 100644 index 000000000000..9265fb525ef3 --- /dev/null +++ b/drivers/soc/renesas/r8a77980-sysc.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car V3H System Controller + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +#include +#include + +#include + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a77980_areas[] __initconst = { + { "always-on", 0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca53-scu", 0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON, + PD_SCU }, + { "ca53-cpu0", 0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu1", 0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu2", 0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "ca53-cpu3", 0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU, + PD_CPU_NOCR }, + { "cr7", 0x240, 0, R8A77980_PD_CR7, R8A77980_PD_ALWAYS_ON }, + { "a3ir", 0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON }, + { "a2ir0", 0x400, 0, R8A77980_PD_A2IR0, R8A77980_PD_A3IR }, + { "a2ir1", 0x400, 1, R8A77980_PD_A2IR1, R8A77980_PD_A3IR }, + { "a2ir2", 0x400, 2, R8A77980_PD_A2IR2, R8A77980_PD_A3IR }, + { "a2ir3", 0x400, 3, R8A77980_PD_A2IR3, R8A77980_PD_A3IR }, + { "a2ir4", 0x400, 4, R8A77980_PD_A2IR4, R8A77980_PD_A3IR }, + { "a2ir5", 0x400, 5, R8A77980_PD_A2IR5, R8A77980_PD_A3IR }, + { "a2sc0", 0x400, 6, R8A77980_PD_A2SC0, R8A77980_PD_A3IR }, + { "a2sc1", 0x400, 7, R8A77980_PD_A2SC1, R8A77980_PD_A3IR }, + { "a2sc2", 0x400, 8, R8A77980_PD_A2SC2, R8A77980_PD_A3IR }, + { "a2sc3", 0x400, 9, R8A77980_PD_A2SC3, R8A77980_PD_A3IR }, + { "a2sc4", 0x400, 10, R8A77980_PD_A2SC4, R8A77980_PD_A3IR }, + { "a2pd0", 0x400, 11, R8A77980_PD_A2PD0, R8A77980_PD_A3IR }, + { "a2pd1", 0x400, 12, R8A77980_PD_A2PD1, R8A77980_PD_A3IR }, + { "a2cn", 0x400, 13, R8A77980_PD_A2CN, R8A77980_PD_A3IR }, + { "a3vip", 0x2c0, 0, R8A77980_PD_A3VIP, R8A77980_PD_ALWAYS_ON }, + { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1, R8A77980_PD_A3VIP }, + { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2, R8A77980_PD_A3VIP }, +}; + +const struct rcar_sysc_info r8a77980_sysc_info __initconst = { + .areas = r8a77980_areas, + .num_areas = ARRAY_SIZE(r8a77980_areas), +}; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 636872bc2416..72b0f4a9ad4e 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -287,6 +287,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = { #ifdef CONFIG_SYSC_R8A77970 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info }, #endif +#ifdef CONFIG_SYSC_R8A77980 + { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info }, +#endif #ifdef CONFIG_SYSC_R8A77995 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info }, #endif diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h index 9d9daf9eb91b..974b18619c08 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h @@ -59,6 +59,7 @@ extern const struct rcar_sysc_info r8a7794_sysc_info; extern const struct rcar_sysc_info r8a7795_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info; extern const struct rcar_sysc_info r8a77970_sysc_info; +extern const struct rcar_sysc_info r8a77980_sysc_info; extern const struct rcar_sysc_info r8a77995_sysc_info; -- cgit v1.2.3 From 8dc09f400a08108984c0bacc4af5cb395a3c5c22 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 2 Feb 2018 21:45:08 +0300 Subject: dt-bindings: arm: document Condor board bindings Document the Condor device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the Condor board. Signed-off-by: Sergei Shtylyov Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 3ccad353acfa..41d3920aaa5e 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -59,6 +59,8 @@ Boards: compatible = "renesas,blanche", "renesas,r8a7792" - BOCK-W compatible = "renesas,bockw", "renesas,r8a7778" + - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01) + compatible = "renesas,condor", "renesas,r8a77980" - Draak (RTP0RC77995SEB0010S) compatible = "renesas,draak", "renesas,r8a77995" - Eagle (RTP0RC77970SEB0010S) -- cgit v1.2.3 From 584fc22ceeda11d5ac40b1659d4708314d3d2675 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Feb 2018 11:02:28 +0100 Subject: dt-bindings: arm: Document Renesas H2-based Stout DT bindings Document the Renesas H2 Stout (ADAS Starterkit) device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the Stout board. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 41d3920aaa5e..98916b3864c2 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -116,6 +116,8 @@ Boards: compatible = "renesas,sk-rzg1e", "renesas,r8a7745" - SK-RZG1M (YR8A77430S000BE) compatible = "renesas,sk-rzg1m", "renesas,r8a7743" + - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) + compatible = "renesas,stout", "renesas,r8a7790" - V3MSK compatible = "renesas,v3msk", "renesas,r8a77970" - Wheat -- cgit v1.2.3 From c0b11cc56c11df42616d9df45da7a140a2162d08 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 13 Feb 2018 10:45:48 +0100 Subject: dt-bindings: arm: Document R-Car M3-N SoC DT bindings Add device tree bindings documentation for Renesas R-Car M3-N (r8a77965) SoC. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 98916b3864c2..63edc11e83ef 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -39,6 +39,8 @@ SoCs: compatible = "renesas,r8a7795" - R-Car M3-W (R8A77960) compatible = "renesas,r8a7796" + - R-Car M3-N (R8A77965) + compatible = "renesas,r8a77965" - R-Car V3M (R8A77970) compatible = "renesas,r8a77970" - R-Car V3H (R8A77980) -- cgit v1.2.3 From 8d6b18a2a2ccbbb3dd53122dae1437fbe588a114 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 17 Jan 2018 16:46:52 +0800 Subject: dt-bindings: ARM: sunxi: Document A80 SoC secure SRAM usage by SMP hotplug On the Allwinner A80 SoC the BROM supports hotplugging the primary core (cpu0) by checking two 32bit values at a specific location within the secure SRAM block. This region needs to be reserved and accessible to the SMP code. Document its usage. Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Chen-Yu Tsai --- .../devicetree/bindings/arm/sunxi/smp-sram.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt new file mode 100644 index 000000000000..082e6a9382d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt @@ -0,0 +1,44 @@ +Allwinner SRAM for smp bringup: +------------------------------------------------ + +Allwinner's A80 SoC uses part of the secure sram for hotplugging of the +primary core (cpu0). Once the core gets powered up it checks if a magic +value is set at a specific location. If it is then the BROM will jump +to the software entry address, instead of executing a standard boot. + +Therefore a reserved section sub-node has to be added to the mmio-sram +declaration. + +Note that this is separate from the Allwinner SRAM controller found in +../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to +any device. + +Also there are no "secure-only" properties. The implementation should +check if this SRAM is usable first. + +Required sub-node properties: +- compatible : depending on the SoC this should be one of: + "allwinner,sun9i-a80-smp-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in ../../misc/sram.txt + +Example: + + sram_b: sram@20000 { + /* 256 KiB secure SRAM at 0x20000 */ + compatible = "mmio-sram"; + reg = <0x00020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00020000 0x40000>; + + smp-sram@1000 { + /* + * This is checked by BROM to determine if + * cpu0 should jump to SMP entry vector + */ + compatible = "allwinner,sun9i-a80-smp-sram"; + reg = <0x1000 0x8>; + }; + }; -- cgit v1.2.3 From 0626d183479480c878c15157a38d6dd962c1dae6 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 Feb 2018 09:04:46 +0100 Subject: arm64: dts: rockchip: add a standalone version of the rk3399 sapphire While the sapphire board is a system-on-module and mostly used with the excavator baseboard, it is also possible to use it standalone without any base. So add a board-variant for this type. Signed-off-by: Heiko Stuebner Tested-by: Vicente Bergas Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts | 12 ++++++++++++ 3 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 9a3e98356b1e..1c1d62d03c4f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -185,6 +185,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; +- Rockchip RK3399 Sapphire board standalone: + Required root node properties: + - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; + - Rockchip RK3399 Sapphire Excavator board: Required root node properties: - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1e57f87f30c4..48a83f882947 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -12,4 +12,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts new file mode 100644 index 000000000000..5a58060447cf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3399-sapphire.dtsi" + +/ { + model = "Sapphire-RK3399 Board"; + compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; +}; -- cgit v1.2.3 From 01182d6529ae499bb73129f4766b45c2ae8e700b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Feb 2018 14:45:57 +0100 Subject: ASoC: Add DT bindings documentation for max9759 amplifier This patch adds DT bindings documentation for Maxim MAX9759 speaker amplifier. Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/maxim,max9759.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/maxim,max9759.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/maxim,max9759.txt b/Documentation/devicetree/bindings/sound/maxim,max9759.txt new file mode 100644 index 000000000000..737a996374d3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/maxim,max9759.txt @@ -0,0 +1,18 @@ +Maxim MAX9759 Speaker Amplifier +=============================== + +Required properties: +- compatible : "maxim,max9759" +- shutdown-gpios : the gpio connected to the shutdown pin +- mute-gpios : the gpio connected to the mute pin +- gain-gpios : the 2 gpios connected to the g1 and g2 pins + +Example: + +max9759: analog-amplifier { + compatible = "maxim,max9759"; + shutdown-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + mute-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + gain-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>, + <&gpio3 25 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From ce15783c510a9905545e7708345454c38b725dd8 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 15 Feb 2018 14:58:45 +0300 Subject: clk: renesas: cpg-mssr: add R8A77980 support Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Rob Herring Reviewed-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 5 +- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a77980-cpg-mssr.c | 227 +++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + 6 files changed, 243 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/renesas/r8a77980-cpg-mssr.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index f1890d0777a6..bc4ea0868dbc 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -23,6 +23,7 @@ Required Properties: - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) + - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) - reg: Base address and length of the memory resource used by the CPG/MSSR @@ -32,8 +33,8 @@ Required Properties: clock-names - clock-names: List of external parent clock names. Valid names are: - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, - r8a7795, r8a7796, r8a77970, r8a77995) - - "extalr" (r8a7795, r8a7796, r8a77970) + r8a7795, r8a7796, r8a77970, r8a77980, r8a77995) + - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980) - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794) - #clock-cells: Must be 2 diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 84b40b95ca0e..43bab4f9c4e2 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -16,6 +16,7 @@ config CLK_RENESAS select CLK_R8A7795 if ARCH_R8A7795 select CLK_R8A7796 if ARCH_R8A7796 select CLK_R8A77970 if ARCH_R8A77970 + select CLK_R8A77980 if ARCH_R8A77980 select CLK_R8A77995 if ARCH_R8A77995 select CLK_SH73A0 if ARCH_SH73A0 @@ -101,6 +102,10 @@ config CLK_R8A77970 bool "R-Car V3M clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG +config CLK_R8A77980 + bool "R-Car V3H clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A77995 bool "R-Car D3 clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 34c4e0b37afa..e20fa195d107 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c new file mode 100644 index 000000000000..7aaae73a321a --- /dev/null +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a77980 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + */ + +#include +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77980_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL1, + CLK_PLL2, + CLK_PLL3, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + + /* Core Clock Outputs */ + DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1), + DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074), + + DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1), + + DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014), +}; + +static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { + DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6), + DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6), + DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6), + DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6), + DEF_MOD("tmu0", 125, R8A77980_CLK_CP), + DEF_MOD("scif4", 203, R8A77980_CLK_S3D4), + DEF_MOD("scif3", 204, R8A77980_CLK_S3D4), + DEF_MOD("scif1", 206, R8A77980_CLK_S3D4), + DEF_MOD("scif0", 207, R8A77980_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A77980_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77980_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77980_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77980_CLK_MSO), + DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3), + DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4), + DEF_MOD("sdif", 314, R8A77980_CLK_SD0), + DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1), + DEF_MOD("intc-ex", 407, R8A77980_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3), + DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1), + DEF_MOD("imp4", 521, R8A77980_CLK_S1D1), + DEF_MOD("thermal", 522, R8A77980_CLK_CP), + DEF_MOD("pwm", 523, R8A77980_CLK_S0D12), + DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1), + DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1), + DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1), + DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1), + DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1), + DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1), + DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1), + DEF_MOD("csi41", 715, R8A77980_CLK_CSI0), + DEF_MOD("csi40", 716, R8A77980_CLK_CSI0), + DEF_MOD("du0", 724, R8A77980_CLK_S2D1), + DEF_MOD("lvds", 727, R8A77980_CLK_S2D1), + DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2), + DEF_MOD("gether", 813, R8A77980_CLK_S3D2), + DEF_MOD("imp3", 824, R8A77980_CLK_S1D1), + DEF_MOD("imp2", 825, R8A77980_CLK_S1D1), + DEF_MOD("imp1", 826, R8A77980_CLK_S1D1), + DEF_MOD("imp0", 827, R8A77980_CLK_S1D1), + DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1), + DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1), + DEF_MOD("impram", 830, R8A77980_CLK_S1D1), + DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1), + DEF_MOD("gpio5", 907, R8A77980_CLK_CP), + DEF_MOD("gpio4", 908, R8A77980_CLK_CP), + DEF_MOD("gpio3", 909, R8A77980_CLK_CP), + DEF_MOD("gpio2", 910, R8A77980_CLK_CP), + DEF_MOD("gpio1", 911, R8A77980_CLK_CP), + DEF_MOD("gpio0", 912, R8A77980_CLK_CP), + DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), + DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2), +}; + +static const unsigned int r8a77980_crit_mod_clks[] __initconst = { + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL2 PLL1 PLL3 + * 14 13 (MHz) + * -------------------------------------------------- + * 0 0 16.66 x 1 x240 x192 x192 + * 0 1 20 x 1 x200 x160 x160 + * 1 0 27 x 1 x148 x118 x118 + * 1 1 33.33 / 2 x240 x192 x192 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ + (((md) & BIT(13)) >> 13)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 192, 1, }, + { 1, 160, 1, 160, 1, }, + { 1, 118, 1, 118, 1, }, + { 2, 192, 1, 192, 1, }, +}; + +static int __init r8a77980_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +} + +const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a77980_core_clks, + .num_core_clks = ARRAY_SIZE(r8a77980_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a77980_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a77980_mod_clks), + .num_hw_mod_clks = 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks = r8a77980_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a77980_crit_mod_clks), + + /* Callbacks */ + .init = r8a77980_cpg_mssr_init, + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index e3cc72c81311..aadfa6df6c4d 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -699,6 +699,12 @@ static const struct of_device_id cpg_mssr_match[] = { .data = &r8a77970_cpg_mssr_info, }, #endif +#ifdef CONFIG_ARCH_R8A77980 + { + .compatible = "renesas,r8a77980-cpg-mssr", + .data = &r8a77980_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A77995 { .compatible = "renesas,r8a77995-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 0745b0930308..143293e3d193 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -140,6 +140,7 @@ extern const struct cpg_mssr_info r8a7794_cpg_mssr_info; extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; +extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; -- cgit v1.2.3 From 14b5057a2f84b9da246e5bda29c9fd914a8f691c Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 20 Feb 2018 12:13:28 +1030 Subject: dt-bindings: aspeed-lpc: Add reset controller This describes the reset controller present in the LPC address space. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley [p.zabel@pengutronix.de: removed a space before tab in indent] Signed-off-by: Philipp Zabel --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..7136432f9905 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -135,3 +135,24 @@ lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; }; + +LPC reset control +----------------- + +The UARTs present in the ASPEED SoC can have their resets tied to the reset +state of the LPC bus. Some systems may chose to modify this configuration. + +Required properties: + + - compatible: "aspeed,ast2500-lpc-reset" or + "aspeed,ast2400-lpc-reset" + - reg: offset and length of the IP in the LHC memory region + - #reset-controller indicates the number of reset cells expected + +Example: + +lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2500-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; +}; -- cgit v1.2.3 From 490e687eb8b274b5d942e1cf61fb01392b86ecce Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:07 +0100 Subject: pinctrl: sh-pfc: Initial R-Car M3-N support Add initial PFC support for R-Car M3-N (r8a77965) SoC. No groups or functions defined, just pin and registers enumeration. Signed-off-by: Jacopo Mondi Reviewed-by: Rob Herring Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a77965.c | 2726 ++++++++++++++++++++ drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + 6 files changed, 2740 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77965.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index dd64dbb4cb0e..bd5370a71666 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -24,6 +24,7 @@ Required Properties: - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. + - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 4ed3761418f9..0621cb51c016 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796 depends on ARCH_R8A7796 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A77965 + def_bool y + depends on ARCH_R8A77965 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A77970 def_bool y depends on ARCH_R8A77970 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 22e758ce1fc2..05b4379f0c98 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o +obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index e9eb7a7c6fac..7461af941659 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -557,6 +557,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7796_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A77965 + { + .compatible = "renesas,pfc-r8a77965", + .data = &r8a77965_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77970 { .compatible = "renesas,pfc-r8a77970", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c new file mode 100644 index 000000000000..3583e2018534 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c @@ -0,0 +1,2726 @@ +// SPDX-License-Identifier: GPL-2. +/* + * R8A77965 processor support - PFC hardware block. + * + * Copyright (C) 2018 Jacopo Mondi + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + */ + +#include + +#include "core.h" +#include "sh_pfc.h" + +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ + SH_PFC_PIN_CFG_PULL_UP | \ + SH_PFC_PIN_CFG_PULL_DOWN) + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_15 F_(D15, IP7_11_8) +#define GPSR0_14 F_(D14, IP7_7_4) +#define GPSR0_13 F_(D13, IP7_3_0) +#define GPSR0_12 F_(D12, IP6_31_28) +#define GPSR0_11 F_(D11, IP6_27_24) +#define GPSR0_10 F_(D10, IP6_23_20) +#define GPSR0_9 F_(D9, IP6_19_16) +#define GPSR0_8 F_(D8, IP6_15_12) +#define GPSR0_7 F_(D7, IP6_11_8) +#define GPSR0_6 F_(D6, IP6_7_4) +#define GPSR0_5 F_(D5, IP6_3_0) +#define GPSR0_4 F_(D4, IP5_31_28) +#define GPSR0_3 F_(D3, IP5_27_24) +#define GPSR0_2 F_(D2, IP5_23_20) +#define GPSR0_1 F_(D1, IP5_19_16) +#define GPSR0_0 F_(D0, IP5_15_12) + +/* GPSR1 */ +#define GPSR1_28 FM(CLKOUT) +#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) +#define GPSR1_26 F_(WE1_N, IP5_7_4) +#define GPSR1_25 F_(WE0_N, IP5_3_0) +#define GPSR1_24 F_(RD_WR_N, IP4_31_28) +#define GPSR1_23 F_(RD_N, IP4_27_24) +#define GPSR1_22 F_(BS_N, IP4_23_20) +#define GPSR1_21 F_(CS1_N, IP4_19_16) +#define GPSR1_20 F_(CS0_N, IP4_15_12) +#define GPSR1_19 F_(A19, IP4_11_8) +#define GPSR1_18 F_(A18, IP4_7_4) +#define GPSR1_17 F_(A17, IP4_3_0) +#define GPSR1_16 F_(A16, IP3_31_28) +#define GPSR1_15 F_(A15, IP3_27_24) +#define GPSR1_14 F_(A14, IP3_23_20) +#define GPSR1_13 F_(A13, IP3_19_16) +#define GPSR1_12 F_(A12, IP3_15_12) +#define GPSR1_11 F_(A11, IP3_11_8) +#define GPSR1_10 F_(A10, IP3_7_4) +#define GPSR1_9 F_(A9, IP3_3_0) +#define GPSR1_8 F_(A8, IP2_31_28) +#define GPSR1_7 F_(A7, IP2_27_24) +#define GPSR1_6 F_(A6, IP2_23_20) +#define GPSR1_5 F_(A5, IP2_19_16) +#define GPSR1_4 F_(A4, IP2_15_12) +#define GPSR1_3 F_(A3, IP2_11_8) +#define GPSR1_2 F_(A2, IP2_7_4) +#define GPSR1_1 F_(A1, IP2_3_0) +#define GPSR1_0 F_(A0, IP1_31_28) + +/* GPSR2 */ +#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) +#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) +#define GPSR2_12 F_(AVB_LINK, IP0_15_12) +#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) +#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) +#define GPSR2_9 F_(AVB_MDC, IP0_3_0) +#define GPSR2_8 F_(PWM2_A, IP1_27_24) +#define GPSR2_7 F_(PWM1_A, IP1_23_20) +#define GPSR2_6 F_(PWM0, IP1_19_16) +#define GPSR2_5 F_(IRQ5, IP1_15_12) +#define GPSR2_4 F_(IRQ4, IP1_11_8) +#define GPSR2_3 F_(IRQ3, IP1_7_4) +#define GPSR2_2 F_(IRQ2, IP1_3_0) +#define GPSR2_1 F_(IRQ1, IP0_31_28) +#define GPSR2_0 F_(IRQ0, IP0_27_24) + +/* GPSR3 */ +#define GPSR3_15 F_(SD1_WP, IP11_23_20) +#define GPSR3_14 F_(SD1_CD, IP11_19_16) +#define GPSR3_13 F_(SD0_WP, IP11_15_12) +#define GPSR3_12 F_(SD0_CD, IP11_11_8) +#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) +#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) +#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) +#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) +#define GPSR3_7 F_(SD1_CMD, IP8_15_12) +#define GPSR3_6 F_(SD1_CLK, IP8_11_8) +#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) +#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) +#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) +#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) +#define GPSR3_1 F_(SD0_CMD, IP7_23_20) +#define GPSR3_0 F_(SD0_CLK, IP7_19_16) + +/* GPSR4 */ +#define GPSR4_17 F_(SD3_DS, IP11_7_4) +#define GPSR4_16 F_(SD3_DAT7, IP11_3_0) +#define GPSR4_15 F_(SD3_DAT6, IP10_31_28) +#define GPSR4_14 F_(SD3_DAT5, IP10_27_24) +#define GPSR4_13 F_(SD3_DAT4, IP10_23_20) +#define GPSR4_12 F_(SD3_DAT3, IP10_19_16) +#define GPSR4_11 F_(SD3_DAT2, IP10_15_12) +#define GPSR4_10 F_(SD3_DAT1, IP10_11_8) +#define GPSR4_9 F_(SD3_DAT0, IP10_7_4) +#define GPSR4_8 F_(SD3_CMD, IP10_3_0) +#define GPSR4_7 F_(SD3_CLK, IP9_31_28) +#define GPSR4_6 F_(SD2_DS, IP9_27_24) +#define GPSR4_5 F_(SD2_DAT3, IP9_23_20) +#define GPSR4_4 F_(SD2_DAT2, IP9_19_16) +#define GPSR4_3 F_(SD2_DAT1, IP9_15_12) +#define GPSR4_2 F_(SD2_DAT0, IP9_11_8) +#define GPSR4_1 F_(SD2_CMD, IP9_7_4) +#define GPSR4_0 F_(SD2_CLK, IP9_3_0) + +/* GPSR5 */ +#define GPSR5_25 F_(MLB_DAT, IP14_19_16) +#define GPSR5_24 F_(MLB_SIG, IP14_15_12) +#define GPSR5_23 F_(MLB_CLK, IP14_11_8) +#define GPSR5_22 FM(MSIOF0_RXD) +#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) +#define GPSR5_20 FM(MSIOF0_TXD) +#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) +#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) +#define GPSR5_17 FM(MSIOF0_SCK) +#define GPSR5_16 F_(HRTS0_N, IP13_27_24) +#define GPSR5_15 F_(HCTS0_N, IP13_23_20) +#define GPSR5_14 F_(HTX0, IP13_19_16) +#define GPSR5_13 F_(HRX0, IP13_15_12) +#define GPSR5_12 F_(HSCK0, IP13_11_8) +#define GPSR5_11 F_(RX2_A, IP13_7_4) +#define GPSR5_10 F_(TX2_A, IP13_3_0) +#define GPSR5_9 F_(SCK2, IP12_31_28) +#define GPSR5_8 F_(RTS1_N, IP12_27_24) +#define GPSR5_7 F_(CTS1_N, IP12_23_20) +#define GPSR5_6 F_(TX1_A, IP12_19_16) +#define GPSR5_5 F_(RX1_A, IP12_15_12) +#define GPSR5_4 F_(RTS0_N, IP12_11_8) +#define GPSR5_3 F_(CTS0_N, IP12_7_4) +#define GPSR5_2 F_(TX0, IP12_3_0) +#define GPSR5_1 F_(RX0, IP11_31_28) +#define GPSR5_0 F_(SCK0, IP11_27_24) + +/* GPSR6 */ +#define GPSR6_31 F_(GP6_31, IP18_7_4) +#define GPSR6_30 F_(GP6_30, IP18_3_0) +#define GPSR6_29 F_(USB30_OVC, IP17_31_28) +#define GPSR6_28 F_(USB30_PWEN, IP17_27_24) +#define GPSR6_27 F_(USB1_OVC, IP17_23_20) +#define GPSR6_26 F_(USB1_PWEN, IP17_19_16) +#define GPSR6_25 F_(USB0_OVC, IP17_15_12) +#define GPSR6_24 F_(USB0_PWEN, IP17_11_8) +#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) +#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) +#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) +#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) +#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) +#define GPSR6_18 F_(SSI_WS78, IP16_19_16) +#define GPSR6_17 F_(SSI_SCK78, IP16_15_12) +#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) +#define GPSR6_15 F_(SSI_WS6, IP16_7_4) +#define GPSR6_14 F_(SSI_SCK6, IP16_3_0) +#define GPSR6_13 FM(SSI_SDATA5) +#define GPSR6_12 FM(SSI_WS5) +#define GPSR6_11 FM(SSI_SCK5) +#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) +#define GPSR6_9 F_(SSI_WS4, IP15_27_24) +#define GPSR6_8 F_(SSI_SCK4, IP15_23_20) +#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) +#define GPSR6_6 F_(SSI_WS349, IP15_15_12) +#define GPSR6_5 F_(SSI_SCK349, IP15_11_8) +#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) +#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) +#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) +#define GPSR6_1 F_(SSI_WS01239, IP14_27_24) +#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) + +/* GPSR7 */ +#define GPSR7_3 FM(GP7_03) +#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_1 FM(AVS2) +#define GPSR7_0 FM(AVS1) + + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) +#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) +#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) +#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) +#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) +#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) +#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0) +#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ +\ + GPSR6_31 \ + GPSR6_30 \ + GPSR6_29 \ + GPSR1_28 GPSR6_28 \ + GPSR1_27 GPSR6_27 \ + GPSR1_26 GPSR6_26 \ + GPSR1_25 GPSR5_25 GPSR6_25 \ + GPSR1_24 GPSR5_24 GPSR6_24 \ + GPSR1_23 GPSR5_23 GPSR6_23 \ + GPSR1_22 GPSR5_22 GPSR6_22 \ + GPSR1_21 GPSR5_21 GPSR6_21 \ + GPSR1_20 GPSR5_20 GPSR6_20 \ + GPSR1_19 GPSR5_19 GPSR6_19 \ + GPSR1_18 GPSR5_18 GPSR6_18 \ + GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ + GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ +GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 + +#define PINMUX_IPSR \ +\ +FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ +FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ +FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ +FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ +FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ +FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ +FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ +FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ +\ +FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ +FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ +FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \ +FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ +FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ +FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ +FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ +\ +FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ +FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ +FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ +FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ +FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ +\ +FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ +FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ +FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ +FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ +FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ +FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ +FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ +FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ +\ +FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ +FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ +FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ +FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ +FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ +FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ +FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ +FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 + +/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) +#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) +#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) +#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) +#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) +#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) +#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) +#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) +#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) +#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) +#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) +#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) +#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) +#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) +#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) +#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) +#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) +#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) +#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) +#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1) +#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) +#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) +#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) +#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) +#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) +#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) +#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) +#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1) +#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) +#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) +#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) +#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) +#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) +#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) +#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) +#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) + +/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) +#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) +#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) +#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) +#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) +#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) +#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) +#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) +#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) +#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ + MOD_SEL2_30 \ + MOD_SEL1_29_28_27 MOD_SEL2_29 \ +MOD_SEL0_28_27 MOD_SEL2_28_27 \ +MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ + MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ +MOD_SEL0_23 MOD_SEL1_23_22_21 \ +MOD_SEL0_22 MOD_SEL2_22 \ +MOD_SEL0_21 MOD_SEL2_21 \ +MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ +MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ +MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ + MOD_SEL2_17 \ +MOD_SEL0_16 MOD_SEL1_16 \ + MOD_SEL1_15_14 \ +MOD_SEL0_14_13 \ + MOD_SEL1_13 \ +MOD_SEL0_12 MOD_SEL1_12 \ +MOD_SEL0_11 MOD_SEL1_11 \ +MOD_SEL0_10 MOD_SEL1_10 \ +MOD_SEL0_9_8 MOD_SEL1_9 \ +MOD_SEL0_7_6 \ + MOD_SEL1_6 \ +MOD_SEL0_5 MOD_SEL1_5 \ +MOD_SEL0_4_3 MOD_SEL1_4 \ + MOD_SEL1_3 \ + MOD_SEL1_2 \ + MOD_SEL1_1 \ + MOD_SEL1_0 MOD_SEL2_0 + +/* + * These pins are not able to be muxed but have other properties + * that can be set, such as drive-strength or pull-up/pull-down enable. + */ +#define PINMUX_STATIC \ + FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ + FM(QSPI0_IO2) FM(QSPI0_IO3) \ + FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ + FM(QSPI1_IO2) FM(QSPI1_IO3) \ + FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ + FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ + FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ + FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ + FM(PRESETOUT) \ + FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ + FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_STATIC + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(AVS1), + PINMUX_SINGLE(AVS2), + PINMUX_SINGLE(CLKOUT), + PINMUX_SINGLE(GP7_03), + PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(MSIOF0_RXD), + PINMUX_SINGLE(MSIOF0_SCK), + PINMUX_SINGLE(MSIOF0_TXD), + PINMUX_SINGLE(SSI_SCK5), + PINMUX_SINGLE(SSI_SDATA5), + PINMUX_SINGLE(SSI_WS5), + + /* IPSR0 */ + PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), + PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), + + PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), + PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), + PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), + PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), + PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), + + PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + + PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + + PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), + PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), + PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), + PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), + PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), + PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), + PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), + PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), + PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), + PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), + PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), + PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), + PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), + PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), + PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), + PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), + PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), + PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), + PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), + PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), + PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), + PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_19_16, PWM0), + PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), + PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), + + PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), + PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + + PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), + PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + + PINMUX_IPSR_GPSR(IP1_31_28, A0), + PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), + PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), + PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), + PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_3_0, A1), + PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), + PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), + PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), + PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), + + PINMUX_IPSR_GPSR(IP2_7_4, A2), + PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), + PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), + PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), + PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), + + PINMUX_IPSR_GPSR(IP2_11_8, A3), + PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), + PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), + PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), + PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), + + PINMUX_IPSR_GPSR(IP2_15_12, A4), + PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), + PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), + PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), + PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), + PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), + + PINMUX_IPSR_GPSR(IP2_19_16, A5), + PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), + PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), + PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), + PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), + PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), + + PINMUX_IPSR_GPSR(IP2_23_20, A6), + PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), + PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), + PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), + PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), + + PINMUX_IPSR_GPSR(IP2_27_24, A7), + PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), + PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), + PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), + PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), + + PINMUX_IPSR_GPSR(IP2_31_28, A8), + PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), + PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_3_0, A9), + PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), + + PINMUX_IPSR_GPSR(IP3_7_4, A10), + PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1), + PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), + + PINMUX_IPSR_GPSR(IP3_11_8, A11), + PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), + PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), + PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), + PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), + PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), + PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), + PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), + PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), + + PINMUX_IPSR_GPSR(IP3_15_12, A12), + PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), + PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), + PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), + PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), + PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), + + PINMUX_IPSR_GPSR(IP3_19_16, A13), + PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), + PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), + PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), + PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), + PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), + + PINMUX_IPSR_GPSR(IP3_23_20, A14), + PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), + PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), + PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), + PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), + PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), + + PINMUX_IPSR_GPSR(IP3_27_24, A15), + PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), + PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), + PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), + PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), + PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), + + PINMUX_IPSR_GPSR(IP3_31_28, A16), + PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), + PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), + PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_3_0, A17), + PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), + PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), + PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), + + PINMUX_IPSR_GPSR(IP4_7_4, A18), + PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), + PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), + PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), + + PINMUX_IPSR_GPSR(IP4_11_8, A19), + PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), + PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), + PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), + + PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), + PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), + + PINMUX_IPSR_GPSR(IP4_19_16, CS1_N), + PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), + PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), + + PINMUX_IPSR_GPSR(IP4_23_20, BS_N), + PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), + PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), + PINMUX_IPSR_GPSR(IP4_23_20, SCK3), + PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), + PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), + PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), + PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), + + PINMUX_IPSR_GPSR(IP4_27_24, RD_N), + PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), + PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), + + PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), + PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), + PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), + PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), + PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), + PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), + PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), + PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), + PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), + PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), + PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), + + PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), + PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), + PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N), + PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), + PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), + PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), + PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), + PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), + + PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), + PINMUX_IPSR_GPSR(IP5_11_8, QCLK), + PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), + PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), + + PINMUX_IPSR_GPSR(IP5_15_12, D0), + PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), + PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), + PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), + + PINMUX_IPSR_GPSR(IP5_19_16, D1), + PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), + PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), + PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), + + PINMUX_IPSR_GPSR(IP5_23_20, D2), + PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), + PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), + + PINMUX_IPSR_GPSR(IP5_27_24, D3), + PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), + PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), + PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), + + PINMUX_IPSR_GPSR(IP5_31_28, D4), + PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), + PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_3_0, D5), + PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), + PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), + + PINMUX_IPSR_GPSR(IP6_7_4, D6), + PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), + PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), + + PINMUX_IPSR_GPSR(IP6_11_8, D7), + PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), + PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), + PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), + + PINMUX_IPSR_GPSR(IP6_15_12, D8), + PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), + PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), + + PINMUX_IPSR_GPSR(IP6_19_16, D9), + PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), + PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), + + PINMUX_IPSR_GPSR(IP6_23_20, D10), + PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), + PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), + PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), + + PINMUX_IPSR_GPSR(IP6_27_24, D11), + PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), + PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), + PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), + PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2), + PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), + + PINMUX_IPSR_GPSR(IP6_31_28, D12), + PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), + PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_3_0, D13), + PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), + PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), + PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), + + PINMUX_IPSR_GPSR(IP7_7_4, D14), + PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), + PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), + PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), + + PINMUX_IPSR_GPSR(IP7_11_8, D15), + PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), + PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), + PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), + PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), + PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), + PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), + + PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), + PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), + PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), + PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), + PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), + + /* IPSR8 */ + PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), + PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), + PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), + PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), + + PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), + PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), + + PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), + PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), + PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), + PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), + PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), + PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), + PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), + PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), + PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), + + PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), + PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), + PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), + PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), + + /* IPSR9 */ + PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), + PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), + + PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), + PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), + + PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), + PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), + + PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), + PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), + + PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), + PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), + + PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), + PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), + + PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), + PINMUX_IPSR_GPSR(IP9_27_24, NFALE), + PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), + + PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), + PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), + + /* IPSR10 */ + PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), + PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), + + PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), + PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), + + PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), + PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), + + PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), + PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), + + PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), + PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), + + PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), + PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), + PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), + + PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), + PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), + PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), + + PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), + PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), + PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), + + /* IPSR11 */ + PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), + PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), + PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), + + PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), + PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), + + PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), + PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), + + PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), + + PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), + PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + + PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), + PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + + PINMUX_IPSR_GPSR(IP11_27_24, SCK0), + PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), + PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), + PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP11_31_28, RX0), + PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), + + /* IPSR12 */ + PINMUX_IPSR_GPSR(IP12_3_0, TX0), + PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), + + PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), + PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), + PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), + + PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), + PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), + PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), + PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), + + PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), + + PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), + PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), + + PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), + PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), + + PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N), + PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), + + PINMUX_IPSR_GPSR(IP12_31_28, SCK2), + PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1), + PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), + PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), + PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), + + /* IPSR13 */ + PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), + PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), + PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), + + PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), + PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), + PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), + PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), + + PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), + PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), + PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), + PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), + + PINMUX_IPSR_GPSR(IP13_15_12, HRX0), + PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), + + PINMUX_IPSR_GPSR(IP13_19_16, HTX0), + PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), + + PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), + PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), + PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), + + PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), + PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), + PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), + PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), + + PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), + PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), + PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), + + /* IPSR14 */ + PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), + PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), + PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), + PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), + + PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), + PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), + PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), + PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), + PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), + + PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), + PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), + PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), + + PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), + PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), + PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), + + PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), + PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), + PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), + + PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), + PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), + + PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), + PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), + + PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), + PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), + + /* IPSR15 */ + PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0), + + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1), + + PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), + PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), + + PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), + PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), + + PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), + PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), + + PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), + PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), + + PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), + PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), + + PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), + PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), + PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), + PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), + PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), + PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), + + /* IPSR16 */ + PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), + PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), + + PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), + PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), + + PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), + PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), + PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), + + PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), + PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), + + PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), + PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), + + PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), + PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), + PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0), + + PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), + PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), + PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), + PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), + + PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0), + PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), + PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), + PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1), + PINMUX_IPSR_GPSR(IP16_31_28, SCK1), + PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), + PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), + + /* IPSR17 */ + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), + PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), + PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), + PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), + + PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), + PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), + PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), + PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), + PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), + PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), + PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), + PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), + PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0), + PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), + PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), + PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), + PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), + PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), + PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1), + PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), + PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), + + PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), + PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), + PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), + PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), + PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), + PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), + PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), + + /* IPSR18 */ + PINMUX_IPSR_GPSR(IP18_3_0, GP6_30), + PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), + PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), + PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), + PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), + + PINMUX_IPSR_GPSR(IP18_7_4, GP6_31), + PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), + PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1), + PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), + PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), + PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), + PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), + PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), + + /* I2C */ + PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), + PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), + +/* + * Static pins can not be muxed between different functions but + * still needs a mark entry in the pinmux list. Add each static + * pin to the list without an associated function. The sh-pfc + * core will do the right thing and skip trying to mux then pin + * while still applying configuration to it + */ +#define FM(x) PINMUX_DATA(x##_MARK, 0), + PINMUX_STATIC +#undef FM +}; + +/* + * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs. + * Physical layout rows: A - AW, cols: 1 - 39. + */ +#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) +#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) +#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), + + /* + * Pins not associated with a GPIO port. + * + * The pin positions are different between different r8a77965 + * packages, all that is needed for the pfc driver is a unique + * number for each pin. To this end use the pin layout from + * R-Car M3SiP to calculate a unique number for each pin. + */ + SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { +}; + +static const struct sh_pfc_function pinmux_functions[] = { +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + GP_1_28_FN, GPSR1_28, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, } + }, + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, } + }, + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, } + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, } + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_25_FN, GPSR5_25, + GP_5_24_FN, GPSR5_24, + GP_5_23_FN, GPSR5_23, + GP_5_22_FN, GPSR5_22, + GP_5_21_FN, GPSR5_21, + GP_5_20_FN, GPSR5_20, + GP_5_19_FN, GPSR5_19, + GP_5_18_FN, GPSR5_18, + GP_5_17_FN, GPSR5_17, + GP_5_16_FN, GPSR5_16, + GP_5_15_FN, GPSR5_15, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, } + }, + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + GP_6_31_FN, GPSR6_31, + GP_6_30_FN, GPSR6_30, + GP_6_29_FN, GPSR6_29, + GP_6_28_FN, GPSR6_28, + GP_6_27_FN, GPSR6_27, + GP_6_26_FN, GPSR6_26, + GP_6_25_FN, GPSR6_25, + GP_6_24_FN, GPSR6_24, + GP_6_23_FN, GPSR6_23, + GP_6_22_FN, GPSR6_22, + GP_6_21_FN, GPSR6_21, + GP_6_20_FN, GPSR6_20, + GP_6_19_FN, GPSR6_19, + GP_6_18_FN, GPSR6_18, + GP_6_17_FN, GPSR6_17, + GP_6_16_FN, GPSR6_16, + GP_6_15_FN, GPSR6_15, + GP_6_14_FN, GPSR6_14, + GP_6_13_FN, GPSR6_13, + GP_6_12_FN, GPSR6_12, + GP_6_11_FN, GPSR6_11, + GP_6_10_FN, GPSR6_10, + GP_6_9_FN, GPSR6_9, + GP_6_8_FN, GPSR6_8, + GP_6_7_FN, GPSR6_7, + GP_6_6_FN, GPSR6_6, + GP_6_5_FN, GPSR6_5, + GP_6_4_FN, GPSR6_4, + GP_6_3_FN, GPSR6_3, + GP_6_2_FN, GPSR6_2, + GP_6_1_FN, GPSR6_1, + GP_6_0_FN, GPSR6_0, } + }, + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_3_FN, GPSR7_3, + GP_7_2_FN, GPSR7_2, + GP_7_1_FN, GPSR7_1, + GP_7_0_FN, GPSR7_0, } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + IP0_31_28 + IP0_27_24 + IP0_23_20 + IP0_19_16 + IP0_15_12 + IP0_11_8 + IP0_7_4 + IP0_3_0 } + }, + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + IP1_31_28 + IP1_27_24 + IP1_23_20 + IP1_19_16 + IP1_15_12 + IP1_11_8 + IP1_7_4 + IP1_3_0 } + }, + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + IP2_31_28 + IP2_27_24 + IP2_23_20 + IP2_19_16 + IP2_15_12 + IP2_11_8 + IP2_7_4 + IP2_3_0 } + }, + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + IP3_31_28 + IP3_27_24 + IP3_23_20 + IP3_19_16 + IP3_15_12 + IP3_11_8 + IP3_7_4 + IP3_3_0 } + }, + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + IP4_31_28 + IP4_27_24 + IP4_23_20 + IP4_19_16 + IP4_15_12 + IP4_11_8 + IP4_7_4 + IP4_3_0 } + }, + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + IP5_31_28 + IP5_27_24 + IP5_23_20 + IP5_19_16 + IP5_15_12 + IP5_11_8 + IP5_7_4 + IP5_3_0 } + }, + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + IP6_31_28 + IP6_27_24 + IP6_23_20 + IP6_19_16 + IP6_15_12 + IP6_11_8 + IP6_7_4 + IP6_3_0 } + }, + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + IP7_31_28 + IP7_27_24 + IP7_23_20 + IP7_19_16 + /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IP7_11_8 + IP7_7_4 + IP7_3_0 } + }, + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + IP8_31_28 + IP8_27_24 + IP8_23_20 + IP8_19_16 + IP8_15_12 + IP8_11_8 + IP8_7_4 + IP8_3_0 } + }, + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + IP9_31_28 + IP9_27_24 + IP9_23_20 + IP9_19_16 + IP9_15_12 + IP9_11_8 + IP9_7_4 + IP9_3_0 } + }, + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + IP10_31_28 + IP10_27_24 + IP10_23_20 + IP10_19_16 + IP10_15_12 + IP10_11_8 + IP10_7_4 + IP10_3_0 } + }, + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + IP11_31_28 + IP11_27_24 + IP11_23_20 + IP11_19_16 + IP11_15_12 + IP11_11_8 + IP11_7_4 + IP11_3_0 } + }, + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + IP12_31_28 + IP12_27_24 + IP12_23_20 + IP12_19_16 + IP12_15_12 + IP12_11_8 + IP12_7_4 + IP12_3_0 } + }, + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + IP13_31_28 + IP13_27_24 + IP13_23_20 + IP13_19_16 + IP13_15_12 + IP13_11_8 + IP13_7_4 + IP13_3_0 } + }, + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + IP14_31_28 + IP14_27_24 + IP14_23_20 + IP14_19_16 + IP14_15_12 + IP14_11_8 + IP14_7_4 + IP14_3_0 } + }, + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + IP15_31_28 + IP15_27_24 + IP15_23_20 + IP15_19_16 + IP15_15_12 + IP15_11_8 + IP15_7_4 + IP15_3_0 } + }, + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + IP16_31_28 + IP16_27_24 + IP16_23_20 + IP16_19_16 + IP16_15_12 + IP16_11_8 + IP16_7_4 + IP16_3_0 } + }, + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + IP17_31_28 + IP17_27_24 + IP17_23_20 + IP17_19_16 + IP17_15_12 + IP17_11_8 + IP17_7_4 + IP17_3_0 } + }, + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IP18_7_4 + IP18_3_0 } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, + 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + MOD_SEL0_31_30_29 + MOD_SEL0_28_27 + MOD_SEL0_26_25_24 + MOD_SEL0_23 + MOD_SEL0_22 + MOD_SEL0_21 + MOD_SEL0_20 + MOD_SEL0_19 + MOD_SEL0_18_17 + MOD_SEL0_16 + 0, 0, /* RESERVED 15 */ + MOD_SEL0_14_13 + MOD_SEL0_12 + MOD_SEL0_11 + MOD_SEL0_10 + MOD_SEL0_9_8 + MOD_SEL0_7_6 + MOD_SEL0_5 + MOD_SEL0_4_3 + /* RESERVED 2, 1, 0 */ + 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 2, 3, 1, 2, 3, 1, 1, 2, 1, + 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + MOD_SEL1_31_30 + MOD_SEL1_29_28_27 + MOD_SEL1_26 + MOD_SEL1_25_24 + MOD_SEL1_23_22_21 + MOD_SEL1_20 + MOD_SEL1_19 + MOD_SEL1_18_17 + MOD_SEL1_16 + MOD_SEL1_15_14 + MOD_SEL1_13 + MOD_SEL1_12 + MOD_SEL1_11 + MOD_SEL1_10 + MOD_SEL1_9 + 0, 0, 0, 0, /* RESERVED 8, 7 */ + MOD_SEL1_6 + MOD_SEL1_5 + MOD_SEL1_4 + MOD_SEL1_3 + MOD_SEL1_2 + MOD_SEL1_1 + MOD_SEL1_0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, + 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, + 4, 4, 4, 3, 1) { + MOD_SEL2_31 + MOD_SEL2_30 + MOD_SEL2_29 + MOD_SEL2_28_27 + MOD_SEL2_26 + MOD_SEL2_25_24_23 + MOD_SEL2_22 + MOD_SEL2_21 + MOD_SEL2_20 + MOD_SEL2_19 + MOD_SEL2_18 + MOD_SEL2_17 + /* RESERVED 16 */ + 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 11, 10, 9, 8 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 7, 6, 5, 4 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 3, 2, 1 */ + 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL2_0 } + }, + { }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { + { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ + { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ + { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ + { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ + { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ + { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ + { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ + { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { + { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ + { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ + { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ + { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ + { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ + { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ + { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ + { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { + { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ + { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ + { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ + { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ + { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ + { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ + { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ + { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { + { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ + { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ + { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ + { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ + { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ + { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ + { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ + { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { + { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ + { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ + { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ + { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { + { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ + { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ + { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ + { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ + { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ + { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ + { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ + { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { + { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ + { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ + { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ + { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ + { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ + { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ + { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ + { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { + { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ + { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ + { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ + { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ + { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ + { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ + { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ + { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { + { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ + { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ + { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ + { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ + { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ + { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ + { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { + { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ + { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ + { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ + { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ + { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ + { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ + { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ + { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { + { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ + { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ + { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ + { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ + { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ + { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ + { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ + { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { + { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ + { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ + { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ + { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ + { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ + { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { + { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */ + { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */ + { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { + { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ + { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ + { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { + { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ + { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ + { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { + { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ + { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ + { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ + { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ + { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ + { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { + { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ + { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ + { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { + { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ + { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ + { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ + { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ + { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ + { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ + { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ + { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { + { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ + { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ + { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ + { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ + { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ + { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ + { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ + { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { + { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ + { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ + { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ + { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ + { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { + { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ + { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ + { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ + { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ + { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { + { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ + { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ + { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ + { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ + { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ + { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ + { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ + { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { + { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ + { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ + { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ + { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ + { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ + { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ + { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ + { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { + { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ + { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ + { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ + { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ + { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ + { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ + { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ + { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { + { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ + { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ + { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ + { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ + { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */ + { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */ + } }, + { }, +}; + +enum ioctrl_regs { + POCCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL] = { 0xe6060380, }, + { /* sentinel */ }, +}; + +static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; + + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) + bit = pin & 0x1f; + + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) + bit = (pin & 0x1f) + 12; + + return bit; +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ + [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ + [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ + [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ + [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ + [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ + [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ + [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ + [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ + [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ + [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ + [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ + [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ + [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ + [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ + [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ + [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ + [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ + [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ + [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ + [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ + [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ + [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ + [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ + [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ + [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ + [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ + [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ + [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ + [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ + [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */ + [ 1] = PIN_NONE, + [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ + [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ + [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ + [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ + [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ + [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 8] = PIN_NONE, + [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { + [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { + [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ + [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ + [ 7] = PIN_NONE, + [ 8] = PIN_NONE, + [ 9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + u32 enable, updown; + unsigned int bit; + + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) + enable |= BIT(bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); +} + +static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { + .pin_to_pocctrl = r8a77965_pin_to_pocctrl, + .get_bias = r8a77965_pinmux_get_bias, + .set_bias = r8a77965_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a77965_pinmux_info = { + .name = "r8a77965_pfc", + .ops = &r8a77965_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 5747ab0472df..7253a8cbb0ea 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -283,6 +283,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info; extern const struct sh_pfc_soc_info r8a7795_pinmux_info; extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; +extern const struct sh_pfc_soc_info r8a77965_pinmux_info; extern const struct sh_pfc_soc_info r8a77970_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; -- cgit v1.2.3 From f3d96f8d23d8e6d0b7642ee946b9b2ac3418fb4d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 3 Jan 2018 16:49:44 +0800 Subject: phy: sun4i-usb: add support for R40 USB PHY Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs. Add support for it. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Acked-by: Rob Herring Tested-by: Hermann Lauer Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + drivers/phy/allwinner/phy-sun4i-usb.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index c1ce5a0a652e..07ca4ec4a745 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -11,6 +11,7 @@ Required properties: * allwinner,sun8i-a33-usb-phy * allwinner,sun8i-a83t-usb-phy * allwinner,sun8i-h3-usb-phy + * allwinner,sun8i-r40-usb-phy * allwinner,sun8i-v3s-usb-phy * allwinner,sun50i-a64-usb-phy - reg : a list of offset + length pairs diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index aa857be692cf..bee798892b21 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -112,6 +112,7 @@ enum sun4i_usb_phy_type { sun8i_a33_phy, sun8i_a83t_phy, sun8i_h3_phy, + sun8i_r40_phy, sun8i_v3s_phy, sun50i_a64_phy, }; @@ -919,6 +920,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .phy0_dual_route = true, }; +static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { + .num_phys = 3, + .type = sun8i_r40_phy, + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, + .enable_pmu_unk1 = true, + .phy0_dual_route = true, +}; + static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .num_phys = 1, .type = sun8i_v3s_phy, @@ -948,6 +959,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg }, { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg }, { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg }, + { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg }, { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg}, -- cgit v1.2.3 From 94ccae556741b3b1e2e526ee41426ed890500cd5 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 24 Jan 2018 13:47:35 +0800 Subject: dt-bindings: hisilicon: add doc for Hi3798CV200 peripheral controller It adds bindings doc for Hi3798CV200 peripheral controller. Signed-off-by: Shawn Guo Signed-off-by: Kishon Vijay Abraham I --- .../bindings/arm/hisilicon/hisilicon.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 7111fbc82a4e..199cd36fe1ba 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -74,6 +74,29 @@ Example: reboot-offset = <0x4>; }; +----------------------------------------------------------------------- +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + ----------------------------------------------------------------------- Hisilicon Hi6220 system controller -- cgit v1.2.3 From 5669f91a086ca377a5f5b15885d03482435006d6 Mon Sep 17 00:00:00 2001 From: Jianguo Sun Date: Wed, 24 Jan 2018 13:47:36 +0800 Subject: dt-bindings: add bindings doc for hi3798cv200 combphy It adds the device tree bindings for PCIE/SATA/USB3 combo PHY found on HiSilicon STB SoCs. Signed-off-by: Jianguo Sun Signed-off-by: Shawn Guo Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-hi3798cv200-combphy.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt new file mode 100644 index 000000000000..17b0c761370a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt @@ -0,0 +1,59 @@ +HiSilicon STB PCIE/SATA/USB3 PHY + +Required properties: +- compatible: Should be "hisilicon,hi3798cv200-combphy" +- reg: Should be the address space for COMBPHY configuration and state + registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and + PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC. +- #phy-cells: Should be 1. The cell number is used to select the phy mode + as defined in . +- clocks: The phandle to clock provider and clock specifier pair. +- resets: The phandle to reset controller and reset specifier pair. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Optional properties: +- hisilicon,fixed-mode: If the phy device doesn't support mode select + but a fixed mode setting, the property should be present to specify + the particular mode. +- hisilicon,mode-select-bits: If the phy device support mode select, + this property should be present to specify the register bits in + peripheral controller, as a 3 integers tuple: + . + +Notes: +- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only + one of them should be present. +- The device node should be a child of peripheral controller that contains + COMBPHY configuration/state and PERI_CTRL register used to select PHY mode. + Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller + bindings. + +Examples: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + hisilicon,fixed-mode = ; + }; + + combphy1: phy@858 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x858 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; + }; +}; -- cgit v1.2.3 From 1f74edf9a5b12447b6be96130b334e8bb98d7e69 Mon Sep 17 00:00:00 2001 From: Xue Liu Date: Tue, 20 Feb 2018 12:55:56 +0100 Subject: ieee802154: Add device tree documentation for MCR20A Signed-off-by: Xue Liu Signed-off-by: Stefan Schmidt --- .../devicetree/bindings/net/ieee802154/mcr20a.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt b/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt new file mode 100644 index 000000000000..2aaef567c5be --- /dev/null +++ b/Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt @@ -0,0 +1,23 @@ +* MCR20A IEEE 802.15.4 * + +Required properties: + - compatible: should be "nxp,mcr20a" + - spi-max-frequency: maximal bus speed, should be set to a frequency + lower than 9000000 depends sync or async operation mode + - reg: the chipselect index + - interrupts: the interrupt generated by the device. Non high-level + can occur deadlocks while handling isr. + +Optional properties: + - rst_b-gpio: GPIO spec for the RST_B pin + +Example: + + mcr20a@0 { + compatible = "nxp,mcr20a"; + spi-max-frequency = <9000000>; + reg = <0>; + interrupts = <17 2>; + interrupt-parent = <&gpio>; + rst_b-gpio = <&gpio 27 1> + }; -- cgit v1.2.3 From a527709b78b3c9979fb47ddd4c3d3fd96182b504 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:06 +0100 Subject: soc: renesas: rcar-sysc: Add R-Car M3-N support Add support for R-Car M3-N (R8A77965) power areas. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- .../bindings/power/renesas,rcar-sysc.txt | 1 + drivers/soc/renesas/Kconfig | 5 +++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r8a77965-sysc.c | 37 ++++++++++++++++++++++ drivers/soc/renesas/rcar-sysc.c | 3 ++ drivers/soc/renesas/rcar-sysc.h | 1 + include/dt-bindings/power/r8a77965-sysc.h | 30 ++++++++++++++++++ 7 files changed, 78 insertions(+) create mode 100644 drivers/soc/renesas/r8a77965-sysc.c create mode 100644 include/dt-bindings/power/r8a77965-sysc.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt index 6284a9550b3c..ab399e559257 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -17,6 +17,7 @@ Required properties: - "renesas,r8a7794-sysc" (R-Car E2) - "renesas,r8a7795-sysc" (R-Car H3) - "renesas,r8a7796-sysc" (R-Car M3-W) + - "renesas,r8a77965-sysc" (R-Car M3-N) - "renesas,r8a77970-sysc" (R-Car V3M) - "renesas,r8a77980-sysc" (R-Car V3H) - "renesas,r8a77995-sysc" (R-Car D3) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 6caa393e3a2d..7106a6330210 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -14,6 +14,7 @@ config SOC_RENESAS select SYSC_R8A7794 if ARCH_R8A7794 select SYSC_R8A7795 if ARCH_R8A7795 select SYSC_R8A7796 if ARCH_R8A7796 + select SYSC_R8A77965 if ARCH_R8A77965 select SYSC_R8A77970 if ARCH_R8A77970 select SYSC_R8A77980 if ARCH_R8A77980 select SYSC_R8A77995 if ARCH_R8A77995 @@ -57,6 +58,10 @@ config SYSC_R8A7796 bool "R-Car M3-W System Controller support" if COMPILE_TEST select SYSC_RCAR +config SYSC_R8A77965 + bool "R-Car M3-N System Controller support" if COMPILE_TEST + select SYSC_RCAR + config SYSC_R8A77970 bool "R-Car V3M System Controller support" if COMPILE_TEST select SYSC_RCAR diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index d3b7bb3284c0..ccb5ec57a262 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SYSC_R8A7792) += r8a7792-sysc.o obj-$(CONFIG_SYSC_R8A7794) += r8a7794-sysc.o obj-$(CONFIG_SYSC_R8A7795) += r8a7795-sysc.o obj-$(CONFIG_SYSC_R8A7796) += r8a7796-sysc.o +obj-$(CONFIG_SYSC_R8A77965) += r8a77965-sysc.o obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o diff --git a/drivers/soc/renesas/r8a77965-sysc.c b/drivers/soc/renesas/r8a77965-sysc.c new file mode 100644 index 000000000000..d7f7928e3c07 --- /dev/null +++ b/drivers/soc/renesas/r8a77965-sysc.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas R-Car M3-N System Controller + * Copyright (C) 2018 Jacopo Mondi + * + * Based on Renesas R-Car M3-W System Controller + * Copyright (C) 2016 Glider bvba + */ + +#include +#include + +#include + +#include "rcar-sysc.h" + +static const struct rcar_sysc_area r8a77965_areas[] __initconst = { + { "always-on", 0, 0, R8A77965_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca57-scu", 0x1c0, 0, R8A77965_PD_CA57_SCU, R8A77965_PD_ALWAYS_ON, + PD_SCU }, + { "ca57-cpu0", 0x80, 0, R8A77965_PD_CA57_CPU0, R8A77965_PD_CA57_SCU, + PD_CPU_NOCR }, + { "ca57-cpu1", 0x80, 1, R8A77965_PD_CA57_CPU1, R8A77965_PD_CA57_SCU, + PD_CPU_NOCR }, + { "cr7", 0x240, 0, R8A77965_PD_CR7, R8A77965_PD_ALWAYS_ON }, + { "a3vc", 0x380, 0, R8A77965_PD_A3VC, R8A77965_PD_ALWAYS_ON }, + { "a3vp", 0x340, 0, R8A77965_PD_A3VP, R8A77965_PD_ALWAYS_ON }, + { "a2vc1", 0x3c0, 1, R8A77965_PD_A2VC1, R8A77965_PD_A3VC }, + { "3dg-a", 0x100, 0, R8A77965_PD_3DG_A, R8A77965_PD_ALWAYS_ON }, + { "3dg-b", 0x100, 1, R8A77965_PD_3DG_B, R8A77965_PD_3DG_A }, + { "a3ir", 0x180, 0, R8A77965_PD_A3IR, R8A77965_PD_ALWAYS_ON }, +}; + +const struct rcar_sysc_info r8a77965_sysc_info __initconst = { + .areas = r8a77965_areas, + .num_areas = ARRAY_SIZE(r8a77965_areas), +}; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 72b0f4a9ad4e..faf20e719361 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -284,6 +284,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = { #ifdef CONFIG_SYSC_R8A7796 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info }, #endif +#ifdef CONFIG_SYSC_R8A77965 + { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info }, +#endif #ifdef CONFIG_SYSC_R8A77970 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info }, #endif diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h index 974b18619c08..dcdc9ec8eba7 100644 --- a/drivers/soc/renesas/rcar-sysc.h +++ b/drivers/soc/renesas/rcar-sysc.h @@ -58,6 +58,7 @@ extern const struct rcar_sysc_info r8a7792_sysc_info; extern const struct rcar_sysc_info r8a7794_sysc_info; extern const struct rcar_sysc_info r8a7795_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info; +extern const struct rcar_sysc_info r8a77965_sysc_info; extern const struct rcar_sysc_info r8a77970_sysc_info; extern const struct rcar_sysc_info r8a77980_sysc_info; extern const struct rcar_sysc_info r8a77995_sysc_info; diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h new file mode 100644 index 000000000000..05a4b5917314 --- /dev/null +++ b/include/dt-bindings/power/r8a77965-sysc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + * Copyright (C) 2016 Glider bvba + */ + +#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77965_PD_CA57_CPU0 0 +#define R8A77965_PD_CA57_CPU1 1 +#define R8A77965_PD_A3VP 9 +#define R8A77965_PD_CA57_SCU 12 +#define R8A77965_PD_CR7 13 +#define R8A77965_PD_A3VC 14 +#define R8A77965_PD_3DG_A 17 +#define R8A77965_PD_3DG_B 18 +#define R8A77965_PD_A3IR 24 +#define R8A77965_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77965_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ -- cgit v1.2.3 From 939c09ca7db29ef2aed3db49be41cb519eb4a55c Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Wed, 25 Oct 2017 15:52:31 +0800 Subject: dt-bindings: nds32 CPU Bindings This patch adds nds32 CPU binding documents. Signed-off-by: Vincent Chen Signed-off-by: Rick Chen Signed-off-by: Zong Li Signed-off-by: Greentime Hu Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/nds32/cpus.txt | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt new file mode 100644 index 000000000000..6f9e311b6589 --- /dev/null +++ b/Documentation/devicetree/bindings/nds32/cpus.txt @@ -0,0 +1,38 @@ +* Andestech Processor Binding + +This binding specifies what properties must be available in the device tree +representation of a Andestech Processor Core, which is the root node in the +tree. + +Required properties: + + - compatible: + Usage: required + Value type: + Definition: Should be "andestech,", "andestech,nds32v3" as fallback. + Must contain "andestech,nds32v3" as the most generic value, in addition to + one of the following identifiers for a particular CPU core: + "andestech,n13" + "andestech,n15" + "andestech,d15" + "andestech,n10" + "andestech,d10" + - device_type + Usage: required + Value type: + Definition: must be "cpu" + - reg: Contains CPU index. + - clock-frequency: Contains the clock frequency for CPU, in Hz. + +* Examples + +/ { + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "andestech,n13", "andestech,nds32v3"; + reg = <0x0>; + clock-frequency = <60000000> + }; + }; +}; -- cgit v1.2.3 From 8f7726d251f381bfad185d3e7a2d60e0bff48acc Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Thu, 28 Dec 2017 17:49:33 +0800 Subject: dt-bindings: nds32 L2 cache controller Bindings This patch adds nds32 L2 cache controller binding documents. Signed-off-by: Greentime Hu Reviewed-by: Rob Herring Acked-by: Arnd Bergmann --- Documentation/devicetree/bindings/nds32/atl2c.txt | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/atl2c.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt new file mode 100644 index 000000000000..da8ab8e7ae9b --- /dev/null +++ b/Documentation/devicetree/bindings/nds32/atl2c.txt @@ -0,0 +1,28 @@ +* Andestech L2 cache Controller + +The level-2 cache controller plays an important role in reducing memory latency +for high performance systems, such as thoese designs with AndesCore processors. +Level-2 cache controller in general enhances overall system performance +signigicantly and the system power consumption might be reduced as well by +reducing DRAM accesses. + +This binding specifies what properties must be available in the device tree +representation of an Andestech L2 cache controller. + +Required properties: + - compatible: + Usage: required + Value type: + Definition: "andestech,atl2c" + - reg : Physical base address and size of cache controller's memory mapped + - cache-unified : Specifies the cache is a unified cache. + - cache-level : Should be set to 2 for a level 2 cache. + +* Example + + cache-controller@e0500000 { + compatible = "andestech,atl2c"; + reg = <0xe0500000 0x1000>; + cache-unified; + cache-level = <2>; + }; -- cgit v1.2.3 From 68d87861029a60425e6f1b27c8986e9d39d5b0c7 Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Mon, 4 Dec 2017 11:26:02 +0800 Subject: dt-bindings: nds32 SoC Bindings This patch adds nds32 SoC(AE3XX and AG101P) binding documents. Signed-off-by: Greentime Hu Reviewed-by: Rob Herring Acked-by: Arnd Bergmann --- .../devicetree/bindings/nds32/andestech-boards | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/nds32/andestech-boards (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards b/Documentation/devicetree/bindings/nds32/andestech-boards new file mode 100644 index 000000000000..f5d75693e3c7 --- /dev/null +++ b/Documentation/devicetree/bindings/nds32/andestech-boards @@ -0,0 +1,40 @@ +Andestech(nds32) AE3XX Platform +----------------------------------------------------------------------------- +The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It +is composed of one Andestech(nds32) processor and AE3XX. + +Required properties (in root node): +- compatible = "andestech,ae3xx"; + +Example: +/dts-v1/; +/ { + compatible = "andestech,ae3xx"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; +}; + +Andestech(nds32) AG101P Platform +----------------------------------------------------------------------------- +AG101P is a generic SoC Platform IP that works with any of Andestech(nds32) +processors to provide a cost-effective and high performance solution for +majority of embedded systems in variety of application domains. Users may +simply attach their IP on one of the system buses together with certain glue +logics to complete a SoC solution for a specific application. With +comprehensive simulation and design environments, users may evaluate the +system performance of their applications and track bugs of their designs +efficiently. The optional hardware development platform further provides real +system environment for early prototyping and software/hardware co-development. + +Required properties (in root node): + compatible = "andestech,ag101p"; + +Example: +/dts-v1/; +/ { + compatible = "andestech,ag101p"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; +}; -- cgit v1.2.3 From ba7cbe51bfbd30176e0d9123552663b5136d48c5 Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Wed, 25 Oct 2017 15:38:09 +0800 Subject: dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller This patch adds an irqchip driver document for the Andestech Internal Vector Interrupt Controller. Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Reviewed-by: Rob Herring Acked-by: Arnd Bergmann --- .../interrupt-controller/andestech,ativic32.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt new file mode 100644 index 000000000000..f4b4193d830e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt @@ -0,0 +1,19 @@ +* Andestech Internal Vector Interrupt Controller + +The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller +suitable for a simpler SoC platform not requiring a more sophisticated and +bigger External Vector Interrupt Controller. + + +Main node required properties: + +- compatible : should at least contain "andestech,ativic32". +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts + +Examples: + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <1>; + interrupt-controller; + }; -- cgit v1.2.3 From d0d7a6fe427c95178e37bbec40fe6da9753dad8d Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Mon, 11 Dec 2017 15:51:31 +0800 Subject: dt-bindings: timer: Add andestech atcpit100 timer binding doc Add a document to describe Andestech atcpit100 timer and binding information. Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Acked-by: Rob Herring Acked-by: Arnd Bergmann --- .../bindings/timer/andestech,atcpit100-timer.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt new file mode 100644 index 000000000000..4c9ea5989e35 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt @@ -0,0 +1,33 @@ +Andestech ATCPIT100 timer +------------------------------------------------------------------ +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX platforms and other designs. + +This timer is a set of compact multi-function timers, which can be +used as pulse width modulators (PWM) as well as simple timers. + +It supports up to 4 PIT channels. Each PIT channel is a +multi-function timer and provide the following usage scenarios: +One 32-bit timer +Two 16-bit timers +Four 8-bit timers +One 16-bit PWM +One 16-bit timer and one 8-bit PWM +Two 8-bit timer and one 8-bit PWM + +Required properties: +- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clocks : a clock to provide the tick rate for "andestech,atcpit100" +- clock-names : should be "PCLK" for the peripheral clock source. + +Examples: + +timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2>; + clocks = <&apb>; + clock-names = "PCLK"; +}; -- cgit v1.2.3 From 298910619d13e9c04680e923fef1e5bbc1790d10 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 24 Oct 2017 13:14:50 +0100 Subject: docs: Remove metag docs Now that arch/metag/ has been removed, remove Meta architecture specific documentation from the Documentation/ directory. Signed-off-by: James Hogan Cc: Jonathan Corbet Cc: linux-metag@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/00-INDEX | 2 - Documentation/admin-guide/kernel-parameters.txt | 4 - Documentation/devicetree/bindings/metag/meta.txt | 30 --- Documentation/metag/00-INDEX | 4 - Documentation/metag/kernel-ABI.txt | 256 ----------------------- 5 files changed, 296 deletions(-) delete mode 100644 Documentation/devicetree/bindings/metag/meta.txt delete mode 100644 Documentation/metag/00-INDEX delete mode 100644 Documentation/metag/kernel-ABI.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index 7f3a0728ccf2..eae1e7193f50 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -276,8 +276,6 @@ memory-hotplug.txt - Hotpluggable memory support, how to use and current status. men-chameleon-bus.txt - info on MEN chameleon bus. -metag/ - - directory with info about Linux on Meta architecture. mic/ - Intel Many Integrated Core (MIC) architecture device driver. mips/ diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 1d1d53f85ddd..30a8d0635898 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1347,10 +1347,6 @@ If specified, z/VM IUCV HVC accepts connections from listed z/VM user IDs only. - hwthread_map= [METAG] Comma-separated list of Linux cpu id to - hardware thread id mappings. - Format: : - keep_bootcon [KNL] Do not unregister boot console at start. This is only useful for debugging when something happens in the window diff --git a/Documentation/devicetree/bindings/metag/meta.txt b/Documentation/devicetree/bindings/metag/meta.txt deleted file mode 100644 index f4457f57ab08..000000000000 --- a/Documentation/devicetree/bindings/metag/meta.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Meta Processor Binding - -This binding specifies what properties must be available in the device tree -representation of a Meta Processor Core, which is the root node in the tree. - -Required properties: - - - compatible: Specifies the compatibility list for the Meta processor. - The type shall be and the value shall include "img,meta". - -Optional properties: - - - clocks: Clock consumer specifiers as described in - Documentation/devicetree/bindings/clock/clock-bindings.txt - - - clock-names: Clock consumer names as described in - Documentation/devicetree/bindings/clock/clock-bindings.txt. - -Clocks are identified by name. Valid clocks are: - - - "core": The Meta core clock from which the Meta timers are derived. - -* Examples - -/ { - compatible = "toumaz,tz1090", "img,meta"; - - clocks = <&meta_core_clk>; - clock-names = "core"; -}; diff --git a/Documentation/metag/00-INDEX b/Documentation/metag/00-INDEX deleted file mode 100644 index db11c513bd5c..000000000000 --- a/Documentation/metag/00-INDEX +++ /dev/null @@ -1,4 +0,0 @@ -00-INDEX - - this file -kernel-ABI.txt - - Documents metag ABI details diff --git a/Documentation/metag/kernel-ABI.txt b/Documentation/metag/kernel-ABI.txt deleted file mode 100644 index 628216603198..000000000000 --- a/Documentation/metag/kernel-ABI.txt +++ /dev/null @@ -1,256 +0,0 @@ - ========================== - KERNEL ABIS FOR METAG ARCH - ========================== - -This document describes the Linux ABIs for the metag architecture, and has the -following sections: - - (*) Outline of registers - (*) Userland registers - (*) Kernel registers - (*) System call ABI - (*) Calling conventions - - -==================== -OUTLINE OF REGISTERS -==================== - -The main Meta core registers are arranged in units: - - UNIT Type DESCRIPTION GP EXT PRIV GLOBAL - ======= ======= =============== ======= ======= ======= ======= - CT Special Control unit - D0 General Data unit 0 0-7 8-15 16-31 16-31 - D1 General Data unit 1 0-7 8-15 16-31 16-31 - A0 General Address unit 0 0-3 4-7 8-15 8-15 - A1 General Address unit 1 0-3 4-7 8-15 8-15 - PC Special PC unit 0 1 - PORT Special Ports - TR Special Trigger unit 0-7 - TT Special Trace unit 0-5 - FX General FP unit 0-15 - -GP registers form part of the main context. - -Extended context registers (EXT) may not be present on all hardware threads and -can be context switched if support is enabled and the appropriate bits are set -in e.g. the D0.8 register to indicate what extended state to preserve. - -Global registers are shared between threads and are privilege protected. - -See arch/metag/include/asm/metag_regs.h for definitions relating to core -registers and the fields and bits they contain. See the TRMs for further details -about special registers. - -Several special registers are preserved in the main context, these are the -interesting ones: - - REG (ALIAS) PURPOSE - ======================= =============================================== - CT.1 (TXMODE) Processor mode bits (particularly for DSP) - CT.2 (TXSTATUS) Condition flags and LSM_STEP (MGET/MSET step) - CT.3 (TXRPT) Branch repeat counter - PC.0 (PC) Program counter - -Some of the general registers have special purposes in the ABI and therefore -have aliases: - - D0 REG (ALIAS) PURPOSE D1 REG (ALIAS) PURPOSE - =============== =============== =============== ======================= - D0.0 (D0Re0) 32bit result D1.0 (D1Re0) Top half of 64bit result - D0.1 (D0Ar6) Argument 6 D1.1 (D1Ar5) Argument 5 - D0.2 (D0Ar4) Argument 4 D1.2 (D1Ar3) Argument 3 - D0.3 (D0Ar2) Argument 2 D1.3 (D1Ar1) Argument 1 - D0.4 (D0FrT) Frame temp D1.4 (D1RtP) Return pointer - D0.5 Call preserved D1.5 Call preserved - D0.6 Call preserved D1.6 Call preserved - D0.7 Call preserved D1.7 Call preserved - - A0 REG (ALIAS) PURPOSE A1 REG (ALIAS) PURPOSE - =============== =============== =============== ======================= - A0.0 (A0StP) Stack pointer A1.0 (A1GbP) Global base pointer - A0.1 (A0FrP) Frame pointer A1.1 (A1LbP) Local base pointer - A0.2 A1.2 - A0.3 A1.3 - - -================== -USERLAND REGISTERS -================== - -All the general purpose D0, D1, A0, A1 registers are preserved when entering the -kernel (including asynchronous events such as interrupts and timer ticks) except -the following which have special purposes in the ABI: - - REGISTERS WHEN STATUS PURPOSE - =============== ======= =============== =============================== - D0.8 DSP Preserved ECH, determines what extended - DSP state to preserve. - A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered - at any time by the creation of a - signal frame. - A1.0 (A1GbP) SMP Clobbered Used as temporary for loading - kernel stack pointer and saving - core context. - A0.15 !SMP Protected Stores kernel stack pointer. - A1.15 ALWAYS Protected Stores kernel base pointer. - -On UP A0.15 is used to store the kernel stack pointer for storing the userland -context. A0.15 is global between hardware threads though which means it cannot -be used on SMP for this purpose. Since no protected local registers are -available A1GbP is reserved for use as a temporary to allow a percpu stack -pointer to be loaded for storing the rest of the context. - - -================ -KERNEL REGISTERS -================ - -When in the kernel the following registers have special purposes in the ABI: - - REGISTERS WHEN STATUS PURPOSE - =============== ======= =============== =============================== - A0.0 (A0StP) ALWAYS Preserved Stack >= A0StP may be clobbered - at any time by the creation of - an irq signal frame. - A1.0 (A1GbP) ALWAYS Preserved Reserved (kernel base pointer). - - -=============== -SYSTEM CALL ABI -=============== - -When a system call is made, the following registers are effective: - - REGISTERS CALL RETURN - =============== ======================= =============================== - D0.0 (D0Re0) Return value (or -errno) - D1.0 (D1Re0) System call number Clobbered - D0.1 (D0Ar6) Syscall arg #6 Preserved - D1.1 (D1Ar5) Syscall arg #5 Preserved - D0.2 (D0Ar4) Syscall arg #4 Preserved - D1.2 (D1Ar3) Syscall arg #3 Preserved - D0.3 (D0Ar2) Syscall arg #2 Preserved - D1.3 (D1Ar1) Syscall arg #1 Preserved - -Due to the limited number of argument registers and some system calls with badly -aligned 64-bit arguments, 64-bit values are always packed in consecutive -arguments, even if this is contrary to the normal calling conventions (where the -two halves would go in a matching pair of data registers). - -For example fadvise64_64 usually has the signature: - - long sys_fadvise64_64(i32 fd, i64 offs, i64 len, i32 advice); - -But for metag fadvise64_64 is wrapped so that the 64-bit arguments are packed: - - long sys_fadvise64_64_metag(i32 fd, i32 offs_lo, - i32 offs_hi, i32 len_lo, - i32 len_hi, i32 advice) - -So the arguments are packed in the registers like this: - - D0 REG (ALIAS) VALUE D1 REG (ALIAS) VALUE - =============== =============== =============== ======================= - D0.1 (D0Ar6) advice D1.1 (D1Ar5) hi(len) - D0.2 (D0Ar4) lo(len) D1.2 (D1Ar3) hi(offs) - D0.3 (D0Ar2) lo(offs) D1.3 (D1Ar1) fd - - -=================== -CALLING CONVENTIONS -=================== - -These calling conventions apply to both user and kernel code. The stack grows -from low addresses to high addresses in the metag ABI. The stack pointer (A0StP) -should always point to the next free address on the stack and should at all -times be 64-bit aligned. The following registers are effective at the point of a -call: - - REGISTERS CALL RETURN - =============== ======================= =============================== - D0.0 (D0Re0) 32bit return value - D1.0 (D1Re0) Upper half of 64bit return value - D0.1 (D0Ar6) 32bit argument #6 Clobbered - D1.1 (D1Ar5) 32bit argument #5 Clobbered - D0.2 (D0Ar4) 32bit argument #4 Clobbered - D1.2 (D1Ar3) 32bit argument #3 Clobbered - D0.3 (D0Ar2) 32bit argument #2 Clobbered - D1.3 (D1Ar1) 32bit argument #1 Clobbered - D0.4 (D0FrT) Clobbered - D1.4 (D1RtP) Return pointer Clobbered - D{0-1}.{5-7} Preserved - A0.0 (A0StP) Stack pointer Preserved - A1.0 (A0GbP) Preserved - A0.1 (A0FrP) Frame pointer Preserved - A1.1 (A0LbP) Preserved - A{0-1},{2-3} Clobbered - -64-bit arguments are placed in matching pairs of registers (i.e. the same -register number in both D0 and D1 units), with the least significant half in D0 -and the most significant half in D1, leaving a gap where necessary. Further -arguments are stored on the stack in reverse order (earlier arguments at higher -addresses): - - ADDRESS 0 1 2 3 4 5 6 7 - =============== ===== ===== ===== ===== ===== ===== ===== ===== - A0StP --> - A0StP-0x08 32bit argument #8 32bit argument #7 - A0StP-0x10 32bit argument #10 32bit argument #9 - -Function prologues tend to look a bit like this: - - /* If frame pointer in use, move it to frame temp register so it can be - easily pushed onto stack */ - MOV D0FrT,A0FrP - - /* If frame pointer in use, set it to stack pointer */ - ADD A0FrP,A0StP,#0 - - /* Preserve D0FrT, D1RtP, D{0-1}.{5-7} on stack, incrementing A0StP */ - MSETL [A0StP++],D0FrT,D0.5,D0.6,D0.7 - - /* Allocate some stack space for local variables */ - ADD A0StP,A0StP,#0x10 - -At this point the stack would look like this: - - ADDRESS 0 1 2 3 4 5 6 7 - =============== ===== ===== ===== ===== ===== ===== ===== ===== - A0StP --> - A0StP-0x08 - A0StP-0x10 - A0StP-0x18 Old D0.7 Old D1.7 - A0StP-0x20 Old D0.6 Old D1.6 - A0StP-0x28 Old D0.5 Old D1.5 - A0FrP --> Old A0FrP (frame ptr) Old D1RtP (return ptr) - A0FrP-0x08 32bit argument #8 32bit argument #7 - A0FrP-0x10 32bit argument #10 32bit argument #9 - -Function epilogues tend to differ depending on the use of a frame pointer. An -example of a frame pointer epilogue: - - /* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack, incrementing A0FrP */ - MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP++] - /* Restore stack pointer to where frame pointer was before increment */ - SUB A0StP,A0FrP,#0x20 - /* Restore frame pointer from frame temp */ - MOV A0FrP,D0FrT - /* Return to caller via restored return pointer */ - MOV PC,D1RtP - -If the function hasn't touched the frame pointer, MGETL cannot be safely used -with A0StP as it always increments and that would expose the stack to clobbering -by interrupts (kernel) or signals (user). Therefore it's common to see the MGETL -split into separate GETL instructions: - - /* Restore D0FrT, D1RtP, D{0-1}.{5-7} from stack */ - GETL D0FrT,D1RtP,[A0StP+#-0x30] - GETL D0.5,D1.5,[A0StP+#-0x28] - GETL D0.6,D1.6,[A0StP+#-0x20] - GETL D0.7,D1.7,[A0StP+#-0x18] - /* Restore stack pointer */ - SUB A0StP,A0StP,#0x30 - /* Return to caller via restored return pointer */ - MOV PC,D1RtP -- cgit v1.2.3 From 9777d8099a4a9df1625b4caaee1388c0158478c5 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 20 Feb 2018 14:19:32 +0200 Subject: dt-bindings: gpio: add raspberry pi GPIO expander binding The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware over I2C. The firmware mailbox interface allows the ARM core to control the GPIO lines. Signed-off-by: Baruch Siach Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/gpio/raspberrypi,firmware-gpio.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt b/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt new file mode 100644 index 000000000000..ce97265e23ba --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt @@ -0,0 +1,30 @@ +Raspberry Pi GPIO expander + +The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The +firmware exposes a mailbox interface that allows the ARM core to control the +GPIO lines on the expander. + +The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi +firmware node. + +Required properties: + +- compatible : Should be "raspberrypi,firmware-gpio" +- gpio-controller : Marks the device node as a gpio controller +- #gpio-cells : Should be two. The first cell is the pin number, and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low + +Example: + +firmware: firmware-rpi { + compatible = "raspberrypi,bcm2835-firmware"; + mboxes = <&mailbox>; + + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; +}; -- cgit v1.2.3 From 39aba4714da62946ef9d081ab6e41462517ccb34 Mon Sep 17 00:00:00 2001 From: Phil Reid Date: Mon, 19 Feb 2018 17:25:19 +0800 Subject: dt-bindings: pinctrl: mcp23s08: add documentation for drive-open-drain This flag set the mcp23s08 device irq type to open drain active low. Acked-by: Rob Herring Signed-off-by: Phil Reid Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt index 9c451c20dda4..a5a8322a31bd 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -45,6 +45,8 @@ Optional properties: - first cell is the pin number - second cell is used to specify flags. - interrupt-controller: Marks the device node as a interrupt controller. +- drive-open-drain: Sets the ODR flag in the IOCON register. This configures + the IRQ output as open drain active low. Optional device specific properties: - microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices -- cgit v1.2.3 From 10c1d542c7e871865bca381842fd04a92d2b95ec Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 15 Feb 2018 12:55:33 -0500 Subject: media: dt-bindings: Add bindings for TDA1997X Define the device tree bindings for the TDA1997X. Acked-by: Rob Herring Acked-by: Sakari Ailus Signed-off-by: Tim Harvey Signed-off-by: Hans Verkuil [hans.verkuil@cisco.com: make a proper commit message] Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/tda1997x.txt | 178 +++++++++++++++++++++ include/dt-bindings/media/tda1997x.h | 74 +++++++++ 2 files changed, 252 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/tda1997x.txt create mode 100644 include/dt-bindings/media/tda1997x.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt new file mode 100644 index 000000000000..e76167999d76 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt @@ -0,0 +1,178 @@ +Device-Tree bindings for the NXP TDA1997x HDMI receiver + +The TDA19971/73 are HDMI video receivers. + +The TDA19971 Video port output pins can be used as follows: + - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4] + - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4] + - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4] + - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2] + - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0] + - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles) + - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles) + - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) + +The TDA19973 Video port output pins can be used as follows: + - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0] + - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0] + - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0] + - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles) + +The Video port output pins are mapped via 4-bit 'pin groups' allowing +for a variety of connection possibilities including swapping pin order within +pin groups. The video_portcfg device-tree property consists of register mapping +pairs which map a chip-specific VP output register to a 4-bit pin group. If +the pin group needs to be bit-swapped you can use the *_S pin-group defines. + +Required Properties: + - compatible : + - "nxp,tda19971" for the TDA19971 + - "nxp,tda19973" for the TDA19973 + - reg : I2C slave address + - interrupts : The interrupt number + - DOVDD-supply : Digital I/O supply + - DVDD-supply : Digital Core supply + - AVDD-supply : Analog supply + - nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups. + +Optional Properties: + - nxp,audout-format : DAI bus format: "i2s" or "spdif". + - nxp,audout-width : width of audio output data bus (1-4). + - nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used). + - nxp,audout-mclk-fs : Multiplication factor between stream rate and codec + mclk. + +The port node shall contain one endpoint child node for its digital +output video port, in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Optional Endpoint Properties: + The following three properties are defined in video-interfaces.txt and + are valid for the output parallel bus endpoint: + - hsync-active: Horizontal synchronization polarity. Defaults to active high. + - vsync-active: Vertical synchronization polarity. Defaults to active high. + - data-active: Data polarity. Defaults to active high. + +Examples: + - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422 + 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same pixclk cycle. + */ + nxp,vidout-portcfg = + /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; + - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 + 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same pixclk cycle. + */ + nxp,vidout-portcfg = + /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; + - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656 + 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins) + hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p8v>; + /* audio */ + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over + * 2 pixclk cycles. + */ + nxp,vidout-portcfg = + /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */ + < TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >, + /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */ + < TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >, + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; diff --git a/include/dt-bindings/media/tda1997x.h b/include/dt-bindings/media/tda1997x.h new file mode 100644 index 000000000000..bd9fbd718ec9 --- /dev/null +++ b/include/dt-bindings/media/tda1997x.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 Gateworks Corporation + */ +#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H +#define _DT_BINDINGS_MEDIA_TDA1997X_H + +/* TDA19973 36bit Video Port control registers */ +#define TDA1997X_VP36_35_32 0 +#define TDA1997X_VP36_31_28 1 +#define TDA1997X_VP36_27_24 2 +#define TDA1997X_VP36_23_20 3 +#define TDA1997X_VP36_19_16 4 +#define TDA1997X_VP36_15_12 5 +#define TDA1997X_VP36_11_08 6 +#define TDA1997X_VP36_07_04 7 +#define TDA1997X_VP36_03_00 8 + +/* TDA19971 24bit Video Port control registers */ +#define TDA1997X_VP24_V23_20 0 +#define TDA1997X_VP24_V19_16 1 +#define TDA1997X_VP24_V15_12 3 +#define TDA1997X_VP24_V11_08 4 +#define TDA1997X_VP24_V07_04 6 +#define TDA1997X_VP24_V03_00 7 + +/* Pin groups */ +#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ +#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ +#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ +#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) +/* pinswapped groups */ +#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) +#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) + +/* Audio bus DAI format */ +#define TDA1997X_I2S16 1 /* I2S 16bit */ +#define TDA1997X_I2S32 2 /* I2S 32bit */ +#define TDA1997X_SPDIF 3 /* SPDIF */ +#define TDA1997X_OBA 4 /* One Bit Audio */ +#define TDA1997X_DST 5 /* Direct Stream Transfer */ +#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ +#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ +#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ +#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ + +/* Audio bus channel layout */ +#define TDA1997X_LAYOUT0 0 /* 2-channel */ +#define TDA1997X_LAYOUT1 1 /* 8-channel */ + +/* Audio bus clock */ +#define TDA1997X_ACLK_16FS 0 +#define TDA1997X_ACLK_32FS 1 +#define TDA1997X_ACLK_64FS 2 +#define TDA1997X_ACLK_128FS 3 +#define TDA1997X_ACLK_256FS 4 +#define TDA1997X_ACLK_512FS 5 + +#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ -- cgit v1.2.3 From 7eab96f386549efcbdf25a5258576fa924242aac Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Fri, 16 Feb 2018 11:55:33 +0100 Subject: dt-bindings: bcm283x: Fix register ranges of bcm2835-i2s Since 517e7a1537a ("ASoC: bcm2835: move to use the clock framework") the bcm2835-i2s requires a clock as DT property. Unfortunately the necessary DT change has never been applied. While we are at it also fix the first PCM register range to cover the PCM_GRAY register. This patch only fixes the affected dt-bindings. Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt Reviewed-by: Rob Herring Signed-off-by: Eric Anholt --- Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 4 ++-- Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt | 9 ++++----- 2 files changed, 6 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt index baf9b34d20bf..b6a8cc0978cd 100644 --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt @@ -74,8 +74,8 @@ Example: bcm2835_i2s: i2s@7e203000 { compatible = "brcm,bcm2835-i2s"; - reg = < 0x7e203000 0x20>, - < 0x7e101098 0x02>; + reg = < 0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; dmas = <&dma 2>, <&dma 3>; diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt index 65783de0aedf..7bb0362828ec 100644 --- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt +++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt @@ -2,9 +2,8 @@ Required properties: - compatible: "brcm,bcm2835-i2s" -- reg: A list of base address and size entries: - * The first entry should cover the PCM registers - * The second entry should cover the PCM clock registers +- reg: Should contain PCM registers location and length. +- clocks: the (PCM) clock to use - dmas: List of DMA controller phandle and DMA request line ordered pairs. - dma-names: Identifier string for each DMA request line in the dmas property. These strings correspond 1:1 with the ordered pairs in dmas. @@ -16,8 +15,8 @@ Example: bcm2835_i2s: i2s@7e203000 { compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x20>, - <0x7e101098 0x02>; + reg = <0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; dmas = <&dma 2>, <&dma 3>; -- cgit v1.2.3 From a327fb0c1a89452195bf6f29359923401a5978ed Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Tue, 16 Jan 2018 04:21:58 -0500 Subject: media: dt-bindings: media: Add bindings for OV5695 Add device tree binding documentation for the OV5695 sensor. Signed-off-by: Shunqian Zheng Reviewed-by: Jacopo Mondi Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/ov5695.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ov5695.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ov5695.txt b/Documentation/devicetree/bindings/media/i2c/ov5695.txt new file mode 100644 index 000000000000..640a63717d96 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ov5695.txt @@ -0,0 +1,41 @@ +* Omnivision OV5695 MIPI CSI-2 sensor + +Required Properties: +- compatible: shall be "ovti,ov5695" +- clocks: reference to the xvclk input clock +- clock-names: shall be "xvclk" +- avdd-supply: Analog voltage supply, 2.8 volts +- dovdd-supply: Digital I/O voltage supply, 1.8 volts +- dvdd-supply: Digital core voltage supply, 1.2 volts +- reset-gpios: Low active reset gpio + +The device node shall contain one 'port' child node with an +'endpoint' subnode for its digital output video port, +in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. +The endpoint optional property 'data-lanes' shall be "<1 2>". + +Example: +&i2c7 { + ov5695: camera-sensor@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&clk_24m_cam>; + + clocks = <&cru SCLK_TESTCLKOUT1>; + clock-names = "xvclk"; + + avdd-supply = <&pp2800_cam>; + dovdd-supply = <&pp1800>; + dvdd-supply = <&pp1250_cam>; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + + port { + wcam_out: endpoint { + remote-endpoint = <&mipi_in_wcam>; + data-lanes = <1 2>; + }; + }; + }; +}; -- cgit v1.2.3 From 36125eec01f4e82726013b13ecad908829da0e46 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Tue, 16 Jan 2018 04:22:00 -0500 Subject: media: dt-bindings: media: Add bindings for OV2685 Add device tree binding documentation for the OV2685 sensor. Signed-off-by: Shunqian Zheng Reviewed-by: Jacopo Mondi Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/ov2685.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ov2685.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ov2685.txt b/Documentation/devicetree/bindings/media/i2c/ov2685.txt new file mode 100644 index 000000000000..625c4a8c0d53 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ov2685.txt @@ -0,0 +1,41 @@ +* Omnivision OV2685 MIPI CSI-2 sensor + +Required Properties: +- compatible: shall be "ovti,ov2685" +- clocks: reference to the xvclk input clock +- clock-names: shall be "xvclk" +- avdd-supply: Analog voltage supply, 2.8 volts +- dovdd-supply: Digital I/O voltage supply, 1.8 volts +- dvdd-supply: Digital core voltage supply, 1.8 volts +- reset-gpios: Low active reset gpio + +The device node shall contain one 'port' child node with an +'endpoint' subnode for its digital output video port, +in accordance with the video interface bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. +The endpoint optional property 'data-lanes' shall be "<1>". + +Example: +&i2c7 { + ov2685: camera-sensor@3c { + compatible = "ovti,ov2685"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&clk_24m_cam>; + + clocks = <&cru SCLK_TESTCLKOUT1>; + clock-names = "xvclk"; + + avdd-supply = <&pp2800_cam>; + dovdd-supply = <&pp1800>; + dvdd-supply = <&pp1800>; + reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1>; + }; + }; + }; +}; -- cgit v1.2.3 From 7b05db639edb650ba46d67ca300635ae89b7320c Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sun, 21 Jan 2018 10:14:16 -0500 Subject: media: ov9650: add device tree binding Now the ov9650 driver supports device tree probing. So this adds a device tree binding documentation. Cc: Sylwester Nawrocki Cc: Jacopo Mondi Cc: H. Nikolaus Schaller Cc: Hugues Fruchet Cc: Mauro Carvalho Chehab Reviewed-by: Rob Herring Signed-off-by: Akinobu Mita Reviewed-by: Jacopo Mondi Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/ov9650.txt | 36 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ov9650.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ov9650.txt b/Documentation/devicetree/bindings/media/i2c/ov9650.txt new file mode 100644 index 000000000000..506dfc52872a --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ov9650.txt @@ -0,0 +1,36 @@ +* Omnivision OV9650/OV9652 CMOS sensor + +Required Properties: +- compatible: shall be one of + "ovti,ov9650" + "ovti,ov9652" +- clocks: reference to the xvclk input clock. + +Optional Properties: +- reset-gpios: reference to the GPIO connected to the resetb pin, if any. + Active is high. +- powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. + Active is high. + +The device node shall contain one 'port' child node with one child 'endpoint' +subnode for its digital output video port, in accordance with the video +interface bindings defined in Documentation/devicetree/bindings/media/ +video-interfaces.txt. + +Example: + +&i2c0 { + ov9650: camera@30 { + compatible = "ovti,ov9650"; + reg = <0x30>; + reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_HIGH>; + clocks = <&xclk>; + + port { + ov9650_0: endpoint { + remote-endpoint = <&vcap1_in0>; + }; + }; + }; +}; diff --git a/MAINTAINERS b/MAINTAINERS index cfd5efa4b205..fdbcf13e97fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10224,6 +10224,7 @@ L: linux-media@vger.kernel.org T: git git://linuxtv.org/media_tree.git S: Maintained F: drivers/media/i2c/ov9650.c +F: Documentation/devicetree/bindings/media/i2c/ov9650.txt ONENAND FLASH DRIVER M: Kyungmin Park -- cgit v1.2.3 From 622b2d10fc28616add3e253ed80010136f272235 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Wed, 24 Jan 2018 04:30:49 -0500 Subject: media: dt-bindings: Add OF properties to ov7670 Describe newly introduced OF properties for ov7670 image sensor. The driver supports two standard properties to configure synchronism signals polarities and one custom property already supported as platform data options to suppress pixel clock during horizontal blankings. Re-phrase child nodes description while at there. Signed-off-by: Jacopo Mondi Reviewed-by: Rob Herring Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/i2c/ov7670.txt | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/ov7670.txt b/Documentation/devicetree/bindings/media/i2c/ov7670.txt index 826b6563b009..2c972a56f3cb 100644 --- a/Documentation/devicetree/bindings/media/i2c/ov7670.txt +++ b/Documentation/devicetree/bindings/media/i2c/ov7670.txt @@ -9,14 +9,21 @@ Required Properties: - clocks: reference to the xclk input clock. - clock-names: should be "xclk". +Required Endpoint Properties: +- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. +- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. + Optional Properties: - reset-gpios: reference to the GPIO connected to the resetb pin, if any. Active is low. - powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any. Active is high. +- ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output + signal during horizontal blankings. -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in +The device node must contain one 'port' child node with one 'endpoint' child +sub-node for its digital output video port, in accordance with the video +interface bindings defined in: Documentation/devicetree/bindings/media/video-interfaces.txt. Example: @@ -34,8 +41,13 @@ Example: assigned-clocks = <&pck0>; assigned-clock-rates = <25000000>; + ov7670,pclk-hb-disable; + port { ov7670_0: endpoint { + hsync-active = <0>; + vsync-active = <0>; + remote-endpoint = <&isi_0>; }; }; -- cgit v1.2.3 From bf79cd635db50fab2319add2462cf803ff76d346 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:04 +0100 Subject: soc: renesas: rcar-rst: Add support for R-Car M3-N Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 + drivers/soc/renesas/Kconfig | 4 ++-- drivers/soc/renesas/rcar-rst.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt index a55b88658446..294a0dae106a 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rst.txt +++ b/Documentation/devicetree/bindings/reset/renesas,rst.txt @@ -26,6 +26,7 @@ Required properties: - "renesas,r8a7794-rst" (R-Car E2) - "renesas,r8a7795-rst" (R-Car H3) - "renesas,r8a7796-rst" (R-Car M3-W) + - "renesas,r8a77965-rst" (R-Car M3-N) - "renesas,r8a77970-rst" (R-Car V3M) - "renesas,r8a77980-rst" (R-Car V3H) - "renesas,r8a77995-rst" (R-Car D3) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 7106a6330210..3bbe6114a420 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -3,8 +3,8 @@ config SOC_RENESAS default y if ARCH_RENESAS select SOC_BUS select RST_RCAR if ARCH_RCAR_GEN1 || ARCH_RCAR_GEN2 || \ - ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77970 || \ - ARCH_R8A77980 || ARCH_R8A77995 + ARCH_R8A7795 || ARCH_R8A7796 || ARCH_R8A77965 || \ + ARCH_R8A77970 || ARCH_R8A77980 || ARCH_R8A77995 select SYSC_R8A7743 if ARCH_R8A7743 select SYSC_R8A7745 if ARCH_R8A7745 select SYSC_R8A7779 if ARCH_R8A7779 diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c index 34136664ece4..8e9cb7996ab0 100644 --- a/drivers/soc/renesas/rcar-rst.c +++ b/drivers/soc/renesas/rcar-rst.c @@ -56,6 +56,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = { /* R-Car Gen3 */ { .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 }, + { .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 }, { .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 }, -- cgit v1.2.3 From 7ce36da900c0a2ff4777d9ba51c4f1cb74205463 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Tue, 20 Feb 2018 16:12:03 +0100 Subject: clk: renesas: cpg-mssr: Add support for R-Car M3-N Initial support for R-Car M3-N (r8a77965), including core and module clocks. Based on Table 8.2d of "R-Car Series, 3rd Generation User's Manual: Hardware (Rev. 0.80, Oct 31, 2017)". Signed-off-by: Jacopo Mondi Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 5 +- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r8a77965-cpg-mssr.c | 334 +++++++++++++++++++++ drivers/clk/renesas/renesas-cpg-mssr.c | 6 + drivers/clk/renesas/renesas-cpg-mssr.h | 1 + include/dt-bindings/clock/r8a77965-cpg-mssr.h | 62 ++++ 7 files changed, 412 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/renesas/r8a77965-cpg-mssr.c create mode 100644 include/dt-bindings/clock/r8a77965-cpg-mssr.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt index bc4ea0868dbc..773a5226342f 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt @@ -22,6 +22,7 @@ Required Properties: - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) + - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N) - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M) - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H) - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) @@ -33,8 +34,8 @@ Required Properties: clock-names - clock-names: List of external parent clock names. Valid names are: - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, - r8a7795, r8a7796, r8a77970, r8a77980, r8a77995) - - "extalr" (r8a7795, r8a7796, r8a77970, r8a77980) + r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995) + - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980) - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794) - #clock-cells: Must be 2 diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 43bab4f9c4e2..ef76c861ec84 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -15,6 +15,7 @@ config CLK_RENESAS select CLK_R8A7794 if ARCH_R8A7794 select CLK_R8A7795 if ARCH_R8A7795 select CLK_R8A7796 if ARCH_R8A7796 + select CLK_R8A77965 if ARCH_R8A77965 select CLK_R8A77970 if ARCH_R8A77970 select CLK_R8A77980 if ARCH_R8A77980 select CLK_R8A77995 if ARCH_R8A77995 @@ -98,6 +99,10 @@ config CLK_R8A7796 bool "R-Car M3-W clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG +config CLK_R8A77965 + bool "R-Car M3-N clock support" if COMPILE_TEST + select CLK_RCAR_GEN3_CPG + config CLK_R8A77970 bool "R-Car V3M clock support" if COMPILE_TEST select CLK_RCAR_GEN3_CPG diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index e20fa195d107..6c0f19636e3e 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c new file mode 100644 index 000000000000..41e506ab557d --- /dev/null +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * r8a77965 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2018 Jacopo Mondi + * + * Based on r8a7795-cpg-mssr.c + * + * Copyright (C) 2015 Glider bvba + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R8A77965_CLK_OSC, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_EXTALR, + + /* Internal Core Clocks */ + CLK_MAIN, + CLK_PLL0, + CLK_PLL1, + CLK_PLL3, + CLK_PLL4, + CLK_PLL1_DIV2, + CLK_PLL1_DIV4, + CLK_S0, + CLK_S1, + CLK_S2, + CLK_S3, + CLK_SDSRC, + CLK_SSPSRC, + CLK_RINT, + + /* Module Clocks */ + MOD_CLK_BASE +}; + +static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + + /* Core Clock Outputs */ + DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), + DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1), + DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1), + DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1), + DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1), + DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1), + DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1), + DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1), + DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1), + + DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074), + DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078), + DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c), + + DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1), + + DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), + DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014), + DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250), + + DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + + DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), +}; + +static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { + DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), + DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), + DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), + DEF_MOD("scif1", 206, R8A77965_CLK_S3D4), + DEF_MOD("scif0", 207, R8A77965_CLK_S3D4), + DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), + DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), + DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), + + DEF_MOD("cmt3", 300, R8A77965_CLK_R), + DEF_MOD("cmt2", 301, R8A77965_CLK_R), + DEF_MOD("cmt1", 302, R8A77965_CLK_R), + DEF_MOD("cmt0", 303, R8A77965_CLK_R), + DEF_MOD("scif2", 310, R8A77965_CLK_S3D4), + DEF_MOD("sdif3", 311, R8A77965_CLK_SD3), + DEF_MOD("sdif2", 312, R8A77965_CLK_SD2), + DEF_MOD("sdif1", 313, R8A77965_CLK_SD1), + DEF_MOD("sdif0", 314, R8A77965_CLK_SD0), + DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1), + DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1), + + DEF_MOD("rwdt", 402, R8A77965_CLK_R), + DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3), + + DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3), + DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3), + DEF_MOD("drif7", 508, R8A77965_CLK_S3D2), + DEF_MOD("drif6", 509, R8A77965_CLK_S3D2), + DEF_MOD("drif5", 510, R8A77965_CLK_S3D2), + DEF_MOD("drif4", 511, R8A77965_CLK_S3D2), + DEF_MOD("drif3", 512, R8A77965_CLK_S3D2), + DEF_MOD("drif2", 513, R8A77965_CLK_S3D2), + DEF_MOD("drif1", 514, R8A77965_CLK_S3D2), + DEF_MOD("drif0", 515, R8A77965_CLK_S3D2), + DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1), + DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1), + DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1), + DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1), + DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1), + DEF_MOD("thermal", 522, R8A77965_CLK_CP), + DEF_MOD("pwm", 523, R8A77965_CLK_S0D12), + + DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2), + DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2), + DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1), + DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1), + DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1), + DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2), + DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2), + DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2), + DEF_MOD("vspb", 626, R8A77965_CLK_S0D1), + DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1), + + DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4), + DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), + DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), + DEF_MOD("du2", 722, R8A77965_CLK_S2D1), + DEF_MOD("du1", 723, R8A77965_CLK_S2D1), + DEF_MOD("du0", 724, R8A77965_CLK_S2D1), + DEF_MOD("lvds", 727, R8A77965_CLK_S2D1), + DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI), + + DEF_MOD("vin7", 804, R8A77965_CLK_S0D2), + DEF_MOD("vin6", 805, R8A77965_CLK_S0D2), + DEF_MOD("vin5", 806, R8A77965_CLK_S0D2), + DEF_MOD("vin4", 807, R8A77965_CLK_S0D2), + DEF_MOD("vin3", 808, R8A77965_CLK_S0D2), + DEF_MOD("vin2", 809, R8A77965_CLK_S0D2), + DEF_MOD("vin1", 810, R8A77965_CLK_S0D2), + DEF_MOD("vin0", 811, R8A77965_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6), + DEF_MOD("imr1", 822, R8A77965_CLK_S0D2), + DEF_MOD("imr0", 823, R8A77965_CLK_S0D2), + + DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4), + DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4), + DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4), + DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4), + DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4), + DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4), + DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2), + DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4), + DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4), + DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6), + DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6), + DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP), + DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6), + DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6), + DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2), + DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2), + DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2), + + DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4), + DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), + DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), + DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), + DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), + DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), + DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), + DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), + DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), + DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), + DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4), + DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), + DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), + DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), + DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), + DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), + DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), + DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), + DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), + DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), + DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), + DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), + DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), + DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), +}; + +static const unsigned int r8a77965_crit_mod_clks[] __initconst = { + MOD_CLK_ID(408), /* INTC-AP (GIC) */ +}; + +/* + * CPG Clock Data + */ + +/* + * MD EXTAL PLL0 PLL1 PLL3 PLL4 + * 14 13 19 17 (MHz) + *----------------------------------------------------------- + * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 + * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 + * 0 0 1 0 Prohibited setting + * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 + * 0 1 0 0 20 x 1 x150 x160 x160 x120 + * 0 1 0 1 20 x 1 x150 x160 x106 x120 + * 0 1 1 0 Prohibited setting + * 0 1 1 1 20 x 1 x150 x160 x160 x120 + * 1 0 0 0 25 x 1 x120 x128 x128 x96 + * 1 0 0 1 25 x 1 x120 x128 x84 x96 + * 1 0 1 0 Prohibited setting + * 1 0 1 1 25 x 1 x120 x128 x128 x96 + * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 + * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 + * 1 1 1 0 Prohibited setting + * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 + */ +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ + (((md) & BIT(13)) >> 11) | \ + (((md) & BIT(19)) >> 18) | \ + (((md) & BIT(17)) >> 17)) + +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { + /* EXTAL div PLL1 mult/div PLL3 mult/div */ + { 1, 192, 1, 192, 1, }, + { 1, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 192, 1, 192, 1, }, + { 1, 160, 1, 160, 1, }, + { 1, 160, 1, 106, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 160, 1, 160, 1, }, + { 1, 128, 1, 128, 1, }, + { 1, 128, 1, 84, 1, }, + { 0, /* Prohibited setting */ }, + { 1, 128, 1, 128, 1, }, + { 2, 192, 1, 192, 1, }, + { 2, 192, 1, 128, 1, }, + { 0, /* Prohibited setting */ }, + { 2, 192, 1, 192, 1, }, +}; + +static int __init r8a77965_cpg_mssr_init(struct device *dev) +{ + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + u32 cpg_mode; + int error; + + error = rcar_rst_read_mode_pins(&cpg_mode); + if (error) + return error; + + cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; + if (!cpg_pll_config->extal_div) { + dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); + return -EINVAL; + } + + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); +}; + +const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = { + /* Core Clocks */ + .core_clks = r8a77965_core_clks, + .num_core_clks = ARRAY_SIZE(r8a77965_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r8a77965_mod_clks, + .num_mod_clks = ARRAY_SIZE(r8a77965_mod_clks), + .num_hw_mod_clks = 12 * 32, + + /* Critical Module Clocks */ + .crit_mod_clks = r8a77965_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a77965_crit_mod_clks), + + /* Callbacks */ + .init = r8a77965_cpg_mssr_init, + .cpg_clk_register = rcar_gen3_cpg_clk_register, +}; diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index aadfa6df6c4d..96c678799623 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -693,6 +693,12 @@ static const struct of_device_id cpg_mssr_match[] = { .data = &r8a7796_cpg_mssr_info, }, #endif +#ifdef CONFIG_CLK_R8A77965 + { + .compatible = "renesas,r8a77965-cpg-mssr", + .data = &r8a77965_cpg_mssr_info, + }, +#endif #ifdef CONFIG_CLK_R8A77970 { .compatible = "renesas,r8a77970-cpg-mssr", diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 143293e3d193..97ccb093c10f 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -139,6 +139,7 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info; extern const struct cpg_mssr_info r8a7794_cpg_mssr_info; extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; +extern const struct cpg_mssr_info r8a77965_cpg_mssr_info; extern const struct cpg_mssr_info r8a77970_cpg_mssr_info; extern const struct cpg_mssr_info r8a77980_cpg_mssr_info; extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h new file mode 100644 index 000000000000..6d3b5a9a6084 --- /dev/null +++ b/include/dt-bindings/clock/r8a77965-cpg-mssr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Jacopo Mondi + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ + +#include + +/* r8a77965 CPG Core Clocks */ +#define R8A77965_CLK_Z 0 +#define R8A77965_CLK_ZR 1 +#define R8A77965_CLK_ZG 2 +#define R8A77965_CLK_ZTR 3 +#define R8A77965_CLK_ZTRD2 4 +#define R8A77965_CLK_ZT 5 +#define R8A77965_CLK_ZX 6 +#define R8A77965_CLK_S0D1 7 +#define R8A77965_CLK_S0D2 8 +#define R8A77965_CLK_S0D3 9 +#define R8A77965_CLK_S0D4 10 +#define R8A77965_CLK_S0D6 11 +#define R8A77965_CLK_S0D8 12 +#define R8A77965_CLK_S0D12 13 +#define R8A77965_CLK_S1D1 14 +#define R8A77965_CLK_S1D2 15 +#define R8A77965_CLK_S1D4 16 +#define R8A77965_CLK_S2D1 17 +#define R8A77965_CLK_S2D2 18 +#define R8A77965_CLK_S2D4 19 +#define R8A77965_CLK_S3D1 20 +#define R8A77965_CLK_S3D2 21 +#define R8A77965_CLK_S3D4 22 +#define R8A77965_CLK_LB 23 +#define R8A77965_CLK_CL 24 +#define R8A77965_CLK_ZB3 25 +#define R8A77965_CLK_ZB3D2 26 +#define R8A77965_CLK_CR 27 +#define R8A77965_CLK_CRD2 28 +#define R8A77965_CLK_SD0H 29 +#define R8A77965_CLK_SD0 30 +#define R8A77965_CLK_SD1H 31 +#define R8A77965_CLK_SD1 32 +#define R8A77965_CLK_SD2H 33 +#define R8A77965_CLK_SD2 34 +#define R8A77965_CLK_SD3H 35 +#define R8A77965_CLK_SD3 36 +#define R8A77965_CLK_SSP2 37 +#define R8A77965_CLK_SSP1 38 +#define R8A77965_CLK_SSPRS 39 +#define R8A77965_CLK_RPC 40 +#define R8A77965_CLK_RPCD2 41 +#define R8A77965_CLK_MSO 42 +#define R8A77965_CLK_CANFD 43 +#define R8A77965_CLK_HDMI 44 +#define R8A77965_CLK_CSI0 45 +#define R8A77965_CLK_CP 46 +#define R8A77965_CLK_CPEX 47 +#define R8A77965_CLK_R 48 +#define R8A77965_CLK_OSC 49 + +#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */ -- cgit v1.2.3 From 994f46610bafd75a5881544bce9dd3acdbe3626a Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Mon, 19 Feb 2018 16:00:35 +0100 Subject: ASoC: stm32: Add S/PDIF to SAI bindings Add S/PDIF IEC6958 protocol support to STM32 SAI bindings. Signed-off-by: olivier moysan Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/st,stm32-sai.txt | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt index b1acc1a256ba..f301cdf0b7e6 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt @@ -45,6 +45,12 @@ SAI subnodes Optional properties: This property sets SAI sub-block as slave of another SAI sub-block. Must contain the phandle and index of the sai sub-block providing the synchronization. + - st,iec60958: support S/PDIF IEC6958 protocol for playback + IEC60958 protocol is not available for capture. + By default, custom protocol is assumed, meaning that protocol is + configured according to protocol defined in related DAI link node, + such as i2s, left justified, right justified, dsp and pdm protocols. + Note: ac97 protocol is not supported by SAI driver The device node should contain one 'port' child node with one child 'endpoint' node, according to the bindings defined in Documentation/devicetree/bindings/ -- cgit v1.2.3 From 9f57ccdcf4ab86c5d0149d39458ccce2a229c9ec Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 18 Dec 2017 05:16:28 -0500 Subject: media: dt-bindings: coda: Add compatible for CodaHx4 on i.MX51 Add a compatible for the CodaHx4 VPU used on i.MX51. Signed-off-by: Philipp Zabel Reviewed-by: Rob Herring Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/coda.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/coda.txt b/Documentation/devicetree/bindings/media/coda.txt index 2865d04e4030..90eb74cc1993 100644 --- a/Documentation/devicetree/bindings/media/coda.txt +++ b/Documentation/devicetree/bindings/media/coda.txt @@ -7,8 +7,9 @@ called VPU (Video Processing Unit). Required properties: - compatible : should be "fsl,-src" for i.MX SoCs: (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27 - (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53 - (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q + (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51 + (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53 + (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q - reg: should be register base and length as documented in the SoC reference manual - interrupts : Should contain the VPU interrupt. For CODA960, -- cgit v1.2.3 From a444e5184f329738691b06ed31addaa0edb6aa01 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Wed, 21 Feb 2018 12:47:55 -0500 Subject: media: dt-bindings: media: Add Renesas CEU bindings Add bindings documentation for Renesas Capture Engine Unit (CEU). Signed-off-by: Jacopo Mondi Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/renesas,ceu.txt | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/renesas,ceu.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.txt b/Documentation/devicetree/bindings/media/renesas,ceu.txt new file mode 100644 index 000000000000..3fc66dfb192c --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,ceu.txt @@ -0,0 +1,81 @@ +Renesas Capture Engine Unit (CEU) +---------------------------------------------- + +The Capture Engine Unit is the image capture interface found in the Renesas +SH Mobile and RZ SoCs. + +The interface supports a single parallel input with data bus width of 8 or 16 +bits. + +Required properties: +- compatible: Shall be "renesas,r7s72100-ceu" for CEU units found in RZ/A1H + and RZ/A1M SoCs. +- reg: Registers address base and size. +- interrupts: The interrupt specifier. + +The CEU supports a single parallel input and should contain a single 'port' +subnode with a single 'endpoint'. Connection to input devices are modeled +according to the video interfaces OF bindings specified in: +Documentation/devicetree/bindings/media/video-interfaces.txt + +Optional endpoint properties applicable to parallel input bus described in +the above mentioned "video-interfaces.txt" file are supported. + +- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. + If property is not present, default is active high. +- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. + If property is not present, default is active high. + +Example: + +The example describes the connection between the Capture Engine Unit and an +OV7670 image sensor connected to i2c1 interface. + +ceu: ceu@e8210000 { + reg = <0xe8210000 0x209c>; + compatible = "renesas,r7s72100-ceu"; + interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&vio_pins>; + + status = "okay"; + + port { + ceu_in: endpoint { + remote-endpoint = <&ov7670_out>; + + hsync-active = <1>; + vsync-active = <0>; + }; + }; +}; + +i2c1: i2c@fcfee400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + + clock-frequency = <100000>; + + ov7670: camera@21 { + compatible = "ovti,ov7670"; + reg = <0x21>; + + pinctrl-names = "default"; + pinctrl-0 = <&vio_pins>; + + reset-gpios = <&port3 11 GPIO_ACTIVE_LOW>; + powerdown-gpios = <&port3 12 GPIO_ACTIVE_HIGH>; + + port { + ov7670_out: endpoint { + remote-endpoint = <&ceu_in>; + + hsync-active = <1>; + vsync-active = <0>; + }; + }; + }; +}; -- cgit v1.2.3 From be2ed207e3745392478e85afa0bb02acdf44c966 Mon Sep 17 00:00:00 2001 From: Haiyue Wang Date: Fri, 2 Feb 2018 10:16:11 +0800 Subject: ipmi: add an Aspeed KCS IPMI BMC driver The KCS (Keyboard Controller Style) interface is used to perform in-band IPMI communication between a server host and its BMC (BaseBoard Management Controllers). This driver exposes the KCS interface on ASpeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are commonly used as BMCs and this driver implements the BMC side of the KCS interface. Signed-off-by: Haiyue Wang Signed-off-by: Corey Minyard --- .../devicetree/bindings/ipmi/aspeed-kcs-bmc.txt | 25 ++ drivers/char/ipmi/Kconfig | 12 + drivers/char/ipmi/Makefile | 1 + drivers/char/ipmi/kcs_bmc_aspeed.c | 319 +++++++++++++++++++++ 4 files changed, 357 insertions(+) create mode 100644 Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt create mode 100644 drivers/char/ipmi/kcs_bmc_aspeed.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt new file mode 100644 index 000000000000..d98a9bf45d6c --- /dev/null +++ b/Documentation/devicetree/bindings/ipmi/aspeed-kcs-bmc.txt @@ -0,0 +1,25 @@ +* Aspeed KCS (Keyboard Controller Style) IPMI interface + +The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs +(Baseboard Management Controllers) and the KCS interface can be +used to perform in-band IPMI communication with their host. + +Required properties: +- compatible : should be one of + "aspeed,ast2400-kcs-bmc" + "aspeed,ast2500-kcs-bmc" +- interrupts : interrupt generated by the controller +- kcs_chan : The LPC channel number in the controller +- kcs_addr : The host CPU IO map address + + +Example: + + kcs3: kcs3@0 { + compatible = "aspeed,ast2500-kcs-bmc"; + reg = <0x0 0x80>; + interrupts = <8>; + kcs_chan = <3>; + kcs_addr = <0xCA2>; + status = "okay"; + }; diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig index 7641b8a2f632..3bda116c8aa0 100644 --- a/drivers/char/ipmi/Kconfig +++ b/drivers/char/ipmi/Kconfig @@ -99,6 +99,18 @@ endif # IPMI_HANDLER config IPMI_KCS_BMC tristate +config ASPEED_KCS_IPMI_BMC + depends on ARCH_ASPEED || COMPILE_TEST + select IPMI_KCS_BMC + select REGMAP_MMIO + tristate "Aspeed KCS IPMI BMC driver" + help + Provides a driver for the KCS (Keyboard Controller Style) IPMI + interface found on Aspeed SOCs (AST2400 and AST2500). + + The driver implements the BMC side of the KCS contorller, it + provides the access of KCS IO space for BMC side. + config ASPEED_BT_IPMI_BMC depends on ARCH_ASPEED || COMPILE_TEST depends on REGMAP && REGMAP_MMIO && MFD_SYSCON diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile index 2abccb30016a..21e9e872d973 100644 --- a/drivers/char/ipmi/Makefile +++ b/drivers/char/ipmi/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_IPMI_WATCHDOG) += ipmi_watchdog.o obj-$(CONFIG_IPMI_POWEROFF) += ipmi_poweroff.o obj-$(CONFIG_IPMI_KCS_BMC) += kcs_bmc.o obj-$(CONFIG_ASPEED_BT_IPMI_BMC) += bt-bmc.o +obj-$(CONFIG_ASPEED_KCS_IPMI_BMC) += kcs_bmc_aspeed.o diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b/drivers/char/ipmi/kcs_bmc_aspeed.c new file mode 100644 index 000000000000..0c4d1a36dae4 --- /dev/null +++ b/drivers/char/ipmi/kcs_bmc_aspeed.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2015-2018, Intel Corporation. + +#define pr_fmt(fmt) "aspeed-kcs-bmc: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kcs_bmc.h" + + +#define DEVICE_NAME "ast-kcs-bmc" + +#define KCS_CHANNEL_MAX 4 + +/* mapped to lpc-bmc@0 IO space */ +#define LPC_HICR0 0x000 +#define LPC_HICR0_LPC3E BIT(7) +#define LPC_HICR0_LPC2E BIT(6) +#define LPC_HICR0_LPC1E BIT(5) +#define LPC_HICR2 0x008 +#define LPC_HICR2_IBFIF3 BIT(3) +#define LPC_HICR2_IBFIF2 BIT(2) +#define LPC_HICR2_IBFIF1 BIT(1) +#define LPC_HICR4 0x010 +#define LPC_HICR4_LADR12AS BIT(7) +#define LPC_HICR4_KCSENBL BIT(2) +#define LPC_LADR3H 0x014 +#define LPC_LADR3L 0x018 +#define LPC_LADR12H 0x01C +#define LPC_LADR12L 0x020 +#define LPC_IDR1 0x024 +#define LPC_IDR2 0x028 +#define LPC_IDR3 0x02C +#define LPC_ODR1 0x030 +#define LPC_ODR2 0x034 +#define LPC_ODR3 0x038 +#define LPC_STR1 0x03C +#define LPC_STR2 0x040 +#define LPC_STR3 0x044 + +/* mapped to lpc-host@80 IO space */ +#define LPC_HICRB 0x080 +#define LPC_HICRB_IBFIF4 BIT(1) +#define LPC_HICRB_LPC4E BIT(0) +#define LPC_LADR4 0x090 +#define LPC_IDR4 0x094 +#define LPC_ODR4 0x098 +#define LPC_STR4 0x09C + +struct aspeed_kcs_bmc { + struct regmap *map; +}; + + +static u8 aspeed_kcs_inb(struct kcs_bmc *kcs_bmc, u32 reg) +{ + struct aspeed_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc); + u32 val = 0; + int rc; + + rc = regmap_read(priv->map, reg, &val); + WARN(rc != 0, "regmap_read() failed: %d\n", rc); + + return rc == 0 ? (u8) val : 0; +} + +static void aspeed_kcs_outb(struct kcs_bmc *kcs_bmc, u32 reg, u8 data) +{ + struct aspeed_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc); + int rc; + + rc = regmap_write(priv->map, reg, data); + WARN(rc != 0, "regmap_write() failed: %d\n", rc); +} + + +/* + * AST_usrGuide_KCS.pdf + * 2. Background: + * we note D for Data, and C for Cmd/Status, default rules are + * A. KCS1 / KCS2 ( D / C:X / X+4 ) + * D / C : CA0h / CA4h + * D / C : CA8h / CACh + * B. KCS3 ( D / C:XX2h / XX3h ) + * D / C : CA2h / CA3h + * D / C : CB2h / CB3h + * C. KCS4 + * D / C : CA4h / CA5h + */ +static void aspeed_kcs_set_address(struct kcs_bmc *kcs_bmc, u16 addr) +{ + struct aspeed_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc); + + switch (kcs_bmc->channel) { + case 1: + regmap_update_bits(priv->map, LPC_HICR4, + LPC_HICR4_LADR12AS, 0); + regmap_write(priv->map, LPC_LADR12H, addr >> 8); + regmap_write(priv->map, LPC_LADR12L, addr & 0xFF); + break; + + case 2: + regmap_update_bits(priv->map, LPC_HICR4, + LPC_HICR4_LADR12AS, LPC_HICR4_LADR12AS); + regmap_write(priv->map, LPC_LADR12H, addr >> 8); + regmap_write(priv->map, LPC_LADR12L, addr & 0xFF); + break; + + case 3: + regmap_write(priv->map, LPC_LADR3H, addr >> 8); + regmap_write(priv->map, LPC_LADR3L, addr & 0xFF); + break; + + case 4: + regmap_write(priv->map, LPC_LADR4, ((addr + 1) << 16) | + addr); + break; + + default: + break; + } +} + +static void aspeed_kcs_enable_channel(struct kcs_bmc *kcs_bmc, bool enable) +{ + struct aspeed_kcs_bmc *priv = kcs_bmc_priv(kcs_bmc); + + switch (kcs_bmc->channel) { + case 1: + if (enable) { + regmap_update_bits(priv->map, LPC_HICR2, + LPC_HICR2_IBFIF1, LPC_HICR2_IBFIF1); + regmap_update_bits(priv->map, LPC_HICR0, + LPC_HICR0_LPC1E, LPC_HICR0_LPC1E); + } else { + regmap_update_bits(priv->map, LPC_HICR0, + LPC_HICR0_LPC1E, 0); + regmap_update_bits(priv->map, LPC_HICR2, + LPC_HICR2_IBFIF1, 0); + } + break; + + case 2: + if (enable) { + regmap_update_bits(priv->map, LPC_HICR2, + LPC_HICR2_IBFIF2, LPC_HICR2_IBFIF2); + regmap_update_bits(priv->map, LPC_HICR0, + LPC_HICR0_LPC2E, LPC_HICR0_LPC2E); + } else { + regmap_update_bits(priv->map, LPC_HICR0, + LPC_HICR0_LPC2E, 0); + regmap_update_bits(priv->map, LPC_HICR2, + LPC_HICR2_IBFIF2, 0); + } + break; + + case 3: + if (enable) { + regmap_update_bits(priv->map, LPC_HICR2, + LPC_HICR2_IBFIF3, LPC_HICR2_IBFIF3); + regmap_update_bits(priv->map, LPC_HICR0, + LPC_HICR0_LPC3E, LPC_HICR0_LPC3E); + regmap_update_bits(priv->map, LPC_HICR4, + LPC_HICR4_KCSENBL, LPC_HICR4_KCSENBL); + } else { + regmap_update_bits(priv->map, LPC_HICR0, + LPC_HICR0_LPC3E, 0); + regmap_update_bits(priv->map, LPC_HICR4, + LPC_HICR4_KCSENBL, 0); + regmap_update_bits(priv->map, LPC_HICR2, + LPC_HICR2_IBFIF3, 0); + } + break; + + case 4: + if (enable) + regmap_update_bits(priv->map, LPC_HICRB, + LPC_HICRB_IBFIF4 | LPC_HICRB_LPC4E, + LPC_HICRB_IBFIF4 | LPC_HICRB_LPC4E); + else + regmap_update_bits(priv->map, LPC_HICRB, + LPC_HICRB_IBFIF4 | LPC_HICRB_LPC4E, + 0); + break; + + default: + break; + } +} + +static irqreturn_t aspeed_kcs_irq(int irq, void *arg) +{ + struct kcs_bmc *kcs_bmc = arg; + + if (!kcs_bmc_handle_event(kcs_bmc)) + return IRQ_HANDLED; + + return IRQ_NONE; +} + +static int aspeed_kcs_config_irq(struct kcs_bmc *kcs_bmc, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int irq; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + return devm_request_irq(dev, irq, aspeed_kcs_irq, IRQF_SHARED, + dev_name(dev), kcs_bmc); +} + +static const struct kcs_ioreg ast_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = { + { .idr = LPC_IDR1, .odr = LPC_ODR1, .str = LPC_STR1 }, + { .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 }, + { .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 }, + { .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 }, +}; + +static int aspeed_kcs_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct aspeed_kcs_bmc *priv; + struct kcs_bmc *kcs_bmc; + u32 chan, addr; + int rc; + + rc = of_property_read_u32(dev->of_node, "kcs_chan", &chan); + if ((rc != 0) || (chan == 0 || chan > KCS_CHANNEL_MAX)) { + dev_err(dev, "no valid 'kcs_chan' configured\n"); + return -ENODEV; + } + + rc = of_property_read_u32(dev->of_node, "kcs_addr", &addr); + if (rc) { + dev_err(dev, "no valid 'kcs_addr' configured\n"); + return -ENODEV; + } + + kcs_bmc = kcs_bmc_alloc(dev, sizeof(*priv), chan); + if (!kcs_bmc) + return -ENOMEM; + + priv = kcs_bmc_priv(kcs_bmc); + priv->map = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->map)) { + dev_err(dev, "Couldn't get regmap\n"); + return -ENODEV; + } + + kcs_bmc->ioreg = ast_kcs_bmc_ioregs[chan - 1]; + kcs_bmc->io_inputb = aspeed_kcs_inb; + kcs_bmc->io_outputb = aspeed_kcs_outb; + + dev_set_drvdata(dev, kcs_bmc); + + aspeed_kcs_set_address(kcs_bmc, addr); + aspeed_kcs_enable_channel(kcs_bmc, true); + rc = aspeed_kcs_config_irq(kcs_bmc, pdev); + if (rc) + return rc; + + rc = misc_register(&kcs_bmc->miscdev); + if (rc) { + dev_err(dev, "Unable to register device\n"); + return rc; + } + + pr_info("channel=%u addr=0x%x idr=0x%x odr=0x%x str=0x%x\n", + chan, addr, + kcs_bmc->ioreg.idr, kcs_bmc->ioreg.odr, kcs_bmc->ioreg.str); + + return 0; +} + +static int aspeed_kcs_remove(struct platform_device *pdev) +{ + struct kcs_bmc *kcs_bmc = dev_get_drvdata(&pdev->dev); + + misc_deregister(&kcs_bmc->miscdev); + + return 0; +} + +static const struct of_device_id ast_kcs_bmc_match[] = { + { .compatible = "aspeed,ast2400-kcs-bmc" }, + { .compatible = "aspeed,ast2500-kcs-bmc" }, + { } +}; + +static struct platform_driver ast_kcs_bmc_driver = { + .driver = { + .name = DEVICE_NAME, + .of_match_table = ast_kcs_bmc_match, + }, + .probe = aspeed_kcs_probe, + .remove = aspeed_kcs_remove, +}; + +module_platform_driver(ast_kcs_bmc_driver); + +MODULE_DEVICE_TABLE(of, ast_kcs_bmc_match); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Haiyue Wang "); +MODULE_DESCRIPTION("Aspeed device interface to the KCS BMC device"); -- cgit v1.2.3 From d0adf769df210248f60d33e62b1d4d14df271c02 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 29 Jan 2018 16:45:47 +0100 Subject: dt-bindings: i2c: document R8A77995 bindings R-Car D3 (R8A77995) SoC has a R-Car Gen3-compatible I2C controller. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index a777477e4547..e91dbafe71e5 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -14,6 +14,7 @@ Required properties: "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. + "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC. "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible device. -- cgit v1.2.3 From 4a4b0f176b848e5050d75cacbdcf9aa86bef7848 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 19:03:42 +0100 Subject: dt-bindings: arm: Document SoC compatible value for Armadillo-800 EVA The compatible property of the root node in a DTS for Atmark Techno Armadillo-800 EVA should include the compatible value for the R-Mobile A1 SoC, too. Fixes: d2c2a0776899ba2d ("ARM: shmobile: Add platform device tree bindings documentation") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 63edc11e83ef..a99359e63b0a 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -56,7 +56,7 @@ Boards: - APE6-EVM compatible = "renesas,ape6evm", "renesas,r8a73a4" - Atmark Techno Armadillo-800 EVA - compatible = "renesas,armadillo800eva" + compatible = "renesas,armadillo800eva", "renesas,r8a7740" - Blanche (RTP0RC7792SEB00010S) compatible = "renesas,blanche", "renesas,r8a7792" - BOCK-W -- cgit v1.2.3 From 790d631dcfec6b073b04bb6809bce4c09baf198a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Feb 2018 22:24:49 -0300 Subject: ASoC: imx-wm8962: Remove machine driver fsl-asoc-card machine driver also handles wm8962, so there is really no need for keeping the dedicated imx-wm8962 driver anymore. Remove the imx-wm8962 machine driver. Suggested-by: Nicolin Chen Signed-off-by: Fabio Estevam Acked-by: Nicolin Chen Reviewed-by: Daniel Baluta Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/fsl-asoc-card.txt | 1 - .../devicetree/bindings/sound/imx-audio-wm8962.txt | 53 ---- sound/soc/fsl/Kconfig | 11 - sound/soc/fsl/Makefile | 2 - sound/soc/fsl/imx-wm8962.c | 312 --------------------- 5 files changed, 379 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt delete mode 100644 sound/soc/fsl/imx-wm8962.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt index f749e2744824..c60a5732d29c 100644 --- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt @@ -28,7 +28,6 @@ The compatible list for this generic sound card currently: (compatible with CS4271 and CS4272) "fsl,imx-audio-wm8962" - (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt) "fsl,imx-audio-sgtl5000" (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt deleted file mode 100644 index acea71bee34f..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt +++ /dev/null @@ -1,53 +0,0 @@ -Freescale i.MX audio complex with WM8962 codec - -Required properties: - - - compatible : "fsl,imx-audio-wm8962" - - - model : The user-visible name of this sound complex - - - ssi-controller : The phandle of the i.MX SSI controller - - - audio-codec : The phandle of the WM8962 audio codec - - - audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, WM8962 - pins, and the jacks on the board: - - Power supplies: - * Mic Bias - - Board connectors: - * Mic Jack - * Headphone Jack - * Ext Spk - - - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) - - - mux-ext-port : The external port of the i.MX audio muxer - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - -sound { - compatible = "fsl,imx6q-sabresd-wm8962", - "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - ssi-controller = <&ssi2>; - audio-codec = <&codec>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "MICBIAS", "AMIC", - "IN3R", "MICBIAS", - "DMIC", "MICBIAS", - "DMICDAT", "DMIC"; - mux-int-port = <2>; - mux-ext-port = <3>; -}; diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 37f9b6201918..6ec19fb4a934 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -231,17 +231,6 @@ config SND_SOC_EUKREA_TLV320 Enable I2S based access to the TLV320AIC23B codec attached to the SSI interface -config SND_SOC_IMX_WM8962 - tristate "SoC Audio support for i.MX boards with wm8962" - depends on OF && I2C && INPUT - select SND_SOC_WM8962 - select SND_SOC_IMX_PCM_DMA - select SND_SOC_IMX_AUDMUX - select SND_SOC_FSL_SSI - help - Say Y if you want to add support for SoC audio on an i.MX board with - a wm8962 codec. - config SND_SOC_IMX_ES8328 tristate "SoC Audio support for i.MX boards with the ES8328 codec" depends on OF && (I2C || SPI) diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile index c67bf1139e1e..de94fa057e24 100644 --- a/sound/soc/fsl/Makefile +++ b/sound/soc/fsl/Makefile @@ -55,7 +55,6 @@ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o snd-soc-wm1133-ev1-objs := wm1133-ev1.o snd-soc-imx-es8328-objs := imx-es8328.o snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o -snd-soc-imx-wm8962-objs := imx-wm8962.o snd-soc-imx-spdif-objs := imx-spdif.o snd-soc-imx-mc13783-objs := imx-mc13783.o @@ -65,6 +64,5 @@ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o obj-$(CONFIG_SND_SOC_IMX_ES8328) += snd-soc-imx-es8328.o obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o -obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o diff --git a/sound/soc/fsl/imx-wm8962.c b/sound/soc/fsl/imx-wm8962.c deleted file mode 100644 index 206b898e554c..000000000000 --- a/sound/soc/fsl/imx-wm8962.c +++ /dev/null @@ -1,312 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Based on imx-sgtl5000.c - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../codecs/wm8962.h" -#include "imx-audmux.h" - -#define DAI_NAME_SIZE 32 - -struct imx_wm8962_data { - struct snd_soc_dai_link dai; - struct snd_soc_card card; - char codec_dai_name[DAI_NAME_SIZE]; - char platform_name[DAI_NAME_SIZE]; - unsigned int clk_frequency; -}; - -struct imx_priv { - struct platform_device *pdev; - int sample_rate; - snd_pcm_format_t sample_format; -}; - -static const struct snd_soc_dapm_widget imx_wm8962_dapm_widgets[] = { - SND_SOC_DAPM_HP("Headphone Jack", NULL), - SND_SOC_DAPM_SPK("Ext Spk", NULL), - SND_SOC_DAPM_MIC("AMIC", NULL), - SND_SOC_DAPM_MIC("DMIC", NULL), -}; - -static int imx_hifi_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct imx_priv *priv = snd_soc_card_get_drvdata(rtd->card); - - priv->sample_rate = params_rate(params); - priv->sample_format = params_format(params); - - return 0; -} - -static const struct snd_soc_ops imx_hifi_ops = { - .hw_params = imx_hifi_hw_params, -}; - -static int imx_wm8962_set_bias_level(struct snd_soc_card *card, - struct snd_soc_dapm_context *dapm, - enum snd_soc_bias_level level) -{ - struct snd_soc_pcm_runtime *rtd; - struct snd_soc_dai *codec_dai; - struct imx_priv *priv = snd_soc_card_get_drvdata(card); - struct imx_wm8962_data *data = snd_soc_card_get_drvdata(card); - struct device *dev = &priv->pdev->dev; - unsigned int pll_out; - int ret; - - rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name); - codec_dai = rtd->codec_dai; - if (dapm->dev != codec_dai->dev) - return 0; - - switch (level) { - case SND_SOC_BIAS_PREPARE: - if (dapm->bias_level == SND_SOC_BIAS_STANDBY) { - if (priv->sample_format == SNDRV_PCM_FORMAT_S24_LE) - pll_out = priv->sample_rate * 384; - else - pll_out = priv->sample_rate * 256; - - ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL, - WM8962_FLL_MCLK, data->clk_frequency, - pll_out); - if (ret < 0) { - dev_err(dev, "failed to start FLL: %d\n", ret); - return ret; - } - - ret = snd_soc_dai_set_sysclk(codec_dai, - WM8962_SYSCLK_FLL, pll_out, - SND_SOC_CLOCK_IN); - if (ret < 0) { - dev_err(dev, "failed to set SYSCLK: %d\n", ret); - return ret; - } - } - break; - - case SND_SOC_BIAS_STANDBY: - if (dapm->bias_level == SND_SOC_BIAS_PREPARE) { - ret = snd_soc_dai_set_sysclk(codec_dai, - WM8962_SYSCLK_MCLK, data->clk_frequency, - SND_SOC_CLOCK_IN); - if (ret < 0) { - dev_err(dev, - "failed to switch away from FLL: %d\n", - ret); - return ret; - } - - ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL, - 0, 0, 0); - if (ret < 0) { - dev_err(dev, "failed to stop FLL: %d\n", ret); - return ret; - } - } - break; - - default: - break; - } - - return 0; -} - -static int imx_wm8962_late_probe(struct snd_soc_card *card) -{ - struct snd_soc_pcm_runtime *rtd; - struct snd_soc_dai *codec_dai; - struct imx_priv *priv = snd_soc_card_get_drvdata(card); - struct imx_wm8962_data *data = snd_soc_card_get_drvdata(card); - struct device *dev = &priv->pdev->dev; - int ret; - - rtd = snd_soc_get_pcm_runtime(card, card->dai_link[0].name); - codec_dai = rtd->codec_dai; - ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK, - data->clk_frequency, SND_SOC_CLOCK_IN); - if (ret < 0) - dev_err(dev, "failed to set sysclk in %s\n", __func__); - - return ret; -} - -static int imx_wm8962_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *ssi_np, *codec_np; - struct platform_device *ssi_pdev; - struct i2c_client *codec_dev; - struct imx_wm8962_data *data; - struct imx_priv *priv; - struct clk *codec_clk; - int int_port, ext_port; - int ret; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->pdev = pdev; - priv->sample_rate = 44100; - priv->sample_format = SNDRV_PCM_FORMAT_S16_LE; - - ret = of_property_read_u32(np, "mux-int-port", &int_port); - if (ret) { - dev_err(&pdev->dev, "mux-int-port missing or invalid\n"); - return ret; - } - ret = of_property_read_u32(np, "mux-ext-port", &ext_port); - if (ret) { - dev_err(&pdev->dev, "mux-ext-port missing or invalid\n"); - return ret; - } - - /* - * The port numbering in the hardware manual starts at 1, while - * the audmux API expects it starts at 0. - */ - int_port--; - ext_port--; - ret = imx_audmux_v2_configure_port(int_port, - IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) | - IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TCLKDIR, - IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port)); - if (ret) { - dev_err(&pdev->dev, "audmux internal port setup failed\n"); - return ret; - } - ret = imx_audmux_v2_configure_port(ext_port, - IMX_AUDMUX_V2_PTCR_SYN, - IMX_AUDMUX_V2_PDCR_RXDSEL(int_port)); - if (ret) { - dev_err(&pdev->dev, "audmux external port setup failed\n"); - return ret; - } - - ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0); - codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0); - if (!ssi_np || !codec_np) { - dev_err(&pdev->dev, "phandle missing or invalid\n"); - ret = -EINVAL; - goto fail; - } - - ssi_pdev = of_find_device_by_node(ssi_np); - if (!ssi_pdev) { - dev_err(&pdev->dev, "failed to find SSI platform device\n"); - ret = -EINVAL; - goto fail; - } - codec_dev = of_find_i2c_device_by_node(codec_np); - if (!codec_dev || !codec_dev->dev.driver) { - dev_err(&pdev->dev, "failed to find codec platform device\n"); - ret = -EINVAL; - goto fail; - } - - data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); - if (!data) { - ret = -ENOMEM; - goto fail; - } - - codec_clk = clk_get(&codec_dev->dev, NULL); - if (IS_ERR(codec_clk)) { - ret = PTR_ERR(codec_clk); - dev_err(&codec_dev->dev, "failed to get codec clk: %d\n", ret); - goto fail; - } - - data->clk_frequency = clk_get_rate(codec_clk); - clk_put(codec_clk); - - data->dai.name = "HiFi"; - data->dai.stream_name = "HiFi"; - data->dai.codec_dai_name = "wm8962"; - data->dai.codec_of_node = codec_np; - data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev); - data->dai.platform_of_node = ssi_np; - data->dai.ops = &imx_hifi_ops; - data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBM_CFM; - - data->card.dev = &pdev->dev; - ret = snd_soc_of_parse_card_name(&data->card, "model"); - if (ret) - goto fail; - ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing"); - if (ret) - goto fail; - data->card.num_links = 1; - data->card.owner = THIS_MODULE; - data->card.dai_link = &data->dai; - data->card.dapm_widgets = imx_wm8962_dapm_widgets; - data->card.num_dapm_widgets = ARRAY_SIZE(imx_wm8962_dapm_widgets); - - data->card.late_probe = imx_wm8962_late_probe; - data->card.set_bias_level = imx_wm8962_set_bias_level; - - platform_set_drvdata(pdev, &data->card); - snd_soc_card_set_drvdata(&data->card, data); - - ret = devm_snd_soc_register_card(&pdev->dev, &data->card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); - goto fail; - } - -fail: - of_node_put(ssi_np); - of_node_put(codec_np); - - return ret; -} - -static const struct of_device_id imx_wm8962_dt_ids[] = { - { .compatible = "fsl,imx-audio-wm8962", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx_wm8962_dt_ids); - -static struct platform_driver imx_wm8962_driver = { - .driver = { - .name = "imx-wm8962", - .pm = &snd_soc_pm_ops, - .of_match_table = imx_wm8962_dt_ids, - }, - .probe = imx_wm8962_probe, -}; -module_platform_driver(imx_wm8962_driver); - -MODULE_AUTHOR("Freescale Semiconductor, Inc."); -MODULE_DESCRIPTION("Freescale i.MX WM8962 ASoC machine driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:imx-wm8962"); -- cgit v1.2.3 From f5ca3ab9bc1b160966c1e5cc7bf831f7b8ec31e5 Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Fri, 23 Feb 2018 10:17:16 +0900 Subject: ASoC: add DT bindings documentation for ROHM BD28623 codec This patch adds DT bindings documentation for ROHM BD28623MUV class D speaker amplifier. Signed-off-by: Katsuhiro Suzuki Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/rohm,bd28623.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rohm,bd28623.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rohm,bd28623.txt b/Documentation/devicetree/bindings/sound/rohm,bd28623.txt new file mode 100644 index 000000000000..d84557c2686e --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rohm,bd28623.txt @@ -0,0 +1,29 @@ +ROHM BD28623MUV Class D speaker amplifier for digital input + +This codec does not have any control buses such as I2C, it detect format and +rate of I2S signal automatically. It has two signals that can be connected +to GPIOs: reset and mute. + +Required properties: +- compatible : should be "rohm,bd28623" +- #sound-dai-cells: should be 0. +- VCCA-supply : regulator phandle for the VCCA supply +- VCCP1-supply : regulator phandle for the VCCP1 supply +- VCCP2-supply : regulator phandle for the VCCP2 supply + +Optional properties: +- reset-gpios : GPIO specifier for the active low reset line +- mute-gpios : GPIO specifier for the active low mute line + +Example: + + codec { + compatible = "rohm,bd28623"; + #sound-dai-cells = <0>; + + VCCA-supply = <&vcc_reg>; + VCCP1-supply = <&vcc_reg>; + VCCP2-supply = <&vcc_reg>; + reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + mute-gpios = <&gpio 1 GPIO_ACTIVE_LOW>; + }; -- cgit v1.2.3 From e51acdb0308b6f2339e5e48636ce452baab5201b Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Tue, 16 Jan 2018 15:56:00 +0100 Subject: dt-bindings: stm32: add support of STM32MP157 This patch adds STM32MP157 SoC bindings. Signed-off-by: Ludovic Barre Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt index 05762b08a7bb..6808ed9ddfd5 100644 --- a/Documentation/devicetree/bindings/arm/stm32.txt +++ b/Documentation/devicetree/bindings/arm/stm32.txt @@ -7,3 +7,4 @@ using one of the following compatible strings: st,stm32f469 st,stm32f746 st,stm32h743 + st,stm32mp157 -- cgit v1.2.3 From 84cb55c422816d96e8871f7663194949eca98fa6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 16:26:43 +0100 Subject: dt-bindings: i2c: sh_mobile: Document R-Car M3-N support Document support for the IIC Bus Interface for DVFS (IIC for DVFS) in the Renesas M3-N (r8a77965) SoC. No driver update is needed. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt index 224390999e81..fc7e17802746 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt @@ -13,6 +13,7 @@ Required properties: - "renesas,iic-r8a7794" (R-Car E2) - "renesas,iic-r8a7795" (R-Car H3) - "renesas,iic-r8a7796" (R-Car M3-W) + - "renesas,iic-r8a77965" (R-Car M3-N) - "renesas,iic-sh73a0" (SH-Mobile AG5) - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1 compatible device) -- cgit v1.2.3 From afe761f8d3e99155b76833421e76553a3ac69577 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 23 Feb 2018 09:43:57 -0600 Subject: soc: ti: Add pm33xx driver for basic suspend support AM335x and AM437x support various low power modes as documented in section 8.1.4.3 of the AM335x Technical Reference Manual and section 6.4.3 of the AM437x Technical Reference Manual. DeepSleep0 mode offers the lowest power mode with limited wakeup sources without a system reboot and is mapped as the suspend state in the kernel. In this state, MPU and PER domains are turned off with the internal RAM held in retention to facilitate the resume process. As part of the boot process, the assembly code is copied over to OCMCRAM so it can be executed to turn of the EMIF and put DDR into self refresh. Both platforms have a Cortex-M3 (WKUP_M3) which assists the MPU in DeepSleep0 entry and exit. WKUP_M3 takes care of the clockdomain and powerdomain transitions based on the intended low power state. MPU needs to load the appropriate WKUP_M3 binary onto the WKUP_M3 memory space before it can leverage any of the PM features like DeepSleep. This loading is handled by the remoteproc driver wkup_m3_rproc. Communication with the WKUP_M3 is handled by a wkup_m3_ipc driver that exposes the specific PM functionality to be used the PM code. In the current implementation when the suspend process is initiated, MPU interrupts the WKUP_M3 to let it know about the intent of entering DeepSleep0 and waits for an ACK. When the ACK is received MPU continues with its suspend process to suspend all the drivers and then jumps to assembly in OCMC RAM. The assembly code puts the external RAM in self-refresh mode, gates the MPU clock, and then finally executes the WFI instruction. Execution of the WFI instruction with MPU clock gated triggers another interrupt to the WKUP_M3 which then continues with the power down sequence wherein the clockdomain and powerdomain transition takes place. As part of the sleep sequence, WKUP_M3 unmasks the interrupt lines for the wakeup sources. WFI execution on WKUP_M3 causes the hardware to disable the main oscillator of the SoC and from here system remains in sleep state until a wake source brings the system into resume path. When a wakeup event occurs, WKUP_M3 starts the power-up sequence by switching on the power domains and finally enabling the clock to MPU. Since the MPU gets powered down as part of the sleep sequence in the resume path ROM code starts executing. The ROM code detects a wakeup from sleep and then jumps to the resume location in OCMC which was populated in one of the IPC registers as part of the suspend sequence. Code is based on work by Vaibhav Bedia. Signed-off-by: Dave Gerlach Acked-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/arm/omap/mpu.txt | 16 + drivers/soc/ti/Kconfig | 9 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/pm33xx.c | 349 +++++++++++++++++++++ 4 files changed, 375 insertions(+) create mode 100644 drivers/soc/ti/pm33xx.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt index 763695db2bd9..f301e636fd52 100644 --- a/Documentation/devicetree/bindings/arm/omap/mpu.txt +++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt @@ -13,6 +13,13 @@ Required properties: Optional properties: - sram: Phandle to the ocmcram node +am335x and am437x only: +- pm-sram: Phandles to ocmcram nodes to be used for power management. + First should be type 'protect-exec' for the driver to use to copy + and run PM functions, second should be regular pool to be used for + data region for code. See Documentation/devicetree/bindings/sram/sram.txt + for more details. + Examples: - For an OMAP5 SMP system: @@ -36,3 +43,12 @@ mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; }; + +- For an AM335x system: + +mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + pm-sram = <&pm_sram_code + &pm_sram_data>; +}; diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 39e152abe6b9..92770d84a288 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -28,6 +28,15 @@ config KEYSTONE_NAVIGATOR_DMA If unsure, say N. +config AMX3_PM + tristate "AMx3 Power Management" + depends on SOC_AM33XX || SOC_AM43XX + depends on WKUP_M3_IPC && TI_EMIF_SRAM && SRAM + help + Enable power management on AM335x and AM437x. Required for suspend to mem + and standby states on both AM335x and AM437x platforms and for deeper cpuidle + c-states on AM335x. + config WKUP_M3_IPC tristate "TI AMx3 Wkup-M3 IPC Driver" depends on WKUP_M3_RPROC diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index 8e205287f120..a22edc0b258a 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o +obj-$(CONFIG_AMX3_PM) += pm33xx.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o diff --git a/drivers/soc/ti/pm33xx.c b/drivers/soc/ti/pm33xx.c new file mode 100644 index 000000000000..652739c7f718 --- /dev/null +++ b/drivers/soc/ti/pm33xx.c @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM33XX Power Management Routines + * + * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Bedia, Dave Gerlach + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \ + (unsigned long)pm_sram->do_wfi) + +static int (*am33xx_do_wfi_sram)(unsigned long unused); +static phys_addr_t am33xx_do_wfi_sram_phys; + +static struct gen_pool *sram_pool, *sram_pool_data; +static unsigned long ocmcram_location, ocmcram_location_data; + +static struct am33xx_pm_platform_data *pm_ops; +static struct am33xx_pm_sram_addr *pm_sram; + +static struct device *pm33xx_dev; +static struct wkup_m3_ipc *m3_ipc; + +static u32 sram_suspend_address(unsigned long addr) +{ + return ((unsigned long)am33xx_do_wfi_sram + + AMX3_PM_SRAM_SYMBOL_OFFSET(addr)); +} + +#ifdef CONFIG_SUSPEND +static int am33xx_pm_suspend(suspend_state_t suspend_state) +{ + int i, ret = 0; + + ret = pm_ops->soc_suspend((unsigned long)suspend_state, + am33xx_do_wfi_sram); + + if (ret) { + dev_err(pm33xx_dev, "PM: Kernel suspend failure\n"); + } else { + i = m3_ipc->ops->request_pm_status(m3_ipc); + + switch (i) { + case 0: + dev_info(pm33xx_dev, + "PM: Successfully put all powerdomains to target state\n"); + break; + case 1: + dev_err(pm33xx_dev, + "PM: Could not transition all powerdomains to target state\n"); + ret = -1; + break; + default: + dev_err(pm33xx_dev, + "PM: CM3 returned unknown result = %d\n", i); + ret = -1; + } + } + + return ret; +} + +static int am33xx_pm_enter(suspend_state_t suspend_state) +{ + int ret = 0; + + switch (suspend_state) { + case PM_SUSPEND_MEM: + case PM_SUSPEND_STANDBY: + ret = am33xx_pm_suspend(suspend_state); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int am33xx_pm_begin(suspend_state_t state) +{ + int ret = -EINVAL; + + switch (state) { + case PM_SUSPEND_MEM: + ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP); + break; + case PM_SUSPEND_STANDBY: + ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY); + break; + } + + return ret; +} + +static void am33xx_pm_end(void) +{ + m3_ipc->ops->finish_low_power(m3_ipc); +} + +static int am33xx_pm_valid(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + case PM_SUSPEND_MEM: + return 1; + default: + return 0; + } +} + +static const struct platform_suspend_ops am33xx_pm_ops = { + .begin = am33xx_pm_begin, + .end = am33xx_pm_end, + .enter = am33xx_pm_enter, + .valid = am33xx_pm_valid, +}; +#endif /* CONFIG_SUSPEND */ + +static void am33xx_pm_set_ipc_ops(void) +{ + u32 resume_address; + int temp; + + temp = ti_emif_get_mem_type(); + if (temp < 0) { + dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n"); + return; + } + m3_ipc->ops->set_mem_type(m3_ipc, temp); + + /* Physical resume address to be used by ROM code */ + resume_address = am33xx_do_wfi_sram_phys + + *pm_sram->resume_offset + 0x4; + + m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address); +} + +static void am33xx_pm_free_sram(void) +{ + gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz); + gen_pool_free(sram_pool_data, ocmcram_location_data, + sizeof(struct am33xx_pm_ro_sram_data)); +} + +/* + * Push the minimal suspend-resume code to SRAM + */ +static int am33xx_pm_alloc_sram(void) +{ + struct device_node *np; + int ret = 0; + + np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu"); + if (!np) { + np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); + if (!np) { + dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n", + __func__); + return -ENODEV; + } + } + + sram_pool = of_gen_pool_get(np, "pm-sram", 0); + if (!sram_pool) { + dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n", + __func__); + ret = -ENODEV; + goto mpu_put_node; + } + + sram_pool_data = of_gen_pool_get(np, "pm-sram", 1); + if (!sram_pool_data) { + dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n", + __func__); + ret = -ENODEV; + goto mpu_put_node; + } + + ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz); + if (!ocmcram_location) { + dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n", + __func__); + ret = -ENOMEM; + goto mpu_put_node; + } + + ocmcram_location_data = gen_pool_alloc(sram_pool_data, + sizeof(struct emif_regs_amx3)); + if (!ocmcram_location_data) { + dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n"); + gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz); + ret = -ENOMEM; + } + +mpu_put_node: + of_node_put(np); + return ret; +} + +static int am33xx_push_sram_idle(void) +{ + struct am33xx_pm_ro_sram_data ro_sram_data; + int ret; + u32 table_addr, ro_data_addr; + void *copy_addr; + + ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data; + ro_sram_data.amx3_pm_sram_data_phys = + gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data); + + /* Save physical address to calculate resume offset during pm init */ + am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool, + ocmcram_location); + + am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location, + pm_sram->do_wfi, + *pm_sram->do_wfi_sz); + if (!am33xx_do_wfi_sram) { + dev_err(pm33xx_dev, + "PM: %s: am33xx_do_wfi copy to sram failed\n", + __func__); + return -ENODEV; + } + + table_addr = + sram_suspend_address((unsigned long)pm_sram->emif_sram_table); + ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr); + if (ret) { + dev_dbg(pm33xx_dev, + "PM: %s: EMIF function copy failed\n", __func__); + return -EPROBE_DEFER; + } + + ro_data_addr = + sram_suspend_address((unsigned long)pm_sram->ro_sram_data); + copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr, + &ro_sram_data, + sizeof(ro_sram_data)); + if (!copy_addr) { + dev_err(pm33xx_dev, + "PM: %s: ro_sram_data copy to sram failed\n", + __func__); + return -ENODEV; + } + + return 0; +} + +static int am33xx_pm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret; + + if (!of_machine_is_compatible("ti,am33xx") && + !of_machine_is_compatible("ti,am43")) + return -ENODEV; + + pm_ops = dev->platform_data; + if (!pm_ops) { + dev_err(dev, "PM: Cannot get core PM ops!\n"); + return -ENODEV; + } + + pm_sram = pm_ops->get_sram_addrs(); + if (!pm_sram) { + dev_err(dev, "PM: Cannot get PM asm function addresses!!\n"); + return -ENODEV; + } + + pm33xx_dev = dev; + + ret = am33xx_pm_alloc_sram(); + if (ret) + return ret; + + ret = am33xx_push_sram_idle(); + if (ret) + goto err_free_sram; + + m3_ipc = wkup_m3_ipc_get(); + if (!m3_ipc) { + dev_dbg(dev, "PM: Cannot get wkup_m3_ipc handle\n"); + ret = -EPROBE_DEFER; + goto err_free_sram; + } + + am33xx_pm_set_ipc_ops(); + +#ifdef CONFIG_SUSPEND + suspend_set_ops(&am33xx_pm_ops); +#endif /* CONFIG_SUSPEND */ + + ret = pm_ops->init(); + if (ret) { + dev_err(dev, "Unable to call core pm init!\n"); + ret = -ENODEV; + goto err_put_wkup_m3_ipc; + } + + return 0; + +err_put_wkup_m3_ipc: + wkup_m3_ipc_put(m3_ipc); +err_free_sram: + am33xx_pm_free_sram(); + pm33xx_dev = NULL; + return ret; +} + +static int am33xx_pm_remove(struct platform_device *pdev) +{ + suspend_set_ops(NULL); + wkup_m3_ipc_put(m3_ipc); + am33xx_pm_free_sram(); + return 0; +} + +static struct platform_driver am33xx_pm_driver = { + .driver = { + .name = "pm33xx", + }, + .probe = am33xx_pm_probe, + .remove = am33xx_pm_remove, +}; +module_platform_driver(am33xx_pm_driver); + +MODULE_ALIAS("platform:pm33xx"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("am33xx power management driver"); -- cgit v1.2.3 From 5b22419ef4d7c39b40fac6a8e0ad40d1e03cbb2a Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 9 Feb 2018 14:28:03 +0530 Subject: ARM: dts: mt7623: Remove "cooling-{min|max}-level" for CPU nodes The "cooling-min-level" and "cooling-max-level" properties are not parsed by any part of the kernel currently and the max cooling state of a CPU cooling device is found by referring to the cpufreq table instead. Remove the unused properties from the CPU nodes. Signed-off-by: Viresh Kumar Reviewed-by: Rob Herring Signed-off-by: Rafael J. Wysocki --- Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 4 ---- arch/arm/boot/dts/mt7623.dtsi | 2 -- 2 files changed, 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt index f6403089edcf..d36f07e0a2bb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt @@ -21,8 +21,6 @@ Optional properties: flow is handled by hardware, hence no software "voltage tracking" is needed. - #cooling-cells: -- cooling-min-level: -- cooling-max-level: Please refer to Documentation/devicetree/bindings/thermal/thermal.txt for detail. @@ -67,8 +65,6 @@ Example 1 (MT7623 SoC): clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <7>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index b750da5362f7..8e7c65464c9d 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -87,8 +87,6 @@ clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <7>; clock-frequency = <1300000000>; }; -- cgit v1.2.3 From 319ce21acca613eac051ace5437cf02a6020d81e Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 9 Feb 2018 14:28:09 +0530 Subject: dt-bindings: cpufreq-dt: Remove "cooling-{min|max}-level" properties The "cooling-min-level" and "cooling-max-level" properties are not parsed by any part of kernel currently and the max cooling state of a CPU cooling device is found by referring to the cpufreq table instead. Remove the unused bindings. Signed-off-by: Viresh Kumar Reviewed-by: Rob Herring Signed-off-by: Rafael J. Wysocki --- Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt | 4 ---- 1 file changed, 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt index dd3929e85dec..332aed8f4597 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt @@ -18,8 +18,6 @@ Optional properties: in unit of nanoseconds. - voltage-tolerance: Specify the CPU voltage tolerance in percentage. - #cooling-cells: -- cooling-min-level: -- cooling-max-level: Please refer to Documentation/devicetree/bindings/thermal/thermal.txt. Examples: @@ -40,8 +38,6 @@ cpus { >; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; - cooling-min-level = <0>; - cooling-max-level = <2>; }; cpu@1 { -- cgit v1.2.3 From 04db44132bc544e12f8c7693db35a080edded6ee Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 19:03:43 +0100 Subject: dt-bindings: arm: Document Renesas V3MSK and Wheat board part numbers The DT binding documentation for the Renesas V3MSK and Wheat boards lacked board part numbers. Signed-off-by: Geert Uytterhoeven [simon: corrected Wheat part number] Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index a99359e63b0a..66edc1406bb8 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -120,9 +120,9 @@ Boards: compatible = "renesas,sk-rzg1m", "renesas,r8a7743" - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD) compatible = "renesas,stout", "renesas,r8a7790" - - V3MSK + - V3MSK (Y-ASK-RCAR-V3M-WS10) compatible = "renesas,v3msk", "renesas,r8a77970" - - Wheat + - Wheat (RTP0RC7792ASKB0000JE) compatible = "renesas,wheat", "renesas,r8a7792" -- cgit v1.2.3 From b604e4a008fe3e5956c5a07139a8168cbe22f46a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 19:03:45 +0100 Subject: dt-bindings: arm: Document Renesas R-Car M3-N-based Salvator-XS board The Renesas Salvator-XS development board can be equipped with an R-Car H3, M3-W, or M3-N SiP, which are pin-compatible. Document board part number and compatible values for the version with R-Car M3-N. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 66edc1406bb8..02c77e58301b 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -112,6 +112,8 @@ Boards: compatible = "renesas,salvator-xs", "renesas,r8a7795" - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) compatible = "renesas,salvator-xs", "renesas,r8a7796" + - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S) + compatible = "renesas,salvator-xs", "renesas,r8a77965" - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" - SK-RZG1E (YR8A77450S000BE) -- cgit v1.2.3 From 09bea76aad76058d7d1dae8f5804751a017967c1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 26 Feb 2018 19:03:44 +0100 Subject: dt-bindings: arm: Document Renesas R-Car M3-N-based Salvator-X board The Renesas Salvator-X development board can be equipped with an R-Car H3, M3-W, or M3-N SiP, which are pin-compatible. Document board part number and compatible values for the version with R-Car M3-N. The board part number was extracted from a big patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 02c77e58301b..d3d1df97834f 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -108,6 +108,8 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7795" - Salvator-X (RTP0RC7796SIPB0011S) compatible = "renesas,salvator-x", "renesas,r8a7796" + - Salvator-X (RTP0RC7796SIPB0011S (M3N)) + compatible = "renesas,salvator-x", "renesas,r8a77965" - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) compatible = "renesas,salvator-xs", "renesas,r8a7795" - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S) -- cgit v1.2.3 From ec2a844ef7c168af4d93b2171ca385aaf25a7dd1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 9 Jan 2018 17:52:06 +0800 Subject: ARM: dts: imx7s: add snvs rtc clock Add i.MX7 SNVS RTC clock. Signed-off-by: Anson Huang Acked-by: Dong Aisheng Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 17 +++++++++++++++++ arch/arm/boot/dts/imx7s.dtsi | 2 ++ 2 files changed, 19 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index 76aec8a3724d..3c1f3a229eab 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: Definition: LP register offset. default it is 0x34. + - clocks + Usage: optional, required if SNVS LP RTC requires explicit + enablement of clocks + Value type: + Definition: a clock specifier describing the clock required for + enabling and disabling SNVS LP RTC. + + - clock-names + Usage: optional, required if SNVS LP RTC requires explicit + enablement of clocks + Value type: + Definition: clock name string should be "snvs-rtc". + EXAMPLE sec_mon_rtc_lp@1 { compatible = "fsl,sec-v4.0-mon-rtc-lp"; interrupts = <93 2>; regmap = <&snvs>; offset = <0x34>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; ===================================================================== @@ -543,6 +558,8 @@ FULL EXAMPLE regmap = <&sec_mon>; offset = <0x34>; interrupts = <93 2>; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; snvs-pwrkey@020cc000 { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9aa2bb998552..02baf425b1ac 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -551,6 +551,8 @@ offset = <0x34>; interrupts = , ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; }; snvs_poweroff: snvs-poweroff { -- cgit v1.2.3 From 890fb16b4cdbc625b9213487c547793a775ad991 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 1 Feb 2018 22:36:20 +0300 Subject: DT: serial: renesas,sci-serial: document R8A77980 bindings R-Car V3H (R8A77980) SoC has the R-Car gen3 compatible SCIF and HSCIF ports, so document the SoC specific bindings. Signed-off-by: Sergei Shtylyov Reviewed-by: Rob Herring Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index cf504d0380ae..ad962f4ec3aa 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -43,6 +43,8 @@ Required properties: - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART. - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART. - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART. + - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART. + - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART. - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART. - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART. - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART. -- cgit v1.2.3 From 66f5325ce93a2e6fd726fca31fea91baf36a392e Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 27 Feb 2018 15:53:07 +0000 Subject: dt-bindings: add maximum power level to SFP binding Add the new maximum power level property to the SFP binding. Signed-off-by: Russell King Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/sff,sfp.txt | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/sff,sfp.txt b/Documentation/devicetree/bindings/net/sff,sfp.txt index f1c441bedf68..929591d52ed6 100644 --- a/Documentation/devicetree/bindings/net/sff,sfp.txt +++ b/Documentation/devicetree/bindings/net/sff,sfp.txt @@ -33,6 +33,10 @@ Optional Properties: Select (AKA RS1) output gpio signal (SFP+ only), low: low Tx rate, high: high Tx rate. Must not be present for SFF modules +- maximum-power-milliwatt : Maximum module power consumption + Specifies the maximum power consumption allowable by a module in the + slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. + Example #1: Direct serdes to SFP connection sfp_eth3: sfp-eth3 { @@ -40,6 +44,7 @@ sfp_eth3: sfp-eth3 { i2c-bus = <&sfp_1g_i2c>; los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>; mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <1000>; pinctrl-names = "default"; pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>; tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From 07455e4e4321129af0053c61191707ccf8289fc7 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 26 Jun 2017 16:02:39 +0100 Subject: dt-bindings: mailbox: add support for mailbox client shared memory Many users of the mailbox controllers depend on the shared memory between the two end points to exchange the main data while using simple doorbell mechanism to alert the end points of the presence of a message. This patch defines device tree bindings to represent such shared memory in a generic way. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/mailbox.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Documentation/devicetree/bindings/mailbox/mailbox.txt index be05b9746c69..af8ecee2ac68 100644 --- a/Documentation/devicetree/bindings/mailbox/mailbox.txt +++ b/Documentation/devicetree/bindings/mailbox/mailbox.txt @@ -23,6 +23,11 @@ Required property: Optional property: - mbox-names: List of identifier strings for each mailbox channel. +- shmem : List of phandle pointing to the shared memory(SHM) area between the + users of these mailboxes for IPC, one for each mailbox. This shared + memory can be part of any memory reserved for the purpose of this + communication between the mailbox client and the remote. + Example: pwr_cntrl: power { @@ -30,3 +35,26 @@ Example: mbox-names = "pwr-ctrl", "rpc"; mboxes = <&mailbox 0 &mailbox 1>; }; + +Example with shared memory(shmem): + + sram: sram@50000000 { + compatible = "mmio-sram"; + reg = <0x50000000 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50000000 0x10000>; + + cl_shmem: shmem@0 { + compatible = "client-shmem"; + reg = <0x0 0x200>; + }; + }; + + client@2e000000 { + ... + mboxes = <&mailbox 0>; + shmem = <&cl_shmem>; + .. + }; -- cgit v1.2.3 From fe7be8b297b279189260f8ce084ea16fab0c2be0 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 5 Jun 2017 17:27:11 +0100 Subject: dt-bindings: arm: add support for ARM System Control and Management Interface(SCMI) protocol This patch adds devicetree binding for System Control and Management Interface (SCMI) Message Protocol used between the Application Cores(AP) and the System Control Processor(SCP). The MHU peripheral provides a mechanism for inter-processor communication between SCP's M3 processor and AP. SCP offers control and management of the core/cluster power states, various power domain DVFS including the core/cluster, certain system clocks configuration, thermal sensors and many others. SCMI protocol is developed as better replacement to the existing SCPI which is not flexible and easily extensible. Cc: Mark Rutland Acked-by: Rob Herring Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/arm,scmi.txt | 179 +++++++++++++++++++++ MAINTAINERS | 4 +- 2 files changed, 181 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/arm,scmi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt new file mode 100644 index 000000000000..5f3719ab7075 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,scmi.txt @@ -0,0 +1,179 @@ +System Control and Management Interface (SCMI) Message Protocol +---------------------------------------------------------- + +The SCMI is intended to allow agents such as OSPM to manage various functions +that are provided by the hardware platform it is running on, including power +and performance functions. + +This binding is intended to define the interface the firmware implementing +the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control +and Management Interface Platform Design Document")[0] provide for OSPM in +the device tree. + +Required properties: + +The scmi node with the following properties shall be under the /firmware/ node. + +- compatible : shall be "arm,scmi" +- mboxes: List of phandle and mailbox channel specifiers. It should contain + exactly one or two mailboxes, one for transmitting messages("tx") + and another optional for receiving the notifications("rx") if + supported. +- shmem : List of phandle pointing to the shared memory(SHM) area as per + generic mailbox client binding. +- #address-cells : should be '1' if the device has sub-nodes, maps to + protocol identifier for a given sub-node. +- #size-cells : should be '0' as 'reg' property doesn't have any size + associated with it. + +Optional properties: + +- mbox-names: shall be "tx" or "rx" depending on mboxes entries. + +See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details +about the generic mailbox controller and client driver bindings. + +The mailbox is the only permitted method of calling the SCMI firmware. +Mailbox doorbell is used as a mechanism to alert the presence of a +messages and/or notification. + +Each protocol supported shall have a sub-node with corresponding compatible +as described in the following sections. If the platform supports dedicated +communication channel for a particular protocol, the 3 properties namely: +mboxes, mbox-names and shmem shall be present in the sub-node corresponding +to that protocol. + +Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol +------------------------------------------------------------ + +This binding uses the common clock binding[1]. + +Required properties: +- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands. + +Power domain bindings for the power domains based on SCMI Message Protocol +------------------------------------------------------------ + +This binding for the SCMI power domain providers uses the generic power +domain binding[2]. + +Required properties: + - #power-domain-cells : Should be 1. Contains the device or the power + domain ID value used by SCMI commands. + +Sensor bindings for the sensors based on SCMI Message Protocol +-------------------------------------------------------------- +SCMI provides an API to access the various sensors on the SoC. + +Required properties: +- #thermal-sensor-cells: should be set to 1. This property follows the + thermal device tree bindings[3]. + + Valid cell values are raw identifiers (Sensor ID) + as used by the firmware. Refer to platform details + for your implementation for the IDs to use. + +SRAM and Shared Memory for SCMI +------------------------------- + +A small area of SRAM is reserved for SCMI communication between application +processors and SCP. + +The properties should follow the generic mmio-sram description found in [4] + +Each sub-node represents the reserved area for SCMI. + +Required sub-node properties: +- reg : The base offset and size of the reserved area with the SRAM +- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based + shared memory + +[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/power/power_domain.txt +[3] Documentation/devicetree/bindings/thermal/thermal.txt +[4] Documentation/devicetree/bindings/sram/sram.txt + +Example: + +sram@50000000 { + compatible = "mmio-sram"; + reg = <0x0 0x50000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x10000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; +}; + +mailbox@40000000 { + .... + #mbox-cells = <1>; + reg = <0x0 0x40000000 0x0 0x10000>; +}; + +firmware { + + ... + + scmi { + compatible = "arm,scmi"; + mboxes = <&mailbox 0 &mailbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; +}; + +cpu@0 { + ... + reg = <0 0>; + clocks = <&scmi_dvfs 0>; +}; + +hdlcd@7ff60000 { + ... + reg = <0 0x7ff60000 0 0x1000>; + clocks = <&scmi_clk 4>; + power-domains = <&scmi_devpd 1>; +}; + +thermal-zones { + soc_thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + /* sensor ID */ + thermal-sensors = <&scmi_sensors0 3>; + ... + }; +}; diff --git a/MAINTAINERS b/MAINTAINERS index 3bdc260e36b7..5c8c55ba22a3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13379,11 +13379,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git S: Supported F: drivers/mfd/syscon.c -SYSTEM CONTROL & POWER INTERFACE (SCPI) Message Protocol drivers +SYSTEM CONTROL & POWER/MANAGEMENT INTERFACE (SCPI/SCMI) Message Protocol drivers M: Sudeep Holla L: linux-arm-kernel@lists.infradead.org S: Maintained -F: Documentation/devicetree/bindings/arm/arm,scpi.txt +F: Documentation/devicetree/bindings/arm/arm,sc[mp]i.txt F: drivers/clk/clk-scpi.c F: drivers/cpufreq/scpi-cpufreq.c F: drivers/firmware/arm_scpi.c -- cgit v1.2.3 From d545afc907fa66b779699b88ec24f7fe7498cbba Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 15 Feb 2018 12:25:08 +0000 Subject: dt-bindings: dmaengine: bam_dma: add remote controlled bindings This patch adds 2 new properties for remote controlled bam dt bindings. 1. num-channels to indicate number of dma channels. 2. qcom,num-ees to indicate number of Execution Environments. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/qcom_bam_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt index 9cbf5d9df8fd..cf5b9e44432c 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt @@ -15,6 +15,10 @@ Required properties: the secure world. - qcom,controlled-remotely : optional, indicates that the bam is controlled by remote proccessor i.e. execution environment. +- num-channels : optional, indicates supported number of DMA channels in a + remotely controlled bam. +- qcom,num-ees : optional, indicates supported number of Execution Environments + in a remotely controlled bam. Example: -- cgit v1.2.3 From 8f6d3b01477e09fc3e53a4935eba095b2357306f Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 21 Feb 2018 23:38:22 +0000 Subject: gpio: Drop TZ1090 drivers Now that arch/metag/ has been removed, along with TZ1090 SoC support, remove the TZ1090 GPIO drivers. They are of no value without the architecture and SoC platform code. Signed-off-by: James Hogan Cc: linux-gpio@vger.kernel.org Cc: linux-metag@vger.kernel.org Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-tz1090-pdc.txt | 45 -- .../devicetree/bindings/gpio/gpio-tz1090.txt | 88 --- drivers/gpio/Kconfig | 15 - drivers/gpio/Makefile | 2 - drivers/gpio/gpio-tz1090-pdc.c | 231 -------- drivers/gpio/gpio-tz1090.c | 602 --------------------- 6 files changed, 983 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-tz1090.txt delete mode 100644 drivers/gpio/gpio-tz1090-pdc.c delete mode 100644 drivers/gpio/gpio-tz1090.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt deleted file mode 100644 index 528f5ef5a893..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt +++ /dev/null @@ -1,45 +0,0 @@ -ImgTec TZ1090 PDC GPIO Controller - -Required properties: -- compatible: Compatible property value should be "img,tz1090-pdc-gpio". - -- reg: Physical base address of the controller and length of memory mapped - region. This starts at and cover the SOC_GPIO_CONTROL registers. - -- gpio-controller: Specifies that the node is a gpio controller. - -- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client - nodes should have the following values. - <[phandle of the gpio controller node] - [PDC gpio number] - [gpio flags]> - - Values for gpio specifier: - - GPIO number: a value in the range 0 to 6. - - GPIO flags: bit field of flags, as defined in . - Only the following flags are supported: - GPIO_ACTIVE_HIGH - GPIO_ACTIVE_LOW - -Optional properties: -- gpio-ranges: Mapping to pin controller pins (as described in - Documentation/devicetree/bindings/gpio/gpio.txt) - -- interrupts: Individual syswake interrupts (other GPIOs cannot interrupt) - - -Example: - - pdc_gpios: gpio-controller@2006500 { - gpio-controller; - #gpio-cells = <2>; - - compatible = "img,tz1090-pdc-gpio"; - reg = <0x02006500 0x100>; - - interrupt-parent = <&pdc>; - interrupts = <8 IRQ_TYPE_NONE>, /* Syswake 0 */ - <9 IRQ_TYPE_NONE>, /* Syswake 1 */ - <10 IRQ_TYPE_NONE>; /* Syswake 2 */ - gpio-ranges = <&pdc_pinctrl 0 0 7>; - }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt deleted file mode 100644 index b05a90e0ab29..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt +++ /dev/null @@ -1,88 +0,0 @@ -ImgTec TZ1090 GPIO Controller - -Required properties: -- compatible: Compatible property value should be "img,tz1090-gpio". - -- reg: Physical base address of the controller and length of memory mapped - region. - -- #address-cells: Should be 1 (for bank subnodes) - -- #size-cells: Should be 0 (for bank subnodes) - -- Each bank of GPIOs should have a subnode to represent it. - - Bank subnode required properties: - - reg: Index of bank in the range 0 to 2. - - - gpio-controller: Specifies that the node is a gpio controller. - - - #gpio-cells: Should be 2. The syntax of the gpio specifier used by client - nodes should have the following values. - <[phandle of the gpio controller node] - [gpio number within the gpio bank] - [gpio flags]> - - Values for gpio specifier: - - GPIO number: a value in the range 0 to 29. - - GPIO flags: bit field of flags, as defined in . - Only the following flags are supported: - GPIO_ACTIVE_HIGH - GPIO_ACTIVE_LOW - - Bank subnode optional properties: - - gpio-ranges: Mapping to pin controller pins (as described in - Documentation/devicetree/bindings/gpio/gpio.txt) - - - interrupts: Interrupt for the entire bank - - - interrupt-controller: Specifies that the node is an interrupt controller - - - #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by - client nodes should have the following values. - <[phandle of the interurupt controller] - [gpio number within the gpio bank] - [irq flags]> - - Values for irq specifier: - - GPIO number: a value in the range 0 to 29 - - IRQ flags: value to describe edge and level triggering, as defined in - . Only the following flags are - supported: - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING - IRQ_TYPE_EDGE_BOTH - IRQ_TYPE_LEVEL_HIGH - IRQ_TYPE_LEVEL_LOW - - - -Example: - - gpios: gpio-controller@2005800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "img,tz1090-gpio"; - reg = <0x02005800 0x90>; - - /* bank 0 with an interrupt */ - gpios0: bank@0 { - #gpio-cells = <2>; - #interrupt-cells = <2>; - reg = <0>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 30>; - interrupt-controller; - }; - - /* bank 2 without interrupt */ - gpios2: bank@2 { - #gpio-cells = <2>; - reg = <2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 60 30>; - }; - }; - - diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 6d481ef03623..2ecd2adbaec6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -480,21 +480,6 @@ config GPIO_THUNDERX Say yes here to support the on-chip GPIO lines on the ThunderX and OCTEON-TX families of SoCs. -config GPIO_TZ1090 - bool "Toumaz Xenif TZ1090 GPIO support" - depends on SOC_TZ1090 - select GENERIC_IRQ_CHIP - default y - help - Say yes here to support Toumaz Xenif TZ1090 GPIOs. - -config GPIO_TZ1090_PDC - bool "Toumaz Xenif TZ1090 PDC GPIO support" - depends on SOC_TZ1090 - default y - help - Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs. - config GPIO_UNIPHIER tristate "UniPhier GPIO support" depends on ARCH_UNIPHIER || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 77f88bc086c4..3ad5e3cb628b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -133,8 +133,6 @@ obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o -obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o -obj-$(CONFIG_GPIO_TZ1090_PDC) += gpio-tz1090-pdc.o obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o diff --git a/drivers/gpio/gpio-tz1090-pdc.c b/drivers/gpio/gpio-tz1090-pdc.c deleted file mode 100644 index 5b7781741ee9..000000000000 --- a/drivers/gpio/gpio-tz1090-pdc.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Toumaz Xenif TZ1090 PDC GPIO handling. - * - * Copyright (C) 2012-2013 Imagination Technologies Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Register offsets from SOC_GPIO_CONTROL0 */ -#define REG_SOC_GPIO_CONTROL0 0x00 -#define REG_SOC_GPIO_CONTROL1 0x04 -#define REG_SOC_GPIO_CONTROL2 0x08 -#define REG_SOC_GPIO_CONTROL3 0x0c -#define REG_SOC_GPIO_STATUS 0x80 - -/* PDC GPIOs go after normal GPIOs */ -#define GPIO_PDC_BASE 90 -#define GPIO_PDC_NGPIO 7 - -/* Out of PDC gpios, only syswakes have irqs */ -#define GPIO_PDC_IRQ_FIRST 2 -#define GPIO_PDC_NIRQ 3 - -/** - * struct tz1090_pdc_gpio - GPIO bank private data - * @chip: Generic GPIO chip for GPIO bank - * @reg: Base of registers, offset for this GPIO bank - * @irq: IRQ numbers for Syswake GPIOs - * - * This is the main private data for the PDC GPIO driver. It encapsulates a - * gpio_chip, and the callbacks for the gpio_chip can access the private data - * with the to_pdc() macro below. - */ -struct tz1090_pdc_gpio { - struct gpio_chip chip; - void __iomem *reg; - int irq[GPIO_PDC_NIRQ]; -}; - -/* Register accesses into the PDC MMIO area */ - -static inline void pdc_write(struct tz1090_pdc_gpio *priv, unsigned int reg_offs, - unsigned int data) -{ - writel(data, priv->reg + reg_offs); -} - -static inline unsigned int pdc_read(struct tz1090_pdc_gpio *priv, - unsigned int reg_offs) -{ - return readl(priv->reg + reg_offs); -} - -/* Generic GPIO interface */ - -static int tz1090_pdc_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct tz1090_pdc_gpio *priv = gpiochip_get_data(chip); - u32 value; - int lstat; - - __global_lock2(lstat); - value = pdc_read(priv, REG_SOC_GPIO_CONTROL1); - value |= BIT(offset); - pdc_write(priv, REG_SOC_GPIO_CONTROL1, value); - __global_unlock2(lstat); - - return 0; -} - -static int tz1090_pdc_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, - int output_value) -{ - struct tz1090_pdc_gpio *priv = gpiochip_get_data(chip); - u32 value; - int lstat; - - __global_lock2(lstat); - /* EXT_POWER doesn't seem to have an output value bit */ - if (offset < 6) { - value = pdc_read(priv, REG_SOC_GPIO_CONTROL0); - if (output_value) - value |= BIT(offset); - else - value &= ~BIT(offset); - pdc_write(priv, REG_SOC_GPIO_CONTROL0, value); - } - - value = pdc_read(priv, REG_SOC_GPIO_CONTROL1); - value &= ~BIT(offset); - pdc_write(priv, REG_SOC_GPIO_CONTROL1, value); - __global_unlock2(lstat); - - return 0; -} - -static int tz1090_pdc_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct tz1090_pdc_gpio *priv = gpiochip_get_data(chip); - return !!(pdc_read(priv, REG_SOC_GPIO_STATUS) & BIT(offset)); -} - -static void tz1090_pdc_gpio_set(struct gpio_chip *chip, unsigned int offset, - int output_value) -{ - struct tz1090_pdc_gpio *priv = gpiochip_get_data(chip); - u32 value; - int lstat; - - /* EXT_POWER doesn't seem to have an output value bit */ - if (offset >= 6) - return; - - __global_lock2(lstat); - value = pdc_read(priv, REG_SOC_GPIO_CONTROL0); - if (output_value) - value |= BIT(offset); - else - value &= ~BIT(offset); - pdc_write(priv, REG_SOC_GPIO_CONTROL0, value); - __global_unlock2(lstat); -} - -static int tz1090_pdc_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - struct tz1090_pdc_gpio *priv = gpiochip_get_data(chip); - unsigned int syswake = offset - GPIO_PDC_IRQ_FIRST; - int irq; - - /* only syswakes have irqs */ - if (syswake >= GPIO_PDC_NIRQ) - return -EINVAL; - - irq = priv->irq[syswake]; - if (!irq) - return -EINVAL; - - return irq; -} - -static int tz1090_pdc_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct resource *res_regs; - struct tz1090_pdc_gpio *priv; - unsigned int i; - - if (!np) { - dev_err(&pdev->dev, "must be instantiated via devicetree\n"); - return -ENOENT; - } - - res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res_regs) { - dev_err(&pdev->dev, "cannot find registers resource\n"); - return -ENOENT; - } - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - dev_err(&pdev->dev, "unable to allocate driver data\n"); - return -ENOMEM; - } - - /* Ioremap the registers */ - priv->reg = devm_ioremap(&pdev->dev, res_regs->start, - resource_size(res_regs)); - if (!priv->reg) { - dev_err(&pdev->dev, "unable to ioremap registers\n"); - return -ENOMEM; - } - - /* Set up GPIO chip */ - priv->chip.label = "tz1090-pdc-gpio"; - priv->chip.parent = &pdev->dev; - priv->chip.direction_input = tz1090_pdc_gpio_direction_input; - priv->chip.direction_output = tz1090_pdc_gpio_direction_output; - priv->chip.get = tz1090_pdc_gpio_get; - priv->chip.set = tz1090_pdc_gpio_set; - priv->chip.free = gpiochip_generic_free; - priv->chip.request = gpiochip_generic_request; - priv->chip.to_irq = tz1090_pdc_gpio_to_irq; - priv->chip.of_node = np; - - /* GPIO numbering */ - priv->chip.base = GPIO_PDC_BASE; - priv->chip.ngpio = GPIO_PDC_NGPIO; - - /* Map the syswake irqs */ - for (i = 0; i < GPIO_PDC_NIRQ; ++i) - priv->irq[i] = irq_of_parse_and_map(np, i); - - /* Add the GPIO bank */ - gpiochip_add_data(&priv->chip, priv); - - return 0; -} - -static struct of_device_id tz1090_pdc_gpio_of_match[] = { - { .compatible = "img,tz1090-pdc-gpio" }, - { }, -}; - -static struct platform_driver tz1090_pdc_gpio_driver = { - .driver = { - .name = "tz1090-pdc-gpio", - .of_match_table = tz1090_pdc_gpio_of_match, - }, - .probe = tz1090_pdc_gpio_probe, -}; - -static int __init tz1090_pdc_gpio_init(void) -{ - return platform_driver_register(&tz1090_pdc_gpio_driver); -} -subsys_initcall(tz1090_pdc_gpio_init); diff --git a/drivers/gpio/gpio-tz1090.c b/drivers/gpio/gpio-tz1090.c deleted file mode 100644 index 0bb9bb583889..000000000000 --- a/drivers/gpio/gpio-tz1090.c +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Toumaz Xenif TZ1090 GPIO handling. - * - * Copyright (C) 2008-2013 Imagination Technologies Ltd. - * - * Based on ARM PXA code and others. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Register offsets from bank base address */ -#define REG_GPIO_DIR 0x00 -#define REG_GPIO_IRQ_PLRT 0x20 -#define REG_GPIO_IRQ_TYPE 0x30 -#define REG_GPIO_IRQ_EN 0x40 -#define REG_GPIO_IRQ_STS 0x50 -#define REG_GPIO_BIT_EN 0x60 -#define REG_GPIO_DIN 0x70 -#define REG_GPIO_DOUT 0x80 - -/* REG_GPIO_IRQ_PLRT */ -#define REG_GPIO_IRQ_PLRT_LOW 0 -#define REG_GPIO_IRQ_PLRT_HIGH 1 - -/* REG_GPIO_IRQ_TYPE */ -#define REG_GPIO_IRQ_TYPE_LEVEL 0 -#define REG_GPIO_IRQ_TYPE_EDGE 1 - -/** - * struct tz1090_gpio_bank - GPIO bank private data - * @chip: Generic GPIO chip for GPIO bank - * @domain: IRQ domain for GPIO bank (may be NULL) - * @reg: Base of registers, offset for this GPIO bank - * @irq: IRQ number for GPIO bank - * @label: Debug GPIO bank label, used for storage of chip->label - * - * This is the main private data for a GPIO bank. It encapsulates a gpio_chip, - * and the callbacks for the gpio_chip can access the private data with the - * to_bank() macro below. - */ -struct tz1090_gpio_bank { - struct gpio_chip chip; - struct irq_domain *domain; - void __iomem *reg; - int irq; - char label[16]; -}; - -/** - * struct tz1090_gpio - Overall GPIO device private data - * @dev: Device (from platform device) - * @reg: Base of GPIO registers - * - * Represents the overall GPIO device. This structure is actually only - * temporary, and used during init. - */ -struct tz1090_gpio { - struct device *dev; - void __iomem *reg; -}; - -/** - * struct tz1090_gpio_bank_info - Temporary registration info for GPIO bank - * @priv: Overall GPIO device private data - * @node: Device tree node specific to this GPIO bank - * @index: Index of bank in range 0-2 - */ -struct tz1090_gpio_bank_info { - struct tz1090_gpio *priv; - struct device_node *node; - unsigned int index; -}; - -/* Convenience register accessors */ -static inline void tz1090_gpio_write(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, u32 data) -{ - iowrite32(data, bank->reg + reg_offs); -} - -static inline u32 tz1090_gpio_read(struct tz1090_gpio_bank *bank, - unsigned int reg_offs) -{ - return ioread32(bank->reg + reg_offs); -} - -/* caller must hold LOCK2 */ -static inline void _tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset) -{ - u32 value; - - value = tz1090_gpio_read(bank, reg_offs); - value &= ~BIT(offset); - tz1090_gpio_write(bank, reg_offs, value); -} - -static void tz1090_gpio_clear_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset) -{ - int lstat; - - __global_lock2(lstat); - _tz1090_gpio_clear_bit(bank, reg_offs, offset); - __global_unlock2(lstat); -} - -/* caller must hold LOCK2 */ -static inline void _tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset) -{ - u32 value; - - value = tz1090_gpio_read(bank, reg_offs); - value |= BIT(offset); - tz1090_gpio_write(bank, reg_offs, value); -} - -static void tz1090_gpio_set_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset) -{ - int lstat; - - __global_lock2(lstat); - _tz1090_gpio_set_bit(bank, reg_offs, offset); - __global_unlock2(lstat); -} - -/* caller must hold LOCK2 */ -static inline void _tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset, - bool val) -{ - u32 value; - - value = tz1090_gpio_read(bank, reg_offs); - value &= ~BIT(offset); - if (val) - value |= BIT(offset); - tz1090_gpio_write(bank, reg_offs, value); -} - -static void tz1090_gpio_mod_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset, - bool val) -{ - int lstat; - - __global_lock2(lstat); - _tz1090_gpio_mod_bit(bank, reg_offs, offset, val); - __global_unlock2(lstat); -} - -static inline int tz1090_gpio_read_bit(struct tz1090_gpio_bank *bank, - unsigned int reg_offs, - unsigned int offset) -{ - return tz1090_gpio_read(bank, reg_offs) & BIT(offset); -} - -/* GPIO chip callbacks */ - -static int tz1090_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset); - - return 0; -} - -static int tz1090_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int output_value) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - int lstat; - - __global_lock2(lstat); - _tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value); - _tz1090_gpio_clear_bit(bank, REG_GPIO_DIR, offset); - __global_unlock2(lstat); - - return 0; -} - -/* - * Return GPIO level - */ -static int tz1090_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - - return !!tz1090_gpio_read_bit(bank, REG_GPIO_DIN, offset); -} - -/* - * Set output GPIO level - */ -static void tz1090_gpio_set(struct gpio_chip *chip, unsigned int offset, - int output_value) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - - tz1090_gpio_mod_bit(bank, REG_GPIO_DOUT, offset, output_value); -} - -static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - int ret; - - ret = pinctrl_gpio_request(chip->base + offset); - if (ret) - return ret; - - tz1090_gpio_set_bit(bank, REG_GPIO_DIR, offset); - tz1090_gpio_set_bit(bank, REG_GPIO_BIT_EN, offset); - - return 0; -} - -static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - - pinctrl_gpio_free(chip->base + offset); - - tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset); -} - -static int tz1090_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); - - if (!bank->domain) - return -EINVAL; - - return irq_create_mapping(bank->domain, offset); -} - -/* IRQ chip handlers */ - -/* Get TZ1090 GPIO chip from irq data provided to generic IRQ callbacks */ -static inline struct tz1090_gpio_bank *irqd_to_gpio_bank(struct irq_data *data) -{ - return (struct tz1090_gpio_bank *)data->domain->host_data; -} - -static void tz1090_gpio_irq_polarity(struct tz1090_gpio_bank *bank, - unsigned int offset, unsigned int polarity) -{ - tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_PLRT, offset, polarity); -} - -static void tz1090_gpio_irq_type(struct tz1090_gpio_bank *bank, - unsigned int offset, unsigned int type) -{ - tz1090_gpio_mod_bit(bank, REG_GPIO_IRQ_TYPE, offset, type); -} - -/* set polarity to trigger on next edge, whether rising or falling */ -static void tz1090_gpio_irq_next_edge(struct tz1090_gpio_bank *bank, - unsigned int offset) -{ - unsigned int value_p, value_i; - int lstat; - - /* - * Set the GPIO's interrupt polarity to the opposite of the current - * input value so that the next edge triggers an interrupt. - */ - __global_lock2(lstat); - value_i = ~tz1090_gpio_read(bank, REG_GPIO_DIN); - value_p = tz1090_gpio_read(bank, REG_GPIO_IRQ_PLRT); - value_p &= ~BIT(offset); - value_p |= value_i & BIT(offset); - tz1090_gpio_write(bank, REG_GPIO_IRQ_PLRT, value_p); - __global_unlock2(lstat); -} - -static unsigned int gpio_startup_irq(struct irq_data *data) -{ - /* - * This warning indicates that the type of the irq hasn't been set - * before enabling the irq. This would normally be done by passing some - * trigger flags to request_irq(). - */ - WARN(irqd_get_trigger_type(data) == IRQ_TYPE_NONE, - "irq type not set before enabling gpio irq %d", data->irq); - - irq_gc_ack_clr_bit(data); - irq_gc_mask_set_bit(data); - return 0; -} - -static int gpio_set_irq_type(struct irq_data *data, unsigned int flow_type) -{ - struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); - unsigned int type; - unsigned int polarity; - - switch (flow_type) { - case IRQ_TYPE_EDGE_BOTH: - type = REG_GPIO_IRQ_TYPE_EDGE; - polarity = REG_GPIO_IRQ_PLRT_LOW; - break; - case IRQ_TYPE_EDGE_RISING: - type = REG_GPIO_IRQ_TYPE_EDGE; - polarity = REG_GPIO_IRQ_PLRT_HIGH; - break; - case IRQ_TYPE_EDGE_FALLING: - type = REG_GPIO_IRQ_TYPE_EDGE; - polarity = REG_GPIO_IRQ_PLRT_LOW; - break; - case IRQ_TYPE_LEVEL_HIGH: - type = REG_GPIO_IRQ_TYPE_LEVEL; - polarity = REG_GPIO_IRQ_PLRT_HIGH; - break; - case IRQ_TYPE_LEVEL_LOW: - type = REG_GPIO_IRQ_TYPE_LEVEL; - polarity = REG_GPIO_IRQ_PLRT_LOW; - break; - default: - return -EINVAL; - } - - tz1090_gpio_irq_type(bank, data->hwirq, type); - irq_setup_alt_chip(data, flow_type); - - if (flow_type == IRQ_TYPE_EDGE_BOTH) - tz1090_gpio_irq_next_edge(bank, data->hwirq); - else - tz1090_gpio_irq_polarity(bank, data->hwirq, polarity); - - return 0; -} - -#ifdef CONFIG_SUSPEND -static int gpio_set_irq_wake(struct irq_data *data, unsigned int on) -{ - struct tz1090_gpio_bank *bank = irqd_to_gpio_bank(data); - -#ifdef CONFIG_PM_DEBUG - pr_info("irq_wake irq%d state:%d\n", data->irq, on); -#endif - - /* wake on gpio block interrupt */ - return irq_set_irq_wake(bank->irq, on); -} -#else -#define gpio_set_irq_wake NULL -#endif - -static void tz1090_gpio_irq_handler(struct irq_desc *desc) -{ - irq_hw_number_t hw; - unsigned int irq_stat, irq_no; - struct tz1090_gpio_bank *bank; - struct irq_desc *child_desc; - - bank = (struct tz1090_gpio_bank *)irq_desc_get_handler_data(desc); - irq_stat = tz1090_gpio_read(bank, REG_GPIO_DIR) & - tz1090_gpio_read(bank, REG_GPIO_IRQ_STS) & - tz1090_gpio_read(bank, REG_GPIO_IRQ_EN) & - 0x3FFFFFFF; /* 30 bits only */ - - for (hw = 0; irq_stat; irq_stat >>= 1, ++hw) { - if (!(irq_stat & 1)) - continue; - - irq_no = irq_linear_revmap(bank->domain, hw); - child_desc = irq_to_desc(irq_no); - - /* Toggle edge for pin with both edges triggering enabled */ - if (irqd_get_trigger_type(&child_desc->irq_data) - == IRQ_TYPE_EDGE_BOTH) - tz1090_gpio_irq_next_edge(bank, hw); - - generic_handle_irq_desc(child_desc); - } -} - -static int tz1090_gpio_bank_probe(struct tz1090_gpio_bank_info *info) -{ - struct device_node *np = info->node; - struct device *dev = info->priv->dev; - struct tz1090_gpio_bank *bank; - struct irq_chip_generic *gc; - int err; - - bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); - if (!bank) { - dev_err(dev, "unable to allocate driver data\n"); - return -ENOMEM; - } - - /* Offset the main registers to the first register in this bank */ - bank->reg = info->priv->reg + info->index * 4; - - /* Set up GPIO chip */ - snprintf(bank->label, sizeof(bank->label), "tz1090-gpio-%u", - info->index); - bank->chip.label = bank->label; - bank->chip.parent = dev; - bank->chip.direction_input = tz1090_gpio_direction_input; - bank->chip.direction_output = tz1090_gpio_direction_output; - bank->chip.get = tz1090_gpio_get; - bank->chip.set = tz1090_gpio_set; - bank->chip.free = tz1090_gpio_free; - bank->chip.request = tz1090_gpio_request; - bank->chip.to_irq = tz1090_gpio_to_irq; - bank->chip.of_node = np; - - /* GPIO numbering from 0 */ - bank->chip.base = info->index * 30; - bank->chip.ngpio = 30; - - /* Add the GPIO bank */ - gpiochip_add_data(&bank->chip, bank); - - /* Get the GPIO bank IRQ if provided */ - bank->irq = irq_of_parse_and_map(np, 0); - - /* The interrupt is optional (it may be used by another core on chip) */ - if (!bank->irq) { - dev_info(dev, "IRQ not provided for bank %u, IRQs disabled\n", - info->index); - return 0; - } - - dev_info(dev, "Setting up IRQs for GPIO bank %u\n", - info->index); - - /* - * Initialise all interrupts to disabled so we don't get - * spurious ones on a dirty boot and hit the BUG_ON in the - * handler. - */ - tz1090_gpio_write(bank, REG_GPIO_IRQ_EN, 0); - - /* Add a virtual IRQ for each GPIO */ - bank->domain = irq_domain_add_linear(np, - bank->chip.ngpio, - &irq_generic_chip_ops, - bank); - - /* Set up a generic irq chip with 2 chip types (level and edge) */ - err = irq_alloc_domain_generic_chips(bank->domain, bank->chip.ngpio, 2, - bank->label, handle_bad_irq, 0, 0, - IRQ_GC_INIT_NESTED_LOCK); - if (err) { - dev_info(dev, - "irq_alloc_domain_generic_chips failed for bank %u, IRQs disabled\n", - info->index); - irq_domain_remove(bank->domain); - return 0; - } - - gc = irq_get_domain_generic_chip(bank->domain, 0); - gc->reg_base = bank->reg; - - /* level chip type */ - gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; - gc->chip_types[0].handler = handle_level_irq; - gc->chip_types[0].regs.ack = REG_GPIO_IRQ_STS; - gc->chip_types[0].regs.mask = REG_GPIO_IRQ_EN; - gc->chip_types[0].chip.irq_startup = gpio_startup_irq; - gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit; - gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; - gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; - gc->chip_types[0].chip.irq_set_type = gpio_set_irq_type; - gc->chip_types[0].chip.irq_set_wake = gpio_set_irq_wake; - gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND; - - /* edge chip type */ - gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; - gc->chip_types[1].handler = handle_edge_irq; - gc->chip_types[1].regs.ack = REG_GPIO_IRQ_STS; - gc->chip_types[1].regs.mask = REG_GPIO_IRQ_EN; - gc->chip_types[1].chip.irq_startup = gpio_startup_irq; - gc->chip_types[1].chip.irq_ack = irq_gc_ack_clr_bit; - gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; - gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; - gc->chip_types[1].chip.irq_set_type = gpio_set_irq_type; - gc->chip_types[1].chip.irq_set_wake = gpio_set_irq_wake; - gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND; - - /* Setup chained handler for this GPIO bank */ - irq_set_chained_handler_and_data(bank->irq, tz1090_gpio_irq_handler, - bank); - - return 0; -} - -static void tz1090_gpio_register_banks(struct tz1090_gpio *priv) -{ - struct device_node *np = priv->dev->of_node; - struct device_node *node; - - for_each_available_child_of_node(np, node) { - struct tz1090_gpio_bank_info info; - u32 addr; - int ret; - - ret = of_property_read_u32(node, "reg", &addr); - if (ret) { - dev_err(priv->dev, "invalid reg on %pOF\n", node); - continue; - } - if (addr >= 3) { - dev_err(priv->dev, "index %u in %pOF out of range\n", - addr, node); - continue; - } - - info.index = addr; - info.node = of_node_get(node); - info.priv = priv; - - ret = tz1090_gpio_bank_probe(&info); - if (ret) { - dev_err(priv->dev, "failure registering %pOF\n", node); - of_node_put(node); - continue; - } - } -} - -static int tz1090_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct resource *res_regs; - struct tz1090_gpio priv; - - if (!np) { - dev_err(&pdev->dev, "must be instantiated via devicetree\n"); - return -ENOENT; - } - - res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res_regs) { - dev_err(&pdev->dev, "cannot find registers resource\n"); - return -ENOENT; - } - - priv.dev = &pdev->dev; - - /* Ioremap the registers */ - priv.reg = devm_ioremap(&pdev->dev, res_regs->start, - resource_size(res_regs)); - if (!priv.reg) { - dev_err(&pdev->dev, "unable to ioremap registers\n"); - return -ENOMEM; - } - - /* Look for banks */ - tz1090_gpio_register_banks(&priv); - - return 0; -} - -static struct of_device_id tz1090_gpio_of_match[] = { - { .compatible = "img,tz1090-gpio" }, - { }, -}; - -static struct platform_driver tz1090_gpio_driver = { - .driver = { - .name = "tz1090-gpio", - .of_match_table = tz1090_gpio_of_match, - }, - .probe = tz1090_gpio_probe, -}; - -static int __init tz1090_gpio_init(void) -{ - return platform_driver_register(&tz1090_gpio_driver); -} -subsys_initcall(tz1090_gpio_init); -- cgit v1.2.3 From 4a7cba71ca77be885f5861623dfb35317061ac0d Mon Sep 17 00:00:00 2001 From: James Hogan Date: Wed, 21 Feb 2018 23:38:21 +0000 Subject: pinctrl: Drop TZ1090 drivers Now that arch/metag/ has been removed, along with TZ1090 SoC support, remove the TZ1090 pinctrl drivers. They are of no value without the architecture and SoC platform code. Signed-off-by: James Hogan Cc: linux-gpio@vger.kernel.org Cc: linux-metag@vger.kernel.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/img,tz1090-pdc-pinctrl.txt | 127 -- .../bindings/pinctrl/img,tz1090-pinctrl.txt | 227 --- drivers/pinctrl/Kconfig | 12 - drivers/pinctrl/Makefile | 2 - drivers/pinctrl/pinctrl-tz1090-pdc.c | 989 ---------- drivers/pinctrl/pinctrl-tz1090.c | 2005 -------------------- 6 files changed, 3362 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt delete mode 100644 Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt delete mode 100644 drivers/pinctrl/pinctrl-tz1090-pdc.c delete mode 100644 drivers/pinctrl/pinctrl-tz1090.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt deleted file mode 100644 index cf9ccdff4455..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt +++ /dev/null @@ -1,127 +0,0 @@ -ImgTec TZ1090 PDC pin controller - -Required properties: -- compatible: "img,tz1090-pdc-pinctrl" -- reg: Should contain the register physical address and length of the - SOC_GPIO_CONTROL registers in the PDC register region. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number -of subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. For this reason, even seemingly boolean -values are actually tristates in this binding: unspecified, off, or on. -Unspecified is represented as an absent property, and off/on are represented as -integer values 0 and 1. - -Required subnode-properties: -- tz1090,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- tz1090,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below, including - which pingroups can be muxed to them. -- supported generic pinconfig properties (for further details see - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt): - - bias-disable - - bias-high-impedance - - bias-bus-hold - - bias-pull-up - - bias-pull-down - - input-schmitt-enable - - input-schmitt-disable - - drive-strength: Integer, control drive strength of pins in mA. - 2: 2mA - 4: 4mA - 8: 8mA - 12: 12mA - - low-power-enable: Flag, power-on-start weak pull-down for invalid power. - - low-power-disable: Flag, power-on-start weak pull-down disabled. - -Note that many of these properties are only valid for certain specific pins -or groups. See the TZ1090 TRM for complete details regarding which groups -support which functionality. The Linux pinctrl driver may also be a useful -reference. - -Valid values for pin and group names are: - - pins: - - These all support bias-high-impediance, bias-pull-up, bias-pull-down, and - bias-bus-hold (which can also be provided to any of the groups below to set - it for all gpio pins in that group). - - gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power. - - mux groups: - - These all support function. - - gpio0 - pins: gpio0. - function: ir_mod_stable_out. - gpio1 - pins: gpio1. - function: ir_mod_power_out. - - drive groups: - - These support input-schmitt-enable, input-schmitt-disable, - drive-strength, low-power-enable, and low-power-disable. - - pdc - pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, - ext_power. - -Example: - - pinctrl_pdc: pinctrl@2006500 { - #gpio-range-cells = <3>; - compatible = "img,tz1090-pdc-pinctrl"; - reg = <0x02006500 0x100>; - }; - -Example board file extracts: - - &pinctrl_pdc { - pinctrl-names = "default"; - pinctrl-0 = <&syswake_default>; - - syswake_default: syswakes { - syswake_cfg { - tz1090,pins = "sys_wake0", - "sys_wake1", - "sys_wake2"; - pull-up; - }; - }; - irmod_default: irmod { - gpio0_cfg { - tz1090,pins = "gpio0"; - tz1090,function = "ir_mod_stable_out"; - }; - gpio1_cfg { - tz1090,pins = "gpio1"; - tz1090,function = "ir_mod_power_out"; - }; - }; - }; - - ir: ir@2006200 { - pinctrl-names = "default"; - pinctrl-0 = <&irmod_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt deleted file mode 100644 index 2dfd9a3fc1e4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt +++ /dev/null @@ -1,227 +0,0 @@ -ImgTec TZ1090 pin controller - -Required properties: -- compatible: "img,tz1090-pinctrl" -- reg: Should contain the register physical address and length of the pad - configuration registers (CR_PADS_* and CR_IF_CTL0). - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -TZ1090's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. For this reason, even seemingly boolean -values are actually tristates in this binding: unspecified, off, or on. -Unspecified is represented as an absent property, and off/on are represented as -integer values 0 and 1. - -Required subnode-properties: -- tz1090,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- tz1090,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below, including - which pingroups can be muxed to them. -- supported generic pinconfig properties (for further details see - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt): - - bias-disable - - bias-high-impedance - - bias-bus-hold - - bias-pull-up - - bias-pull-down - - input-schmitt-enable - - input-schmitt-disable - - drive-strength: Integer, control drive strength of pins in mA. - 2: 2mA - 4: 4mA - 8: 8mA - 12: 12mA - - -Note that many of these properties are only valid for certain specific pins -or groups. See the TZ1090 TRM for complete details regarding which groups -support which functionality. The Linux pinctrl driver may also be a useful -reference. - -Valid values for pin and group names are: - - gpio pins: - - These all support bias-high-impediance, bias-pull-up, bias-pull-down, and - bias-bus-hold (which can also be provided to any of the groups below to set - it for all pins in that group). - - They also all support the some form of muxing. Any pins which are contained - in one of the mux groups (see below) can be muxed only to the functions - supported by the mux group. All other pins can be muxed to the "perip" - function which enables them with their intended peripheral. - - Different pins in the same mux group cannot be muxed to different functions, - however it is possible to mux only a subset of the pins in a mux group to a - particular function and leave the remaining pins unmuxed. This is useful if - the board connects certain pins in a group to other devices to be controlled - by GPIO, and you don't want the usual peripheral to have any control of the - pin. - - ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7, - i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out, - i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on, - scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd, - sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3, - spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0, - spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0, - tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7, - tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5, - tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0, - tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7, - tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts, - uart0_rxd, uart0_txd, uart1_rxd, uart1_txd. - - bias-high-impediance: supported. - bias-pull-up: supported. - bias-pull-down: supported. - bias-bus-hold: supported. - function: perip or those supported by pin's mux group. - - other pins: - - These other pins are part of various pin groups below, but can't be - controlled as GPIOs. They do however support bias-high-impediance, - bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided - to any of the groups below to set it for all pins in that group). - - clk_out0, clk_out1, tck, tdi, tdo, tms, trst. - - bias-high-impediance: supported. - bias-pull-up: supported. - bias-pull-down: supported. - bias-bus-hold: supported. - - mux groups: - - These all support function, and some support drive configs. - - afe - pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0, - ant_sel1, gain0, gain1, gain2, gain3, gain4, - gain5, gain6, gain7. - function: afe, ts_out_0. - input-schmitt-enable: supported. - input-schmitt-disable: supported. - drive-strength: supported. - pdm_d - pins: pdm_d. - function: pdm_dac, usb_vbus. - sdh - pins: sdh_cd, sdh_wp, sdh_clk_in. - function: sdh, sdio. - sdio - pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, - sdio_d3. - function: sdio, sdh. - spi1_cs2 - pins: spi1_cs2. - function: spi1_cs2, usb_vbus. - tft - pins: tft_red0, tft_red1, tft_red2, tft_red3, - tft_red4, tft_red5, tft_red6, tft_red7, - tft_green0, tft_green1, tft_green2, tft_green3, - tft_green4, tft_green5, tft_green6, tft_green7, - tft_blue0, tft_blue1, tft_blue2, tft_blue3, - tft_blue4, tft_blue5, tft_blue6, tft_blue7, - tft_vdden_gd, tft_panelclk, tft_blank_ls, - tft_vsync_ns, tft_hsync_nr, tft_vd12acb, - tft_pwrsave. - function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1, - lcd_trace, phy_ringosc. - input-schmitt-enable: supported. - input-schmitt-disable: supported. - drive-strength: supported. - - drive groups: - - These all support input-schmitt-enable, input-schmitt-disable, - and drive-strength. - - jtag - pins: tck, trst, tdi, tdo, tms. - scb1 - pins: scb1_sdat, scb1_sclk. - scb2 - pins: scb2_sdat, scb2_sclk. - spi0 - pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din. - spi1 - pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din. - uart - pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts, - uart1_txd, uart1_rxd. - drive_i2s - pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, - i2s_lrclk_out, i2s_bclk_out, i2s_mclk. - drive_pdm - pins: clk_out0, pdm_b, pdm_a. - drive_scb0 - pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c. - drive_sdio - pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3, - sdh_wp, sdh_cd, sdh_clk_in. - - convenience groups: - - These are just convenient groupings of pins and don't support any drive - configs. - - uart0 - pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd. - uart1 - pins: uart1_rxd, uart1_txd. - scb0 - pins: scb0_sclk, scb0_sdat. - i2s - pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, - i2s_lrclk_out, i2s_mclk. - -Example: - - pinctrl: pinctrl@2005800 { - #gpio-range-cells = <3>; - compatible = "img,tz1090-pinctrl"; - reg = <0x02005800 0xe4>; - }; - -Example board file extract: - - &pinctrl { - uart0_default: uart0 { - uart0_cfg { - tz1090,pins = "uart0_rxd", - "uart0_txd"; - tz1090,function = "perip"; - }; - }; - tft_default: tft { - tft_cfg { - tz1090,pins = "tft"; - tz1090,function = "tft"; - }; - }; - }; - - uart@2004b00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_default>; - }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0f254b35c378..f5ef8201c09f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -263,18 +263,6 @@ config PINCTRL_ST select PINCONF select GPIOLIB_IRQCHIP -config PINCTRL_TZ1090 - bool "Toumaz Xenif TZ1090 pin control driver" - depends on SOC_TZ1090 - select PINMUX - select GENERIC_PINCONF - -config PINCTRL_TZ1090_PDC - bool "Toumaz Xenif TZ1090 PDC pin control driver" - depends on SOC_TZ1090 - select PINMUX - select PINCONF - config PINCTRL_U300 bool "U300 pin controller driver" depends on ARCH_U300 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d3692633e9ed..6255546735ff 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -34,8 +34,6 @@ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ -obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o -obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c deleted file mode 100644 index b16d1c96b7eb..000000000000 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ /dev/null @@ -1,989 +0,0 @@ -/* - * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins - * - * Copyright (c) 2013, Imagination Technologies Ltd. - * - * Derived from Tegra code: - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. - * - * Derived from code: - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010 NVIDIA Corporation - * Copyright (C) 2009-2011 ST-Ericsson AB - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * The registers may be shared with other threads/cores, so we need to use the - * metag global lock2 for atomicity. - */ -#include - -#include "core.h" -#include "pinconf.h" - -/* Register offsets from bank base address */ -#define REG_GPIO_CONTROL0 0x00 -#define REG_GPIO_CONTROL2 0x08 - -/* Register field information */ -#define REG_GPIO_CONTROL2_PU_PD_S 16 -#define REG_GPIO_CONTROL2_PDC_POS_S 4 -#define REG_GPIO_CONTROL2_PDC_DR_S 2 -#define REG_GPIO_CONTROL2_PDC_SR_S 1 -#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0 - -/* PU_PD field values */ -#define REG_PU_PD_TRISTATE 0 -#define REG_PU_PD_UP 1 -#define REG_PU_PD_DOWN 2 -#define REG_PU_PD_REPEATER 3 - -/* DR field values */ -#define REG_DR_2mA 0 -#define REG_DR_4mA 1 -#define REG_DR_8mA 2 -#define REG_DR_12mA 3 - -/** - * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct tz1090_pdc_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -/** - * struct tz1090_pdc_pingroup - TZ1090 PDC pin group - * @name: Name of pin group. - * @pins: Array of pin numbers in this pin group. - * @npins: Number of pins in this pin group. - * @func: Function enabled by the mux. - * @reg: Mux register offset. - * @bit: Mux register bit. - * @drv: Drive control supported, otherwise it's a mux. - * This means Schmitt, Slew, and Drive strength. - * - * A representation of a group of pins (possibly just one pin) in the TZ1090 - * PDC pin controller. Each group allows some parameter or parameters to be - * configured. The most common is mux function selection. - */ -struct tz1090_pdc_pingroup { - const char *name; - const unsigned int *pins; - unsigned int npins; - int func; - u16 reg; - u8 bit; - bool drv; -}; - -/* - * All PDC pins can be GPIOs. Define these first to match how the GPIO driver - * names/numbers its pins. - */ - -enum tz1090_pdc_pin { - TZ1090_PDC_PIN_GPIO0, - TZ1090_PDC_PIN_GPIO1, - TZ1090_PDC_PIN_SYS_WAKE0, - TZ1090_PDC_PIN_SYS_WAKE1, - TZ1090_PDC_PIN_SYS_WAKE2, - TZ1090_PDC_PIN_IR_DATA, - TZ1090_PDC_PIN_EXT_POWER, -}; - -/* Pin names */ - -static const struct pinctrl_pin_desc tz1090_pdc_pins[] = { - /* PDC GPIOs */ - PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"), - PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"), - PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"), - PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"), - PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"), - PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"), - PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"), -}; - -/* Pin group pins */ - -static const unsigned int gpio0_pins[] = { - TZ1090_PDC_PIN_GPIO0, -}; - -static const unsigned int gpio1_pins[] = { - TZ1090_PDC_PIN_GPIO1, -}; - -static const unsigned int pdc_pins[] = { - TZ1090_PDC_PIN_GPIO0, - TZ1090_PDC_PIN_GPIO1, - TZ1090_PDC_PIN_SYS_WAKE0, - TZ1090_PDC_PIN_SYS_WAKE1, - TZ1090_PDC_PIN_SYS_WAKE2, - TZ1090_PDC_PIN_IR_DATA, - TZ1090_PDC_PIN_EXT_POWER, -}; - -/* Mux functions */ - -enum tz1090_pdc_mux { - /* PDC_GPIO0 mux */ - TZ1090_PDC_MUX_IR_MOD_STABLE_OUT, - /* PDC_GPIO1 mux */ - TZ1090_PDC_MUX_IR_MOD_POWER_OUT, -}; - -/* Pin groups a function can be muxed to */ - -static const char * const gpio0_groups[] = { - "gpio0", -}; - -static const char * const gpio1_groups[] = { - "gpio1", -}; - -#define FUNCTION(mux, fname, group) \ - [(TZ1090_PDC_MUX_ ## mux)] = { \ - .name = #fname, \ - .groups = group##_groups, \ - .ngroups = ARRAY_SIZE(group##_groups), \ - } - -/* Must correlate with enum tz1090_pdc_mux */ -static const struct tz1090_pdc_function tz1090_pdc_functions[] = { - /* MUX fn pingroups */ - FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0), - FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1), -}; - -/** - * MUX_PG() - Initialise a pin group with mux control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register of mux field - */ -#define MUX_PG(pg_name, f0, mux_r, mux_b) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .func = TZ1090_PDC_MUX_ ## f0, \ - .reg = (REG_ ## mux_r), \ - .bit = (mux_b), \ - } - -/** - * DRV_PG() - Initialise a pin group with drive control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - */ -#define DRV_PG(pg_name) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .drv = true, \ - } - -static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = { - /* Muxing pin groups */ - /* pg_name, f0, mux register, mux bit */ - MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7), - MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6), - - /* Drive pin groups */ - /* pg_name */ - DRV_PG(pdc), -}; - -/** - * struct tz1090_pdc_pmx - Private pinctrl data - * @dev: Platform device - * @pctl: Pin control device - * @regs: Register region - * @lock: Lock protecting coherency of mux_en and gpio_en - * @mux_en: Muxes that have been enabled - * @gpio_en: Muxable GPIOs that have been enabled - */ -struct tz1090_pdc_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *regs; - spinlock_t lock; - u32 mux_en; - u32 gpio_en; -}; - -static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg) -{ - return ioread32(pmx->regs + reg); -} - -static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg) -{ - iowrite32(val, pmx->regs + reg); -} - -/* - * Pin control operations - */ - -static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_pdc_groups); -} - -static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl, - unsigned int group) -{ - return tz1090_pdc_groups[group].name; -} - -static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - *pins = tz1090_pdc_groups[group].pins; - *num_pins = tz1090_pdc_groups[group].npins; - - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned int offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} -#endif - -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - unsigned int reserve) -{ - unsigned int old_num = *reserved_maps; - unsigned int new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, - unsigned int *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -/** - * get_group_selector() - returns the group selector for a group - * @pin_group: the pin group to look up - * - * This is the same as pinctrl_get_group_selector except it doesn't produce an - * error message if the group isn't found or debug messages. - */ -static int get_group_selector(const char *pin_group) -{ - unsigned int group; - - for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group) - if (!strcmp(tz1090_pdc_groups[group].name, pin_group)) - return group; - - return -EINVAL; -} - -static int add_map_configs(struct device *dev, - struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - const char *group, unsigned long *configs, - unsigned int num_configs) -{ - unsigned long *dup_configs; - enum pinctrl_map_type type; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - /* - * We support both pins and pin groups, but we need to figure out which - * one we have. - */ - if (get_group_selector(group) >= 0) - type = PIN_MAP_TYPE_CONFIGS_GROUP; - else - type = PIN_MAP_TYPE_CONFIGS_PIN; - (*map)[*num_maps].type = type; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned int num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev, - struct device_node *np, - struct pinctrl_map **map, - unsigned int *reserved_maps, - unsigned int *num_maps) -{ - int ret; - const char *function; - unsigned long *configs = NULL; - unsigned int num_configs = 0; - unsigned int reserve; - struct property *prop; - const char *group; - - ret = of_property_read_string(np, "tz1090,function", &function); - if (ret < 0) { - /* EINVAL=missing, which is fine since it's optional */ - if (ret != -EINVAL) - dev_err(dev, - "could not parse property function\n"); - function = NULL; - } - - ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); - if (ret) - return ret; - - reserve = 0; - if (function != NULL) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "tz1090,pins"); - if (ret < 0) { - dev_err(dev, "could not parse property pins\n"); - goto exit; - } - reserve *= ret; - - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "tz1090,pins", prop, group) { - if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned int *num_maps) -{ - unsigned int reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np, - map, &reserved_maps, - num_maps); - if (ret < 0) { - tz1090_pdc_pinctrl_dt_free_map(pctldev, *map, - *num_maps); - return ret; - } - } - - return 0; -} - -static const struct pinctrl_ops tz1090_pdc_pinctrl_ops = { - .get_groups_count = tz1090_pdc_pinctrl_get_groups_count, - .get_group_name = tz1090_pdc_pinctrl_get_group_name, - .get_group_pins = tz1090_pdc_pinctrl_get_group_pins, -#ifdef CONFIG_DEBUG_FS - .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show, -#endif - .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map, - .dt_free_map = tz1090_pdc_pinctrl_dt_free_map, -}; - -/* - * Pin mux operations - */ - -static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_pdc_functions); -} - -static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - return tz1090_pdc_functions[function].name; -} - -static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const num_groups) -{ - *groups = tz1090_pdc_functions[function].groups; - *num_groups = tz1090_pdc_functions[function].ngroups; - - return 0; -} - -/** - * tz1090_pdc_pinctrl_mux() - update mux bit - * @pmx: Pinmux data - * @grp: Pin mux group - */ -static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx, - const struct tz1090_pdc_pingroup *grp) -{ - u32 reg, select; - unsigned int pin_shift = grp->pins[0]; - unsigned long flags; - - /* select = mux && !gpio */ - select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1; - - /* set up the mux */ - __global_lock2(flags); - reg = pmx_read(pmx, grp->reg); - reg &= ~BIT(grp->bit); - reg |= select << grp->bit; - pmx_write(pmx, reg, grp->reg); - __global_unlock2(flags); -} - -static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev, - unsigned int function, - unsigned int group) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; - - dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", - __func__, - function, tz1090_pdc_functions[function].name, - group, tz1090_pdc_groups[group].name); - - /* is it even a mux? */ - if (grp->drv) - return -EINVAL; - - /* does this group even control the function? */ - if (function != grp->func) - return -EINVAL; - - /* record the pin being muxed and update mux bit */ - spin_lock(&pmx->lock); - pmx->mux_en |= BIT(grp->pins[0]); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); - return 0; -} - -static const struct tz1090_pdc_pingroup *find_mux_group( - struct tz1090_pdc_pmx *pmx, - unsigned int pin) -{ - const struct tz1090_pdc_pingroup *grp; - unsigned int group; - - grp = tz1090_pdc_groups; - for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) { - /* only match muxes */ - if (grp->drv) - continue; - - /* with a matching pin */ - if (grp->pins[0] == pin) - return grp; - } - - return NULL; -} - -static int tz1090_pdc_pinctrl_gpio_request_enable( - struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); - - if (grp) { - /* record the pin in GPIO use and update mux bit */ - spin_lock(&pmx->lock); - pmx->gpio_en |= BIT(pin); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); - } - return 0; -} - -static void tz1090_pdc_pinctrl_gpio_disable_free( - struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); - - if (grp) { - /* record the pin not in GPIO use and update mux bit */ - spin_lock(&pmx->lock); - pmx->gpio_en &= ~BIT(pin); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); - } -} - -static const struct pinmux_ops tz1090_pdc_pinmux_ops = { - .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, - .get_function_name = tz1090_pdc_pinctrl_get_func_name, - .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, - .set_mux = tz1090_pdc_pinctrl_set_mux, - .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, - .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, -}; - -/* - * Pin config operations - */ - -static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, - unsigned int pin, - enum pin_config_param param, - bool report_err, - u32 *reg, u32 *width, u32 *mask, u32 *shift, - u32 *val) -{ - /* Find information about parameter's register */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *val = REG_PU_PD_TRISTATE; - break; - case PIN_CONFIG_BIAS_PULL_UP: - *val = REG_PU_PD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - *val = REG_PU_PD_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - *val = REG_PU_PD_REPEATER; - break; - default: - return -ENOTSUPP; - } - - /* Only input bias parameters supported */ - *reg = REG_GPIO_CONTROL2; - *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2; - *width = 2; - - /* Calculate field information */ - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - int ret; - u32 reg, width, mask, shift, val, tmp, arg; - - /* Get register information */ - ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Extract field from register */ - tmp = pmx_read(pmx, reg); - arg = ((tmp & mask) >> shift) == val; - - /* Config not active */ - if (!arg) - return -EINVAL; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - unsigned int arg; - int ret; - u32 reg, width, mask, shift, val, tmp; - unsigned long flags; - int i; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", - __func__, tz1090_pdc_pins[pin].name, configs[i]); - - /* Get register information */ - ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Unpack argument and range check it */ - if (arg > 1) { - dev_dbg(pctldev->dev, "%s: arg %u out of range\n", - __func__, arg); - return -EINVAL; - } - - /* Write register field */ - __global_lock2(flags); - tmp = pmx_read(pmx, reg); - tmp &= ~mask; - if (arg) - tmp |= val << shift; - pmx_write(pmx, tmp, reg); - __global_unlock2(flags); - } /* for each config */ - - return 0; -} - -static const int tz1090_pdc_boolean_map[] = { - [0] = -EINVAL, - [1] = 1, -}; - -static const int tz1090_pdc_dr_map[] = { - [REG_DR_2mA] = 2, - [REG_DR_4mA] = 4, - [REG_DR_8mA] = 8, - [REG_DR_12mA] = 12, -}; - -static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, - const struct tz1090_pdc_pingroup *g, - enum pin_config_param param, - bool report_err, u32 *reg, u32 *width, - u32 *mask, u32 *shift, const int **map) -{ - /* Drive configuration applies in groups, but not to all groups. */ - if (!g->drv) { - if (report_err) - dev_dbg(pctldev->dev, - "%s: group %s has no drive control\n", - __func__, g->name); - return -ENOTSUPP; - } - - /* Find information about drive parameter's register */ - *reg = REG_GPIO_CONTROL2; - switch (param) { - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S; - *width = 1; - *map = tz1090_pdc_boolean_map; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - *shift = REG_GPIO_CONTROL2_PDC_DR_S; - *width = 2; - *map = tz1090_pdc_dr_map; - break; - case PIN_CONFIG_LOW_POWER_MODE: - *shift = REG_GPIO_CONTROL2_PDC_POS_S; - *width = 1; - *map = tz1090_pdc_boolean_map; - break; - default: - return -ENOTSUPP; - } - - /* Calculate field information */ - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *config) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; - enum pin_config_param param = pinconf_to_config_param(*config); - int ret, arg; - u32 reg, width, mask, shift, val; - const int *map; - - /* Get register information */ - ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, &map); - if (ret < 0) - return ret; - - /* Extract field from register */ - val = pmx_read(pmx, reg); - arg = map[(val & mask) >> shift]; - if (arg < 0) - return arg; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; - enum pin_config_param param; - const unsigned int *pit; - unsigned int i; - int ret, arg; - u32 reg, width, mask, shift, val; - unsigned long flags; - const int *map; - int j; - - for (j = 0; j < num_configs; j++) { - param = pinconf_to_config_param(configs[j]); - - dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", - __func__, g->name, configs[j]); - - /* Get register information */ - ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, - &map); - if (ret < 0) { - /* - * Maybe we're trying to set a per-pin configuration - * of a group, so do the pins one by one. This is - * mainly as a convenience. - */ - for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { - ret = tz1090_pdc_pinconf_set(pctldev, *pit, - configs, num_configs); - if (ret) - return ret; - } - return 0; - } - - /* Unpack argument and map it to register value */ - arg = pinconf_to_config_argument(configs[j]); - for (i = 0; i < BIT(width); ++i) { - if (map[i] == arg || (map[i] == -EINVAL && !arg)) { - /* Write register field */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~mask; - val |= i << shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); - goto next_config; - } - } - - dev_dbg(pctldev->dev, "%s: arg %u not supported\n", - __func__, arg); - return 0; - -next_config: - ; - } /* for each config */ - - return 0; -} - -static const struct pinconf_ops tz1090_pdc_pinconf_ops = { - .is_generic = true, - .pin_config_get = tz1090_pdc_pinconf_get, - .pin_config_set = tz1090_pdc_pinconf_set, - .pin_config_group_get = tz1090_pdc_pinconf_group_get, - .pin_config_group_set = tz1090_pdc_pinconf_group_set, - .pin_config_config_dbg_show = pinconf_generic_dump_config, -}; - -/* - * Pin control driver setup - */ - -static struct pinctrl_desc tz1090_pdc_pinctrl_desc = { - .pctlops = &tz1090_pdc_pinctrl_ops, - .pmxops = &tz1090_pdc_pinmux_ops, - .confops = &tz1090_pdc_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev) -{ - struct tz1090_pdc_pmx *pmx; - struct resource *res; - - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); - if (!pmx) - return -ENOMEM; - - pmx->dev = &pdev->dev; - spin_lock_init(&pmx->lock); - - tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev); - tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins; - tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pmx->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pmx->regs)) - return PTR_ERR(pmx->regs); - - pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pdc_pinctrl_desc, - pmx); - if (IS_ERR(pmx->pctl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pmx->pctl); - } - - platform_set_drvdata(pdev, pmx); - - dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n"); - - return 0; -} - -static const struct of_device_id tz1090_pdc_pinctrl_of_match[] = { - { .compatible = "img,tz1090-pdc-pinctrl", }, - { }, -}; - -static struct platform_driver tz1090_pdc_pinctrl_driver = { - .driver = { - .name = "tz1090-pdc-pinctrl", - .of_match_table = tz1090_pdc_pinctrl_of_match, - }, - .probe = tz1090_pdc_pinctrl_probe, -}; - -static int __init tz1090_pdc_pinctrl_init(void) -{ - return platform_driver_register(&tz1090_pdc_pinctrl_driver); -} -arch_initcall(tz1090_pdc_pinctrl_init); - -static void __exit tz1090_pdc_pinctrl_exit(void) -{ - platform_driver_unregister(&tz1090_pdc_pinctrl_driver); -} -module_exit(tz1090_pdc_pinctrl_exit); - -MODULE_AUTHOR("Imagination Technologies Ltd."); -MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c deleted file mode 100644 index 2379ce2be365..000000000000 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ /dev/null @@ -1,2005 +0,0 @@ -/* - * Pinctrl driver for the Toumaz Xenif TZ1090 SoC - * - * Copyright (c) 2013, Imagination Technologies Ltd. - * - * Derived from Tegra code: - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. - * - * Derived from code: - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010 NVIDIA Corporation - * Copyright (C) 2009-2011 ST-Ericsson AB - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * The registers may be shared with other threads/cores, so we need to use the - * metag global lock2 for atomicity. - */ -#include - -#include "core.h" -#include "pinconf.h" - -/* Register offsets from bank base address */ -#define REG_PINCTRL_SELECT 0x10 -#define REG_PINCTRL_SCHMITT 0x90 -#define REG_PINCTRL_PU_PD 0xa0 -#define REG_PINCTRL_SR 0xc0 -#define REG_PINCTRL_DR 0xd0 -#define REG_PINCTRL_IF_CTL 0xe0 - -/* REG_PINCTRL_PU_PD field values */ -#define REG_PU_PD_TRISTATE 0 -#define REG_PU_PD_UP 1 -#define REG_PU_PD_DOWN 2 -#define REG_PU_PD_REPEATER 3 - -/* REG_PINCTRL_DR field values */ -#define REG_DR_2mA 0 -#define REG_DR_4mA 1 -#define REG_DR_8mA 2 -#define REG_DR_12mA 3 - -/** - * struct tz1090_function - TZ1090 pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct tz1090_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -/** - * struct tz1090_muxdesc - TZ1090 individual mux description - * @funcs: Function for each mux value. - * @reg: Mux register offset. 0 if unsupported. - * @bit: Mux register bit. 0 if unsupported. - * @width: Mux field width. 0 if unsupported. - * - * A representation of a group of signals (possibly just one signal) in the - * TZ1090 which can be muxed to a set of functions or sub muxes. - */ -struct tz1090_muxdesc { - int funcs[5]; - u16 reg; - u8 bit; - u8 width; -}; - -/** - * struct tz1090_pingroup - TZ1090 pin group - * @name: Name of pin group. - * @pins: Array of pin numbers in this pin group. - * @npins: Number of pins in this pin group. - * @mux: Top level mux. - * @drv: Drive control supported, 0 if unsupported. - * This means Schmitt, Slew, and Drive strength. - * @slw_bit: Slew register bit. 0 if unsupported. - * The same bit is used for Schmitt, and Drive (*2). - * @func: Currently muxed function. - * @func_count: Number of pins using current mux function. - * - * A representation of a group of pins (possibly just one pin) in the TZ1090 - * pin controller. Each group allows some parameter or parameters to be - * configured. The most common is mux function selection. - */ -struct tz1090_pingroup { - const char *name; - const unsigned int *pins; - unsigned int npins; - struct tz1090_muxdesc mux; - - bool drv; - u8 slw_bit; - - int func; - unsigned int func_count; -}; - -/* - * Most pins affected by the pinmux can also be GPIOs. Define these first. - * These must match how the GPIO driver names/numbers its pins. - */ - -enum tz1090_pin { - /* GPIO pins */ - TZ1090_PIN_SDIO_CLK, - TZ1090_PIN_SDIO_CMD, - TZ1090_PIN_SDIO_D0, - TZ1090_PIN_SDIO_D1, - TZ1090_PIN_SDIO_D2, - TZ1090_PIN_SDIO_D3, - TZ1090_PIN_SDH_CD, - TZ1090_PIN_SDH_WP, - TZ1090_PIN_SPI0_MCLK, - TZ1090_PIN_SPI0_CS0, - TZ1090_PIN_SPI0_CS1, - TZ1090_PIN_SPI0_CS2, - TZ1090_PIN_SPI0_DOUT, - TZ1090_PIN_SPI0_DIN, - TZ1090_PIN_SPI1_MCLK, - TZ1090_PIN_SPI1_CS0, - TZ1090_PIN_SPI1_CS1, - TZ1090_PIN_SPI1_CS2, - TZ1090_PIN_SPI1_DOUT, - TZ1090_PIN_SPI1_DIN, - TZ1090_PIN_UART0_RXD, - TZ1090_PIN_UART0_TXD, - TZ1090_PIN_UART0_CTS, - TZ1090_PIN_UART0_RTS, - TZ1090_PIN_UART1_RXD, - TZ1090_PIN_UART1_TXD, - TZ1090_PIN_SCB0_SDAT, - TZ1090_PIN_SCB0_SCLK, - TZ1090_PIN_SCB1_SDAT, - TZ1090_PIN_SCB1_SCLK, - TZ1090_PIN_SCB2_SDAT, - TZ1090_PIN_SCB2_SCLK, - TZ1090_PIN_I2S_MCLK, - TZ1090_PIN_I2S_BCLK_OUT, - TZ1090_PIN_I2S_LRCLK_OUT, - TZ1090_PIN_I2S_DOUT0, - TZ1090_PIN_I2S_DOUT1, - TZ1090_PIN_I2S_DOUT2, - TZ1090_PIN_I2S_DIN, - TZ1090_PIN_PDM_A, - TZ1090_PIN_PDM_B, - TZ1090_PIN_PDM_C, - TZ1090_PIN_PDM_D, - TZ1090_PIN_TFT_RED0, - TZ1090_PIN_TFT_RED1, - TZ1090_PIN_TFT_RED2, - TZ1090_PIN_TFT_RED3, - TZ1090_PIN_TFT_RED4, - TZ1090_PIN_TFT_RED5, - TZ1090_PIN_TFT_RED6, - TZ1090_PIN_TFT_RED7, - TZ1090_PIN_TFT_GREEN0, - TZ1090_PIN_TFT_GREEN1, - TZ1090_PIN_TFT_GREEN2, - TZ1090_PIN_TFT_GREEN3, - TZ1090_PIN_TFT_GREEN4, - TZ1090_PIN_TFT_GREEN5, - TZ1090_PIN_TFT_GREEN6, - TZ1090_PIN_TFT_GREEN7, - TZ1090_PIN_TFT_BLUE0, - TZ1090_PIN_TFT_BLUE1, - TZ1090_PIN_TFT_BLUE2, - TZ1090_PIN_TFT_BLUE3, - TZ1090_PIN_TFT_BLUE4, - TZ1090_PIN_TFT_BLUE5, - TZ1090_PIN_TFT_BLUE6, - TZ1090_PIN_TFT_BLUE7, - TZ1090_PIN_TFT_VDDEN_GD, - TZ1090_PIN_TFT_PANELCLK, - TZ1090_PIN_TFT_BLANK_LS, - TZ1090_PIN_TFT_VSYNC_NS, - TZ1090_PIN_TFT_HSYNC_NR, - TZ1090_PIN_TFT_VD12ACB, - TZ1090_PIN_TFT_PWRSAVE, - TZ1090_PIN_TX_ON, - TZ1090_PIN_RX_ON, - TZ1090_PIN_PLL_ON, - TZ1090_PIN_PA_ON, - TZ1090_PIN_RX_HP, - TZ1090_PIN_GAIN0, - TZ1090_PIN_GAIN1, - TZ1090_PIN_GAIN2, - TZ1090_PIN_GAIN3, - TZ1090_PIN_GAIN4, - TZ1090_PIN_GAIN5, - TZ1090_PIN_GAIN6, - TZ1090_PIN_GAIN7, - TZ1090_PIN_ANT_SEL0, - TZ1090_PIN_ANT_SEL1, - TZ1090_PIN_SDH_CLK_IN, - - /* Non-GPIO pins */ - TZ1090_PIN_TCK, - TZ1090_PIN_TRST, - TZ1090_PIN_TDI, - TZ1090_PIN_TDO, - TZ1090_PIN_TMS, - TZ1090_PIN_CLK_OUT0, - TZ1090_PIN_CLK_OUT1, - - NUM_GPIOS = TZ1090_PIN_TCK, -}; - -/* Pin names */ - -static const struct pinctrl_pin_desc tz1090_pins[] = { - /* GPIO pins */ - PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"), - PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"), - PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"), - PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"), - PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"), - PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"), - PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"), - PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"), - PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"), - PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"), - PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"), - PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"), - PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"), - PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"), - PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"), - PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"), - PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"), - PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"), - PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"), - PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"), - PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"), - PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"), - PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"), - PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"), - PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"), - PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"), - PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"), - PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"), - PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"), - PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"), - PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"), - PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"), - PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"), - PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"), - PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"), - PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"), - PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"), - PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"), - PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"), - PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"), - PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"), - PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"), - PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"), - PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"), - PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"), - PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"), - PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"), - PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"), - PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"), - PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"), - PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"), - PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"), - PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"), - PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"), - PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"), - PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"), - PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"), - PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"), - PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"), - PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"), - PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"), - - /* Non-GPIO pins */ - PINCTRL_PIN(TZ1090_PIN_TCK, "tck"), - PINCTRL_PIN(TZ1090_PIN_TRST, "trst"), - PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"), - PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"), - PINCTRL_PIN(TZ1090_PIN_TMS, "tms"), - PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"), - PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"), -}; - -/* Pins in each pin group */ - -static const unsigned int spi1_cs2_pins[] = { - TZ1090_PIN_SPI1_CS2, -}; - -static const unsigned int pdm_d_pins[] = { - TZ1090_PIN_PDM_D, -}; - -static const unsigned int tft_pins[] = { - TZ1090_PIN_TFT_RED0, - TZ1090_PIN_TFT_RED1, - TZ1090_PIN_TFT_RED2, - TZ1090_PIN_TFT_RED3, - TZ1090_PIN_TFT_RED4, - TZ1090_PIN_TFT_RED5, - TZ1090_PIN_TFT_RED6, - TZ1090_PIN_TFT_RED7, - TZ1090_PIN_TFT_GREEN0, - TZ1090_PIN_TFT_GREEN1, - TZ1090_PIN_TFT_GREEN2, - TZ1090_PIN_TFT_GREEN3, - TZ1090_PIN_TFT_GREEN4, - TZ1090_PIN_TFT_GREEN5, - TZ1090_PIN_TFT_GREEN6, - TZ1090_PIN_TFT_GREEN7, - TZ1090_PIN_TFT_BLUE0, - TZ1090_PIN_TFT_BLUE1, - TZ1090_PIN_TFT_BLUE2, - TZ1090_PIN_TFT_BLUE3, - TZ1090_PIN_TFT_BLUE4, - TZ1090_PIN_TFT_BLUE5, - TZ1090_PIN_TFT_BLUE6, - TZ1090_PIN_TFT_BLUE7, - TZ1090_PIN_TFT_VDDEN_GD, - TZ1090_PIN_TFT_PANELCLK, - TZ1090_PIN_TFT_BLANK_LS, - TZ1090_PIN_TFT_VSYNC_NS, - TZ1090_PIN_TFT_HSYNC_NR, - TZ1090_PIN_TFT_VD12ACB, - TZ1090_PIN_TFT_PWRSAVE, -}; - -static const unsigned int afe_pins[] = { - TZ1090_PIN_TX_ON, - TZ1090_PIN_RX_ON, - TZ1090_PIN_PLL_ON, - TZ1090_PIN_PA_ON, - TZ1090_PIN_RX_HP, - TZ1090_PIN_ANT_SEL0, - TZ1090_PIN_ANT_SEL1, - TZ1090_PIN_GAIN0, - TZ1090_PIN_GAIN1, - TZ1090_PIN_GAIN2, - TZ1090_PIN_GAIN3, - TZ1090_PIN_GAIN4, - TZ1090_PIN_GAIN5, - TZ1090_PIN_GAIN6, - TZ1090_PIN_GAIN7, -}; - -static const unsigned int sdio_pins[] = { - TZ1090_PIN_SDIO_CLK, - TZ1090_PIN_SDIO_CMD, - TZ1090_PIN_SDIO_D0, - TZ1090_PIN_SDIO_D1, - TZ1090_PIN_SDIO_D2, - TZ1090_PIN_SDIO_D3, -}; - -static const unsigned int sdh_pins[] = { - TZ1090_PIN_SDH_CD, - TZ1090_PIN_SDH_WP, - TZ1090_PIN_SDH_CLK_IN, -}; - -static const unsigned int spi0_pins[] = { - TZ1090_PIN_SPI0_MCLK, - TZ1090_PIN_SPI0_CS0, - TZ1090_PIN_SPI0_CS1, - TZ1090_PIN_SPI0_CS2, - TZ1090_PIN_SPI0_DOUT, - TZ1090_PIN_SPI0_DIN, -}; - -static const unsigned int spi1_pins[] = { - TZ1090_PIN_SPI1_MCLK, - TZ1090_PIN_SPI1_CS0, - TZ1090_PIN_SPI1_CS1, - TZ1090_PIN_SPI1_CS2, - TZ1090_PIN_SPI1_DOUT, - TZ1090_PIN_SPI1_DIN, -}; - -static const unsigned int uart0_pins[] = { - TZ1090_PIN_UART0_RTS, - TZ1090_PIN_UART0_CTS, - TZ1090_PIN_UART0_TXD, - TZ1090_PIN_UART0_RXD, -}; - -static const unsigned int uart1_pins[] = { - TZ1090_PIN_UART1_TXD, - TZ1090_PIN_UART1_RXD, -}; - -static const unsigned int uart_pins[] = { - TZ1090_PIN_UART1_TXD, - TZ1090_PIN_UART1_RXD, - TZ1090_PIN_UART0_RTS, - TZ1090_PIN_UART0_CTS, - TZ1090_PIN_UART0_TXD, - TZ1090_PIN_UART0_RXD, -}; - -static const unsigned int scb0_pins[] = { - TZ1090_PIN_SCB0_SDAT, - TZ1090_PIN_SCB0_SCLK, -}; - -static const unsigned int scb1_pins[] = { - TZ1090_PIN_SCB1_SDAT, - TZ1090_PIN_SCB1_SCLK, -}; - -static const unsigned int scb2_pins[] = { - TZ1090_PIN_SCB2_SDAT, - TZ1090_PIN_SCB2_SCLK, -}; - -static const unsigned int i2s_pins[] = { - TZ1090_PIN_I2S_MCLK, - TZ1090_PIN_I2S_BCLK_OUT, - TZ1090_PIN_I2S_LRCLK_OUT, - TZ1090_PIN_I2S_DOUT0, - TZ1090_PIN_I2S_DOUT1, - TZ1090_PIN_I2S_DOUT2, - TZ1090_PIN_I2S_DIN, -}; - -static const unsigned int jtag_pins[] = { - TZ1090_PIN_TCK, - TZ1090_PIN_TRST, - TZ1090_PIN_TDI, - TZ1090_PIN_TDO, - TZ1090_PIN_TMS, -}; - -/* Pins in each drive pin group */ - -static const unsigned int drive_sdio_pins[] = { - TZ1090_PIN_SDIO_CLK, - TZ1090_PIN_SDIO_CMD, - TZ1090_PIN_SDIO_D0, - TZ1090_PIN_SDIO_D1, - TZ1090_PIN_SDIO_D2, - TZ1090_PIN_SDIO_D3, - TZ1090_PIN_SDH_WP, - TZ1090_PIN_SDH_CD, - TZ1090_PIN_SDH_CLK_IN, -}; - -static const unsigned int drive_i2s_pins[] = { - TZ1090_PIN_CLK_OUT1, - TZ1090_PIN_I2S_DIN, - TZ1090_PIN_I2S_DOUT0, - TZ1090_PIN_I2S_DOUT1, - TZ1090_PIN_I2S_DOUT2, - TZ1090_PIN_I2S_LRCLK_OUT, - TZ1090_PIN_I2S_BCLK_OUT, - TZ1090_PIN_I2S_MCLK, -}; - -static const unsigned int drive_scb0_pins[] = { - TZ1090_PIN_SCB0_SCLK, - TZ1090_PIN_SCB0_SDAT, - TZ1090_PIN_PDM_D, - TZ1090_PIN_PDM_C, -}; - -static const unsigned int drive_pdm_pins[] = { - TZ1090_PIN_CLK_OUT0, - TZ1090_PIN_PDM_B, - TZ1090_PIN_PDM_A, -}; - -/* Pin groups each function can be muxed to */ - -/* - * The magic "perip" function allows otherwise non-muxing pins to be enabled in - * peripheral mode. - */ -static const char * const perip_groups[] = { - /* non-muxing convenient gpio pingroups */ - "uart", - "uart0", - "uart1", - "spi0", - "spi1", - "scb0", - "scb1", - "scb2", - "i2s", - /* individual pins not part of a pin mux group */ - "spi0_mclk", - "spi0_cs0", - "spi0_cs1", - "spi0_cs2", - "spi0_dout", - "spi0_din", - "spi1_mclk", - "spi1_cs0", - "spi1_cs1", - "spi1_dout", - "spi1_din", - "uart0_rxd", - "uart0_txd", - "uart0_cts", - "uart0_rts", - "uart1_rxd", - "uart1_txd", - "scb0_sdat", - "scb0_sclk", - "scb1_sdat", - "scb1_sclk", - "scb2_sdat", - "scb2_sclk", - "i2s_mclk", - "i2s_bclk_out", - "i2s_lrclk_out", - "i2s_dout0", - "i2s_dout1", - "i2s_dout2", - "i2s_din", - "pdm_a", - "pdm_b", - "pdm_c", -}; - -static const char * const sdh_sdio_groups[] = { - "sdh", - "sdio", - /* sdh pins */ - "sdh_cd", - "sdh_wp", - "sdh_clk_in", - /* sdio pins */ - "sdio_clk", - "sdio_cmd", - "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", -}; - -static const char * const spi1_cs2_groups[] = { - "spi1_cs2", -}; - -static const char * const pdm_dac_groups[] = { - "pdm_d", -}; - -static const char * const usb_vbus_groups[] = { - "spi1_cs2", - "pdm_d", -}; - -static const char * const afe_groups[] = { - "afe", - /* afe pins */ - "tx_on", - "rx_on", - "pll_on", - "pa_on", - "rx_hp", - "ant_sel0", - "ant_sel1", - "gain0", - "gain1", - "gain2", - "gain3", - "gain4", - "gain5", - "gain6", - "gain7", -}; - -static const char * const tft_groups[] = { - "tft", - /* tft pins */ - "tft_red0", - "tft_red1", - "tft_red2", - "tft_red3", - "tft_red4", - "tft_red5", - "tft_red6", - "tft_red7", - "tft_green0", - "tft_green1", - "tft_green2", - "tft_green3", - "tft_green4", - "tft_green5", - "tft_green6", - "tft_green7", - "tft_blue0", - "tft_blue1", - "tft_blue2", - "tft_blue3", - "tft_blue4", - "tft_blue5", - "tft_blue6", - "tft_blue7", - "tft_vdden_gd", - "tft_panelclk", - "tft_blank_ls", - "tft_vsync_ns", - "tft_hsync_nr", - "tft_vd12acb", - "tft_pwrsave", -}; - -/* Mux functions that can be used by a mux */ - -enum tz1090_mux { - /* internal placeholder */ - TZ1090_MUX_NA = -1, - /* magic per-non-muxing-GPIO-pin peripheral mode mux */ - TZ1090_MUX_PERIP, - /* SDH/SDIO mux */ - TZ1090_MUX_SDH, - TZ1090_MUX_SDIO, - /* USB_VBUS muxes */ - TZ1090_MUX_SPI1_CS2, - TZ1090_MUX_PDM_DAC, - TZ1090_MUX_USB_VBUS, - /* AFE mux */ - TZ1090_MUX_AFE, - TZ1090_MUX_TS_OUT_0, - /* EXT_DAC mux */ - TZ1090_MUX_DAC, - TZ1090_MUX_NOT_IQADC_STB, - TZ1090_MUX_IQDAC_STB, - /* TFT mux */ - TZ1090_MUX_TFT, - TZ1090_MUX_EXT_DAC, - TZ1090_MUX_TS_OUT_1, - TZ1090_MUX_LCD_TRACE, - TZ1090_MUX_PHY_RINGOSC, -}; - -#define FUNCTION(mux, fname, group) \ - [(TZ1090_MUX_ ## mux)] = { \ - .name = #fname, \ - .groups = group##_groups, \ - .ngroups = ARRAY_SIZE(group##_groups), \ - } -/* For intermediate functions with submuxes */ -#define NULL_FUNCTION(mux, fname) \ - [(TZ1090_MUX_ ## mux)] = { \ - .name = #fname, \ - } - -/* Must correlate with enum tz1090_mux */ -static const struct tz1090_function tz1090_functions[] = { - /* FUNCTION function name pingroups */ - FUNCTION(PERIP, perip, perip), - FUNCTION(SDH, sdh, sdh_sdio), - FUNCTION(SDIO, sdio, sdh_sdio), - FUNCTION(SPI1_CS2, spi1_cs2, spi1_cs2), - FUNCTION(PDM_DAC, pdm_dac, pdm_dac), - FUNCTION(USB_VBUS, usb_vbus, usb_vbus), - FUNCTION(AFE, afe, afe), - FUNCTION(TS_OUT_0, ts_out_0, afe), - FUNCTION(DAC, ext_dac, tft), - FUNCTION(NOT_IQADC_STB, not_iqadc_stb, tft), - FUNCTION(IQDAC_STB, iqdac_stb, tft), - FUNCTION(TFT, tft, tft), - NULL_FUNCTION(EXT_DAC, _ext_dac), - FUNCTION(TS_OUT_1, ts_out_1, tft), - FUNCTION(LCD_TRACE, lcd_trace, tft), - FUNCTION(PHY_RINGOSC, phy_ringosc, tft), -}; - -/* Sub muxes */ - -/** - * MUX() - Initialise a mux description. - * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) - * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) - * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) - * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) - * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register that the mux field begins - * @mux_w: Width of mux field in register - */ -#define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ - { \ - .funcs = { \ - TZ1090_MUX_ ## f0, \ - TZ1090_MUX_ ## f1, \ - TZ1090_MUX_ ## f2, \ - TZ1090_MUX_ ## f3, \ - TZ1090_MUX_ ## f4, \ - }, \ - .reg = (REG_PINCTRL_ ## mux_r), \ - .bit = (mux_b), \ - .width = (mux_w), \ - } - -/** - * DEFINE_SUBMUX() - Defines a submux description separate from a pin group. - * @mux: Mux name (_submux is appended) - * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) - * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) - * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) - * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) - * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register that the mux field begins - * @mux_w: Width of mux field in register - * - * A sub mux is a nested mux that can be bound to a magic function number used - * by another mux description. For example value 4 of the top level mux might - * correspond to a function which has a submux pointed to in tz1090_submux[]. - * The outer mux can then take on any function in the top level mux or the - * submux, and if a submux function is chosen both muxes are updated to route - * the signal from the submux. - * - * The submux can be defined with DEFINE_SUBMUX and pointed to from - * tz1090_submux[] using SUBMUX. - */ -#define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ - static struct tz1090_muxdesc mux ## _submux = \ - MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) - -/** - * SUBMUX() - Link a submux to a function number. - * @f: Function name (TZ1090_MUX_ is prepended) - * @submux: Submux name (_submux is appended) - * - * For use in tz1090_submux[] initialisation to link an intermediate function - * number to a particular submux description. It indicates that when the - * function is chosen the signal is connected to the submux. - */ -#define SUBMUX(f, submux) [(TZ1090_MUX_ ## f)] = &(submux ## _submux) - -/** - * MUX_PG() - Initialise a pin group with mux control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) - * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) - * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) - * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) - * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register that the mux field begins - * @mux_w: Width of mux field in register - */ -#define MUX_PG(pg_name, f0, f1, f2, f3, f4, \ - mux_r, mux_b, mux_w) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .mux = MUX(f0, f1, f2, f3, f4, \ - mux_r, mux_b, mux_w), \ - } - -/** - * SIMPLE_PG() - Initialise a simple convenience pin group - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * - * A simple pin group is simply used for binding pins together so they can be - * referred to by a single name instead of having to list every pin - * individually. - */ -#define SIMPLE_PG(pg_name) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - } - -/** - * DRV_PG() - Initialise a pin group with drive control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * @slw_b: Slew register bit. - * The same bit is used for Schmitt, and Drive (*2). - */ -#define DRV_PG(pg_name, slw_b) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .drv = true, \ - .slw_bit = (slw_b), \ - } - -/* - * Define main muxing pin groups - */ - -/* submuxes */ - -/* name f0, f1, f2, f3, f4, mux r/b/w */ -DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2); - -/* bind submuxes to internal functions */ -static struct tz1090_muxdesc *tz1090_submux[] = { - SUBMUX(EXT_DAC, ext_dac), -}; - -/* - * These are the pin mux groups. Pin muxing can be enabled and disabled for each - * pin individually so these groups are internal. The mapping of pins to pin mux - * group is below (tz1090_mux_pins). - */ -static struct tz1090_pingroup tz1090_mux_groups[] = { - /* Muxing pin groups */ - /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */ - MUX_PG(sdh, SDH, SDIO, NA, NA, NA, IF_CTL, 20, 2), - MUX_PG(sdio, SDIO, SDH, NA, NA, NA, IF_CTL, 16, 2), - MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA, NA, NA, IF_CTL, 10, 2), - MUX_PG(pdm_d, PDM_DAC, USB_VBUS, NA, NA, NA, IF_CTL, 8, 2), - MUX_PG(afe, AFE, TS_OUT_0, NA, NA, NA, IF_CTL, 4, 2), - MUX_PG(tft, TFT, EXT_DAC, TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL, 0, 3), -}; - -/* - * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[]. - * Pins which aren't muxable to multiple peripherals are set to - * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable - * peripheral control of the pin. - * - * This array is initialised in tz1090_init_mux_pins(). - */ -static u8 tz1090_mux_pins[NUM_GPIOS]; - -/* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */ -#define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups) - -/** - * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping. - * - * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in - * each pin mux group in tz1090_mux_groups[]. - * - * It is assumed that no pin mux groups overlap (share pins). - */ -static void __init tz1090_init_mux_pins(void) -{ - unsigned int g, p; - const struct tz1090_pingroup *grp; - const unsigned int *pin; - - for (p = 0; p < NUM_GPIOS; ++p) - tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX; - - grp = tz1090_mux_groups; - for (g = 0, grp = tz1090_mux_groups; - g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp) - for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin) - tz1090_mux_pins[*pin] = g; -} - -/* - * These are the externally visible pin groups. Some of them allow group control - * of drive configuration. Some are just simple convenience pingroups. All the - * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the - * same pins. - * Pseudo pin groups follow in the group numbers after this array for each GPIO - * pin. Any group used for muxing must have all pins belonging to the same pin - * mux group. - */ -static struct tz1090_pingroup tz1090_groups[] = { - /* Pin groups with drive control (with no out of place pins) */ - /* pg_name, slw/schmitt/drv b */ - DRV_PG(jtag, 11 /* 11, 22 */), - DRV_PG(tft, 10 /* 10, 20 */), - DRV_PG(scb2, 9 /* 9, 18 */), - DRV_PG(spi0, 7 /* 7, 14 */), - DRV_PG(uart, 5 /* 5, 10 */), - DRV_PG(scb1, 4 /* 4, 8 */), - DRV_PG(spi1, 3 /* 3, 6 */), - DRV_PG(afe, 0 /* 0, 0 */), - - /* - * Drive specific pin groups (with odd combinations of pins which makes - * the pin group naming somewhat arbitrary) - */ - /* pg_name, slw/schmitt/drv b */ - DRV_PG(drive_sdio, 8 /* 8, 16 */), /* sdio_* + sdh_* */ - DRV_PG(drive_i2s, 6 /* 6, 12 */), /* i2s_* + clk_out1 */ - DRV_PG(drive_scb0, 2 /* 2, 4 */), /* scb0_* + pdm_{c,d} */ - DRV_PG(drive_pdm, 1 /* 1, 2 */), /* pdm_{a,b} + clk_out0 */ - - /* Convenience pin groups */ - /* pg_name */ - SIMPLE_PG(uart0), - SIMPLE_PG(uart1), - SIMPLE_PG(scb0), - SIMPLE_PG(i2s), - SIMPLE_PG(sdh), - SIMPLE_PG(sdio), - - /* pseudo-pingroups for each GPIO pin follow */ -}; - -/** - * struct tz1090_pmx - Private pinctrl data - * @dev: Platform device - * @pctl: Pin control device - * @regs: Register region - * @lock: Lock protecting coherency of pin_en, gpio_en, and SELECT regs - * @pin_en: Pins that have been enabled (32 pins packed into each element) - * @gpio_en: GPIOs that have been enabled (32 pins packed into each element) - */ -struct tz1090_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *regs; - spinlock_t lock; - u32 pin_en[3]; - u32 gpio_en[3]; -}; - -static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg) -{ - return ioread32(pmx->regs + reg); -} - -static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg) -{ - iowrite32(val, pmx->regs + reg); -} - -/* - * Pin control operations - */ - -/* each GPIO pin has it's own pseudo pingroup containing only itself */ - -static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS; -} - -static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - if (group < ARRAY_SIZE(tz1090_groups)) { - /* normal pingroup */ - return tz1090_groups[group].name; - } else { - /* individual gpio pin pseudo-pingroup */ - unsigned int pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pins[pin].name; - } -} - -static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - if (group < ARRAY_SIZE(tz1090_groups)) { - /* normal pingroup */ - *pins = tz1090_groups[group].pins; - *num_pins = tz1090_groups[group].npins; - } else { - /* individual gpio pin pseudo-pingroup */ - unsigned int pin = group - ARRAY_SIZE(tz1090_groups); - *pins = &tz1090_pins[pin].number; - *num_pins = 1; - } - - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned int offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} -#endif - -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - unsigned int reserve) -{ - unsigned int old_num = *reserved_maps; - unsigned int new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, - unsigned int *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int add_map_configs(struct device *dev, - struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - const char *group, unsigned long *configs, - unsigned int num_configs) -{ - unsigned long *dup_configs; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned int num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev, - struct device_node *np, - struct pinctrl_map **map, - unsigned int *reserved_maps, - unsigned int *num_maps) -{ - int ret; - const char *function; - unsigned long *configs = NULL; - unsigned int num_configs = 0; - unsigned int reserve; - struct property *prop; - const char *group; - - ret = of_property_read_string(np, "tz1090,function", &function); - if (ret < 0) { - /* EINVAL=missing, which is fine since it's optional */ - if (ret != -EINVAL) - dev_err(dev, "could not parse property function\n"); - function = NULL; - } - - ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); - if (ret) - return ret; - - reserve = 0; - if (function != NULL) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "tz1090,pins"); - if (ret < 0) { - dev_err(dev, "could not parse property pins\n"); - goto exit; - } - reserve *= ret; - - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "tz1090,pins", prop, group) { - if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned int *num_maps) -{ - unsigned int reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, - &reserved_maps, - num_maps); - if (ret < 0) { - tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -} - -static const struct pinctrl_ops tz1090_pinctrl_ops = { - .get_groups_count = tz1090_pinctrl_get_groups_count, - .get_group_name = tz1090_pinctrl_get_group_name, - .get_group_pins = tz1090_pinctrl_get_group_pins, -#ifdef CONFIG_DEBUG_FS - .pin_dbg_show = tz1090_pinctrl_pin_dbg_show, -#endif - .dt_node_to_map = tz1090_pinctrl_dt_node_to_map, - .dt_free_map = tz1090_pinctrl_dt_free_map, -}; - -/* - * Pin mux operations - */ - -static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_functions); -} - -static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - return tz1090_functions[function].name; -} - -static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const num_groups) -{ - /* pingroup functions */ - *groups = tz1090_functions[function].groups; - *num_groups = tz1090_functions[function].ngroups; - return 0; -} - -/** - * tz1090_pinctrl_select() - update bit in SELECT register - * @pmx: Pinmux data - * @pin: Pin number (must be within GPIO range) - */ -static void tz1090_pinctrl_select(struct tz1090_pmx *pmx, - unsigned int pin) -{ - u32 reg, reg_shift, select, val; - unsigned int pmx_index, pmx_shift; - unsigned long flags; - - /* uses base 32 instead of base 30 */ - pmx_index = pin >> 5; - pmx_shift = pin & 0x1f; - - /* select = !perip || gpio */ - select = ((~pmx->pin_en[pmx_index] | - pmx->gpio_en[pmx_index]) >> pmx_shift) & 1; - - /* find register and bit offset (base 30) */ - reg = REG_PINCTRL_SELECT + 4*(pin / 30); - reg_shift = pin % 30; - - /* modify gpio select bit */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~BIT(reg_shift); - val |= select << reg_shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); -} - -/** - * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin - * @pmx: Pinmux data - * @pin: Pin number - * @gpio_select: true to enable pin as GPIO, - * false to leave control to whatever function is enabled - * - * Records that GPIO usage is enabled/disabled so that enabling a function - * doesn't override the SELECT register bit. - */ -static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx, - unsigned int pin, - bool gpio_select) -{ - unsigned int index, shift; - u32 gpio_en; - - if (pin >= NUM_GPIOS) - return; - - /* uses base 32 instead of base 30 */ - index = pin >> 5; - shift = pin & 0x1f; - - spin_lock(&pmx->lock); - - /* keep a record whether gpio is selected */ - gpio_en = pmx->gpio_en[index]; - gpio_en &= ~BIT(shift); - if (gpio_select) - gpio_en |= BIT(shift); - pmx->gpio_en[index] = gpio_en; - - /* update the select bit */ - tz1090_pinctrl_select(pmx, pin); - - spin_unlock(&pmx->lock); -} - -/** - * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin - * @pmx: Pinmux data - * @pin: Pin number - * @perip_select: true to enable peripheral interface when not GPIO, - * false to leave pin in GPIO mode - * - * Records that peripheral usage is enabled/disabled so that SELECT register can - * be set appropriately when GPIO is disabled. - */ -static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx, - unsigned int pin, - bool perip_select) -{ - unsigned int index, shift; - u32 pin_en; - - if (pin >= NUM_GPIOS) - return; - - /* uses base 32 instead of base 30 */ - index = pin >> 5; - shift = pin & 0x1f; - - spin_lock(&pmx->lock); - - /* keep a record whether peripheral is selected */ - pin_en = pmx->pin_en[index]; - pin_en &= ~BIT(shift); - if (perip_select) - pin_en |= BIT(shift); - pmx->pin_en[index] = pin_en; - - /* update the select bit */ - tz1090_pinctrl_select(pmx, pin); - - spin_unlock(&pmx->lock); -} - -/** - * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function. - * @pmx: Pinmux data - * @desc: Pinmux description - * @function: Function to switch to - * - * Enable a particular function on a pin mux group. Since pin mux descriptions - * are nested this function is recursive. - */ -static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx, - const struct tz1090_muxdesc *desc, - unsigned int function) -{ - const int *fit; - unsigned long flags; - int mux; - unsigned int func, ret; - u32 reg, mask; - - /* find the mux value for this function, searching recursively */ - for (mux = 0, fit = desc->funcs; - mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) { - func = *fit; - if (func == function) - goto found_mux; - - /* maybe it's a sub-mux */ - if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) { - ret = tz1090_pinctrl_enable_mux(pmx, - tz1090_submux[func], - function); - if (!ret) - goto found_mux; - } - } - - return -EINVAL; -found_mux: - - /* Set up the mux */ - if (desc->width) { - mask = (BIT(desc->width) - 1) << desc->bit; - __global_lock2(flags); - reg = pmx_read(pmx, desc->reg); - reg &= ~mask; - reg |= (mux << desc->bit) & mask; - pmx_write(pmx, reg, desc->reg); - __global_unlock2(flags); - } - - return 0; -} - -/** - * tz1090_pinctrl_enable() - Enable a function on a pin group. - * @pctldev: Pin control data - * @function: Function index to enable - * @group: Group index to enable - * - * Enable a particular function on a group of pins. The per GPIO pin pseudo pin - * groups can be used (in which case the pin will be enabled in peripheral mode - * and if it belongs to a pin mux group the mux will be switched if it isn't - * already in use. Some convenience pin groups can also be used in which case - * the effect is the same as enabling the function on each individual pin in the - * group. - */ -static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev, - unsigned int function, unsigned int group) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct tz1090_pingroup *grp; - int ret; - unsigned int pin_num, mux_group, i, npins; - const unsigned int *pins; - - /* group of pins? */ - if (group < ARRAY_SIZE(tz1090_groups)) { - grp = &tz1090_groups[group]; - npins = grp->npins; - pins = grp->pins; - /* - * All pins in the group must belong to the same mux group, - * which allows us to just use the mux group of the first pin. - * By explicitly listing permitted pingroups for each function - * the pinmux core should ensure this is always the case. - */ - } else { - pin_num = group - ARRAY_SIZE(tz1090_groups); - npins = 1; - pins = &pin_num; - } - mux_group = tz1090_mux_pins[*pins]; - - /* no mux group, but can still be individually muxed to peripheral */ - if (mux_group >= TZ1090_MUX_GROUP_MAX) { - if (function == TZ1090_MUX_PERIP) - goto mux_pins; - return -EINVAL; - } - - /* mux group already set to a different function? */ - grp = &tz1090_mux_groups[mux_group]; - if (grp->func_count && grp->func != function) { - dev_err(pctldev->dev, - "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n", - __func__, tz1090_functions[function].name, - tz1090_functions[grp->func].name); - return -EBUSY; - } - - dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n", - __func__, npins, grp->name, tz1090_functions[function].name); - - /* if first pin in mux group to be enabled, enable the group mux */ - if (!grp->func_count) { - grp->func = function; - ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function); - if (ret) - return ret; - } - /* add pins to ref count and mux individually to peripheral */ - grp->func_count += npins; -mux_pins: - for (i = 0; i < npins; ++i) - tz1090_pinctrl_perip_select(pmx, pins[i], true); - - return 0; -} - -/** - * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. - * @pctldev: Pin control data - * @range: GPIO range - * @pin: Pin number - * - * Puts a particular pin into GPIO mode, disabling peripheral control until it's - * disabled again. - */ -static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - tz1090_pinctrl_gpio_select(pmx, pin, true); - return 0; -} - -/** - * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode. - * @pctldev: Pin control data - * @range: GPIO range - * @pin: Pin number - * - * Take a particular pin out of GPIO mode. If the pin is enabled for a - * peripheral it will return to peripheral mode. - */ -static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - tz1090_pinctrl_gpio_select(pmx, pin, false); -} - -static const struct pinmux_ops tz1090_pinmux_ops = { - .get_functions_count = tz1090_pinctrl_get_funcs_count, - .get_function_name = tz1090_pinctrl_get_func_name, - .get_function_groups = tz1090_pinctrl_get_func_groups, - .set_mux = tz1090_pinctrl_set_mux, - .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, - .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, -}; - -/* - * Pin config operations - */ - -struct tz1090_pinconf_pullup { - unsigned char index; - unsigned char shift; -}; - -/* The mapping of pin to pull up/down register index and shift */ -static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = { - {5, 22}, /* 0 - TZ1090_PIN_SDIO_CLK */ - {0, 14}, /* 1 - TZ1090_PIN_SDIO_CMD */ - {0, 6}, /* 2 - TZ1090_PIN_SDIO_D0 */ - {0, 8}, /* 3 - TZ1090_PIN_SDIO_D1 */ - {0, 10}, /* 4 - TZ1090_PIN_SDIO_D2 */ - {0, 12}, /* 5 - TZ1090_PIN_SDIO_D3 */ - {0, 2}, /* 6 - TZ1090_PIN_SDH_CD */ - {0, 4}, /* 7 - TZ1090_PIN_SDH_WP */ - {0, 16}, /* 8 - TZ1090_PIN_SPI0_MCLK */ - {0, 18}, /* 9 - TZ1090_PIN_SPI0_CS0 */ - {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */ - {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */ - {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */ - {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */ - {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */ - {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */ - {1, 0}, /* 16 - TZ1090_PIN_SPI1_CS1 */ - {1, 2}, /* 17 - TZ1090_PIN_SPI1_CS2 */ - {1, 4}, /* 18 - TZ1090_PIN_SPI1_DOUT */ - {1, 6}, /* 19 - TZ1090_PIN_SPI1_DIN */ - {1, 8}, /* 20 - TZ1090_PIN_UART0_RXD */ - {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */ - {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */ - {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */ - {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */ - {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */ - {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */ - {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */ - {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */ - {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */ - - {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */ - {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */ - {2, 0}, /* 32 - TZ1090_PIN_I2S_MCLK */ - {2, 2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */ - {2, 4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */ - {2, 6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */ - {2, 8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */ - {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */ - {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */ - {4, 12}, /* 39 - TZ1090_PIN_PDM_A */ - {4, 14}, /* 40 - TZ1090_PIN_PDM_B */ - {4, 18}, /* 41 - TZ1090_PIN_PDM_C */ - {4, 20}, /* 42 - TZ1090_PIN_PDM_D */ - {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */ - {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */ - {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */ - {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */ - {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */ - {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */ - {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */ - {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */ - {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */ - {3, 0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */ - {3, 2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */ - {3, 4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */ - {3, 6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */ - {3, 8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */ - {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */ - {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */ - {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */ - - {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */ - {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */ - {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */ - {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */ - {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */ - {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */ - {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */ - {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */ - {4, 0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */ - {4, 2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */ - {4, 4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */ - {4, 6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */ - {4, 8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */ - {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */ - {4, 24}, /* 74 - TZ1090_PIN_TX_ON */ - {4, 26}, /* 75 - TZ1090_PIN_RX_ON */ - {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */ - {4, 30}, /* 77 - TZ1090_PIN_PA_ON */ - {5, 0}, /* 78 - TZ1090_PIN_RX_HP */ - {5, 6}, /* 79 - TZ1090_PIN_GAIN0 */ - {5, 8}, /* 80 - TZ1090_PIN_GAIN1 */ - {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */ - {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */ - {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */ - {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */ - {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */ - {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */ - {5, 2}, /* 87 - TZ1090_PIN_ANT_SEL0 */ - {5, 4}, /* 88 - TZ1090_PIN_ANT_SEL1 */ - {0, 0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */ - - {5, 24}, /* 90 - TZ1090_PIN_TCK */ - {5, 26}, /* 91 - TZ1090_PIN_TRST */ - {5, 28}, /* 92 - TZ1090_PIN_TDI */ - {5, 30}, /* 93 - TZ1090_PIN_TDO */ - {6, 0}, /* 94 - TZ1090_PIN_TMS */ - {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */ - {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */ -}; - -static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev, - unsigned int pin, - enum pin_config_param param, - bool report_err, - u32 *reg, u32 *width, u32 *mask, u32 *shift, - u32 *val) -{ - struct tz1090_pinconf_pullup *pu; - - /* All supported pins have controllable input bias */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *val = REG_PU_PD_TRISTATE; - break; - case PIN_CONFIG_BIAS_PULL_UP: - *val = REG_PU_PD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - *val = REG_PU_PD_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - *val = REG_PU_PD_REPEATER; - break; - default: - return -ENOTSUPP; - } - - /* Only input bias parameters supported */ - pu = &tz1090_pinconf_pullup[pin]; - *reg = REG_PINCTRL_PU_PD + 4*pu->index; - *shift = pu->shift; - *width = 2; - - /* Calculate field information */ - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - int ret; - u32 reg, width, mask, shift, val, tmp, arg; - - /* Get register information */ - ret = tz1090_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Extract field from register */ - tmp = pmx_read(pmx, reg); - arg = ((tmp & mask) >> shift) == val; - - /* Config not active */ - if (!arg) - return -EINVAL; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - unsigned int arg; - int ret; - u32 reg, width, mask, shift, val, tmp; - unsigned long flags; - int i; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", - __func__, tz1090_pins[pin].name, configs[i]); - - /* Get register information */ - ret = tz1090_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Unpack argument and range check it */ - if (arg > 1) { - dev_dbg(pctldev->dev, "%s: arg %u out of range\n", - __func__, arg); - return -EINVAL; - } - - /* Write register field */ - __global_lock2(flags); - tmp = pmx_read(pmx, reg); - tmp &= ~mask; - if (arg) - tmp |= val << shift; - pmx_write(pmx, tmp, reg); - __global_unlock2(flags); - } /* for each config */ - - return 0; -} - -static const int tz1090_boolean_map[] = { - [0] = -EINVAL, - [1] = 1, -}; - -static const int tz1090_dr_map[] = { - [REG_DR_2mA] = 2, - [REG_DR_4mA] = 4, - [REG_DR_8mA] = 8, - [REG_DR_12mA] = 12, -}; - -static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev, - const struct tz1090_pingroup *g, - enum pin_config_param param, - bool report_err, - u32 *reg, u32 *width, u32 *mask, u32 *shift, - const int **map) -{ - /* Drive configuration applies in groups, but not to all groups. */ - if (!g->drv) { - if (report_err) - dev_dbg(pctldev->dev, - "%s: group %s has no drive control\n", - __func__, g->name); - return -ENOTSUPP; - } - - /* Find information about drive parameter's register */ - switch (param) { - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - *reg = REG_PINCTRL_SCHMITT; - *width = 1; - *map = tz1090_boolean_map; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - *reg = REG_PINCTRL_DR; - *width = 2; - *map = tz1090_dr_map; - break; - default: - return -ENOTSUPP; - } - - /* Calculate field information */ - *shift = g->slw_bit * *width; - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *config) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pingroup *g; - enum pin_config_param param = pinconf_to_config_param(*config); - int ret, arg; - unsigned int pin; - u32 reg, width, mask, shift, val; - const int *map; - - if (group >= ARRAY_SIZE(tz1090_groups)) { - pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pinconf_get(pctldev, pin, config); - } - - g = &tz1090_groups[group]; - if (g->npins == 1) { - pin = g->pins[0]; - ret = tz1090_pinconf_get(pctldev, pin, config); - if (ret != -ENOTSUPP) - return ret; - } - - /* Get register information */ - ret = tz1090_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, &map); - if (ret < 0) - return ret; - - /* Extract field from register */ - val = pmx_read(pmx, reg); - arg = map[(val & mask) >> shift]; - if (arg < 0) - return arg; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pingroup *g; - enum pin_config_param param; - unsigned int arg, pin, i; - const unsigned int *pit; - int ret; - u32 reg, width, mask, shift, val; - unsigned long flags; - const int *map; - int j; - - if (group >= ARRAY_SIZE(tz1090_groups)) { - pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pinconf_set(pctldev, pin, configs, num_configs); - } - - g = &tz1090_groups[group]; - if (g->npins == 1) { - pin = g->pins[0]; - ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs); - if (ret != -ENOTSUPP) - return ret; - } - - for (j = 0; j < num_configs; j++) { - param = pinconf_to_config_param(configs[j]); - - dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", - __func__, g->name, configs[j]); - - /* Get register information */ - ret = tz1090_pinconf_group_reg(pctldev, g, param, true, ®, - &width, &mask, &shift, &map); - if (ret < 0) { - /* - * Maybe we're trying to set a per-pin configuration - * of a group, so do the pins one by one. This is - * mainly as a convenience. - */ - for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { - ret = tz1090_pinconf_set(pctldev, *pit, configs, - num_configs); - if (ret) - return ret; - } - return 0; - } - - /* Unpack argument and map it to register value */ - arg = pinconf_to_config_argument(configs[j]); - for (i = 0; i < BIT(width); ++i) { - if (map[i] == arg || (map[i] == -EINVAL && !arg)) { - /* Write register field */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~mask; - val |= i << shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); - goto next_config; - } - } - - dev_dbg(pctldev->dev, "%s: arg %u not supported\n", - __func__, arg); - return -EINVAL; - -next_config: - ; - } /* for each config */ - - return 0; -} - -static const struct pinconf_ops tz1090_pinconf_ops = { - .is_generic = true, - .pin_config_get = tz1090_pinconf_get, - .pin_config_set = tz1090_pinconf_set, - .pin_config_group_get = tz1090_pinconf_group_get, - .pin_config_group_set = tz1090_pinconf_group_set, - .pin_config_config_dbg_show = pinconf_generic_dump_config, -}; - -/* - * Pin control driver setup - */ - -static struct pinctrl_desc tz1090_pinctrl_desc = { - .pctlops = &tz1090_pinctrl_ops, - .pmxops = &tz1090_pinmux_ops, - .confops = &tz1090_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int tz1090_pinctrl_probe(struct platform_device *pdev) -{ - struct tz1090_pmx *pmx; - struct resource *res; - - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); - if (!pmx) - return -ENOMEM; - - pmx->dev = &pdev->dev; - spin_lock_init(&pmx->lock); - - tz1090_pinctrl_desc.name = dev_name(&pdev->dev); - tz1090_pinctrl_desc.pins = tz1090_pins; - tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pmx->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pmx->regs)) - return PTR_ERR(pmx->regs); - - pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pinctrl_desc, - pmx); - if (IS_ERR(pmx->pctl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pmx->pctl); - } - - platform_set_drvdata(pdev, pmx); - - dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n"); - - return 0; -} - -static const struct of_device_id tz1090_pinctrl_of_match[] = { - { .compatible = "img,tz1090-pinctrl", }, - { }, -}; - -static struct platform_driver tz1090_pinctrl_driver = { - .driver = { - .name = "tz1090-pinctrl", - .of_match_table = tz1090_pinctrl_of_match, - }, - .probe = tz1090_pinctrl_probe, -}; - -static int __init tz1090_pinctrl_init(void) -{ - tz1090_init_mux_pins(); - return platform_driver_register(&tz1090_pinctrl_driver); -} -arch_initcall(tz1090_pinctrl_init); - -static void __exit tz1090_pinctrl_exit(void) -{ - platform_driver_unregister(&tz1090_pinctrl_driver); -} -module_exit(tz1090_pinctrl_exit); - -MODULE_AUTHOR("Imagination Technologies Ltd."); -MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match); -- cgit v1.2.3 From af7b9b7983c4bae7ca931f3d18c10ae572b5673c Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Wed, 14 Feb 2018 11:27:58 +0800 Subject: dt-bindings: PCI: MediaTek: fix dtc warnings dtc recently added PCI bus checks. Fix these warnings: Warning (pci_bridge): Node /pcie@1a140000/pcie@0,0 missing bus-range for PCI bridge Warning (pci_bridge): Node /pcie@1a140000/pcie@1,0 missing bus-range for PCI bridge Warning (pci_bridge): Node /pcie@1a140000/pcie@2,0 missing bus-range for PCI bridge Warning (unit_address_format): Failed prerequisite 'pci_bridge' Warning (pci_device_reg): Failed prerequisite 'pci_bridge' Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge' Signed-off-by: Ryder Lee Signed-off-by: Lorenzo Pieralisi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt index 3a6ce55dd310..20227a875ac8 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt @@ -78,7 +78,7 @@ Examples for MT7623: #reset-cells = <1>; }; - pcie: pcie-controller@1a140000 { + pcie: pcie@1a140000 { compatible = "mediatek,mt7623-pcie"; device_type = "pci"; reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */ @@ -111,7 +111,6 @@ Examples for MT7623: 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ pcie@0,0 { - device_type = "pci"; reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -123,7 +122,6 @@ Examples for MT7623: }; pcie@1,0 { - device_type = "pci"; reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -135,7 +133,6 @@ Examples for MT7623: }; pcie@2,0 { - device_type = "pci"; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -148,6 +145,7 @@ Examples for MT7623: }; Examples for MT2712: + pcie: pcie@11700000 { compatible = "mediatek,mt2712-pcie"; device_type = "pci"; @@ -169,7 +167,6 @@ Examples for MT2712: ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; pcie0: pcie@0,0 { - device_type = "pci"; reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -189,7 +186,6 @@ Examples for MT2712: }; pcie1: pcie@1,0 { - device_type = "pci"; reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -210,6 +206,7 @@ Examples for MT2712: }; Examples for MT7622: + pcie: pcie@1a140000 { compatible = "mediatek,mt7622-pcie"; device_type = "pci"; @@ -243,7 +240,6 @@ Examples for MT7622: ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; pcie0: pcie@0,0 { - device_type = "pci"; reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -263,7 +259,6 @@ Examples for MT7622: }; pcie1: pcie@1,0 { - device_type = "pci"; reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; -- cgit v1.2.3 From 7e065fb9ccce89fe667fdbd9a177eaec59a359fc Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 22 Feb 2018 16:22:46 +0100 Subject: pinctrl: artpec6: dt: add missing pin group uart5nocts Add missing pin group uart5nocts (all pins except cts), which has been supported by the artpec6 pinctrl driver since its initial submission. Fixes: 00df0582eab1 ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC") Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt index 47284f85ec80..c3f9826692bc 100644 --- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt @@ -20,7 +20,8 @@ Required subnode-properties: gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0, - uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0 + uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0, + uart5nocts cpuclkout: cpuclkoutgrp0 udlclkout: udlclkoutgrp0 i2c1: i2c1grp0 @@ -37,7 +38,7 @@ Required subnode-properties: uart2: uart2grp0, uart2grp1 uart3: uart3grp0 uart4: uart4grp0 - uart5: uart5grp0 + uart5: uart5grp0, uart5nocts nand: nandgrp0 sdio0: sdio0grp0 sdio1: sdio1grp0 -- cgit v1.2.3 From 928af2247785f7a1aec21e82a3ceba7c0c85f593 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 22 Feb 2018 16:22:47 +0100 Subject: pinctrl: artpec6: dt: add smaller groups for uarts Add group configuration for uarts that are cut down variants, the standard being full, i.e. all signals, flow control, i.e. rx/tx and cts/rts, and rx/tx only. This allows us to be more precise in which pins we're actually using. Unfortunately the existing naming scheme leaves things to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS, yet uart0grp0 means all pins. Since the exising suffixes have different meaning for different uarts, and the fact that we cannot change the name of existing groups, makes it hard to use a descriptive name for the newly added groups. Signed-off-by: Niklas Cassel Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt index c3f9826692bc..678f5097058e 100644 --- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt @@ -19,8 +19,9 @@ Required subnode-properties: Available functions and groups (function: group0, group1...): gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, - spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0, - uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0, + spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, + uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, + uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, uart5nocts cpuclkout: cpuclkoutgrp0 udlclkout: udlclkoutgrp0 @@ -33,12 +34,12 @@ Required subnode-properties: spi0: spi0grp0 spi1: spi1grp0 pciedebug: pciedebuggrp0 - uart0: uart0grp0, uart0grp1 - uart1: uart1grp0 - uart2: uart2grp0, uart2grp1 + uart0: uart0grp0, uart0grp1, uart0grp2 + uart1: uart1grp0, uart1grp1 + uart2: uart2grp0, uart2grp1, uart2grp2 uart3: uart3grp0 - uart4: uart4grp0 - uart5: uart5grp0, uart5nocts + uart4: uart4grp0, uart4grp1 + uart5: uart5grp0, uart5grp1, uart5nocts nand: nandgrp0 sdio0: sdio0grp0 sdio1: sdio1grp0 -- cgit v1.2.3 From fc471710c62f28942aef5950384e0bffd224f249 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Fri, 23 Feb 2018 18:16:21 +0800 Subject: dt-bindings: pinctrl: mediatek: use - instead of _ in examples It should be good that no use "_" is in examples. Consequently, those nodes in certain files which have an inappropriate name containing "_" are all being replaced with "-". Signed-off-by: Sean Wang Cc: Linus Walleij Cc: Rob Herring Cc: Mark Rutland Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index afa8a18ea11a..e7d6f81c227f 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -76,12 +76,12 @@ Examples: ... { - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscfg-pctl-a@10005000 { compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; - syscfg_pctl_b: syscfg_pctl_b@1020c020 { + syscfg_pctl_b: syscfg-pctl-b@1020c020 { compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; reg = <0 0x1020C020 0 0x1000>; }; -- cgit v1.2.3 From c910d6ad2f0af58a0754ac74f3934200a050ac2c Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Sat, 24 Feb 2018 10:07:17 +0800 Subject: dt-bindings: gpio: Add Spreadtrum GPIO controller documentation This patch adds the device tree bindings for the Spreadtrum GPIO controller. The gpios will be supported by the GPIO generic library. Signed-off-by: Baolin Wang Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-sprd.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sprd.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt new file mode 100644 index 000000000000..eca97d45388f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt @@ -0,0 +1,28 @@ +Spreadtrum GPIO controller bindings + +The controller's registers are organized as sets of sixteen 16-bit +registers with each set controlling a bank of up to 16 pins. A single +interrupt is shared for all of the banks handled by the controller. + +Required properties: +- compatible: Should be "sprd,sc9860-gpio". +- reg: Define the base and range of the I/O address space containing +the GPIO controller registers. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be <2>. The first cell is the gpio number and +the second cell is used to specify optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be <2>. Specifies the number of cells needed +to encode interrupt source. +- interrupts: Should be the port interrupt shared by all the gpios. + +Example: + ap_gpio: gpio@40280000 { + compatible = "sprd,sc9860-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; -- cgit v1.2.3 From 2ba08d75eb77a59e8476801b734ff9981c3492b6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 2 Mar 2018 09:20:36 +0530 Subject: dt-bindings: pinctrl: Add bindings for Actions S900 SoC Add pinctrl bindings for Actions Semi S900 SoC Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/pinctrl/actions,s900-pinctrl.txt | 178 +++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt new file mode 100644 index 000000000000..fb87c7d74f2e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt @@ -0,0 +1,178 @@ +Actions Semi S900 Pin Controller + +This binding describes the pin controller found in the S900 SoC. + +Required Properties: + +- compatible: Should be "actions,s900-pinctrl" +- reg: Should contain the register base address and size of + the pin controller. +- clocks: phandle of the clock feeding the pin controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Pinmux functions are available only for the pin groups while pinconf +parameters are available for both pin groups and individual pins. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +Required Properties: + +- pins: An array of strings, each string containing the name of a pin. + These pins are used for selecting the pull control and schmitt + trigger parameters. The following are the list of pins + available: + + eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, + eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, + sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, + i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, + eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, + lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, + lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, + lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, + sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, + sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, + uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, + uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, + uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, + i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, + csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, + csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, + dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, + csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, + sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, + nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, + nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, + nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, + nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, + nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, + nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 + +- groups: An array of strings, each string containing the name of a pin + group. These pin groups are used for selecting the pinmux + functions. + + lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, + sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, + rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, + rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, + i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, + pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, + eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, + eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, + lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, + spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, + uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, + csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, + dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, + nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, + csi1_dn0_dp0_mfp, uart4_rx_tx_mfp + + + These pin groups are used for selecting the drive strength + parameters. + + sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, + rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, + rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, + sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, + i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, + lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, + sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, + spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, + uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv + + These pin groups are used for selecting the slew rate + parameters. + + sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, + rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, + rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, + i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, + pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, + spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, + uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, + sensor0_sr + +- function: An array of strings, each string containing the name of the + pinmux functions. These functions can only be selected by + the corresponding pin groups. The following are the list of + pinmux functions available: + + eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, + sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, + usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, + nand1, spdif, sirq0, sirq1, sirq2 + +Optional Properties: + +- bias-bus-hold: No arguments. The specified pins should retain the previous + state value. +- bias-high-impedance: No arguments. The specified pins should be configured + as high impedance. +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- slew-rate: Integer. Sets slew rate for the specified pins. + Valid values are: + <0> - Slow + <1> - Fast +- drive-strength: Integer. Selects the drive strength for the specified + pins in mA. + Valid values are: + <2> + <4> + <8> + <12> + +Example: + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + + uart2-default: uart2-default { + pinmux { + groups = "lvds_oep_odn_mfp"; + function = "uart2"; + }; + pinconf { + groups = "lvds_oep_odn_drv"; + drive-strength = <12>; + }; + }; + }; -- cgit v1.2.3 From 695788fd1b41938e86b9fba9670f751599836b2d Mon Sep 17 00:00:00 2001 From: "lionel.debieve@st.com" Date: Thu, 15 Feb 2018 14:03:09 +0100 Subject: dt-bindings: rng: add reset node for stm32 Adding optional resets property for rng. Signed-off-by: Lionel Debieve Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt index 47f04176f93b..cb7ca78135ff 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt @@ -11,6 +11,9 @@ Required properties: - interrupts : The designated IRQ line for the RNG - clocks : The clock needed to enable the RNG +Optional properties: +- resets : The reset to properly start RNG + Example: rng: rng@50060800 { -- cgit v1.2.3 From a888df9b89b785c6dc6fcbf886f0ccda57f98b3a Mon Sep 17 00:00:00 2001 From: "lionel.debieve@st.com" Date: Thu, 15 Feb 2018 14:03:11 +0100 Subject: dt-bindings: rng: add clock detection error for stm32 Add optional property to enable the clock detection error on rng block. It is used to allow slow clock source which give correct entropy for rng. Signed-off-by: Lionel Debieve Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/st,stm32-rng.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt index cb7ca78135ff..1dfa7d51e006 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.txt +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.txt @@ -13,6 +13,7 @@ Required properties: Optional properties: - resets : The reset to properly start RNG +- clock-error-detect : Enable the clock detection management Example: -- cgit v1.2.3 From 9d3a45ea209fd1daf3bb9e66a07caf59bf7da9fc Mon Sep 17 00:00:00 2001 From: Gilad Ben-Yossef Date: Mon, 19 Feb 2018 14:51:22 +0000 Subject: dt-bindings: Add DT bindings for ccree 710 and 630p Add device tree bindings for Arm CryptoCell 710 and 630p hardware revisions. Signed-off-by: Gilad Ben-Yossef Reviewed-by: Rob Herring Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/crypto/arm-cryptocell.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt index cec8d5d74e26..c2598ab27f2e 100644 --- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt +++ b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt @@ -1,7 +1,8 @@ Arm TrustZone CryptoCell cryptographic engine Required properties: -- compatible: Should be "arm,cryptocell-712-ree". +- compatible: Should be one of: "arm,cryptocell-712-ree", + "arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree". - reg: Base physical address of the engine and length of memory mapped region. - interrupts: Interrupt number for the device. -- cgit v1.2.3 From e3e44549163539b51056b569013ec69c47b1be0a Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 19 Feb 2018 23:35:55 +0100 Subject: dt-bindings: mtd: remove pxa3xx NAND controller documentation The deprecated pxa3xx_nand.c driver does not exist anymore, it has been replaced by marvell_nand.c which has its own up-to-date documentation. Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Tested-by: Robert Jarzmik Signed-off-by: Boris Brezillon --- .../devicetree/bindings/mtd/pxa3xx-nand.txt | 50 ---------------------- 1 file changed, 50 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt deleted file mode 100644 index d4ee4da58463..000000000000 --- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt +++ /dev/null @@ -1,50 +0,0 @@ -PXA3xx NAND DT bindings - -Required properties: - - - compatible: Should be set to one of the following: - marvell,pxa3xx-nand - marvell,armada370-nand - marvell,armada-8k-nand - - reg: The register base for the controller - - interrupts: The interrupt to map - - #address-cells: Set to <1> if the node includes partitions - - marvell,system-controller: Set to retrieve the syscon node that handles - NAND controller related registers (only required - with marvell,armada-8k-nand compatible). - -Optional properties: - - - dmas: dma data channel, see dma.txt binding doc - - marvell,nand-enable-arbiter: Set to enable the bus arbiter - - marvell,nand-keep-config: Set to keep the NAND controller config as set - by the bootloader - - num-cs: Number of chipselect lines to use - - nand-on-flash-bbt: boolean to enable on flash bbt option if - not present false - - nand-ecc-strength: number of bits to correct per ECC step - - nand-ecc-step-size: number of data bytes covered by a single ECC step - -The following ECC strength and step size are currently supported: - - - nand-ecc-strength = <1>, nand-ecc-step-size = <512> - - nand-ecc-strength = <4>, nand-ecc-step-size = <512> - - nand-ecc-strength = <8>, nand-ecc-step-size = <512> - -Example: - - nand0: nand@43100000 { - compatible = "marvell,pxa3xx-nand"; - reg = <0x43100000 90>; - interrupts = <45>; - dmas = <&pdma 97 0>; - dma-names = "data"; - #address-cells = <1>; - - marvell,nand-enable-arbiter; - marvell,nand-keep-config; - num-cs = <1>; - - /* partitions (optional) */ - }; - -- cgit v1.2.3 From c0879ed6188789c6252e91cedabf46236cfa1d42 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 23 Feb 2018 12:11:00 +0100 Subject: dt-bindings: iio: adc: stm32-dfsdm: fix types, add missing pinctrl - Add missing pinctrl description. Support is made optional as dfsdm may use internal sources (e.g. via registers) - Fix typo in IIO STM32 DFSDM filter "MANCH_F" description. Basically, this should be "falling edge = logic 0", not "1" that applies to "MANCH_R". BTW, make the description complete by describing both rising/falling edges as described in reference manuals. Fixes: 6c82f947fc97 ("IIO: add DT bindings for stm32 DFSDM filter") Signed-off-by: Fabrice Gasnier Reviewed-by: Rob Herring Signed-off-by: Jonathan Cameron --- Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt index 911492da48f3..ed7520d1d051 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt @@ -32,6 +32,10 @@ Optional properties: to "clock" property. Frequency must be a multiple of the rcc clock frequency. If not, SPI CLKOUT frequency will not be accurate. +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration + nodes to set pins in mode of operation for dfsdm + on external pin. Contents of a STM32 DFSDM child nodes: -------------------------------------- @@ -68,8 +72,8 @@ Optional properties: - st,adc-channel-types: Single-ended channel input type. - "SPI_R": SPI with data on rising edge (default) - "SPI_F": SPI with data on falling edge - - "MANCH_R": manchester codec, rising edge = logic 0 - - "MANCH_F": manchester codec, falling edge = logic 1 + - "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1 + - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0 - st,adc-channel-clk-src: Conversion clock source. - "CLKIN": external SPI clock (CLKIN x) - "CLKOUT": internal SPI clock (CLKOUT) (default) -- cgit v1.2.3 From 2b77f0083a7c2e57ecc38d82b11213dc51f733c8 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Thu, 8 Feb 2018 14:11:08 +0100 Subject: watchdog: imx2_wdt: allow setting timeout in devicetree By following best practice described in Documentation/watchdog/watchdog-kernel-api.txt, it also let us to set timout-sec property in devicetree. Signed-off-by: Marcus Folkesson Reviewed-by: Guenter Roeck Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt | 2 ++ drivers/watchdog/imx2_wdt.c | 8 ++------ 2 files changed, 4 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt index 107280ef0025..adc6b76fcb3a 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt @@ -11,6 +11,7 @@ Optional properties: detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. - fsl,ext-reset-output: If present the watchdog device is configured to assert its external reset (WDOG_B) instead of issuing a software reset. +- timeout-sec : Contains the watchdog timeout in seconds Examples: @@ -19,4 +20,5 @@ wdt@73f98000 { reg = <0x73f98000 0x4000>; interrupts = <58>; big-endian; + timeout-sec = <20>; }; diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c index 518dfa1047cb..f07850d2c977 100644 --- a/drivers/watchdog/imx2_wdt.c +++ b/drivers/watchdog/imx2_wdt.c @@ -76,7 +76,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -static unsigned timeout = IMX2_WDT_DEFAULT_TIME; +static unsigned timeout; module_param(timeout, uint, 0); MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")"); @@ -281,6 +281,7 @@ static int __init imx2_wdt_probe(struct platform_device *pdev) wdog->info = &imx2_wdt_info; wdog->ops = &imx2_wdt_ops; wdog->min_timeout = 1; + wdog->timeout = IMX2_WDT_DEFAULT_TIME; wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000; wdog->parent = &pdev->dev; @@ -299,11 +300,6 @@ static int __init imx2_wdt_probe(struct platform_device *pdev) wdev->ext_reset = of_property_read_bool(pdev->dev.of_node, "fsl,ext-reset-output"); - wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME); - if (wdog->timeout != timeout) - dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n", - timeout, wdog->timeout); - platform_set_drvdata(pdev, wdog); watchdog_set_drvdata(wdog, wdev); watchdog_set_nowayout(wdog, nowayout); -- cgit v1.2.3 From 1d1dedc2169416198a48cd43cee9bdd1a9c939ac Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Sun, 11 Feb 2018 21:08:42 +0100 Subject: watchdog: sunxi: allow setting timeout in devicetree watchdog_init_timeout() will allways pick timeout_param since it defaults to a valid timeout. By following best practice described in Documentation/watchdog/watchdog-kernel-api.txt, it also let us to set timout-sec property in devicetree. Signed-off-by: Marcus Folkesson Reviewed-by: Guenter Roeck Reviewed-by: Rob Herring Reviewed-by: Chen-Yu Tsai Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 4 ++++ drivers/watchdog/sunxi_wdt.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index 62dd5baad70e..49900e72f6b1 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -6,9 +6,13 @@ Required properties: "allwinner,sun6i-a31-wdt" - reg : Specifies base physical address and size of the registers. +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + Example: wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; + timeout-sec = <10>; }; diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c index 802e31b1416d..c6c73656997e 100644 --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c @@ -39,7 +39,7 @@ #define DRV_VERSION "1.0" static bool nowayout = WATCHDOG_NOWAYOUT; -static unsigned int timeout = WDT_MAX_TIMEOUT; +static unsigned int timeout; /* * This structure stores the register offsets for different variants -- cgit v1.2.3 From f70b14540aecf09a158734c2c3db11bf9557b34f Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Sun, 11 Feb 2018 21:08:43 +0100 Subject: watchdog: sirfsoc: allow setting timeout in devicetree watchdog_init_timeout() will allways pick timeout_param since it defaults to a valid timeout. By following best practice described in Documentation/watchdog/watchdog-kernel-api.txt, it also let us to set timout-sec property in devicetree. Signed-off-by: Marcus Folkesson Reviewed-by: Guenter Roeck Reviewed-by: Rob Herring Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt | 4 ++++ drivers/watchdog/sirfsoc_wdt.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt index 9cbc76c89b2b..0dce5e3100b4 100644 --- a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt @@ -5,10 +5,14 @@ Required properties: - reg: Address range of tick timer/WDT register set - interrupts: interrupt number to the cpu +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + Example: timer@b0020000 { compatible = "sirf,prima2-tick"; reg = <0xb0020000 0x1000>; interrupts = <0>; + timeout-sec = <30>; }; diff --git a/drivers/watchdog/sirfsoc_wdt.c b/drivers/watchdog/sirfsoc_wdt.c index 4eea351e09b0..ac0c9d2c4aee 100644 --- a/drivers/watchdog/sirfsoc_wdt.c +++ b/drivers/watchdog/sirfsoc_wdt.c @@ -29,7 +29,7 @@ #define SIRFSOC_WDT_MAX_TIMEOUT (10 * 60) /* 10 mins */ #define SIRFSOC_WDT_DEFAULT_TIMEOUT 30 /* 30 secs */ -static unsigned int timeout = SIRFSOC_WDT_DEFAULT_TIMEOUT; +static unsigned int timeout; static bool nowayout = WATCHDOG_NOWAYOUT; module_param(timeout, uint, 0); -- cgit v1.2.3 From b82e6953acf46466b97bc592492f206b719f58b5 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Sun, 11 Feb 2018 21:08:45 +0100 Subject: watchdog: mtk: allow setting timeout in devicetree watchdog_init_timeout() will allways pick timeout_param since it defaults to a valid timeout. By following best practice described in Documentation/watchdog/watchdog-kernel-api.txt, it also let us to set timout-sec property in devicetree. Signed-off-by: Marcus Folkesson Reviewed-by: Guenter Roeck Acked-by: Matthias Brugger Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 4 ++++ drivers/watchdog/mtk_wdt.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 5b38a30e608c..859dee167b91 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -11,9 +11,13 @@ Required properties: - reg : Specifies base physical address and size of the registers. +Optional properties: +- timeout-sec: contains the watchdog timeout in seconds. + Example: wdt: watchdog@10000000 { compatible = "mediatek,mt6589-wdt"; reg = <0x10000000 0x18>; + timeout-sec = <10>; }; diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 7ed417a765c7..fcdc10ec28a3 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -57,7 +57,7 @@ #define DRV_VERSION "1.0" static bool nowayout = WATCHDOG_NOWAYOUT; -static unsigned int timeout = WDT_MAX_TIMEOUT; +static unsigned int timeout; struct mtk_wdt_dev { struct watchdog_device wdt_dev; -- cgit v1.2.3 From 4590d62cb16bebdc36b951067eeeaef02ea213c3 Mon Sep 17 00:00:00 2001 From: Marcus Folkesson Date: Sun, 11 Feb 2018 21:08:46 +0100 Subject: watchdog: meson: allow setting timeout in devicetree watchdog_init_timeout() will allways pick timeout_param since it defaults to a valid timeout. By following best practice described in Documentation/watchdog/watchdog-kernel-api.txt, it also let us to set timout-sec property in devicetree. Signed-off-by: Marcus Folkesson Reviewed-by: Guenter Roeck Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- Documentation/devicetree/bindings/watchdog/meson-wdt.txt | 4 ++++ drivers/watchdog/meson_wdt.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt index 8a6d84cb36c9..7588cc3971bf 100644 --- a/Documentation/devicetree/bindings/watchdog/meson-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/meson-wdt.txt @@ -9,9 +9,13 @@ Required properties: "amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs - reg : Specifies base physical address and size of the registers. +Optional properties: +- timeout-sec: contains the watchdog timeout in seconds. + Example: wdt: watchdog@c1109900 { compatible = "amlogic,meson6-wdt"; reg = <0xc1109900 0x8>; + timeout-sec = <10>; }; diff --git a/drivers/watchdog/meson_wdt.c b/drivers/watchdog/meson_wdt.c index 304274c67735..cd0275a6cdac 100644 --- a/drivers/watchdog/meson_wdt.c +++ b/drivers/watchdog/meson_wdt.c @@ -36,7 +36,7 @@ #define MESON_SEC_TO_TC(s, c) ((s) * (c)) static bool nowayout = WATCHDOG_NOWAYOUT; -static unsigned int timeout = MESON_WDT_TIMEOUT; +static unsigned int timeout; struct meson_wdt_data { unsigned int enable; -- cgit v1.2.3 From db1de9dd83341382f00ed1872d82b266e9137657 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 27 Feb 2018 14:54:56 +0900 Subject: dmaengine: usb-dmac: add binding for r8a77965 This patch adds binding for r8a77965 (R-Car M3-N). Signed-off-by: Yoshihiro Shimoda Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt index f3d1f151ba80..9dc935e24e55 100644 --- a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt @@ -11,6 +11,7 @@ Required Properties: - "renesas,r8a7794-usb-dmac" (R-Car E2) - "renesas,r8a7795-usb-dmac" (R-Car H3) - "renesas,r8a7796-usb-dmac" (R-Car M3-W) + - "renesas,r8a77965-usb-dmac" (R-Car M3-N) - reg: base address and length of the registers block for the DMAC - interrupts: interrupt specifiers for the DMAC, one for each entry in interrupt-names. -- cgit v1.2.3 From 788778b0d21a6d5cd5bc6c880591119e17932327 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 18 Jan 2018 01:28:11 +0900 Subject: mmc: tmio: deprecate "toshiba, mmc-wrprotect-disable" DT property This property is equivalent to "disable-wp" defined in Documentation/devicetree/bindings/mmc/mmc.txt The TMIO MMC core calls mmc_of_parse(), and it sets MMC_CAP2_NO_WRITE_PROTECT if "disable-wp" property is present. We do not need a vendor-specific property to do the same thing. Let's remove the description from the dt-binding to prevent new boards from using it. I am keeping the driver code for existing DT files, but added comments that this is deprecated. Signed-off-by: Masahiro Yamada Acked-by: Rob Herring Reviewed-by: Wolfram Sang Signed-off-by: Ulf Hansson Tested-by: Wolfram Sang --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 - drivers/mmc/host/tmio_mmc_core.c | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index d8685cb83325..2d5287eeed95 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -50,7 +50,6 @@ Required properties: 2: R7S72100 Optional properties: -- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable - pinctrl-names: should be "default", "state_uhs" - pinctrl-0: should contain default/high speed pin ctrl - pinctrl-1: should contain uhs mode pin ctrl diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index fb5a29c93ec5..f5da8bbf6dd3 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -1120,6 +1120,11 @@ static void tmio_mmc_of_parse(struct platform_device *pdev, if (!np) return; + /* + * DEPRECATED: + * For new platforms, please use "disable-wp" instead of + * "toshiba,mmc-wrprotect-disable" + */ if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL)) mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT; } -- cgit v1.2.3 From df1d7c8d45a50aa0441b413bbd8f4d51438038a8 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Mon, 5 Mar 2018 15:03:19 +0800 Subject: mmc: dt-bindings: add support for MT7622 SoC Add the devicetree binding for MT7622 SoC Signed-off-by: Sean Wang Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 9b8017670870..f33467a54a05 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 + "mediatek,mt7622-mmc": for MT7622 SoC "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC - reg: physical base address of the controller and length -- cgit v1.2.3 From eae3c955bbe37f075035765716b948a8491c46b1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 5 Mar 2018 16:18:49 -0800 Subject: dt-bindings: memory: ti-emif: add edac support under emif Certain revisions of the TI EMIF IP contain ECC support in them. Reflect this in the DT binding. Also, add interrupts property as a required property for the emif controller, as all revisions of the emif IP contain interrupt support; this might remain unused by the kernel driver though. Reviewed-by: Rob Herring Signed-off-by: Tero Kristo Signed-off-by: Santosh Shilimkar --- .../devicetree/bindings/memory-controllers/ti/emif.txt | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt index 621b41c79faa..44d71469c914 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt @@ -3,7 +3,9 @@ EMIF - External Memory Interface - is an SDRAM controller used in TI SoCs. EMIF supports, based on the IP revision, one or more of DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance -of the EMIF IP and memory parts attached to it. +of the EMIF IP and memory parts attached to it. Certain revisions +of the EMIF controller also contain optional ECC support, which +corrects one bit errors and detects two bit errors. Required properties: - compatible : Should be of the form "ti,emif-" where @@ -11,6 +13,8 @@ Required properties: compatible should be one of the following: "ti,emif-am3352" "ti,emif-am4372" + "ti,emif-dra7xx" + "ti,emif-keystone" - phy-type : indicating the DDR phy type. Following are the allowed values @@ -22,6 +26,7 @@ Required properties: - ti,hwmods : For TI hwmods processing and omap device creation the value shall be "emif" where is the number of the EMIF instance with base 1. +- interrupts : interrupt used by the controller Required only for "ti,emif-am3352" and "ti,emif-am4372": - sram : Phandles for generic sram driver nodes, @@ -71,3 +76,9 @@ emif: emif@4c000000 { sram = <&pm_sram_code &pm_sram_data>; }; + +emif1: emif@4c000000 { + compatible = "ti,emif-dra7xx"; + reg = <0x4c000000 0x200>; + interrupts = ; +}; -- cgit v1.2.3 From 1888d3ddc3d6a2511be86045cfb2e7ea5fc67c44 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Thu, 15 Feb 2018 18:51:41 +0000 Subject: drivers/bus: Move Arm CCN PMU driver The arm-ccn driver is purely a perf driver for the CCN PMU, not a bus driver in the sense of the other residents of drivers/bus/, so let's move it to the appropriate place for SoC PMU drivers. Not to mention moving the documentation accordingly as well. Acked-by: Pawel Moll Acked-by: Will Deacon Signed-off-by: Robin Murphy Signed-off-by: Arnd Bergmann --- Documentation/arm/CCN.txt | 59 - Documentation/devicetree/bindings/arm/ccn.txt | 22 - Documentation/devicetree/bindings/perf/arm-ccn.txt | 22 + Documentation/perf/arm-ccn.txt | 59 + drivers/bus/Kconfig | 8 - drivers/bus/Makefile | 2 - drivers/bus/arm-ccn.c | 1597 -------------------- drivers/perf/Kconfig | 7 + drivers/perf/Makefile | 1 + drivers/perf/arm-ccn.c | 1597 ++++++++++++++++++++ 10 files changed, 1686 insertions(+), 1688 deletions(-) delete mode 100644 Documentation/arm/CCN.txt delete mode 100644 Documentation/devicetree/bindings/arm/ccn.txt create mode 100644 Documentation/devicetree/bindings/perf/arm-ccn.txt create mode 100644 Documentation/perf/arm-ccn.txt delete mode 100644 drivers/bus/arm-ccn.c create mode 100644 drivers/perf/arm-ccn.c (limited to 'Documentation/devicetree') diff --git a/Documentation/arm/CCN.txt b/Documentation/arm/CCN.txt deleted file mode 100644 index 15cdb7bc57c3..000000000000 --- a/Documentation/arm/CCN.txt +++ /dev/null @@ -1,59 +0,0 @@ -ARM Cache Coherent Network -========================== - -CCN-504 is a ring-bus interconnect consisting of 11 crosspoints -(XPs), with each crosspoint supporting up to two device ports, -so nodes (devices) 0 and 1 are connected to crosspoint 0, -nodes 2 and 3 to crosspoint 1 etc. - -PMU (perf) driver ------------------ - -The CCN driver registers a perf PMU driver, which provides -description of available events and configuration options -in sysfs, see /sys/bus/event_source/devices/ccn*. - -The "format" directory describes format of the config, config1 -and config2 fields of the perf_event_attr structure. The "events" -directory provides configuration templates for all documented -events, that can be used with perf tool. For example "xp_valid_flit" -is an equivalent of "type=0x8,event=0x4". Other parameters must be -explicitly specified. - -For events originating from device, "node" defines its index. - -Crosspoint PMU events require "xp" (index), "bus" (bus number) -and "vc" (virtual channel ID). - -Crosspoint watchpoint-based events (special "event" value 0xfe) -require "xp" and "vc" as as above plus "port" (device port index), -"dir" (transmit/receive direction), comparator values ("cmp_l" -and "cmp_h") and "mask", being index of the comparator mask. -Masks are defined separately from the event description -(due to limited number of the config values) in the "cmp_mask" -directory, with first 8 configurable by user and additional -4 hardcoded for the most frequent use cases. - -Cycle counter is described by a "type" value 0xff and does -not require any other settings. - -The driver also provides a "cpumask" sysfs attribute, which contains -a single CPU ID, of the processor which will be used to handle all -the CCN PMU events. It is recommended that the user space tools -request the events on this processor (if not, the perf_event->cpu value -will be overwritten anyway). In case of this processor being offlined, -the events are migrated to another one and the attribute is updated. - -Example of perf tool use: - -/ # perf list | grep ccn - ccn/cycles/ [Kernel PMU event] -<...> - ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event] -<...> - -/ # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ - sleep 1 - -The driver does not support sampling, therefore "perf record" will -not work. Per-task (without "-a") perf sessions are not supported. diff --git a/Documentation/devicetree/bindings/arm/ccn.txt b/Documentation/devicetree/bindings/arm/ccn.txt deleted file mode 100644 index 43b5a71a5a9d..000000000000 --- a/Documentation/devicetree/bindings/arm/ccn.txt +++ /dev/null @@ -1,22 +0,0 @@ -* ARM CCN (Cache Coherent Network) - -Required properties: - -- compatible: (standard compatible string) should be one of: - "arm,ccn-502" - "arm,ccn-504" - "arm,ccn-508" - -- reg: (standard registers property) physical address and size - (16MB) of the configuration registers block - -- interrupts: (standard interrupt property) single interrupt - generated by the control block - -Example: - - ccn@2000000000 { - compatible = "arm,ccn-504"; - reg = <0x20 0x00000000 0 0x1000000>; - interrupts = <0 181 4>; - }; diff --git a/Documentation/devicetree/bindings/perf/arm-ccn.txt b/Documentation/devicetree/bindings/perf/arm-ccn.txt new file mode 100644 index 000000000000..43b5a71a5a9d --- /dev/null +++ b/Documentation/devicetree/bindings/perf/arm-ccn.txt @@ -0,0 +1,22 @@ +* ARM CCN (Cache Coherent Network) + +Required properties: + +- compatible: (standard compatible string) should be one of: + "arm,ccn-502" + "arm,ccn-504" + "arm,ccn-508" + +- reg: (standard registers property) physical address and size + (16MB) of the configuration registers block + +- interrupts: (standard interrupt property) single interrupt + generated by the control block + +Example: + + ccn@2000000000 { + compatible = "arm,ccn-504"; + reg = <0x20 0x00000000 0 0x1000000>; + interrupts = <0 181 4>; + }; diff --git a/Documentation/perf/arm-ccn.txt b/Documentation/perf/arm-ccn.txt new file mode 100644 index 000000000000..15cdb7bc57c3 --- /dev/null +++ b/Documentation/perf/arm-ccn.txt @@ -0,0 +1,59 @@ +ARM Cache Coherent Network +========================== + +CCN-504 is a ring-bus interconnect consisting of 11 crosspoints +(XPs), with each crosspoint supporting up to two device ports, +so nodes (devices) 0 and 1 are connected to crosspoint 0, +nodes 2 and 3 to crosspoint 1 etc. + +PMU (perf) driver +----------------- + +The CCN driver registers a perf PMU driver, which provides +description of available events and configuration options +in sysfs, see /sys/bus/event_source/devices/ccn*. + +The "format" directory describes format of the config, config1 +and config2 fields of the perf_event_attr structure. The "events" +directory provides configuration templates for all documented +events, that can be used with perf tool. For example "xp_valid_flit" +is an equivalent of "type=0x8,event=0x4". Other parameters must be +explicitly specified. + +For events originating from device, "node" defines its index. + +Crosspoint PMU events require "xp" (index), "bus" (bus number) +and "vc" (virtual channel ID). + +Crosspoint watchpoint-based events (special "event" value 0xfe) +require "xp" and "vc" as as above plus "port" (device port index), +"dir" (transmit/receive direction), comparator values ("cmp_l" +and "cmp_h") and "mask", being index of the comparator mask. +Masks are defined separately from the event description +(due to limited number of the config values) in the "cmp_mask" +directory, with first 8 configurable by user and additional +4 hardcoded for the most frequent use cases. + +Cycle counter is described by a "type" value 0xff and does +not require any other settings. + +The driver also provides a "cpumask" sysfs attribute, which contains +a single CPU ID, of the processor which will be used to handle all +the CCN PMU events. It is recommended that the user space tools +request the events on this processor (if not, the perf_event->cpu value +will be overwritten anyway). In case of this processor being offlined, +the events are migrated to another one and the attribute is updated. + +Example of perf tool use: + +/ # perf list | grep ccn + ccn/cycles/ [Kernel PMU event] +<...> + ccn/xp_valid_flit,xp=?,port=?,vc=?,dir=?/ [Kernel PMU event] +<...> + +/ # perf stat -a -e ccn/cycles/,ccn/xp_valid_flit,xp=1,port=0,vc=1,dir=1/ \ + sleep 1 + +The driver does not support sampling, therefore "perf record" will +not work. Per-task (without "-a") perf sessions are not supported. diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 57e011d36a79..116446c42c6b 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -48,14 +48,6 @@ config ARM_CCI5xx_PMU If unsure, say Y -config ARM_CCN - tristate "ARM CCN driver support" - depends on ARM || ARM64 - depends on PERF_EVENTS - help - PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) - interconnect. - config BRCMSTB_GISB_ARB bool "Broadcom STB GISB bus arbiter" depends on ARM || ARM64 || MIPS diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 9bcd0bf3954b..19733afddd0a 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -5,8 +5,6 @@ # Interconnect bus drivers for ARM platforms obj-$(CONFIG_ARM_CCI) += arm-cci.o -obj-$(CONFIG_ARM_CCN) += arm-ccn.o - obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o diff --git a/drivers/bus/arm-ccn.c b/drivers/bus/arm-ccn.c deleted file mode 100644 index b52332e52ca5..000000000000 --- a/drivers/bus/arm-ccn.c +++ /dev/null @@ -1,1597 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Copyright (C) 2014 ARM Limited - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CCN_NUM_XP_PORTS 2 -#define CCN_NUM_VCS 4 -#define CCN_NUM_REGIONS 256 -#define CCN_REGION_SIZE 0x10000 - -#define CCN_ALL_OLY_ID 0xff00 -#define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0 -#define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f -#define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8 -#define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f - -#define CCN_MN_ERRINT_STATUS 0x0008 -#define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11 -#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02 -#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20 -#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22 -#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04 -#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40 -#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44 -#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08 -#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80 -#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88 -#define CCN_MN_OLY_COMP_LIST_63_0 0x01e0 -#define CCN_MN_ERR_SIG_VAL_63_0 0x0300 -#define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1) - -#define CCN_DT_ACTIVE_DSM 0x0000 -#define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8) -#define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff -#define CCN_DT_CTL 0x0028 -#define CCN_DT_CTL__DT_EN (1 << 0) -#define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8) -#define CCN_DT_PMCCNTR 0x0140 -#define CCN_DT_PMCCNTRSR 0x0190 -#define CCN_DT_PMOVSR 0x0198 -#define CCN_DT_PMOVSR_CLR 0x01a0 -#define CCN_DT_PMOVSR_CLR__MASK 0x1f -#define CCN_DT_PMCR 0x01a8 -#define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6) -#define CCN_DT_PMCR__PMU_EN (1 << 0) -#define CCN_DT_PMSR 0x01b0 -#define CCN_DT_PMSR_REQ 0x01b8 -#define CCN_DT_PMSR_CLR 0x01c0 - -#define CCN_HNF_PMU_EVENT_SEL 0x0600 -#define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) -#define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf - -#define CCN_XP_DT_CONFIG 0x0300 -#define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4) -#define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf -#define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0 -#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1 -#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n)) -#define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n)) -#define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n)) -#define CCN_XP_DT_INTERFACE_SEL 0x0308 -#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8) -#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1 -#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8) -#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1 -#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8) -#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3 -#define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40) -#define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40) -#define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40) -#define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40) -#define CCN_XP_DT_CONTROL 0x0370 -#define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0) -#define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4) -#define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf -#define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf -#define CCN_XP_PMU_EVENT_SEL 0x0600 -#define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7) -#define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f - -#define CCN_SBAS_PMU_EVENT_SEL 0x0600 -#define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) -#define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf - -#define CCN_RNI_PMU_EVENT_SEL 0x0600 -#define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) -#define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf - -#define CCN_TYPE_MN 0x01 -#define CCN_TYPE_DT 0x02 -#define CCN_TYPE_HNF 0x04 -#define CCN_TYPE_HNI 0x05 -#define CCN_TYPE_XP 0x08 -#define CCN_TYPE_SBSX 0x0c -#define CCN_TYPE_SBAS 0x10 -#define CCN_TYPE_RNI_1P 0x14 -#define CCN_TYPE_RNI_2P 0x15 -#define CCN_TYPE_RNI_3P 0x16 -#define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */ -#define CCN_TYPE_RND_2P 0x19 -#define CCN_TYPE_RND_3P 0x1a -#define CCN_TYPE_CYCLES 0xff /* Pseudotype */ - -#define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */ - -#define CCN_NUM_PMU_EVENTS 4 -#define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */ -#define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */ -#define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS - -#define CCN_NUM_PREDEFINED_MASKS 4 -#define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0) -#define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1) -#define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2) -#define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3) - -struct arm_ccn_component { - void __iomem *base; - u32 type; - - DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS); - union { - struct { - DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS); - } xp; - }; -}; - -#define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \ - struct arm_ccn_dt, pmu), struct arm_ccn, dt) - -struct arm_ccn_dt { - int id; - void __iomem *base; - - spinlock_t config_lock; - - DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1); - struct { - struct arm_ccn_component *source; - struct perf_event *event; - } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1]; - - struct { - u64 l, h; - } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS]; - - struct hrtimer hrtimer; - - cpumask_t cpu; - struct hlist_node node; - - struct pmu pmu; -}; - -struct arm_ccn { - struct device *dev; - void __iomem *base; - unsigned int irq; - - unsigned sbas_present:1; - unsigned sbsx_present:1; - - int num_nodes; - struct arm_ccn_component *node; - - int num_xps; - struct arm_ccn_component *xp; - - struct arm_ccn_dt dt; - int mn_id; -}; - -static int arm_ccn_node_to_xp(int node) -{ - return node / CCN_NUM_XP_PORTS; -} - -static int arm_ccn_node_to_xp_port(int node) -{ - return node % CCN_NUM_XP_PORTS; -} - - -/* - * Bit shifts and masks in these defines must be kept in sync with - * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below! - */ -#define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff) -#define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff) -#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff) -#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff) -#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3) -#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3) -#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7) -#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1) -#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf) - -static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port) -{ - *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24)); - *config |= (node_xp << 0) | (type << 8) | (port << 24); -} - -static ssize_t arm_ccn_pmu_format_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct dev_ext_attribute *ea = container_of(attr, - struct dev_ext_attribute, attr); - - return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var); -} - -#define CCN_FORMAT_ATTR(_name, _config) \ - struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \ - { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \ - NULL), _config } - -static CCN_FORMAT_ATTR(node, "config:0-7"); -static CCN_FORMAT_ATTR(xp, "config:0-7"); -static CCN_FORMAT_ATTR(type, "config:8-15"); -static CCN_FORMAT_ATTR(event, "config:16-23"); -static CCN_FORMAT_ATTR(port, "config:24-25"); -static CCN_FORMAT_ATTR(bus, "config:24-25"); -static CCN_FORMAT_ATTR(vc, "config:26-28"); -static CCN_FORMAT_ATTR(dir, "config:29-29"); -static CCN_FORMAT_ATTR(mask, "config:30-33"); -static CCN_FORMAT_ATTR(cmp_l, "config1:0-62"); -static CCN_FORMAT_ATTR(cmp_h, "config2:0-59"); - -static struct attribute *arm_ccn_pmu_format_attrs[] = { - &arm_ccn_pmu_format_attr_node.attr.attr, - &arm_ccn_pmu_format_attr_xp.attr.attr, - &arm_ccn_pmu_format_attr_type.attr.attr, - &arm_ccn_pmu_format_attr_event.attr.attr, - &arm_ccn_pmu_format_attr_port.attr.attr, - &arm_ccn_pmu_format_attr_bus.attr.attr, - &arm_ccn_pmu_format_attr_vc.attr.attr, - &arm_ccn_pmu_format_attr_dir.attr.attr, - &arm_ccn_pmu_format_attr_mask.attr.attr, - &arm_ccn_pmu_format_attr_cmp_l.attr.attr, - &arm_ccn_pmu_format_attr_cmp_h.attr.attr, - NULL -}; - -static const struct attribute_group arm_ccn_pmu_format_attr_group = { - .name = "format", - .attrs = arm_ccn_pmu_format_attrs, -}; - - -struct arm_ccn_pmu_event { - struct device_attribute attr; - u32 type; - u32 event; - int num_ports; - int num_vcs; - const char *def; - int mask; -}; - -#define CCN_EVENT_ATTR(_name) \ - __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL) - -/* - * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on - * their ports in XP they are connected to. For the sake of usability they are - * explicitly defined here (and translated into a relevant watchpoint in - * arm_ccn_pmu_event_init()) so the user can easily request them without deep - * knowledge of the flit format. - */ - -#define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \ - .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \ - .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \ - .def = _def, .mask = _mask, } - -#define CCN_EVENT_HNI(_name, _def, _mask) { \ - .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \ - .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ - .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } - -#define CCN_EVENT_SBSX(_name, _def, _mask) { \ - .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \ - .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ - .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } - -#define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \ - .type = CCN_TYPE_HNF, .event = _event, } - -#define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \ - .type = CCN_TYPE_XP, .event = _event, \ - .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, } - -/* - * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending - * on configuration. One of them is picked to represent the whole group, - * as they all share the same event types. - */ -#define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \ - .type = CCN_TYPE_RNI_3P, .event = _event, } - -#define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \ - .type = CCN_TYPE_SBAS, .event = _event, } - -#define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \ - .type = CCN_TYPE_CYCLES } - - -static ssize_t arm_ccn_pmu_event_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); - struct arm_ccn_pmu_event *event = container_of(attr, - struct arm_ccn_pmu_event, attr); - ssize_t res; - - res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type); - if (event->event) - res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x", - event->event); - if (event->def) - res += snprintf(buf + res, PAGE_SIZE - res, ",%s", - event->def); - if (event->mask) - res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x", - event->mask); - - /* Arguments required by an event */ - switch (event->type) { - case CCN_TYPE_CYCLES: - break; - case CCN_TYPE_XP: - res += snprintf(buf + res, PAGE_SIZE - res, - ",xp=?,vc=?"); - if (event->event == CCN_EVENT_WATCHPOINT) - res += snprintf(buf + res, PAGE_SIZE - res, - ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?"); - else - res += snprintf(buf + res, PAGE_SIZE - res, - ",bus=?"); - - break; - case CCN_TYPE_MN: - res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id); - break; - default: - res += snprintf(buf + res, PAGE_SIZE - res, ",node=?"); - break; - } - - res += snprintf(buf + res, PAGE_SIZE - res, "\n"); - - return res; -} - -static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj, - struct attribute *attr, int index) -{ - struct device *dev = kobj_to_dev(kobj); - struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); - struct device_attribute *dev_attr = container_of(attr, - struct device_attribute, attr); - struct arm_ccn_pmu_event *event = container_of(dev_attr, - struct arm_ccn_pmu_event, attr); - - if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present) - return 0; - if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present) - return 0; - - return attr->mode; -} - -static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = { - CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE), - CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE), - CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE), - CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), - CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), - CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), - CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), - CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", - CCN_IDX_MASK_ORDER), - CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), - CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), - CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), - CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), - CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", - CCN_IDX_MASK_ORDER), - CCN_EVENT_HNF(cache_miss, 0x1), - CCN_EVENT_HNF(l3_sf_cache_access, 0x02), - CCN_EVENT_HNF(cache_fill, 0x3), - CCN_EVENT_HNF(pocq_retry, 0x4), - CCN_EVENT_HNF(pocq_reqs_recvd, 0x5), - CCN_EVENT_HNF(sf_hit, 0x6), - CCN_EVENT_HNF(sf_evictions, 0x7), - CCN_EVENT_HNF(snoops_sent, 0x8), - CCN_EVENT_HNF(snoops_broadcast, 0x9), - CCN_EVENT_HNF(l3_eviction, 0xa), - CCN_EVENT_HNF(l3_fill_invalid_way, 0xb), - CCN_EVENT_HNF(mc_retries, 0xc), - CCN_EVENT_HNF(mc_reqs, 0xd), - CCN_EVENT_HNF(qos_hh_retry, 0xe), - CCN_EVENT_RNI(rdata_beats_p0, 0x1), - CCN_EVENT_RNI(rdata_beats_p1, 0x2), - CCN_EVENT_RNI(rdata_beats_p2, 0x3), - CCN_EVENT_RNI(rxdat_flits, 0x4), - CCN_EVENT_RNI(txdat_flits, 0x5), - CCN_EVENT_RNI(txreq_flits, 0x6), - CCN_EVENT_RNI(txreq_flits_retried, 0x7), - CCN_EVENT_RNI(rrt_full, 0x8), - CCN_EVENT_RNI(wrt_full, 0x9), - CCN_EVENT_RNI(txreq_flits_replayed, 0xa), - CCN_EVENT_XP(upload_starvation, 0x1), - CCN_EVENT_XP(download_starvation, 0x2), - CCN_EVENT_XP(respin, 0x3), - CCN_EVENT_XP(valid_flit, 0x4), - CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT), - CCN_EVENT_SBAS(rdata_beats_p0, 0x1), - CCN_EVENT_SBAS(rxdat_flits, 0x4), - CCN_EVENT_SBAS(txdat_flits, 0x5), - CCN_EVENT_SBAS(txreq_flits, 0x6), - CCN_EVENT_SBAS(txreq_flits_retried, 0x7), - CCN_EVENT_SBAS(rrt_full, 0x8), - CCN_EVENT_SBAS(wrt_full, 0x9), - CCN_EVENT_SBAS(txreq_flits_replayed, 0xa), - CCN_EVENT_CYCLES(cycles), -}; - -/* Populated in arm_ccn_init() */ -static struct attribute - *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1]; - -static const struct attribute_group arm_ccn_pmu_events_attr_group = { - .name = "events", - .is_visible = arm_ccn_pmu_events_is_visible, - .attrs = arm_ccn_pmu_events_attrs, -}; - - -static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name) -{ - unsigned long i; - - if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1])) - return NULL; - i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a'; - - switch (name[1]) { - case 'l': - return &ccn->dt.cmp_mask[i].l; - case 'h': - return &ccn->dt.cmp_mask[i].h; - default: - return NULL; - } -} - -static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); - u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); - - return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL; -} - -static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); - u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); - int err = -EINVAL; - - if (mask) - err = kstrtoull(buf, 0, mask); - - return err ? err : count; -} - -#define CCN_CMP_MASK_ATTR(_name) \ - struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ - __ATTR(_name, S_IRUGO | S_IWUSR, \ - arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store) - -#define CCN_CMP_MASK_ATTR_RO(_name) \ - struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ - __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL) - -static CCN_CMP_MASK_ATTR(0l); -static CCN_CMP_MASK_ATTR(0h); -static CCN_CMP_MASK_ATTR(1l); -static CCN_CMP_MASK_ATTR(1h); -static CCN_CMP_MASK_ATTR(2l); -static CCN_CMP_MASK_ATTR(2h); -static CCN_CMP_MASK_ATTR(3l); -static CCN_CMP_MASK_ATTR(3h); -static CCN_CMP_MASK_ATTR(4l); -static CCN_CMP_MASK_ATTR(4h); -static CCN_CMP_MASK_ATTR(5l); -static CCN_CMP_MASK_ATTR(5h); -static CCN_CMP_MASK_ATTR(6l); -static CCN_CMP_MASK_ATTR(6h); -static CCN_CMP_MASK_ATTR(7l); -static CCN_CMP_MASK_ATTR(7h); -static CCN_CMP_MASK_ATTR_RO(8l); -static CCN_CMP_MASK_ATTR_RO(8h); -static CCN_CMP_MASK_ATTR_RO(9l); -static CCN_CMP_MASK_ATTR_RO(9h); -static CCN_CMP_MASK_ATTR_RO(al); -static CCN_CMP_MASK_ATTR_RO(ah); -static CCN_CMP_MASK_ATTR_RO(bl); -static CCN_CMP_MASK_ATTR_RO(bh); - -static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = { - &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr, - &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr, - &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr, - &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr, - &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr, - &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr, - &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr, - &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr, - &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr, - &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr, - &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr, - &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr, - NULL -}; - -static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { - .name = "cmp_mask", - .attrs = arm_ccn_pmu_cmp_mask_attrs, -}; - -static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); - - return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu); -} - -static struct device_attribute arm_ccn_pmu_cpumask_attr = - __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL); - -static struct attribute *arm_ccn_pmu_cpumask_attrs[] = { - &arm_ccn_pmu_cpumask_attr.attr, - NULL, -}; - -static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = { - .attrs = arm_ccn_pmu_cpumask_attrs, -}; - -/* - * Default poll period is 10ms, which is way over the top anyway, - * as in the worst case scenario (an event every cycle), with 1GHz - * clocked bus, the smallest, 32 bit counter will overflow in - * more than 4s. - */ -static unsigned int arm_ccn_pmu_poll_period_us = 10000; -module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint, - S_IRUGO | S_IWUSR); - -static ktime_t arm_ccn_pmu_timer_period(void) -{ - return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000); -} - - -static const struct attribute_group *arm_ccn_pmu_attr_groups[] = { - &arm_ccn_pmu_events_attr_group, - &arm_ccn_pmu_format_attr_group, - &arm_ccn_pmu_cmp_mask_attr_group, - &arm_ccn_pmu_cpumask_attr_group, - NULL -}; - - -static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size) -{ - int bit; - - do { - bit = find_first_zero_bit(bitmap, size); - if (bit >= size) - return -EAGAIN; - } while (test_and_set_bit(bit, bitmap)); - - return bit; -} - -/* All RN-I and RN-D nodes have identical PMUs */ -static int arm_ccn_pmu_type_eq(u32 a, u32 b) -{ - if (a == b) - return 1; - - switch (a) { - case CCN_TYPE_RNI_1P: - case CCN_TYPE_RNI_2P: - case CCN_TYPE_RNI_3P: - case CCN_TYPE_RND_1P: - case CCN_TYPE_RND_2P: - case CCN_TYPE_RND_3P: - switch (b) { - case CCN_TYPE_RNI_1P: - case CCN_TYPE_RNI_2P: - case CCN_TYPE_RNI_3P: - case CCN_TYPE_RND_1P: - case CCN_TYPE_RND_2P: - case CCN_TYPE_RND_3P: - return 1; - } - break; - } - - return 0; -} - -static int arm_ccn_pmu_event_alloc(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - u32 node_xp, type, event_id; - struct arm_ccn_component *source; - int bit; - - node_xp = CCN_CONFIG_NODE(event->attr.config); - type = CCN_CONFIG_TYPE(event->attr.config); - event_id = CCN_CONFIG_EVENT(event->attr.config); - - /* Allocate the cycle counter */ - if (type == CCN_TYPE_CYCLES) { - if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER, - ccn->dt.pmu_counters_mask)) - return -EAGAIN; - - hw->idx = CCN_IDX_PMU_CYCLE_COUNTER; - ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; - - return 0; - } - - /* Allocate an event counter */ - hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, - CCN_NUM_PMU_EVENT_COUNTERS); - if (hw->idx < 0) { - dev_dbg(ccn->dev, "No more counters available!\n"); - return -EAGAIN; - } - - if (type == CCN_TYPE_XP) - source = &ccn->xp[node_xp]; - else - source = &ccn->node[node_xp]; - ccn->dt.pmu_counters[hw->idx].source = source; - - /* Allocate an event source or a watchpoint */ - if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT) - bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask, - CCN_NUM_XP_WATCHPOINTS); - else - bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask, - CCN_NUM_PMU_EVENTS); - if (bit < 0) { - dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n", - node_xp); - clear_bit(hw->idx, ccn->dt.pmu_counters_mask); - return -EAGAIN; - } - hw->config_base = bit; - - ccn->dt.pmu_counters[hw->idx].event = event; - - return 0; -} - -static void arm_ccn_pmu_event_release(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - - if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) { - clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); - } else { - struct arm_ccn_component *source = - ccn->dt.pmu_counters[hw->idx].source; - - if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP && - CCN_CONFIG_EVENT(event->attr.config) == - CCN_EVENT_WATCHPOINT) - clear_bit(hw->config_base, source->xp.dt_cmp_mask); - else - clear_bit(hw->config_base, source->pmu_events_mask); - clear_bit(hw->idx, ccn->dt.pmu_counters_mask); - } - - ccn->dt.pmu_counters[hw->idx].source = NULL; - ccn->dt.pmu_counters[hw->idx].event = NULL; -} - -static int arm_ccn_pmu_event_init(struct perf_event *event) -{ - struct arm_ccn *ccn; - struct hw_perf_event *hw = &event->hw; - u32 node_xp, type, event_id; - int valid; - int i; - struct perf_event *sibling; - - if (event->attr.type != event->pmu->type) - return -ENOENT; - - ccn = pmu_to_arm_ccn(event->pmu); - - if (hw->sample_period) { - dev_warn(ccn->dev, "Sampling not supported!\n"); - return -EOPNOTSUPP; - } - - if (has_branch_stack(event) || event->attr.exclude_user || - event->attr.exclude_kernel || event->attr.exclude_hv || - event->attr.exclude_idle || event->attr.exclude_host || - event->attr.exclude_guest) { - dev_warn(ccn->dev, "Can't exclude execution levels!\n"); - return -EINVAL; - } - - if (event->cpu < 0) { - dev_warn(ccn->dev, "Can't provide per-task data!\n"); - return -EOPNOTSUPP; - } - /* - * Many perf core operations (eg. events rotation) operate on a - * single CPU context. This is obvious for CPU PMUs, where one - * expects the same sets of events being observed on all CPUs, - * but can lead to issues for off-core PMUs, like CCN, where each - * event could be theoretically assigned to a different CPU. To - * mitigate this, we enforce CPU assignment to one, selected - * processor (the one described in the "cpumask" attribute). - */ - event->cpu = cpumask_first(&ccn->dt.cpu); - - node_xp = CCN_CONFIG_NODE(event->attr.config); - type = CCN_CONFIG_TYPE(event->attr.config); - event_id = CCN_CONFIG_EVENT(event->attr.config); - - /* Validate node/xp vs topology */ - switch (type) { - case CCN_TYPE_MN: - if (node_xp != ccn->mn_id) { - dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp); - return -EINVAL; - } - break; - case CCN_TYPE_XP: - if (node_xp >= ccn->num_xps) { - dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp); - return -EINVAL; - } - break; - case CCN_TYPE_CYCLES: - break; - default: - if (node_xp >= ccn->num_nodes) { - dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp); - return -EINVAL; - } - if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) { - dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n", - type, node_xp); - return -EINVAL; - } - break; - } - - /* Validate event ID vs available for the type */ - for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid; - i++) { - struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i]; - u32 port = CCN_CONFIG_PORT(event->attr.config); - u32 vc = CCN_CONFIG_VC(event->attr.config); - - if (!arm_ccn_pmu_type_eq(type, e->type)) - continue; - if (event_id != e->event) - continue; - if (e->num_ports && port >= e->num_ports) { - dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n", - port, node_xp); - return -EINVAL; - } - if (e->num_vcs && vc >= e->num_vcs) { - dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n", - vc, node_xp); - return -EINVAL; - } - valid = 1; - } - if (!valid) { - dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n", - event_id, node_xp); - return -EINVAL; - } - - /* Watchpoint-based event for a node is actually set on XP */ - if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) { - u32 port; - - type = CCN_TYPE_XP; - port = arm_ccn_node_to_xp_port(node_xp); - node_xp = arm_ccn_node_to_xp(node_xp); - - arm_ccn_pmu_config_set(&event->attr.config, - node_xp, type, port); - } - - /* - * We must NOT create groups containing mixed PMUs, although software - * events are acceptable (for example to create a CCN group - * periodically read when a hrtimer aka cpu-clock leader triggers). - */ - if (event->group_leader->pmu != event->pmu && - !is_software_event(event->group_leader)) - return -EINVAL; - - list_for_each_entry(sibling, &event->group_leader->sibling_list, - group_entry) - if (sibling->pmu != event->pmu && - !is_software_event(sibling)) - return -EINVAL; - - return 0; -} - -static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx) -{ - u64 res; - - if (idx == CCN_IDX_PMU_CYCLE_COUNTER) { -#ifdef readq - res = readq(ccn->dt.base + CCN_DT_PMCCNTR); -#else - /* 40 bit counter, can do snapshot and read in two parts */ - writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); - while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) - ; - writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); - res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; - res <<= 32; - res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); -#endif - } else { - res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); - } - - return res; -} - -static void arm_ccn_pmu_event_update(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - u64 prev_count, new_count, mask; - - do { - prev_count = local64_read(&hw->prev_count); - new_count = arm_ccn_pmu_read_counter(ccn, hw->idx); - } while (local64_xchg(&hw->prev_count, new_count) != prev_count); - - mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; - - local64_add((new_count - prev_count) & mask, &event->count); -} - -static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - struct arm_ccn_component *xp; - u32 val, dt_cfg; - - /* Nothing to do for cycle counter */ - if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) - return; - - if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) - xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)]; - else - xp = &ccn->xp[arm_ccn_node_to_xp( - CCN_CONFIG_NODE(event->attr.config))]; - - if (enable) - dt_cfg = hw->event_base; - else - dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH; - - spin_lock(&ccn->dt.config_lock); - - val = readl(xp->base + CCN_XP_DT_CONFIG); - val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK << - CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx)); - val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); - writel(val, xp->base + CCN_XP_DT_CONFIG); - - spin_unlock(&ccn->dt.config_lock); -} - -static void arm_ccn_pmu_event_start(struct perf_event *event, int flags) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - - local64_set(&event->hw.prev_count, - arm_ccn_pmu_read_counter(ccn, hw->idx)); - hw->state = 0; - - /* Set the DT bus input, engaging the counter */ - arm_ccn_pmu_xp_dt_config(event, 1); -} - -static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags) -{ - struct hw_perf_event *hw = &event->hw; - - /* Disable counting, setting the DT bus to pass-through mode */ - arm_ccn_pmu_xp_dt_config(event, 0); - - if (flags & PERF_EF_UPDATE) - arm_ccn_pmu_event_update(event); - - hw->state |= PERF_HES_STOPPED; -} - -static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - struct arm_ccn_component *source = - ccn->dt.pmu_counters[hw->idx].source; - unsigned long wp = hw->config_base; - u32 val; - u64 cmp_l = event->attr.config1; - u64 cmp_h = event->attr.config2; - u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; - u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; - - hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); - - /* Direction (RX/TX), device (port) & virtual channel */ - val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); - val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK << - CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp)); - val |= CCN_CONFIG_DIR(event->attr.config) << - CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp); - val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK << - CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp)); - val |= CCN_CONFIG_PORT(event->attr.config) << - CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp); - val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK << - CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp)); - val |= CCN_CONFIG_VC(event->attr.config) << - CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp); - writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); - - /* Comparison values */ - writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); - writel((cmp_l >> 32) & 0x7fffffff, - source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); - writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); - writel((cmp_h >> 32) & 0x0fffffff, - source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); - - /* Mask */ - writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); - writel((mask_l >> 32) & 0x7fffffff, - source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); - writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); - writel((mask_h >> 32) & 0x0fffffff, - source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); -} - -static void arm_ccn_pmu_xp_event_config(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - struct arm_ccn_component *source = - ccn->dt.pmu_counters[hw->idx].source; - u32 val, id; - - hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); - - id = (CCN_CONFIG_VC(event->attr.config) << 4) | - (CCN_CONFIG_BUS(event->attr.config) << 3) | - (CCN_CONFIG_EVENT(event->attr.config) << 0); - - val = readl(source->base + CCN_XP_PMU_EVENT_SEL); - val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK << - CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); - val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); - writel(val, source->base + CCN_XP_PMU_EVENT_SEL); -} - -static void arm_ccn_pmu_node_event_config(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - struct arm_ccn_component *source = - ccn->dt.pmu_counters[hw->idx].source; - u32 type = CCN_CONFIG_TYPE(event->attr.config); - u32 val, port; - - port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config)); - hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, - hw->config_base); - - /* These *_event_sel regs should be identical, but let's make sure... */ - BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL); - BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL); - BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) != - CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1)); - BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) != - CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1)); - BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK != - CCN_SBAS_PMU_EVENT_SEL__ID__MASK); - BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK != - CCN_RNI_PMU_EVENT_SEL__ID__MASK); - if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS && - !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P))) - return; - - /* Set the event id for the pre-allocated counter */ - val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); - val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK << - CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); - val |= CCN_CONFIG_EVENT(event->attr.config) << - CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); - writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); -} - -static void arm_ccn_pmu_event_config(struct perf_event *event) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - struct hw_perf_event *hw = &event->hw; - u32 xp, offset, val; - - /* Cycle counter requires no setup */ - if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) - return; - - if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) - xp = CCN_CONFIG_XP(event->attr.config); - else - xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config)); - - spin_lock(&ccn->dt.config_lock); - - /* Set the DT bus "distance" register */ - offset = (hw->idx / 4) * 4; - val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); - val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK << - CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4)); - val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); - writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); - - if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) { - if (CCN_CONFIG_EVENT(event->attr.config) == - CCN_EVENT_WATCHPOINT) - arm_ccn_pmu_xp_watchpoint_config(event); - else - arm_ccn_pmu_xp_event_config(event); - } else { - arm_ccn_pmu_node_event_config(event); - } - - spin_unlock(&ccn->dt.config_lock); -} - -static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn) -{ - return bitmap_weight(ccn->dt.pmu_counters_mask, - CCN_NUM_PMU_EVENT_COUNTERS + 1); -} - -static int arm_ccn_pmu_event_add(struct perf_event *event, int flags) -{ - int err; - struct hw_perf_event *hw = &event->hw; - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - - err = arm_ccn_pmu_event_alloc(event); - if (err) - return err; - - /* - * Pin the timer, so that the overflows are handled by the chosen - * event->cpu (this is the same one as presented in "cpumask" - * attribute). - */ - if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1) - hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), - HRTIMER_MODE_REL_PINNED); - - arm_ccn_pmu_event_config(event); - - hw->state = PERF_HES_STOPPED; - - if (flags & PERF_EF_START) - arm_ccn_pmu_event_start(event, PERF_EF_UPDATE); - - return 0; -} - -static void arm_ccn_pmu_event_del(struct perf_event *event, int flags) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); - - arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE); - - arm_ccn_pmu_event_release(event); - - if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0) - hrtimer_cancel(&ccn->dt.hrtimer); -} - -static void arm_ccn_pmu_event_read(struct perf_event *event) -{ - arm_ccn_pmu_event_update(event); -} - -static void arm_ccn_pmu_enable(struct pmu *pmu) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); - - u32 val = readl(ccn->dt.base + CCN_DT_PMCR); - val |= CCN_DT_PMCR__PMU_EN; - writel(val, ccn->dt.base + CCN_DT_PMCR); -} - -static void arm_ccn_pmu_disable(struct pmu *pmu) -{ - struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); - - u32 val = readl(ccn->dt.base + CCN_DT_PMCR); - val &= ~CCN_DT_PMCR__PMU_EN; - writel(val, ccn->dt.base + CCN_DT_PMCR); -} - -static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) -{ - u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); - int idx; - - if (!pmovsr) - return IRQ_NONE; - - writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); - - BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS); - - for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) { - struct perf_event *event = dt->pmu_counters[idx].event; - int overflowed = pmovsr & BIT(idx); - - WARN_ON_ONCE(overflowed && !event && - idx != CCN_IDX_PMU_CYCLE_COUNTER); - - if (!event || !overflowed) - continue; - - arm_ccn_pmu_event_update(event); - } - - return IRQ_HANDLED; -} - -static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer) -{ - struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, - hrtimer); - unsigned long flags; - - local_irq_save(flags); - arm_ccn_pmu_overflow_handler(dt); - local_irq_restore(flags); - - hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period()); - return HRTIMER_RESTART; -} - - -static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) -{ - struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); - struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); - unsigned int target; - - if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) - return 0; - target = cpumask_any_but(cpu_online_mask, cpu); - if (target >= nr_cpu_ids) - return 0; - perf_pmu_migrate_context(&dt->pmu, cpu, target); - cpumask_set_cpu(target, &dt->cpu); - if (ccn->irq) - WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0); - return 0; -} - -static DEFINE_IDA(arm_ccn_pmu_ida); - -static int arm_ccn_pmu_init(struct arm_ccn *ccn) -{ - int i; - char *name; - int err; - - /* Initialize DT subsystem */ - ccn->dt.base = ccn->base + CCN_REGION_SIZE; - spin_lock_init(&ccn->dt.config_lock); - writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); - writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); - writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN, - ccn->dt.base + CCN_DT_PMCR); - writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); - for (i = 0; i < ccn->num_xps; i++) { - writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); - writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << - CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) | - (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << - CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) | - CCN_XP_DT_CONTROL__DT_ENABLE, - ccn->xp[i].base + CCN_XP_DT_CONTROL); - } - ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; - ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; - ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; - ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; - ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; - ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); - ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; - ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); - - /* Get a convenient /sys/event_source/devices/ name */ - ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL); - if (ccn->dt.id == 0) { - name = "ccn"; - } else { - name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", - ccn->dt.id); - if (!name) { - err = -ENOMEM; - goto error_choose_name; - } - } - - /* Perf driver registration */ - ccn->dt.pmu = (struct pmu) { - .module = THIS_MODULE, - .attr_groups = arm_ccn_pmu_attr_groups, - .task_ctx_nr = perf_invalid_context, - .event_init = arm_ccn_pmu_event_init, - .add = arm_ccn_pmu_event_add, - .del = arm_ccn_pmu_event_del, - .start = arm_ccn_pmu_event_start, - .stop = arm_ccn_pmu_event_stop, - .read = arm_ccn_pmu_event_read, - .pmu_enable = arm_ccn_pmu_enable, - .pmu_disable = arm_ccn_pmu_disable, - }; - - /* No overflow interrupt? Have to use a timer instead. */ - if (!ccn->irq) { - dev_info(ccn->dev, "No access to interrupts, using timer.\n"); - hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, - HRTIMER_MODE_REL); - ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; - } - - /* Pick one CPU which we will use to collect data from CCN... */ - cpumask_set_cpu(get_cpu(), &ccn->dt.cpu); - - /* Also make sure that the overflow interrupt is handled by this CPU */ - if (ccn->irq) { - err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu); - if (err) { - dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); - goto error_set_affinity; - } - } - - err = perf_pmu_register(&ccn->dt.pmu, name, -1); - if (err) - goto error_pmu_register; - - cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, - &ccn->dt.node); - put_cpu(); - return 0; - -error_pmu_register: -error_set_affinity: - put_cpu(); -error_choose_name: - ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); - for (i = 0; i < ccn->num_xps; i++) - writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); - writel(0, ccn->dt.base + CCN_DT_PMCR); - return err; -} - -static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn) -{ - int i; - - cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, - &ccn->dt.node); - if (ccn->irq) - irq_set_affinity_hint(ccn->irq, NULL); - for (i = 0; i < ccn->num_xps; i++) - writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); - writel(0, ccn->dt.base + CCN_DT_PMCR); - perf_pmu_unregister(&ccn->dt.pmu); - ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); -} - -static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn, - int (*callback)(struct arm_ccn *ccn, int region, - void __iomem *base, u32 type, u32 id)) -{ - int region; - - for (region = 0; region < CCN_NUM_REGIONS; region++) { - u32 val, type, id; - void __iomem *base; - int err; - - val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + - 4 * (region / 32)); - if (!(val & (1 << (region % 32)))) - continue; - - base = ccn->base + region * CCN_REGION_SIZE; - val = readl(base + CCN_ALL_OLY_ID); - type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) & - CCN_ALL_OLY_ID__OLY_ID__MASK; - id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) & - CCN_ALL_OLY_ID__NODE_ID__MASK; - - err = callback(ccn, region, base, type, id); - if (err) - return err; - } - - return 0; -} - -static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region, - void __iomem *base, u32 type, u32 id) -{ - - if (type == CCN_TYPE_XP && id >= ccn->num_xps) - ccn->num_xps = id + 1; - else if (id >= ccn->num_nodes) - ccn->num_nodes = id + 1; - - return 0; -} - -static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region, - void __iomem *base, u32 type, u32 id) -{ - struct arm_ccn_component *component; - - dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type); - - switch (type) { - case CCN_TYPE_MN: - ccn->mn_id = id; - return 0; - case CCN_TYPE_DT: - return 0; - case CCN_TYPE_XP: - component = &ccn->xp[id]; - break; - case CCN_TYPE_SBSX: - ccn->sbsx_present = 1; - component = &ccn->node[id]; - break; - case CCN_TYPE_SBAS: - ccn->sbas_present = 1; - /* Fall-through */ - default: - component = &ccn->node[id]; - break; - } - - component->base = base; - component->type = type; - - return 0; -} - - -static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn, - const u32 *err_sig_val) -{ - /* This should be really handled by firmware... */ - dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n", - err_sig_val[5], err_sig_val[4], err_sig_val[3], - err_sig_val[2], err_sig_val[1], err_sig_val[0]); - dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n"); - writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE, - ccn->base + CCN_MN_ERRINT_STATUS); - - return IRQ_HANDLED; -} - - -static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id) -{ - irqreturn_t res = IRQ_NONE; - struct arm_ccn *ccn = dev_id; - u32 err_sig_val[6]; - u32 err_or; - int i; - - /* PMU overflow is a special case */ - err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); - if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) { - err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT; - res = arm_ccn_pmu_overflow_handler(&ccn->dt); - } - - /* Have to read all err_sig_vals to clear them */ - for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) { - err_sig_val[i] = readl(ccn->base + - CCN_MN_ERR_SIG_VAL_63_0 + i * 4); - err_or |= err_sig_val[i]; - } - if (err_or) - res |= arm_ccn_error_handler(ccn, err_sig_val); - - if (res != IRQ_NONE) - writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT, - ccn->base + CCN_MN_ERRINT_STATUS); - - return res; -} - - -static int arm_ccn_probe(struct platform_device *pdev) -{ - struct arm_ccn *ccn; - struct resource *res; - unsigned int irq; - int err; - - ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); - if (!ccn) - return -ENOMEM; - ccn->dev = &pdev->dev; - platform_set_drvdata(pdev, ccn); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - - if (!devm_request_mem_region(ccn->dev, res->start, - resource_size(res), pdev->name)) - return -EBUSY; - - ccn->base = devm_ioremap(ccn->dev, res->start, - resource_size(res)); - if (!ccn->base) - return -EFAULT; - - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res) - return -EINVAL; - irq = res->start; - - /* Check if we can use the interrupt */ - writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE, - ccn->base + CCN_MN_ERRINT_STATUS); - if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & - CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) { - /* Can set 'disable' bits, so can acknowledge interrupts */ - writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE, - ccn->base + CCN_MN_ERRINT_STATUS); - err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, - IRQF_NOBALANCING | IRQF_NO_THREAD, - dev_name(ccn->dev), ccn); - if (err) - return err; - - ccn->irq = irq; - } - - - /* Build topology */ - - err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num); - if (err) - return err; - - ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node), - GFP_KERNEL); - ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node), - GFP_KERNEL); - if (!ccn->node || !ccn->xp) - return -ENOMEM; - - err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes); - if (err) - return err; - - return arm_ccn_pmu_init(ccn); -} - -static int arm_ccn_remove(struct platform_device *pdev) -{ - struct arm_ccn *ccn = platform_get_drvdata(pdev); - - arm_ccn_pmu_cleanup(ccn); - - return 0; -} - -static const struct of_device_id arm_ccn_match[] = { - { .compatible = "arm,ccn-502", }, - { .compatible = "arm,ccn-504", }, - {}, -}; -MODULE_DEVICE_TABLE(of, arm_ccn_match); - -static struct platform_driver arm_ccn_driver = { - .driver = { - .name = "arm-ccn", - .of_match_table = arm_ccn_match, - }, - .probe = arm_ccn_probe, - .remove = arm_ccn_remove, -}; - -static int __init arm_ccn_init(void) -{ - int i, ret; - - ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE, - "perf/arm/ccn:online", NULL, - arm_ccn_pmu_offline_cpu); - if (ret) - return ret; - - for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++) - arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr; - - ret = platform_driver_register(&arm_ccn_driver); - if (ret) - cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); - return ret; -} - -static void __exit arm_ccn_exit(void) -{ - platform_driver_unregister(&arm_ccn_driver); - cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); -} - -module_init(arm_ccn_init); -module_exit(arm_ccn_exit); - -MODULE_AUTHOR("Pawel Moll "); -MODULE_LICENSE("GPL"); diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index da5724cd89cf..331b6d992b5a 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -5,6 +5,13 @@ menu "Performance monitor support" depends on PERF_EVENTS +config ARM_CCN + tristate "ARM CCN driver support" + depends on ARM || ARM64 + help + PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) + interconnect. + config ARM_PMU depends on ARM || ARM64 bool "ARM PMU framework" diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index c2f27419bdf0..5004abee0f3a 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_ARM_CCN) += arm-ccn.o obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c new file mode 100644 index 000000000000..b52332e52ca5 --- /dev/null +++ b/drivers/perf/arm-ccn.c @@ -0,0 +1,1597 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Copyright (C) 2014 ARM Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CCN_NUM_XP_PORTS 2 +#define CCN_NUM_VCS 4 +#define CCN_NUM_REGIONS 256 +#define CCN_REGION_SIZE 0x10000 + +#define CCN_ALL_OLY_ID 0xff00 +#define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0 +#define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f +#define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8 +#define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f + +#define CCN_MN_ERRINT_STATUS 0x0008 +#define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11 +#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02 +#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20 +#define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22 +#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04 +#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40 +#define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44 +#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08 +#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80 +#define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88 +#define CCN_MN_OLY_COMP_LIST_63_0 0x01e0 +#define CCN_MN_ERR_SIG_VAL_63_0 0x0300 +#define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1) + +#define CCN_DT_ACTIVE_DSM 0x0000 +#define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8) +#define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff +#define CCN_DT_CTL 0x0028 +#define CCN_DT_CTL__DT_EN (1 << 0) +#define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8) +#define CCN_DT_PMCCNTR 0x0140 +#define CCN_DT_PMCCNTRSR 0x0190 +#define CCN_DT_PMOVSR 0x0198 +#define CCN_DT_PMOVSR_CLR 0x01a0 +#define CCN_DT_PMOVSR_CLR__MASK 0x1f +#define CCN_DT_PMCR 0x01a8 +#define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6) +#define CCN_DT_PMCR__PMU_EN (1 << 0) +#define CCN_DT_PMSR 0x01b0 +#define CCN_DT_PMSR_REQ 0x01b8 +#define CCN_DT_PMSR_CLR 0x01c0 + +#define CCN_HNF_PMU_EVENT_SEL 0x0600 +#define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) +#define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf + +#define CCN_XP_DT_CONFIG 0x0300 +#define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4) +#define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf +#define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0 +#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1 +#define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n)) +#define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n)) +#define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n)) +#define CCN_XP_DT_INTERFACE_SEL 0x0308 +#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8) +#define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1 +#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8) +#define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1 +#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8) +#define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3 +#define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40) +#define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40) +#define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40) +#define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40) +#define CCN_XP_DT_CONTROL 0x0370 +#define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0) +#define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4) +#define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf +#define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf +#define CCN_XP_PMU_EVENT_SEL 0x0600 +#define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7) +#define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f + +#define CCN_SBAS_PMU_EVENT_SEL 0x0600 +#define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) +#define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf + +#define CCN_RNI_PMU_EVENT_SEL 0x0600 +#define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4) +#define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf + +#define CCN_TYPE_MN 0x01 +#define CCN_TYPE_DT 0x02 +#define CCN_TYPE_HNF 0x04 +#define CCN_TYPE_HNI 0x05 +#define CCN_TYPE_XP 0x08 +#define CCN_TYPE_SBSX 0x0c +#define CCN_TYPE_SBAS 0x10 +#define CCN_TYPE_RNI_1P 0x14 +#define CCN_TYPE_RNI_2P 0x15 +#define CCN_TYPE_RNI_3P 0x16 +#define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */ +#define CCN_TYPE_RND_2P 0x19 +#define CCN_TYPE_RND_3P 0x1a +#define CCN_TYPE_CYCLES 0xff /* Pseudotype */ + +#define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */ + +#define CCN_NUM_PMU_EVENTS 4 +#define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */ +#define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */ +#define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS + +#define CCN_NUM_PREDEFINED_MASKS 4 +#define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0) +#define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1) +#define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2) +#define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3) + +struct arm_ccn_component { + void __iomem *base; + u32 type; + + DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS); + union { + struct { + DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS); + } xp; + }; +}; + +#define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \ + struct arm_ccn_dt, pmu), struct arm_ccn, dt) + +struct arm_ccn_dt { + int id; + void __iomem *base; + + spinlock_t config_lock; + + DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1); + struct { + struct arm_ccn_component *source; + struct perf_event *event; + } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1]; + + struct { + u64 l, h; + } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS]; + + struct hrtimer hrtimer; + + cpumask_t cpu; + struct hlist_node node; + + struct pmu pmu; +}; + +struct arm_ccn { + struct device *dev; + void __iomem *base; + unsigned int irq; + + unsigned sbas_present:1; + unsigned sbsx_present:1; + + int num_nodes; + struct arm_ccn_component *node; + + int num_xps; + struct arm_ccn_component *xp; + + struct arm_ccn_dt dt; + int mn_id; +}; + +static int arm_ccn_node_to_xp(int node) +{ + return node / CCN_NUM_XP_PORTS; +} + +static int arm_ccn_node_to_xp_port(int node) +{ + return node % CCN_NUM_XP_PORTS; +} + + +/* + * Bit shifts and masks in these defines must be kept in sync with + * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below! + */ +#define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff) +#define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff) +#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff) +#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff) +#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3) +#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3) +#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7) +#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1) +#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf) + +static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port) +{ + *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24)); + *config |= (node_xp << 0) | (type << 8) | (port << 24); +} + +static ssize_t arm_ccn_pmu_format_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *ea = container_of(attr, + struct dev_ext_attribute, attr); + + return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var); +} + +#define CCN_FORMAT_ATTR(_name, _config) \ + struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \ + { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \ + NULL), _config } + +static CCN_FORMAT_ATTR(node, "config:0-7"); +static CCN_FORMAT_ATTR(xp, "config:0-7"); +static CCN_FORMAT_ATTR(type, "config:8-15"); +static CCN_FORMAT_ATTR(event, "config:16-23"); +static CCN_FORMAT_ATTR(port, "config:24-25"); +static CCN_FORMAT_ATTR(bus, "config:24-25"); +static CCN_FORMAT_ATTR(vc, "config:26-28"); +static CCN_FORMAT_ATTR(dir, "config:29-29"); +static CCN_FORMAT_ATTR(mask, "config:30-33"); +static CCN_FORMAT_ATTR(cmp_l, "config1:0-62"); +static CCN_FORMAT_ATTR(cmp_h, "config2:0-59"); + +static struct attribute *arm_ccn_pmu_format_attrs[] = { + &arm_ccn_pmu_format_attr_node.attr.attr, + &arm_ccn_pmu_format_attr_xp.attr.attr, + &arm_ccn_pmu_format_attr_type.attr.attr, + &arm_ccn_pmu_format_attr_event.attr.attr, + &arm_ccn_pmu_format_attr_port.attr.attr, + &arm_ccn_pmu_format_attr_bus.attr.attr, + &arm_ccn_pmu_format_attr_vc.attr.attr, + &arm_ccn_pmu_format_attr_dir.attr.attr, + &arm_ccn_pmu_format_attr_mask.attr.attr, + &arm_ccn_pmu_format_attr_cmp_l.attr.attr, + &arm_ccn_pmu_format_attr_cmp_h.attr.attr, + NULL +}; + +static const struct attribute_group arm_ccn_pmu_format_attr_group = { + .name = "format", + .attrs = arm_ccn_pmu_format_attrs, +}; + + +struct arm_ccn_pmu_event { + struct device_attribute attr; + u32 type; + u32 event; + int num_ports; + int num_vcs; + const char *def; + int mask; +}; + +#define CCN_EVENT_ATTR(_name) \ + __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL) + +/* + * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on + * their ports in XP they are connected to. For the sake of usability they are + * explicitly defined here (and translated into a relevant watchpoint in + * arm_ccn_pmu_event_init()) so the user can easily request them without deep + * knowledge of the flit format. + */ + +#define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \ + .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \ + .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \ + .def = _def, .mask = _mask, } + +#define CCN_EVENT_HNI(_name, _def, _mask) { \ + .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \ + .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ + .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } + +#define CCN_EVENT_SBSX(_name, _def, _mask) { \ + .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \ + .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \ + .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } + +#define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \ + .type = CCN_TYPE_HNF, .event = _event, } + +#define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \ + .type = CCN_TYPE_XP, .event = _event, \ + .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, } + +/* + * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending + * on configuration. One of them is picked to represent the whole group, + * as they all share the same event types. + */ +#define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \ + .type = CCN_TYPE_RNI_3P, .event = _event, } + +#define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \ + .type = CCN_TYPE_SBAS, .event = _event, } + +#define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \ + .type = CCN_TYPE_CYCLES } + + +static ssize_t arm_ccn_pmu_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); + struct arm_ccn_pmu_event *event = container_of(attr, + struct arm_ccn_pmu_event, attr); + ssize_t res; + + res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type); + if (event->event) + res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x", + event->event); + if (event->def) + res += snprintf(buf + res, PAGE_SIZE - res, ",%s", + event->def); + if (event->mask) + res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x", + event->mask); + + /* Arguments required by an event */ + switch (event->type) { + case CCN_TYPE_CYCLES: + break; + case CCN_TYPE_XP: + res += snprintf(buf + res, PAGE_SIZE - res, + ",xp=?,vc=?"); + if (event->event == CCN_EVENT_WATCHPOINT) + res += snprintf(buf + res, PAGE_SIZE - res, + ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?"); + else + res += snprintf(buf + res, PAGE_SIZE - res, + ",bus=?"); + + break; + case CCN_TYPE_MN: + res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id); + break; + default: + res += snprintf(buf + res, PAGE_SIZE - res, ",node=?"); + break; + } + + res += snprintf(buf + res, PAGE_SIZE - res, "\n"); + + return res; +} + +static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj, + struct attribute *attr, int index) +{ + struct device *dev = kobj_to_dev(kobj); + struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); + struct device_attribute *dev_attr = container_of(attr, + struct device_attribute, attr); + struct arm_ccn_pmu_event *event = container_of(dev_attr, + struct arm_ccn_pmu_event, attr); + + if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present) + return 0; + if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present) + return 0; + + return attr->mode; +} + +static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = { + CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE), + CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE), + CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE), + CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), + CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), + CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), + CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), + CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", + CCN_IDX_MASK_ORDER), + CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY), + CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY), + CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY), + CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY), + CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000", + CCN_IDX_MASK_ORDER), + CCN_EVENT_HNF(cache_miss, 0x1), + CCN_EVENT_HNF(l3_sf_cache_access, 0x02), + CCN_EVENT_HNF(cache_fill, 0x3), + CCN_EVENT_HNF(pocq_retry, 0x4), + CCN_EVENT_HNF(pocq_reqs_recvd, 0x5), + CCN_EVENT_HNF(sf_hit, 0x6), + CCN_EVENT_HNF(sf_evictions, 0x7), + CCN_EVENT_HNF(snoops_sent, 0x8), + CCN_EVENT_HNF(snoops_broadcast, 0x9), + CCN_EVENT_HNF(l3_eviction, 0xa), + CCN_EVENT_HNF(l3_fill_invalid_way, 0xb), + CCN_EVENT_HNF(mc_retries, 0xc), + CCN_EVENT_HNF(mc_reqs, 0xd), + CCN_EVENT_HNF(qos_hh_retry, 0xe), + CCN_EVENT_RNI(rdata_beats_p0, 0x1), + CCN_EVENT_RNI(rdata_beats_p1, 0x2), + CCN_EVENT_RNI(rdata_beats_p2, 0x3), + CCN_EVENT_RNI(rxdat_flits, 0x4), + CCN_EVENT_RNI(txdat_flits, 0x5), + CCN_EVENT_RNI(txreq_flits, 0x6), + CCN_EVENT_RNI(txreq_flits_retried, 0x7), + CCN_EVENT_RNI(rrt_full, 0x8), + CCN_EVENT_RNI(wrt_full, 0x9), + CCN_EVENT_RNI(txreq_flits_replayed, 0xa), + CCN_EVENT_XP(upload_starvation, 0x1), + CCN_EVENT_XP(download_starvation, 0x2), + CCN_EVENT_XP(respin, 0x3), + CCN_EVENT_XP(valid_flit, 0x4), + CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT), + CCN_EVENT_SBAS(rdata_beats_p0, 0x1), + CCN_EVENT_SBAS(rxdat_flits, 0x4), + CCN_EVENT_SBAS(txdat_flits, 0x5), + CCN_EVENT_SBAS(txreq_flits, 0x6), + CCN_EVENT_SBAS(txreq_flits_retried, 0x7), + CCN_EVENT_SBAS(rrt_full, 0x8), + CCN_EVENT_SBAS(wrt_full, 0x9), + CCN_EVENT_SBAS(txreq_flits_replayed, 0xa), + CCN_EVENT_CYCLES(cycles), +}; + +/* Populated in arm_ccn_init() */ +static struct attribute + *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1]; + +static const struct attribute_group arm_ccn_pmu_events_attr_group = { + .name = "events", + .is_visible = arm_ccn_pmu_events_is_visible, + .attrs = arm_ccn_pmu_events_attrs, +}; + + +static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name) +{ + unsigned long i; + + if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1])) + return NULL; + i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a'; + + switch (name[1]) { + case 'l': + return &ccn->dt.cmp_mask[i].l; + case 'h': + return &ccn->dt.cmp_mask[i].h; + default: + return NULL; + } +} + +static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); + u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); + + return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL; +} + +static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); + u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); + int err = -EINVAL; + + if (mask) + err = kstrtoull(buf, 0, mask); + + return err ? err : count; +} + +#define CCN_CMP_MASK_ATTR(_name) \ + struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ + __ATTR(_name, S_IRUGO | S_IWUSR, \ + arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store) + +#define CCN_CMP_MASK_ATTR_RO(_name) \ + struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \ + __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL) + +static CCN_CMP_MASK_ATTR(0l); +static CCN_CMP_MASK_ATTR(0h); +static CCN_CMP_MASK_ATTR(1l); +static CCN_CMP_MASK_ATTR(1h); +static CCN_CMP_MASK_ATTR(2l); +static CCN_CMP_MASK_ATTR(2h); +static CCN_CMP_MASK_ATTR(3l); +static CCN_CMP_MASK_ATTR(3h); +static CCN_CMP_MASK_ATTR(4l); +static CCN_CMP_MASK_ATTR(4h); +static CCN_CMP_MASK_ATTR(5l); +static CCN_CMP_MASK_ATTR(5h); +static CCN_CMP_MASK_ATTR(6l); +static CCN_CMP_MASK_ATTR(6h); +static CCN_CMP_MASK_ATTR(7l); +static CCN_CMP_MASK_ATTR(7h); +static CCN_CMP_MASK_ATTR_RO(8l); +static CCN_CMP_MASK_ATTR_RO(8h); +static CCN_CMP_MASK_ATTR_RO(9l); +static CCN_CMP_MASK_ATTR_RO(9h); +static CCN_CMP_MASK_ATTR_RO(al); +static CCN_CMP_MASK_ATTR_RO(ah); +static CCN_CMP_MASK_ATTR_RO(bl); +static CCN_CMP_MASK_ATTR_RO(bh); + +static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = { + &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr, + &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr, + &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr, + &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr, + &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr, + &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr, + &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr, + &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr, + &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr, + &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr, + &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr, + &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr, + NULL +}; + +static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = { + .name = "cmp_mask", + .attrs = arm_ccn_pmu_cmp_mask_attrs, +}; + +static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev)); + + return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu); +} + +static struct device_attribute arm_ccn_pmu_cpumask_attr = + __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL); + +static struct attribute *arm_ccn_pmu_cpumask_attrs[] = { + &arm_ccn_pmu_cpumask_attr.attr, + NULL, +}; + +static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = { + .attrs = arm_ccn_pmu_cpumask_attrs, +}; + +/* + * Default poll period is 10ms, which is way over the top anyway, + * as in the worst case scenario (an event every cycle), with 1GHz + * clocked bus, the smallest, 32 bit counter will overflow in + * more than 4s. + */ +static unsigned int arm_ccn_pmu_poll_period_us = 10000; +module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint, + S_IRUGO | S_IWUSR); + +static ktime_t arm_ccn_pmu_timer_period(void) +{ + return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000); +} + + +static const struct attribute_group *arm_ccn_pmu_attr_groups[] = { + &arm_ccn_pmu_events_attr_group, + &arm_ccn_pmu_format_attr_group, + &arm_ccn_pmu_cmp_mask_attr_group, + &arm_ccn_pmu_cpumask_attr_group, + NULL +}; + + +static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size) +{ + int bit; + + do { + bit = find_first_zero_bit(bitmap, size); + if (bit >= size) + return -EAGAIN; + } while (test_and_set_bit(bit, bitmap)); + + return bit; +} + +/* All RN-I and RN-D nodes have identical PMUs */ +static int arm_ccn_pmu_type_eq(u32 a, u32 b) +{ + if (a == b) + return 1; + + switch (a) { + case CCN_TYPE_RNI_1P: + case CCN_TYPE_RNI_2P: + case CCN_TYPE_RNI_3P: + case CCN_TYPE_RND_1P: + case CCN_TYPE_RND_2P: + case CCN_TYPE_RND_3P: + switch (b) { + case CCN_TYPE_RNI_1P: + case CCN_TYPE_RNI_2P: + case CCN_TYPE_RNI_3P: + case CCN_TYPE_RND_1P: + case CCN_TYPE_RND_2P: + case CCN_TYPE_RND_3P: + return 1; + } + break; + } + + return 0; +} + +static int arm_ccn_pmu_event_alloc(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + u32 node_xp, type, event_id; + struct arm_ccn_component *source; + int bit; + + node_xp = CCN_CONFIG_NODE(event->attr.config); + type = CCN_CONFIG_TYPE(event->attr.config); + event_id = CCN_CONFIG_EVENT(event->attr.config); + + /* Allocate the cycle counter */ + if (type == CCN_TYPE_CYCLES) { + if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER, + ccn->dt.pmu_counters_mask)) + return -EAGAIN; + + hw->idx = CCN_IDX_PMU_CYCLE_COUNTER; + ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; + + return 0; + } + + /* Allocate an event counter */ + hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, + CCN_NUM_PMU_EVENT_COUNTERS); + if (hw->idx < 0) { + dev_dbg(ccn->dev, "No more counters available!\n"); + return -EAGAIN; + } + + if (type == CCN_TYPE_XP) + source = &ccn->xp[node_xp]; + else + source = &ccn->node[node_xp]; + ccn->dt.pmu_counters[hw->idx].source = source; + + /* Allocate an event source or a watchpoint */ + if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT) + bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask, + CCN_NUM_XP_WATCHPOINTS); + else + bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask, + CCN_NUM_PMU_EVENTS); + if (bit < 0) { + dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n", + node_xp); + clear_bit(hw->idx, ccn->dt.pmu_counters_mask); + return -EAGAIN; + } + hw->config_base = bit; + + ccn->dt.pmu_counters[hw->idx].event = event; + + return 0; +} + +static void arm_ccn_pmu_event_release(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + + if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) { + clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); + } else { + struct arm_ccn_component *source = + ccn->dt.pmu_counters[hw->idx].source; + + if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP && + CCN_CONFIG_EVENT(event->attr.config) == + CCN_EVENT_WATCHPOINT) + clear_bit(hw->config_base, source->xp.dt_cmp_mask); + else + clear_bit(hw->config_base, source->pmu_events_mask); + clear_bit(hw->idx, ccn->dt.pmu_counters_mask); + } + + ccn->dt.pmu_counters[hw->idx].source = NULL; + ccn->dt.pmu_counters[hw->idx].event = NULL; +} + +static int arm_ccn_pmu_event_init(struct perf_event *event) +{ + struct arm_ccn *ccn; + struct hw_perf_event *hw = &event->hw; + u32 node_xp, type, event_id; + int valid; + int i; + struct perf_event *sibling; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + ccn = pmu_to_arm_ccn(event->pmu); + + if (hw->sample_period) { + dev_warn(ccn->dev, "Sampling not supported!\n"); + return -EOPNOTSUPP; + } + + if (has_branch_stack(event) || event->attr.exclude_user || + event->attr.exclude_kernel || event->attr.exclude_hv || + event->attr.exclude_idle || event->attr.exclude_host || + event->attr.exclude_guest) { + dev_warn(ccn->dev, "Can't exclude execution levels!\n"); + return -EINVAL; + } + + if (event->cpu < 0) { + dev_warn(ccn->dev, "Can't provide per-task data!\n"); + return -EOPNOTSUPP; + } + /* + * Many perf core operations (eg. events rotation) operate on a + * single CPU context. This is obvious for CPU PMUs, where one + * expects the same sets of events being observed on all CPUs, + * but can lead to issues for off-core PMUs, like CCN, where each + * event could be theoretically assigned to a different CPU. To + * mitigate this, we enforce CPU assignment to one, selected + * processor (the one described in the "cpumask" attribute). + */ + event->cpu = cpumask_first(&ccn->dt.cpu); + + node_xp = CCN_CONFIG_NODE(event->attr.config); + type = CCN_CONFIG_TYPE(event->attr.config); + event_id = CCN_CONFIG_EVENT(event->attr.config); + + /* Validate node/xp vs topology */ + switch (type) { + case CCN_TYPE_MN: + if (node_xp != ccn->mn_id) { + dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp); + return -EINVAL; + } + break; + case CCN_TYPE_XP: + if (node_xp >= ccn->num_xps) { + dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp); + return -EINVAL; + } + break; + case CCN_TYPE_CYCLES: + break; + default: + if (node_xp >= ccn->num_nodes) { + dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp); + return -EINVAL; + } + if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) { + dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n", + type, node_xp); + return -EINVAL; + } + break; + } + + /* Validate event ID vs available for the type */ + for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid; + i++) { + struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i]; + u32 port = CCN_CONFIG_PORT(event->attr.config); + u32 vc = CCN_CONFIG_VC(event->attr.config); + + if (!arm_ccn_pmu_type_eq(type, e->type)) + continue; + if (event_id != e->event) + continue; + if (e->num_ports && port >= e->num_ports) { + dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n", + port, node_xp); + return -EINVAL; + } + if (e->num_vcs && vc >= e->num_vcs) { + dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n", + vc, node_xp); + return -EINVAL; + } + valid = 1; + } + if (!valid) { + dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n", + event_id, node_xp); + return -EINVAL; + } + + /* Watchpoint-based event for a node is actually set on XP */ + if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) { + u32 port; + + type = CCN_TYPE_XP; + port = arm_ccn_node_to_xp_port(node_xp); + node_xp = arm_ccn_node_to_xp(node_xp); + + arm_ccn_pmu_config_set(&event->attr.config, + node_xp, type, port); + } + + /* + * We must NOT create groups containing mixed PMUs, although software + * events are acceptable (for example to create a CCN group + * periodically read when a hrtimer aka cpu-clock leader triggers). + */ + if (event->group_leader->pmu != event->pmu && + !is_software_event(event->group_leader)) + return -EINVAL; + + list_for_each_entry(sibling, &event->group_leader->sibling_list, + group_entry) + if (sibling->pmu != event->pmu && + !is_software_event(sibling)) + return -EINVAL; + + return 0; +} + +static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx) +{ + u64 res; + + if (idx == CCN_IDX_PMU_CYCLE_COUNTER) { +#ifdef readq + res = readq(ccn->dt.base + CCN_DT_PMCCNTR); +#else + /* 40 bit counter, can do snapshot and read in two parts */ + writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); + while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) + ; + writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); + res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; + res <<= 32; + res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); +#endif + } else { + res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); + } + + return res; +} + +static void arm_ccn_pmu_event_update(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + u64 prev_count, new_count, mask; + + do { + prev_count = local64_read(&hw->prev_count); + new_count = arm_ccn_pmu_read_counter(ccn, hw->idx); + } while (local64_xchg(&hw->prev_count, new_count) != prev_count); + + mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; + + local64_add((new_count - prev_count) & mask, &event->count); +} + +static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + struct arm_ccn_component *xp; + u32 val, dt_cfg; + + /* Nothing to do for cycle counter */ + if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) + return; + + if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) + xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)]; + else + xp = &ccn->xp[arm_ccn_node_to_xp( + CCN_CONFIG_NODE(event->attr.config))]; + + if (enable) + dt_cfg = hw->event_base; + else + dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH; + + spin_lock(&ccn->dt.config_lock); + + val = readl(xp->base + CCN_XP_DT_CONFIG); + val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK << + CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx)); + val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx); + writel(val, xp->base + CCN_XP_DT_CONFIG); + + spin_unlock(&ccn->dt.config_lock); +} + +static void arm_ccn_pmu_event_start(struct perf_event *event, int flags) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + + local64_set(&event->hw.prev_count, + arm_ccn_pmu_read_counter(ccn, hw->idx)); + hw->state = 0; + + /* Set the DT bus input, engaging the counter */ + arm_ccn_pmu_xp_dt_config(event, 1); +} + +static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags) +{ + struct hw_perf_event *hw = &event->hw; + + /* Disable counting, setting the DT bus to pass-through mode */ + arm_ccn_pmu_xp_dt_config(event, 0); + + if (flags & PERF_EF_UPDATE) + arm_ccn_pmu_event_update(event); + + hw->state |= PERF_HES_STOPPED; +} + +static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + struct arm_ccn_component *source = + ccn->dt.pmu_counters[hw->idx].source; + unsigned long wp = hw->config_base; + u32 val; + u64 cmp_l = event->attr.config1; + u64 cmp_h = event->attr.config2; + u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; + u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; + + hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); + + /* Direction (RX/TX), device (port) & virtual channel */ + val = readl(source->base + CCN_XP_DT_INTERFACE_SEL); + val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK << + CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp)); + val |= CCN_CONFIG_DIR(event->attr.config) << + CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp); + val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK << + CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp)); + val |= CCN_CONFIG_PORT(event->attr.config) << + CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp); + val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK << + CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp)); + val |= CCN_CONFIG_VC(event->attr.config) << + CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp); + writel(val, source->base + CCN_XP_DT_INTERFACE_SEL); + + /* Comparison values */ + writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp)); + writel((cmp_l >> 32) & 0x7fffffff, + source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4); + writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp)); + writel((cmp_h >> 32) & 0x0fffffff, + source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4); + + /* Mask */ + writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp)); + writel((mask_l >> 32) & 0x7fffffff, + source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4); + writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp)); + writel((mask_h >> 32) & 0x0fffffff, + source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4); +} + +static void arm_ccn_pmu_xp_event_config(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + struct arm_ccn_component *source = + ccn->dt.pmu_counters[hw->idx].source; + u32 val, id; + + hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); + + id = (CCN_CONFIG_VC(event->attr.config) << 4) | + (CCN_CONFIG_BUS(event->attr.config) << 3) | + (CCN_CONFIG_EVENT(event->attr.config) << 0); + + val = readl(source->base + CCN_XP_PMU_EVENT_SEL); + val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK << + CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); + val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); + writel(val, source->base + CCN_XP_PMU_EVENT_SEL); +} + +static void arm_ccn_pmu_node_event_config(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + struct arm_ccn_component *source = + ccn->dt.pmu_counters[hw->idx].source; + u32 type = CCN_CONFIG_TYPE(event->attr.config); + u32 val, port; + + port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config)); + hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, + hw->config_base); + + /* These *_event_sel regs should be identical, but let's make sure... */ + BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL); + BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL); + BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) != + CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1)); + BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) != + CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1)); + BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK != + CCN_SBAS_PMU_EVENT_SEL__ID__MASK); + BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK != + CCN_RNI_PMU_EVENT_SEL__ID__MASK); + if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS && + !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P))) + return; + + /* Set the event id for the pre-allocated counter */ + val = readl(source->base + CCN_HNF_PMU_EVENT_SEL); + val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK << + CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); + val |= CCN_CONFIG_EVENT(event->attr.config) << + CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); + writel(val, source->base + CCN_HNF_PMU_EVENT_SEL); +} + +static void arm_ccn_pmu_event_config(struct perf_event *event) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + struct hw_perf_event *hw = &event->hw; + u32 xp, offset, val; + + /* Cycle counter requires no setup */ + if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) + return; + + if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) + xp = CCN_CONFIG_XP(event->attr.config); + else + xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config)); + + spin_lock(&ccn->dt.config_lock); + + /* Set the DT bus "distance" register */ + offset = (hw->idx / 4) * 4; + val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); + val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK << + CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4)); + val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4); + writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); + + if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) { + if (CCN_CONFIG_EVENT(event->attr.config) == + CCN_EVENT_WATCHPOINT) + arm_ccn_pmu_xp_watchpoint_config(event); + else + arm_ccn_pmu_xp_event_config(event); + } else { + arm_ccn_pmu_node_event_config(event); + } + + spin_unlock(&ccn->dt.config_lock); +} + +static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn) +{ + return bitmap_weight(ccn->dt.pmu_counters_mask, + CCN_NUM_PMU_EVENT_COUNTERS + 1); +} + +static int arm_ccn_pmu_event_add(struct perf_event *event, int flags) +{ + int err; + struct hw_perf_event *hw = &event->hw; + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + + err = arm_ccn_pmu_event_alloc(event); + if (err) + return err; + + /* + * Pin the timer, so that the overflows are handled by the chosen + * event->cpu (this is the same one as presented in "cpumask" + * attribute). + */ + if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1) + hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), + HRTIMER_MODE_REL_PINNED); + + arm_ccn_pmu_event_config(event); + + hw->state = PERF_HES_STOPPED; + + if (flags & PERF_EF_START) + arm_ccn_pmu_event_start(event, PERF_EF_UPDATE); + + return 0; +} + +static void arm_ccn_pmu_event_del(struct perf_event *event, int flags) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu); + + arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE); + + arm_ccn_pmu_event_release(event); + + if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0) + hrtimer_cancel(&ccn->dt.hrtimer); +} + +static void arm_ccn_pmu_event_read(struct perf_event *event) +{ + arm_ccn_pmu_event_update(event); +} + +static void arm_ccn_pmu_enable(struct pmu *pmu) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); + + u32 val = readl(ccn->dt.base + CCN_DT_PMCR); + val |= CCN_DT_PMCR__PMU_EN; + writel(val, ccn->dt.base + CCN_DT_PMCR); +} + +static void arm_ccn_pmu_disable(struct pmu *pmu) +{ + struct arm_ccn *ccn = pmu_to_arm_ccn(pmu); + + u32 val = readl(ccn->dt.base + CCN_DT_PMCR); + val &= ~CCN_DT_PMCR__PMU_EN; + writel(val, ccn->dt.base + CCN_DT_PMCR); +} + +static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) +{ + u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); + int idx; + + if (!pmovsr) + return IRQ_NONE; + + writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); + + BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS); + + for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) { + struct perf_event *event = dt->pmu_counters[idx].event; + int overflowed = pmovsr & BIT(idx); + + WARN_ON_ONCE(overflowed && !event && + idx != CCN_IDX_PMU_CYCLE_COUNTER); + + if (!event || !overflowed) + continue; + + arm_ccn_pmu_event_update(event); + } + + return IRQ_HANDLED; +} + +static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer) +{ + struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, + hrtimer); + unsigned long flags; + + local_irq_save(flags); + arm_ccn_pmu_overflow_handler(dt); + local_irq_restore(flags); + + hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period()); + return HRTIMER_RESTART; +} + + +static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); + struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); + unsigned int target; + + if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) + return 0; + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + perf_pmu_migrate_context(&dt->pmu, cpu, target); + cpumask_set_cpu(target, &dt->cpu); + if (ccn->irq) + WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0); + return 0; +} + +static DEFINE_IDA(arm_ccn_pmu_ida); + +static int arm_ccn_pmu_init(struct arm_ccn *ccn) +{ + int i; + char *name; + int err; + + /* Initialize DT subsystem */ + ccn->dt.base = ccn->base + CCN_REGION_SIZE; + spin_lock_init(&ccn->dt.config_lock); + writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); + writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); + writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN, + ccn->dt.base + CCN_DT_PMCR); + writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); + for (i = 0; i < ccn->num_xps; i++) { + writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG); + writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << + CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) | + (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS << + CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) | + CCN_XP_DT_CONTROL__DT_ENABLE, + ccn->xp[i].base + CCN_XP_DT_CONTROL); + } + ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; + ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; + ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; + ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; + ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; + ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); + ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; + ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); + + /* Get a convenient /sys/event_source/devices/ name */ + ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL); + if (ccn->dt.id == 0) { + name = "ccn"; + } else { + name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d", + ccn->dt.id); + if (!name) { + err = -ENOMEM; + goto error_choose_name; + } + } + + /* Perf driver registration */ + ccn->dt.pmu = (struct pmu) { + .module = THIS_MODULE, + .attr_groups = arm_ccn_pmu_attr_groups, + .task_ctx_nr = perf_invalid_context, + .event_init = arm_ccn_pmu_event_init, + .add = arm_ccn_pmu_event_add, + .del = arm_ccn_pmu_event_del, + .start = arm_ccn_pmu_event_start, + .stop = arm_ccn_pmu_event_stop, + .read = arm_ccn_pmu_event_read, + .pmu_enable = arm_ccn_pmu_enable, + .pmu_disable = arm_ccn_pmu_disable, + }; + + /* No overflow interrupt? Have to use a timer instead. */ + if (!ccn->irq) { + dev_info(ccn->dev, "No access to interrupts, using timer.\n"); + hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; + } + + /* Pick one CPU which we will use to collect data from CCN... */ + cpumask_set_cpu(get_cpu(), &ccn->dt.cpu); + + /* Also make sure that the overflow interrupt is handled by this CPU */ + if (ccn->irq) { + err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu); + if (err) { + dev_err(ccn->dev, "Failed to set interrupt affinity!\n"); + goto error_set_affinity; + } + } + + err = perf_pmu_register(&ccn->dt.pmu, name, -1); + if (err) + goto error_pmu_register; + + cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, + &ccn->dt.node); + put_cpu(); + return 0; + +error_pmu_register: +error_set_affinity: + put_cpu(); +error_choose_name: + ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); + for (i = 0; i < ccn->num_xps; i++) + writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); + writel(0, ccn->dt.base + CCN_DT_PMCR); + return err; +} + +static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn) +{ + int i; + + cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE, + &ccn->dt.node); + if (ccn->irq) + irq_set_affinity_hint(ccn->irq, NULL); + for (i = 0; i < ccn->num_xps; i++) + writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL); + writel(0, ccn->dt.base + CCN_DT_PMCR); + perf_pmu_unregister(&ccn->dt.pmu); + ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); +} + +static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn, + int (*callback)(struct arm_ccn *ccn, int region, + void __iomem *base, u32 type, u32 id)) +{ + int region; + + for (region = 0; region < CCN_NUM_REGIONS; region++) { + u32 val, type, id; + void __iomem *base; + int err; + + val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 + + 4 * (region / 32)); + if (!(val & (1 << (region % 32)))) + continue; + + base = ccn->base + region * CCN_REGION_SIZE; + val = readl(base + CCN_ALL_OLY_ID); + type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) & + CCN_ALL_OLY_ID__OLY_ID__MASK; + id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) & + CCN_ALL_OLY_ID__NODE_ID__MASK; + + err = callback(ccn, region, base, type, id); + if (err) + return err; + } + + return 0; +} + +static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region, + void __iomem *base, u32 type, u32 id) +{ + + if (type == CCN_TYPE_XP && id >= ccn->num_xps) + ccn->num_xps = id + 1; + else if (id >= ccn->num_nodes) + ccn->num_nodes = id + 1; + + return 0; +} + +static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region, + void __iomem *base, u32 type, u32 id) +{ + struct arm_ccn_component *component; + + dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type); + + switch (type) { + case CCN_TYPE_MN: + ccn->mn_id = id; + return 0; + case CCN_TYPE_DT: + return 0; + case CCN_TYPE_XP: + component = &ccn->xp[id]; + break; + case CCN_TYPE_SBSX: + ccn->sbsx_present = 1; + component = &ccn->node[id]; + break; + case CCN_TYPE_SBAS: + ccn->sbas_present = 1; + /* Fall-through */ + default: + component = &ccn->node[id]; + break; + } + + component->base = base; + component->type = type; + + return 0; +} + + +static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn, + const u32 *err_sig_val) +{ + /* This should be really handled by firmware... */ + dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n", + err_sig_val[5], err_sig_val[4], err_sig_val[3], + err_sig_val[2], err_sig_val[1], err_sig_val[0]); + dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n"); + writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE, + ccn->base + CCN_MN_ERRINT_STATUS); + + return IRQ_HANDLED; +} + + +static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id) +{ + irqreturn_t res = IRQ_NONE; + struct arm_ccn *ccn = dev_id; + u32 err_sig_val[6]; + u32 err_or; + int i; + + /* PMU overflow is a special case */ + err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0); + if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) { + err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT; + res = arm_ccn_pmu_overflow_handler(&ccn->dt); + } + + /* Have to read all err_sig_vals to clear them */ + for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) { + err_sig_val[i] = readl(ccn->base + + CCN_MN_ERR_SIG_VAL_63_0 + i * 4); + err_or |= err_sig_val[i]; + } + if (err_or) + res |= arm_ccn_error_handler(ccn, err_sig_val); + + if (res != IRQ_NONE) + writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT, + ccn->base + CCN_MN_ERRINT_STATUS); + + return res; +} + + +static int arm_ccn_probe(struct platform_device *pdev) +{ + struct arm_ccn *ccn; + struct resource *res; + unsigned int irq; + int err; + + ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL); + if (!ccn) + return -ENOMEM; + ccn->dev = &pdev->dev; + platform_set_drvdata(pdev, ccn); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + if (!devm_request_mem_region(ccn->dev, res->start, + resource_size(res), pdev->name)) + return -EBUSY; + + ccn->base = devm_ioremap(ccn->dev, res->start, + resource_size(res)); + if (!ccn->base) + return -EFAULT; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) + return -EINVAL; + irq = res->start; + + /* Check if we can use the interrupt */ + writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE, + ccn->base + CCN_MN_ERRINT_STATUS); + if (readl(ccn->base + CCN_MN_ERRINT_STATUS) & + CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) { + /* Can set 'disable' bits, so can acknowledge interrupts */ + writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE, + ccn->base + CCN_MN_ERRINT_STATUS); + err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, + IRQF_NOBALANCING | IRQF_NO_THREAD, + dev_name(ccn->dev), ccn); + if (err) + return err; + + ccn->irq = irq; + } + + + /* Build topology */ + + err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num); + if (err) + return err; + + ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node), + GFP_KERNEL); + ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node), + GFP_KERNEL); + if (!ccn->node || !ccn->xp) + return -ENOMEM; + + err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes); + if (err) + return err; + + return arm_ccn_pmu_init(ccn); +} + +static int arm_ccn_remove(struct platform_device *pdev) +{ + struct arm_ccn *ccn = platform_get_drvdata(pdev); + + arm_ccn_pmu_cleanup(ccn); + + return 0; +} + +static const struct of_device_id arm_ccn_match[] = { + { .compatible = "arm,ccn-502", }, + { .compatible = "arm,ccn-504", }, + {}, +}; +MODULE_DEVICE_TABLE(of, arm_ccn_match); + +static struct platform_driver arm_ccn_driver = { + .driver = { + .name = "arm-ccn", + .of_match_table = arm_ccn_match, + }, + .probe = arm_ccn_probe, + .remove = arm_ccn_remove, +}; + +static int __init arm_ccn_init(void) +{ + int i, ret; + + ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE, + "perf/arm/ccn:online", NULL, + arm_ccn_pmu_offline_cpu); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++) + arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr; + + ret = platform_driver_register(&arm_ccn_driver); + if (ret) + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); + return ret; +} + +static void __exit arm_ccn_exit(void) +{ + platform_driver_unregister(&arm_ccn_driver); + cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE); +} + +module_init(arm_ccn_init); +module_exit(arm_ccn_exit); + +MODULE_AUTHOR("Pawel Moll "); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From d6bdd009c21db3f677dd1d1bbb8c20bc819074bc Mon Sep 17 00:00:00 2001 From: Brendan Higgins Date: Thu, 17 Aug 2017 07:20:09 -0700 Subject: arm: dts: add Nuvoton NPCM750 device tree Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins Reviewed-by: Tomer Maimon Reviewed-by: Avi Fishman Reviewed-by: Joel Stanley Reviewed-by: Rob Herring Tested-by: Tomer Maimon Tested-by: Avi Fishman Tested-by: Joel Stanley Signed-off-by: Arnd Bergmann --- .../arm/cpu-enable-method/nuvoton,npcm750-smp | 42 ++++++ .../devicetree/bindings/arm/npcm/npcm.txt | 6 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 35 +++++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 165 +++++++++++++++++++++ 5 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp new file mode 100644 index 000000000000..8e043301e28e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp @@ -0,0 +1,42 @@ +========================================================= +Secondary CPU enable-method "nuvoton,npcm750-smp" binding +========================================================= + +To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be +defined in the "cpus" node. + +Enable method name: "nuvoton,npcm750-smp" +Compatible machines: "nuvoton,npcm750" +Compatible CPUs: "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"nuvoton,npcm750-gcr". + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt new file mode 100644 index 000000000000..2d87d9ecea85 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt @@ -0,0 +1,6 @@ +NPCM Platforms Device Tree Bindings +----------------------------------- +NPCM750 SoC +Required root node properties: + - compatible = "nuvoton,npcm750"; + diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ade7a38543dc..eeab5dac50ab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -304,6 +304,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb +dtb-$(CONFIG_ARCH_NPCM750) += \ + nuvoton-npcm750-evb.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts new file mode 100644 index 000000000000..cabde3d5be8a --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" + +/ { + model = "Nuvoton npcm750 Development Board (Device Tree)"; + compatible = "nuvoton,npcm750"; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..839e45cfd695 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk 10>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk 10>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00900000>; + + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", + "simple-mfd"; + reg = <0x800000 0x1000>; + }; + + scu: scu@3fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x3fe000 0x1000>; + }; + + l2: cache-controller@3fc000 { + compatible = "arm,pl310-cache"; + reg = <0x3fc000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + clocks = <&clk 22>; + arm,shared-override; + }; + + gic: interrupt-controller@3ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x3ff000 0x1000>, + <0x3fe100 0x100>; + }; + + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk 15>; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00300000>; + + timer0: timer@8000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = ; + reg = <0x8000 0x1000>; + clocks = <&clk 15>; + }; + + serial0: serial@1000 { + compatible = "ns16550a"; + reg = <0x1000 0x1000>; + clocks = <&clk 14>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial1: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x1000>; + clocks = <&clk 14>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial2: serial@3000 { + compatible = "ns16550a"; + reg = <0x3000 0x1000>; + clocks = <&clk 14>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + + serial3: serial@4000 { + compatible = "ns16550a"; + reg = <0x4000 0x1000>; + clocks = <&clk 14>; + interrupts = ; + reg-shift = <2>; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3 From 2380ca5f1f46412d08c96ebea996e049548829bd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 14 Nov 2017 09:59:03 +0000 Subject: dt-bindings: PCI: rcar: Add device tree support for r8a7743 Add support for r8a7743. The Renesas RZ/G1M(R8A7743)PCIe controller is identical to the R-Car Gen2 family. No driver change is needed due to the fallback compatible value "renesas,pcie-rcar-gen2". Adding the SoC-specific compatible values here has three purposes: 1. Document which SoCs have this hardware module, 2. Allow checkpatch to validate compatible values. 3. Allow the driver to support SoC specific implementations in future as necessary. Signed-off-by: Biju Das Signed-off-by: Lorenzo Pieralisi Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Acked-by: Simon Horman --- Documentation/devicetree/bindings/pci/rcar-pci.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt index 76ba3a61d1a3..1fb614e615da 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt @@ -1,13 +1,15 @@ * Renesas R-Car PCIe interface Required properties: -compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC; +compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; + "renesas,pcie-r8a7779" for the R8A7779 SoC; "renesas,pcie-r8a7790" for the R8A7790 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; "renesas,pcie-r8a7793" for the R8A7793 SoC; "renesas,pcie-r8a7795" for the R8A7795 SoC; "renesas,pcie-r8a7796" for the R8A7796 SoC; - "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device. + "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or + RZ/G1 compatible device. "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device. When compatible with the generic version, nodes must list the -- cgit v1.2.3 From 593aa2b405f992b59b51b30fed426510fa1a513d Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Tue, 27 Feb 2018 08:11:29 +0100 Subject: dt-bindings: add bindings for USB physical connector These bindings allow to describe most known standard USB connectors and it should be possible to extend it if necessary. USB connectors, beside USB can be used to route other protocols, for example UART, Audio, MHL. In such case every device passing data through the connector should have appropriate graph bindings. Signed-off-by: Andrzej Hajda Reviewed-by: Rob Herring Signed-off-by: Chanwoo Choi --- .../bindings/connector/usb-connector.txt | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/connector/usb-connector.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt new file mode 100644 index 000000000000..e1463f14af38 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/usb-connector.txt @@ -0,0 +1,75 @@ +USB Connector +============= + +USB connector node represents physical USB connector. It should be +a child of USB interface controller. + +Required properties: +- compatible: describes type of the connector, must be one of: + "usb-a-connector", + "usb-b-connector", + "usb-c-connector". + +Optional properties: +- label: symbolic name for the connector, +- type: size of the connector, should be specified in case of USB-A, USB-B + non-fullsize connectors: "mini", "micro". + +Required nodes: +- any data bus to the connector should be modeled using the OF graph bindings + specified in bindings/graph.txt, unless the bus is between parent node and + the connector. Since single connector can have multpile data buses every bus + has assigned OF graph port number as follows: + 0: High Speed (HS), present in all connectors, + 1: Super Speed (SS), present in SS capable connectors, + 2: Sideband use (SBU), present in USB-C. + +Examples +-------- + +1. Micro-USB connector with HS lines routed via controller (MUIC): + +muic-max77843@66 { + ... + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; +}; + +2. USB-C connector attached to CC controller (s2mm005), HS lines routed +to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort. +DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. + +ccic: s2mm005@33 { + ... + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&max77865_usbc_hs>; + }; + }; + port@1 { + reg = <1>; + usb_con_ss: endpoint { + remote-endpoint = <&usbdrd_phy_ss>; + }; + }; + port@2 { + reg = <2>; + usb_con_sbu: endpoint { + remote-endpoint = <&dp_aux>; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 14217173217e021c1f354269e61f3c1d5affc42e Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Tue, 27 Feb 2018 08:11:30 +0100 Subject: dt-bindings: add bindings for Samsung micro-USB 11-pin connector Samsung micro-USB 11-pin connector beside standard micro-USB pins, has pins dedicated to route MHL traffic. Signed-off-by: Andrzej Hajda Reviewed-by: Rob Herring Signed-off-by: Chanwoo Choi --- .../connector/samsung,usb-connector-11pin.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt new file mode 100644 index 000000000000..22256e295a7a --- /dev/null +++ b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt @@ -0,0 +1,49 @@ +Samsung micro-USB 11-pin connector +================================== + +Samsung micro-USB 11-pin connector is an extension of micro-USB connector. +It is present in multiple Samsung mobile devices. +It has additional pins to route MHL traffic simultanously with USB. + +The bindings are superset of usb-connector bindings for micro-USB connector[1]. + +Required properties: +- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector", +- type: must be "micro". + +Required nodes: +- any data bus to the connector should be modeled using the OF graph bindings + specified in bindings/graph.txt, unless the bus is between parent node and + the connector. Since single connector can have multpile data buses every bus + has assigned OF graph port number as follows: + 0: High Speed (HS), + 3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB. + +[1]: bindings/connector/usb-connector.txt + +Example +------- + +Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines +connected to HDMI-MHL bridge (sii8620): + +muic-max77843@66 { + ... + usb_con: connector { + compatible = "samsung,usb-connector-11pin", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + usb_con_mhl: endpoint { + remote-endpoint = <&sii8620_mhl>; + }; + }; + }; + }; +}; -- cgit v1.2.3 From feac8c8bb9d087c8b5d2415c00c095735799eb6c Mon Sep 17 00:00:00 2001 From: Yasunari Takiguchi Date: Thu, 18 Jan 2018 03:43:51 -0500 Subject: media: Add document file for CXD2880 SPI I/F This is the document file for Sony CXD2880 DVB-T2/T tuner + demodulator. It contains the description of the SPI adapter binding. Signed-off-by: Yasunari Takiguchi Signed-off-by: Masayuki Yamamoto Signed-off-by: Hideki Nozawa Signed-off-by: Kota Yonezawa Signed-off-by: Toshihiko Matsumoto Signed-off-by: Satoshi Watanabe Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/spi/sony-cxd2880.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt new file mode 100644 index 000000000000..fc5aa263abe5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/spi/sony-cxd2880.txt @@ -0,0 +1,14 @@ +Sony CXD2880 DVB-T2/T tuner + demodulator driver SPI adapter + +Required properties: +- compatible: Should be "sony,cxd2880". +- reg: SPI chip select number for the device. +- spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz). + +Example: + +cxd2880@0 { + compatible = "sony,cxd2880"; + reg = <0>; /* CE0 */ + spi-max-frequency = <55000000>; /* 55MHz */ +}; -- cgit v1.2.3 From 9db7d4b32cbccb5807e2e1f22e2fafc80034ee6d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 4 Mar 2018 15:35:50 +0100 Subject: ASoC: rt5651: Add devicetree-bindings for jack-detect Add new properties to the rt5651 dt-bindings for configuring the jack-detect source and over-current detect settings. Cc: devicetree@vger.kernel.org Signed-off-by: Hans de Goede Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5651.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5651.txt b/Documentation/devicetree/bindings/sound/rt5651.txt index 3875233095f5..7890aa9477f8 100644 --- a/Documentation/devicetree/bindings/sound/rt5651.txt +++ b/Documentation/devicetree/bindings/sound/rt5651.txt @@ -16,6 +16,23 @@ Optional properties: - realtek,dmic-en Boolean. true if dmic is used. +- realtek,jack-detect-source + u32. Valid values: + 1: Use JD1_1 pin for jack-dectect + 2: Use JD1_2 pin for jack-dectect + 3: Use JD2 pin for jack-dectect + +- realtek,over-current-threshold-microamp + u32, micbias over-current detection threshold in µA, valid values are + 600, 1500 and 2000µA. + +- realtek,over-current-scale-factor + u32, micbias over-current detection scale-factor, valid values are: + 0: Scale current by 0.5 + 1: Scale current by 0.75 + 2: Scale current by 1.0 + 3: Scale current by 1.5 + Pins on the device (for linking into audio routes) for RT5651: * DMIC L1 -- cgit v1.2.3 From 09f7fcfa727966361d576fcfdb9c5ad77ddf5092 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 7 Mar 2018 00:24:13 -0300 Subject: ASoC: wm8524: Remove unit address WM8524 does not use I2C nor SPI, hence no 'reg' property is used, so remove the unit address from the bindings example to conform. This avoids users getting dtc warnings when they copy the binding example to a real dts file. Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/wm8524.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/wm8524.txt b/Documentation/devicetree/bindings/sound/wm8524.txt index 20c62002cbcd..0f0553563fc1 100644 --- a/Documentation/devicetree/bindings/sound/wm8524.txt +++ b/Documentation/devicetree/bindings/sound/wm8524.txt @@ -10,7 +10,7 @@ Required properties: Example: -codec: wm8524@0 { +codec: wm8524 { compatible = "wlf,wm8524"; wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; -- cgit v1.2.3 From f625b1ade245ad6810909923585dd07f24391861 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 15 Feb 2018 13:22:48 +0000 Subject: PCI: qcom: Add missing supplies required for msm8996 This patch adds supplies that are required for msm8996. vdda is analog supply that go in to controller, and vddpe_3v3 is supply to PCIe endpoint. Without these supplies PCIe endpoints which require power supplies are not enumerated at all, as there is no one to power it up. Signed-off-by: Srinivas Kandagatla Signed-off-by: Lorenzo Pieralisi Acked-by: Stanimir Varbanov Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie.txt | 4 ++++ drivers/pci/dwc/pcie-qcom.c | 23 +++++++++++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3c9d321b3d3b..1fd703bd73e0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -189,6 +189,10 @@ Value type: Definition: A phandle to the analog power supply for IC which generates reference clock +- vddpe-3v3-supply: + Usage: optional + Value type: + Definition: A phandle to the PCIe endpoint power supply - phys: Usage: required for apq8084 diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index 6310c66e265c..a7c12f737690 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -102,12 +102,14 @@ struct qcom_pcie_resources_1_0_0 { struct regulator *vdda; }; +#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 struct qcom_pcie_resources_2_3_2 { struct clk *aux_clk; struct clk *master_clk; struct clk *slave_clk; struct clk *cfg_clk; struct clk *pipe_clk; + struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; struct qcom_pcie_resources_2_4_0 { @@ -521,6 +523,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + int ret; + + res->supplies[0].supply = "vdda"; + res->supplies[1].supply = "vddpe-3v3"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), + res->supplies); + if (ret) + return ret; res->aux_clk = devm_clk_get(dev, "aux"); if (IS_ERR(res->aux_clk)) @@ -550,6 +560,8 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) clk_disable_unprepare(res->master_clk); clk_disable_unprepare(res->cfg_clk); clk_disable_unprepare(res->aux_clk); + + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie) @@ -567,10 +579,16 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) u32 val; int ret; + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); + if (ret < 0) { + dev_err(dev, "cannot enable regulators\n"); + return ret; + } + ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); - return ret; + goto err_aux_clk; } ret = clk_prepare_enable(res->cfg_clk); @@ -621,6 +639,9 @@ err_master_clk: err_cfg_clk: clk_disable_unprepare(res->aux_clk); +err_aux_clk: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + return ret; } -- cgit v1.2.3 From 58dfb24349e1d0aa6461d2b0f2811b46fe350280 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 2 Mar 2018 09:12:01 +0800 Subject: PCI: histb: Add an optional regulator for PCIe port power control The power supplies to PCIe port are often controlled by GPIO on some board designs. Let's add an optional regulator which can be backed by GPIO to control the power. Signed-off-by: Shawn Guo Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- .../bindings/pci/hisilicon-histb-pcie.txt | 1 + drivers/pci/dwc/pcie-histb.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt index c84bc027930b..760b4d740616 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -34,6 +34,7 @@ Required properties Optional properties: - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal. +- vpcie-supply: The regulator in charge of PCIe port power. - phys: List of phandle and phy mode specifier, should be 0. - phy-names: Must be "phy". diff --git a/drivers/pci/dwc/pcie-histb.c b/drivers/pci/dwc/pcie-histb.c index 17ed604f5741..4cef0a514944 100644 --- a/drivers/pci/dwc/pcie-histb.c +++ b/drivers/pci/dwc/pcie-histb.c @@ -61,6 +61,7 @@ struct histb_pcie { struct reset_control *bus_reset; void __iomem *ctrl; int reset_gpio; + struct regulator *vpcie; }; static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg) @@ -227,6 +228,9 @@ static void histb_pcie_host_disable(struct histb_pcie *hipcie) if (gpio_is_valid(hipcie->reset_gpio)) gpio_set_value_cansleep(hipcie->reset_gpio, 0); + + if (hipcie->vpcie) + regulator_disable(hipcie->vpcie); } static int histb_pcie_host_enable(struct pcie_port *pp) @@ -237,6 +241,14 @@ static int histb_pcie_host_enable(struct pcie_port *pp) int ret; /* power on PCIe device if have */ + if (hipcie->vpcie) { + ret = regulator_enable(hipcie->vpcie); + if (ret) { + dev_err(dev, "failed to enable regulator: %d\n", ret); + return ret; + } + } + if (gpio_is_valid(hipcie->reset_gpio)) gpio_set_value_cansleep(hipcie->reset_gpio, 1); @@ -282,6 +294,8 @@ err_pipe_clk: err_sys_clk: clk_disable_unprepare(hipcie->bus_clk); err_bus_clk: + if (hipcie->vpcie) + regulator_disable(hipcie->vpcie); return ret; } @@ -331,6 +345,13 @@ static int histb_pcie_probe(struct platform_device *pdev) return PTR_ERR(pci->dbi_base); } + hipcie->vpcie = devm_regulator_get_optional(dev, "vpcie"); + if (IS_ERR(hipcie->vpcie)) { + if (PTR_ERR(hipcie->vpcie) == -EPROBE_DEFER) + return -EPROBE_DEFER; + hipcie->vpcie = NULL; + } + hipcie->reset_gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &of_flags); if (of_flags & OF_GPIO_ACTIVE_LOW) -- cgit v1.2.3 From 22936c3e6e8cdd9641fdf1362dc9369dd35246c8 Mon Sep 17 00:00:00 2001 From: Brandon Streiff Date: Mon, 5 Mar 2018 16:05:22 -0600 Subject: dt-bindings: net: dsa: marvell: describe compatibility string There are two compatibility strings for mv88e6xxx, but it isn't clear from the documentation why only those two exist when the mv88e6xxx driver supports more than the 6085 and 6190. Briefly describe how the compatible property is used, and provide guidance on which to use. The model list comes from looking at port_base_addr values (0x0 vs 0x10) in drivers/net/dsa/mv88e6xxx/chip.c. Signed-off-by: Brandon Streiff Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/dsa/marvell.txt | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt index 1d4d0f49c9d0..caf71e2fe24a 100644 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt @@ -13,9 +13,18 @@ placed as a child node of an mdio device. The properties described here are those specific to Marvell devices. Additional required and optional properties can be found in dsa.txt. +The compatibility string is used only to find an identification register, +which is at a different MDIO base address in different switch families. +- "marvell,mv88e6085" : Switch has base address 0x10. Use with models: + 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, + 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321, + 6341, 6350, 6351, 6352 +- "marvell,mv88e6190" : Switch has base address 0x00. Use with models: + 6190, 6190X, 6191, 6290, 6390, 6390X + Required properties: - compatible : Should be one of "marvell,mv88e6085" or - "marvell,mv88e6190" + "marvell,mv88e6190" as indicated above - reg : Address on the MII bus for the switch. Optional properties: -- cgit v1.2.3 From 6adb1b9538e6414ce746ade8d170d362a657ca41 Mon Sep 17 00:00:00 2001 From: John Keeping Date: Thu, 1 Mar 2018 10:34:47 +0000 Subject: dt-bindings: rockchip-dw-mshc: use consistent clock names The names of these clocks are "ciu-drive" and "ciu-sample" as described for the clock-names property. Avoid confusion by spelling these correctly everywhere they are referenced. Signed-off-by: John Keeping Reviewed-by: Heiko Stuebner Reviewed-by: Shawn Lin Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index c6558785e61b..8ce49b255974 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt @@ -21,7 +21,7 @@ Required Properties: - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399 Optional Properties: -* clocks: from common clock binding: if ciu_drive and ciu_sample are +* clocks: from common clock binding: if ciu-drive and ciu-sample are specified in clock-names, should contain handles to these clocks. * clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt @@ -29,7 +29,7 @@ Optional Properties: to control the clock phases, "ciu-sample" is required for tuning high- speed modes. -* rockchip,default-sample-phase: The default phase to set ciu_sample at +* rockchip,default-sample-phase: The default phase to set ciu-sample at probing, low speeds or in case where all phases work at tuning time. If not specified 0 deg will be used. -- cgit v1.2.3 From a7a16068ad9da8b5d0c75449a5d80ef3a4b01fd9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 23 Feb 2018 15:19:28 +0100 Subject: dt-bindings: xilinx: Add description for ZynqMP Record xlnx,zynqmp compatible string. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 1f7995357888..549e70a022cb 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -5,3 +5,13 @@ shall have the following properties. Required root node properties: - compatible = "xlnx,zynq-7000"; + +--------------------------------------------------------------- + +Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings + +Boards with ZynqMP SOC based on an ARM Cortex A53 processor +shall have the following properties. + +Required root node properties: + - compatible = "xlnx,zynqmp"; -- cgit v1.2.3 From 5869ba0653b903587e2b8cfb530656a5c0441c03 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Jan 2016 14:57:27 +0530 Subject: arm64: zynqmp: Add support for Xilinx zcu100-revC This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display port and usbs. Board is using fixed clocks because clock driver hasn't been merged yet. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 6 + arch/arm64/boot/dts/xilinx/Makefile | 1 + arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 289 ++++++++++++++++++++++ 4 files changed, 509 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 549e70a022cb..29039b645807 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -15,3 +15,9 @@ shall have the following properties. Required root node properties: - compatible = "xlnx,zynqmp"; + + +Additional compatible strings: + +- Xilinx 96boards compatible board zcu100 + "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index eba179b23b17..7266a6a9c0cd 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi new file mode 100644 index 000000000000..9c09baca7dd7 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/ { + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk600: clk600 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + dp_aclk: clock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-accuracy = <100>; + }; + + dp_aud_clk: clock1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-accuracy = <100>; + }; + + dpdma_clk: dpdma_clk { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <533000000>; + }; + + drm_clock: drm_clock { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <262750000>; + clock-accuracy = <0x64>; + }; +}; + +&can0 { + clocks = <&clk100 &clk100>; +}; + +&can1 { + clocks = <&clk100 &clk100>; +}; + +&fpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&lpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem2 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem3 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gpio { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&sata { + clocks = <&clk250>; +}; + +&sdhci0 { + clocks = <&clk200 &clk200>; +}; + +&sdhci1 { + clocks = <&clk200 &clk200>; +}; + +&spi0 { + clocks = <&clk200 &clk200>; +}; + +&spi1 { + clocks = <&clk200 &clk200>; +}; + +&uart0 { + clocks = <&clk100 &clk100>; +}; + +&uart1 { + clocks = <&clk100 &clk100>; +}; + +&usb0 { + clocks = <&clk250>, <&clk250>; +}; + +&usb1 { + clocks = <&clk250>, <&clk250>; +}; + +&watchdog0 { + clocks = <&clk250>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts new file mode 100644 index 000000000000..3e862a9faf26 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU100 revC + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek + * Nathalie Chan King Choy + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include +#include +#include + +/ { + model = "ZynqMP ZCU100 RevC"; + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; + + aliases { + i2c0 = &i2c1; + rtc0 = &rtc; + serial0 = &uart1; + serial1 = &uart0; + serial2 = &dcc; + spi0 = &spi0; + spi1 = &spi1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw4 { + label = "sw4"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + ds2 { + label = "ds2"; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds3 { + label = "ds3"; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; /* WLAN tx */ + default-state = "off"; + }; + + ds4 { + label = "ds4"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0rx"; /* WLAN rx */ + default-state = "off"; + }; + + ds5 { + label = "ds5"; + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + }; + + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ + label = "vbus_det"; + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + bt_power { + label = "bt_power"; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + wmmcsdio_fixed: fixedregulator-mmcsdio { + compatible = "regulator-fixed"; + regulator-name = "wmmcsdio_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + sdio_pwrseq: sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + }; +}; + +&dcc { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ + "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + i2c-mux@75 { /* u11 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2csw_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + label = "LS-I2C0"; + }; + i2csw_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + label = "LS-I2C1"; + }; + i2csw_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + label = "HS-I2C2"; + }; + i2csw_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + label = "HS-I2C3"; + }; + i2csw_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + pmic: pmic@5e { /* Custom TI PMIC u33 */ + compatible = "ti,tps65086"; + reg = <0x5e>; + interrupt-parent = <&gpio>; + interrupts = <77 GPIO_ACTIVE_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + i2csw_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* PS_PMBUS */ + ina226@40 { /* u35 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <10000>; + /* MIO31 is alert which should be routed to PMUFW */ + }; + }; + i2csw_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* + * Not Connected + */ + }; + i2csw_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* + * usb5744 (DNP) - U5 + * 100kHz - this is default freq for us + */ + }; + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD0 only supports 3.3V, no level shifter */ +&sdhci0 { + status = "okay"; + no-1-8-v; + broken-cd; /* CD has to be enabled by default */ + disable-wp; +}; + +&sdhci1 { + status = "okay"; + bus-width = <0x4>; + non-removable; + disable-wp; + cap-power-off-card; + mmc-pwrseq = <&sdio_pwrseq>; + vqmmc-supply = <&wmmcsdio_fixed>; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wifi@2 { + compatible = "ti,wl1831"; + reg = <2>; + interrupt-parent = <&gpio>; + interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ + }; +}; + +&spi0 { /* Low Speed connector */ + status = "okay"; + label = "LS-SPI0"; +}; + +&spi1 { /* High Speed connector */ + status = "okay"; + label = "HS-SPI1"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3 From ef797b53705c18773b03cd7d8b60a25c904e7a4f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Jan 2018 15:52:47 +0100 Subject: arm64: zynqmp: Add support for Xilinx zcu102 This patch is adding revA, revB and rev1.0. There are also other revisions between which should be backward compatible with previous versions. Unfortunately all revs are still in use. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 5 + arch/arm64/boot/dts/xilinx/Makefile | 3 + .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 548 +++++++++++++++++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 40 ++ 5 files changed, 632 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 29039b645807..2b922ec3c82a 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -21,3 +21,8 @@ Additional compatible strings: - Xilinx 96boards compatible board zcu100 "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" + +- Xilinx evaluation board zcu102 + "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102" + "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102" + "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 7266a6a9c0cd..24e3ce801304 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -1,3 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts new file mode 100644 index 000000000000..6647e97edba3 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU102 Rev1.0 + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +#include "zynqmp-zcu102-revB.dts" + +/ { + model = "ZynqMP ZCU102 Rev1.0"; + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +}; + +&eeprom { + #address-cells = <1>; + #size-cells = <1>; + + board_sn: board-sn@0 { + reg = <0x0 0x14>; + }; + + eth_mac: eth-mac@20 { + reg = <0x20 0x6>; + }; + + board_name: board-name@d0 { + reg = <0xd0 0x6>; + }; + + board_revision: board-revision@e0 { + reg = <0xe0 0x3>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts new file mode 100644 index 000000000000..5b4ffe646a9b --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU102 RevA + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include +#include + +/ { + model = "ZynqMP ZCU102 RevA"; + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@21 { + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - PS_GTR_LAN_SEL0 + * 1 - PS_GTR_LAN_SEL1 + * 2 - PS_GTR_LAN_SEL2 + * 3 - PS_GTR_LAN_SEL3 + * 4 - PCI_CLK_DIR_SEL + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7, 10 - 17 - not connected + */ + + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + output-low; /* PCIE = 0, DP = 1 */ + line-name = "sel0"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel1"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + output-high; /* PCIE = 0, USB0 = 1 */ + line-name = "sel2"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + output-high; /* PCIE = 0, SATA = 1 */ + line-name = "sel3"; + }; + }; + + tca6416_u61: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2c-mux@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "maxim,max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "maxim,max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "maxim,max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "maxim,max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "maxim,max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "maxim,max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "maxim,max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "maxim,max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "maxim,max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "maxim,max15303"; + reg = <0x1a>; + }; + max15303@1d { /* u18 */ + compatible = "maxim,max15303"; + reg = <0x1d>; + }; + max15303@20 { /* u8 */ + compatible = "maxim,max15303"; + status = "disabled"; /* unreachable */ + reg = <0x20>; + }; + + max20751@72 { /* u95 */ + compatible = "maxim,max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 */ + compatible = "maxim,max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u69 */ + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 {/* SI5328 - u20 */ + reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + }; + }; + /* 5 - 7 unconnected */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts new file mode 100644 index 000000000000..af4d86882a5c --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU102 RevB + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +#include "zynqmp-zcu102-revA.dts" + +/ { + model = "ZynqMP ZCU102 RevB"; + compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; +}; + +&gem3 { + phy-handle = <&phyc>; + phyc: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; + /* Cleanup from RevA */ + /delete-node/ phy@21; +}; + +/* Fix collision with u61 */ +&i2c0 { + i2c-mux@75 { + i2c@2 { + max15303@1b { /* u8 */ + compatible = "maxim,max15303"; + reg = <0x1b>; + }; + /delete-node/ max15303@20; + }; + }; +}; -- cgit v1.2.3 From 612eac3b72fa00aebb41d1e29cbf00daaffc07ac Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Jan 2018 16:10:05 +0100 Subject: arm64: zynqmp: Add support for Xilinx zcu104-revA Xilinx zcu104 is another customer board. It is sort of zcu102 clone with some differences. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 3 + arch/arm64/boot/dts/xilinx/Makefile | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 195 ++++++++++++++++++++++ 3 files changed, 199 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 2b922ec3c82a..a9ce08a68711 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -26,3 +26,6 @@ Additional compatible strings: "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102" "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102" "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102" + +- Xilinx evaluation board zcu104 + "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 24e3ce801304..1c039e59c7c3 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts new file mode 100644 index 000000000000..d4ad19a38c93 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU104 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include + +/ { + model = "ZynqMP ZCU104 RevA"; + compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ + reg = <0x6c>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ + reg = <0x43>; + }; + irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ + reg = <0x4d>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + tca6416_u97: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - IRPS5401_ALERT_B + * 1 - HDMI_8T49N241_INT_ALM + * 2 - MAX6643_OT_B + * 3 - MAX6643_FANFAIL_B + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - FMC_LPC_PRSNT_M2C_B + * 4, 10 - 17 - not connected + */ + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + /* 3, 6 not connected */ + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + disable-wp; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3 From 9243d4d3908d65fece5153697bda1030c405d094 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 18 Jan 2018 16:34:51 +0100 Subject: arm64: zynqmp: Add support for Xilinx zcu106-revA Xilinx zcu106 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 3 + arch/arm64/boot/dts/xilinx/Makefile | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 522 ++++++++++++++++++++++ 3 files changed, 526 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index a9ce08a68711..8503fabf90ee 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -29,3 +29,6 @@ Additional compatible strings: - Xilinx evaluation board zcu104 "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104" + +- Xilinx evaluation board zcu106 + "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 1c039e59c7c3..922c5da39600 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts new file mode 100644 index 000000000000..668f7f26716a --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU106 + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include +#include + +/ { + model = "ZynqMP ZCU106 RevA"; + compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - SFP_SI5328_INT_ALM + * 1 - HDMI_SI5328_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMC_HPC0_PRSNT_M2C_B + * 11 - FMC_HPC1_PRSNT_M2C_B + * 2-4, 7, 12-17 - not connected + */ + }; + + tca6416_u61: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2c-mux@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "maxim,max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "maxim,max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "maxim,max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "maxim,max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "maxim,max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "maxim,max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "maxim,max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "maxim,max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "maxim,max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "maxim,max15303"; + reg = <0x1a>; + }; + max15303@1b { /* u8 */ + compatible = "maxim,max15303"; + reg = <0x1b>; + }; + max15303@1d { /* u18 */ + compatible = "maxim,max15303"; + reg = <0x1d>; + }; + + max20751@72 { /* u95 */ + compatible = "maxim,max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 */ + compatible = "maxim,max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u69 */ + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 {/* SI5328 - u20 */ + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; /* FAN controller */ + temp@4c {/* lm96163 - u128 */ + compatible = "national,lm96163"; + reg = <0x4c>; + }; + }; + /* 6 - 7 unconnected */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3 From b8aee0229d1e678253e0681b7ed518aa810ad027 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Jan 2018 13:03:56 +0100 Subject: arm64: zynqmp: Add support for Xilinx zcu111-revA Xilinx zcu111 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 3 + arch/arm64/boot/dts/xilinx/Makefile | 1 + arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 444 ++++++++++++++++++++++ 3 files changed, 448 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 8503fabf90ee..c2bc75774010 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -32,3 +32,6 @@ Additional compatible strings: - Xilinx evaluation board zcu106 "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106" + +- Xilinx evaluation board zcu111 + "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 922c5da39600..d15c9dc1d8f2 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts new file mode 100644 index 000000000000..9a9dd6a0142b --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU111 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include +#include + +/ { + model = "ZynqMP ZCU111 RevA"; + compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u22: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - MAX6643_OT_B + * 1 - MAX6643_FANFAIL_B + * 2 - MIO26_PMU_INPUT_LS + * 4 - SFP_SI5382_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMCP_HSPC_PRSNT_M2C_B + * 11 - CLK_SPI_MUX_SEL0 + * 12 - CLK_SPI_MUX_SEL1 + * 16 - IRPS5401_ALERT_B + * 17 - INA226_PMBUS_ALERT + * 3, 7, 13-15 - not connected + */ + }; + + i2c-mux@75 { /* u23 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + ina226@40 { /* u67 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u59 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u61 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u60 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u64 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u69 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + ina226@47 { /* u66 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@48 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + ina226@49 { /* u63 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u3 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u71 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + ina226@4c { /* u77 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + ina226@4d { /* u73 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + ina226@4e { /* u79 */ + compatible = "ti,ina226"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ + reg = <0x43>; + }; + irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ + reg = <0x44>; + }; + irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ + reg = <0x45>; + }; + /* u68 IR38064 +0 */ + /* u70 IR38060 +1 */ + /* u74 IR38060 +2 */ + /* u75 IR38060 +6 */ + /* J19 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@74 { /* u26 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u88 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u46 */ + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 { /* SI5328 - u48 */ + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + sc18is603@2f { /* sc18is602 - u93 */ + compatible = "nxp,sc18is603"; + reg = <0x2f>; + /* 4 gpios for CS not handled by driver */ + /* + * USB2ANY cable or + * LMK04208 - u90 or + * LMX2594 - u102 or + * LMX2594 - u103 or + * LMX2594 - u104 + */ + }; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* FMC connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u27 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; -- cgit v1.2.3 From d665c7435f18871e77395e4575c0f7209c5cdc10 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Jan 2018 13:11:01 +0100 Subject: arm64: zynqmp: Add support for Xilinx zc12XX boards These 3 boards requires minimal support to get Linux up and running. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 9 ++++ arch/arm64/boot/dts/xilinx/Makefile | 3 ++ arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 +++++++++++++++++++++++ arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++++++++++++++++++ arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++++++++++++++++++ 5 files changed, 150 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index c2bc75774010..aceccf2bf43b 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -19,6 +19,15 @@ Required root node properties: Additional compatible strings: +- Xilinx internal board zc1232 + "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232" + +- Xilinx internal board zc1254 + "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254" + +- Xilinx internal board zc1275 + "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275" + - Xilinx 96boards compatible board zcu100 "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index d15c9dc1d8f2..bdda451afaad 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts new file mode 100644 index 000000000000..0f7b4cf6078e --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1232 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP ZC1232 RevA"; + compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts new file mode 100644 index 000000000000..9092828f92ec --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1254 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP ZC1254 RevA"; + compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts new file mode 100644 index 000000000000..4f404c580eec --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1275 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP ZC1275 RevA"; + compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From e2fc49e19898538184191cbf2bc15f240081efad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 19 Jan 2018 13:15:44 +0100 Subject: arm64: zynqmp: Add support for Xilinx zc1751 Xilinx zc1751 boards is used for silicon validation. Board can be extended with 5 FMCs/DCs cards to connect various IPs. Describe all these combinations. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 3 + arch/arm64/boot/dts/xilinx/Makefile | 5 + .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 131 +++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 168 +++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 150 +++++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 178 +++++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 125 +++++++++++++++ 7 files changed, 760 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index aceccf2bf43b..0cf6fb61631d 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -28,6 +28,9 @@ Additional compatible strings: - Xilinx internal board zc1275 "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275" +- Xilinx internal board zc1751 + "xlnx,zynqmp-zc1751" + - Xilinx 96boards compatible board zcu100 "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100" diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index bdda451afaad..c2a0c00272e2 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -3,6 +3,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts new file mode 100644 index 000000000000..9a3e39d1294f --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm015-dc1 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include + +/ { + model = "ZynqMP zc1751-xm015-dc1 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + i2c0 = &i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@55 { + compatible = "atmel,24c64"; /* 24AA64 */ + reg = <0x55>; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* eMMC */ +&sdhci0 { + status = "okay"; + bus-width = <8>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts new file mode 100644 index 000000000000..11cc67184fa9 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm016-dc2 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include + +/ { + model = "ZynqMP zc1751-xm016-dc2 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem2; + i2c0 = &i2c0; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &spi0; + spi1 = &spi1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem2 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@5 { + reg = <5>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + + spi0_flash0: flash0@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf080", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "data"; + reg = <0x0 0x100000>; + }; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + + spi1_flash0: flash0@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <20000000>; + reg = <0>; + + partition@0 { + label = "data"; + reg = <0x0 0x84000>; + }; + }; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts new file mode 100644 index 000000000000..7a49deeae647 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm017-dc3 + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm017-dc3 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { /* VSC8211 */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +/* just eeprom here */ +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +/* eeprom24c02 and SE98A temp chip pca9306 */ +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +&sdhci1 { /* emmc with some settings */ + status = "okay"; +}; + +/* main */ +&uart0 { + status = "okay"; +}; + +/* DB9 */ +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts new file mode 100644 index 000000000000..54c7b4f1d1e4 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm018-dc4 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm018-dc4"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + ethernet1 = &gem1; + ethernet2 = &gem2; + ethernet3 = &gem3; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy7>; +}; + +&gem2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy3>; +}; + +&gem3 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy8>; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts new file mode 100644 index 000000000000..b8b5ff13818d --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm019-dc5 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Siva Durga Prasad + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include + +/ { + model = "ZynqMP zc1751-xm019-dc5 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem1; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci0; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem1 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; + no-1-8-v; +}; + +&ttc0 { + status = "okay"; +}; + +&ttc1 { + status = "okay"; +}; + +&ttc2 { + status = "okay"; +}; + +&ttc3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- cgit v1.2.3 From c7cf9964bafdcd08480bd1d79fb0d624c12a0c78 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Jan 2018 14:25:16 +0100 Subject: arm: zynq: Add Xilinx cc108 board The board contains 7z010 with 512MB memory, ethernet, qspi, uart, usbs and sd. But board is not supporting booting from sd card. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 5 ++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-cc108.dts | 75 ++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-cc108.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 0cf6fb61631d..e8c02eaf6184 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -6,6 +6,11 @@ shall have the following properties. Required root node properties: - compatible = "xlnx,zynq-7000"; +Additional compatible strings: + +- Xilinx internal board cc108 + "xlnx,zynq-cc108" + --------------------------------------------------------------- Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ade7a38543dc..c6810e84d4d7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8750-apc8750.dtb \ wm8850-w70v2.dtb dtb-$(CONFIG_ARCH_ZYNQ) += \ + zynq-cc108.dtb \ zynq-microzed.dtb \ zynq-parallella.dtb \ zynq-zc702.dtb \ diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/zynq-cc108.dts new file mode 100644 index 000000000000..1a0f631c1d8d --- /dev/null +++ b/arch/arm/boot/dts/zynq-cc108.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CC108 board DTS + * + * (C) Copyright 2007-2018 Xilinx, Inc. + * (C) Copyright 2007-2013 Michal Simek + * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd + * + * Michal SIMEK + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci1 { + status = "okay"; + broken-cd ; + wp-inverted ; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; -- cgit v1.2.3 From eac38299d21ed7bf9c774c27aec653bf7067ccfd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Jan 2018 14:58:44 +0100 Subject: arm: zynq: Add support for Xilinx zc770 xm010 dc1 board zc770 is based board which is extended by FMC/DC cards for SoC validation. FMCs/DCs are supposed to cover all SoC configurations. FMC/DC contains ethernet port, can, i2c, sd, qspi, spi, uart and usb. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 3 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zc770-xm010.dts | 95 ++++++++++++++++++++++++ 3 files changed, 99 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-zc770-xm010.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index e8c02eaf6184..3581f2d021a5 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -11,6 +11,9 @@ Additional compatible strings: - Xilinx internal board cc108 "xlnx,zynq-cc108" +- Xilinx internal board zc770 with different FMC cards + "xlnx,zynq-zc770-xm010" + --------------------------------------------------------------- Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c6810e84d4d7..be9ffae2a1ec 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1067,6 +1067,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-parallella.dtb \ zynq-zc702.dtb \ zynq-zc706.dtb \ + zynq-zc770-xm010.dtb \ zynq-zed.dtb \ zynq-zybo.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts new file mode 100644 index 000000000000..6884f1ad66b7 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc770-xm010.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM010 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + serial0 = &uart1; + spi1 = &spi1; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + +}; + +&sdhci0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <1000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "data"; + reg = <0x0 0x100000>; + }; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; -- cgit v1.2.3 From 0d18af0a8f75f635651fb23817bd99318214448e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Jan 2018 15:07:46 +0100 Subject: arm: zynq: Add support for Xilinx zc770 xm011 dc2 board zc770 is based board which is extended by FMC/DC cards for SoC validation. FMCs/DCs are supposed to cover all SoC configurations. FMC/DC contains can, i2c, nand uart, spi and usb. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zc770-xm011.dts | 64 ++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-zc770-xm011.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 3581f2d021a5..c3d08632ce07 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -13,6 +13,7 @@ Additional compatible strings: - Xilinx internal board zc770 with different FMC cards "xlnx,zynq-zc770-xm010" + "xlnx,zynq-zc770-xm011" --------------------------------------------------------------- diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index be9ffae2a1ec..801a46a88e93 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1068,6 +1068,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zc770-xm010.dtb \ + zynq-zc770-xm011.dtb \ zynq-zed.dtb \ zynq-zybo.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts new file mode 100644 index 000000000000..b78883cee96a --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + i2c0 = &i2c1; + serial0 = &uart1; + spi0 = &spi0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + usb_phy1: phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&can0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy1>; +}; -- cgit v1.2.3 From 0d032bb92f8d3843bcc690fd2f5c6534bf2deb1e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Jan 2018 15:12:16 +0100 Subject: arm: zynq: Add support for Xilinx zc770 xm012 dc3 board zc770 is based board which is extended by FMC/DC cards for SoC validation. FMCs/DCs are supposed to cover all SoC configurations. FMC/DC contains can, 2x i2c, nor flash, spi and uart. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zc770-xm012.dts | 64 ++++++++++++++++++++++++ 3 files changed, 66 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-zc770-xm012.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index c3d08632ce07..d1ce0d5c7281 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -14,6 +14,7 @@ Additional compatible strings: - Xilinx internal board zc770 with different FMC cards "xlnx,zynq-zc770-xm010" "xlnx,zynq-zc770-xm011" + "xlnx,zynq-zc770-xm012" --------------------------------------------------------------- diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 801a46a88e93..2c74b935ad1c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1069,6 +1069,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc706.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ + zynq-zc770-xm012.dtb \ zynq-zed.dtb \ zynq-zybo.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/zynq-zc770-xm012.dts new file mode 100644 index 000000000000..c3169d63600d --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc770-xm012.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM012 board DTS + * + * Copyright (C) 2013-2018 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial0 = &uart1; + spi0 = &spi1; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + eeprom0: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + eeprom1: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; +}; + +&uart1 { + status = "okay"; +}; -- cgit v1.2.3 From 73793093ab17121620d7d409ab944060364a4ed3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Jan 2018 15:15:42 +0100 Subject: arm: zynq: Add support for Xilinx zc770 xm013 dc4 board zc770 is based board which is extended by FMC/DC cards for SoC validation. FMCs/DCs are supposed to cover all SoC configurations. FMC/DC contains can, ethernet, i2c, qspi, spi and uart. Signed-off-by: Michal Simek Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/xilinx.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zc770-xm013.dts | 78 ++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 arch/arm/boot/dts/zynq-zc770-xm013.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index d1ce0d5c7281..06e07952d509 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -15,6 +15,7 @@ Additional compatible strings: "xlnx,zynq-zc770-xm010" "xlnx,zynq-zc770-xm011" "xlnx,zynq-zc770-xm012" + "xlnx,zynq-zc770-xm013" --------------------------------------------------------------- diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2c74b935ad1c..d5de3748a80a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1070,6 +1070,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ + zynq-zc770-xm013.dtb \ zynq-zed.dtb \ zynq-zybo.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts new file mode 100644 index 000000000000..8bb66859d774 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZC770 XM013 board DTS + * + * Copyright (C) 2013 Xilinx, Inc. + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + model = "Xilinx Zynq"; + + aliases { + ethernet0 = &gem1; + i2c0 = &i2c1; + serial0 = &uart0; + spi1 = &spi0; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + device_type = "ethernet-phy"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + si570: clock-generator@55 { + #clock-cells = <0>; + compatible = "silabs,si570"; + temperature-stability = <50>; + reg = <0x55>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; +}; + +&spi0 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + eeprom: eeprom@0 { + at25,byte-len = <8192>; + at25,addr-mode = <2>; + at25,page-size = <32>; + + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <1000000>; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From ba5c7a032c2ae66d5467820daab898e5f9048405 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Wed, 28 Feb 2018 11:25:52 +0900 Subject: arm: dts: zynq: Add Digilent Zybo Z7 board This add a DTS for the Digilent Zybo Z7 board. This board is the successor board of Zybo, these are almost the same except for ps-clk-frequency specifications. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Rob Herring Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/arm/xilinx.txt | 3 ++ arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/zynq-zybo-z7.dts | 58 ++++++++++++++++++++++++ 3 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/zynq-zybo-z7.dts (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt index 06e07952d509..b9043bc35c14 100644 --- a/Documentation/devicetree/bindings/arm/xilinx.txt +++ b/Documentation/devicetree/bindings/arm/xilinx.txt @@ -17,6 +17,9 @@ Additional compatible strings: "xlnx,zynq-zc770-xm012" "xlnx,zynq-zc770-xm013" +- Digilent Zybo Z7 board + "digilent,zynq-zybo-z7" + --------------------------------------------------------------- Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d5de3748a80a..7741adcc72f6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1072,7 +1072,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ - zynq-zybo.dtb + zynq-zybo.dtb \ + zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ armada-370-db.dtb \ armada-370-dlink-dns327l.dtb \ diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts new file mode 100644 index 000000000000..1e713dc98920 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq ZYBO Z7 Development Board"; + compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = ""; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio0 46 1>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + device_type = "ethernet-phy"; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; -- cgit v1.2.3 From ecf66ac2a06b16c7de00361c659b123b541e5f6a Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Tue, 16 Jan 2018 16:27:03 +0530 Subject: dt-bindings: phy-qcom-qusb2: Update binding for QUSB2 V2 version Update generic compatible string for QUSB2 V2 PHY. This will allow all targets using QUSB2 V2 use same string. Acked-by: Rob Herring Signed-off-by: Manu Gautam Reviewed-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt index aa0fcb05acb3..42c97426836e 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt @@ -4,7 +4,10 @@ Qualcomm QUSB2 phy controller QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. Required properties: - - compatible: compatible list, contains "qcom,msm8996-qusb2-phy". + - compatible: compatible list, contains + "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, + "qcom,qusb2-v2-phy" for QUSB2 V2 PHY. + - reg: offset and length of the PHY register set. - #phy-cells: must be 0. -- cgit v1.2.3 From 8587b220f05e4f09e6b2b7c0c078b9ee7f8cfd9e Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Tue, 16 Jan 2018 16:27:07 +0530 Subject: dt-bindings: phy-qcom-qmp: Update bindings for QMP V3 USB PHY Update compatible string and clock names for QMP version V3 USB PHY. Acked-by: Rob Herring Signed-off-by: Manu Gautam Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index b6a9f2b92bab..dcf1b8f691d5 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -8,7 +8,8 @@ Required properties: - compatible: compatible list, contains: "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, - "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, + "qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy. - reg: offset and length of register set for PHY's common serdes block. @@ -25,10 +26,13 @@ Required properties: - clock-names: "cfg_ahb" for phy config clock, "aux" for phy aux clock, "ref" for 19.2 MHz ref clk, + "com_aux" for phy common block aux clock, For "qcom,msm8996-qmp-pcie-phy" must contain: "aux", "cfg_ahb", "ref". For "qcom,msm8996-qmp-usb3-phy" must contain: "aux", "cfg_ahb", "ref". + For "qcom,qmp-v3-usb3-phy" must contain: + "aux", "cfg_ahb", "ref", "com_aux". - resets: a list of phandles and reset controller specifier pairs, one for each entry in reset-names. -- cgit v1.2.3 From d2eced94562f9d69705887e497fee0d17c3099eb Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 28 Jan 2018 21:22:41 +0100 Subject: dt-bindings: phy: meson-gxl-usb2-phy: add the reset line and clock The OTG capable USB2 PHY has a reset line (which is shared with other components, such as the USB3 PHY for example) and a clock (which are both part of different registers). Add the properties for the reset line and clocks as optional ones since not all PHYs have them (currently only the OTG capable PHY is known to use these). Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt index a105494a0fc9..b84a02ebffdf 100644 --- a/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt +++ b/Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt @@ -6,6 +6,10 @@ Required properties: - #phys-cells: must be 0 (see phy-bindings.txt in this directory) Optional properties: +- clocks: a phandle to the clock of this PHY +- clock-names: must be "phy" +- resets: a phandle to the reset line of this PHY +- reset-names: must be "phy" - phy-supply: see phy-bindings.txt in this directory -- cgit v1.2.3 From be02637f6b741875aa0779c35f31591738aa2cd9 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 15 Feb 2018 09:44:52 +0200 Subject: dt-bindings: clock: ti: add latching support to mux and divider clocks Certain hardware configurations, like dra76x, have some of the clock registers partitioned in a funky manner that requires the clock control setup to be latched for PRCM to be notified of the change. This is accomplished with a separate control bit under the register. Add support for this clock latching support to divider and mux clocks. Signed-off-by: Tero Kristo Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/clock/ti/divider.txt | 3 +++ Documentation/devicetree/bindings/clock/ti/mux.txt | 3 +++ 2 files changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/divider.txt b/Documentation/devicetree/bindings/clock/ti/divider.txt index 35a6f5c7e5c2..9b13b32974f9 100644 --- a/Documentation/devicetree/bindings/clock/ti/divider.txt +++ b/Documentation/devicetree/bindings/clock/ti/divider.txt @@ -75,6 +75,9 @@ Optional properties: - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0, see [2] - ti,set-rate-parent : clk_set_rate is propagated to parent +- ti,latch-bit : latch the divider value to HW, only needed if the register + access requires this. As an example dra76x DPLL_GMAC H14 divider implements + such behavior. Examples: dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 { diff --git a/Documentation/devicetree/bindings/clock/ti/mux.txt b/Documentation/devicetree/bindings/clock/ti/mux.txt index 2d0d170f8001..eec8994b9be8 100644 --- a/Documentation/devicetree/bindings/clock/ti/mux.txt +++ b/Documentation/devicetree/bindings/clock/ti/mux.txt @@ -48,6 +48,9 @@ Optional properties: zero - ti,set-rate-parent : clk_set_rate is propagated to parent clock, not supported by the composite-mux-clock subtype +- ti,latch-bit : latch the mux value to HW, only needed if the register + access requires this. As an example, dra7x DPLL_GMAC H14 muxing + implements such behavior. Examples: -- cgit v1.2.3 From 63338a38db955cb4e0352c11b78732157c78d30b Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Wed, 7 Mar 2018 08:39:12 +0100 Subject: jailhouse: Provide detection for non-x86 systems Implement jailhouse_paravirt() via device tree probing on architectures != x86. Will be used by the PCI core. Signed-off-by: Jan Kiszka Signed-off-by: Thomas Gleixner Reviewed-by: Juergen Gross Cc: jailhouse-dev@googlegroups.com Cc: Mark Rutland Cc: linux-pci@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: Andy Shevchenko Cc: Rob Herring Cc: Bjorn Helgaas Link: https://lkml.kernel.org/r/dae9fe0c6e63141c28ca90492fa5712b4c33ffb5.1520408357.git.jan.kiszka@siemens.com --- Documentation/devicetree/bindings/jailhouse.txt | 8 ++++++++ arch/x86/include/asm/jailhouse_para.h | 2 +- include/linux/hypervisor.h | 17 +++++++++++++++-- 3 files changed, 24 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/jailhouse.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/jailhouse.txt b/Documentation/devicetree/bindings/jailhouse.txt new file mode 100644 index 000000000000..2901c25ff340 --- /dev/null +++ b/Documentation/devicetree/bindings/jailhouse.txt @@ -0,0 +1,8 @@ +Jailhouse non-root cell device tree bindings +-------------------------------------------- + +When running in a non-root Jailhouse cell (partition), the device tree of this +platform shall have a top-level "hypervisor" node with the following +properties: + +- compatible = "jailhouse,cell" diff --git a/arch/x86/include/asm/jailhouse_para.h b/arch/x86/include/asm/jailhouse_para.h index 875b54376689..b885a961a150 100644 --- a/arch/x86/include/asm/jailhouse_para.h +++ b/arch/x86/include/asm/jailhouse_para.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL2.0 */ /* - * Jailhouse paravirt_ops implementation + * Jailhouse paravirt detection * * Copyright (c) Siemens AG, 2015-2017 * diff --git a/include/linux/hypervisor.h b/include/linux/hypervisor.h index b19563f9a8eb..fc08b433c856 100644 --- a/include/linux/hypervisor.h +++ b/include/linux/hypervisor.h @@ -8,15 +8,28 @@ */ #ifdef CONFIG_X86 + +#include #include + static inline void hypervisor_pin_vcpu(int cpu) { x86_platform.hyper.pin_vcpu(cpu); } -#else + +#else /* !CONFIG_X86 */ + +#include + static inline void hypervisor_pin_vcpu(int cpu) { } -#endif + +static inline bool jailhouse_paravirt(void) +{ + return of_find_compatible_node(NULL, NULL, "jailhouse,cell"); +} + +#endif /* !CONFIG_X86 */ #endif /* __LINUX_HYPEVISOR_H */ -- cgit v1.2.3 From 5be2dae281e8ac9137120fdd08a62f766529e626 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 20 Feb 2018 13:58:09 +0200 Subject: dt-bindings: tegra: Add missing chips and NVIDIA boards Add compatibility strings for supported but undocumented Tegra chips (Tegra114/124/132/210/186/194) and reference boards. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index 7f1411bbabf7..32f62bb7006d 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt @@ -9,6 +9,12 @@ following compatible values: nvidia,tegra20 nvidia,tegra30 + nvidia,tegra114 + nvidia,tegra124 + nvidia,tegra132 + nvidia,tegra210 + nvidia,tegra186 + nvidia,tegra194 Boards ------------------------------------------- @@ -26,8 +32,18 @@ board-specific compatible values: nvidia,cardhu nvidia,cardhu-a02 nvidia,cardhu-a04 + nvidia,dalmore nvidia,harmony + nvidia,jetson-tk1 + nvidia,norrin + nvidia,p2371-0000 + nvidia,p2371-2180 + nvidia,p2571 + nvidia,p2771-0000 + nvidia,p2972-0000 + nvidia,roth nvidia,seaboard + nvidia,tn7 nvidia,ventana toradex,apalis_t30 toradex,apalis_t30-eval -- cgit v1.2.3 From ff0286cbccacc300f4fb47c60a9e5629889dda04 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Tue, 20 Feb 2018 13:58:10 +0200 Subject: dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc The Tegra194 power management controller has one additional register aperture to be specified in the device tree node. Signed-off-by: Mikko Perttunen Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt index 078a58b0302f..5a3bf7c5a7a0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt @@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC) Required properties: - compatible: Should contain one of the following: - "nvidia,tegra186-pmc": for Tegra186 + - "nvidia,tegra194-pmc": for Tegra194 - reg: Must contain an (offset, length) pair of the register set for each entry in reg-names. - reg-names: Must include the following entries: @@ -10,6 +11,7 @@ Required properties: - "wake" - "aotag" - "scratch" + - "misc" (Only for Tegra194) Optional properties: - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal. -- cgit v1.2.3 From a7ca2a709dbce8ef712fc829f686672d0c0256bf Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 22 Feb 2018 15:38:25 +0100 Subject: dt-bindings: phy: Clarify ULPI PHY source clock cdev2 is not actually a clock on Tegra20 but rather a pinmux pad group. PLL_P_OUT4 is the source clock for the ULPI PHY and is output to the DAP_MCLK2 pad. Signed-off-by: Marcel Ziswiler Reviewed-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt index a9aa79fb90ed..1aa6f2674af5 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt @@ -21,7 +21,9 @@ Required properties : - timer: The timeout clock (clk_m). Present if phy_type == utmi. - utmi-pads: The clock needed to access the UTMI pad control registers. Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2). + - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 + with pad group aka "nvidia,pins" cdev2 and pin mux option config aka + "nvidia,function" pllp_out4). Present if phy_type == ulpi, and ULPI link mode is in use. - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. -- cgit v1.2.3 From 2c7305569296719094c9f67481249e2e61dbee6a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Sat, 10 Feb 2018 02:33:22 +0100 Subject: dt/bindings: Fix binding examples for Tegra GMI controller Fix devicetree binding examples for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. While at it also remove double new lines as a left over from Rob's commit 4da722ca19f3 ("dt-bindings: Remove "status" from examples"). Signed-off-by: Marcel Ziswiler Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt index 3e21eb822811..c1e70621799b 100644 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt @@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the controllers with a simple-bus node since they are all connected to the same chip-select (CS4), in this example external address decoding is provided: -gmi@70090000 { +gmi@70009000 { compatible = "nvidia,tegra20-gmi"; reg = <0x70009000 0x1000>; #address-cells = <2>; @@ -84,7 +84,6 @@ gmi@70090000 { reset-names = "gmi"; ranges = <4 0 0xd0000000 0xfffffff>; - bus@4,0 { compatible = "simple-bus"; #address-cells = <1>; @@ -109,7 +108,7 @@ gmi@70090000 { Example with one SJA1000 CAN controller connected to the GMI bus on CS4: -gmi@70090000 { +gmi@70009000 { compatible = "nvidia,tegra20-gmi"; reg = <0x70009000 0x1000>; #address-cells = <2>; @@ -120,7 +119,6 @@ gmi@70090000 { reset-names = "gmi"; ranges = <4 0 0xd0000000 0xfffffff>; - can@4,0 { reg = <4 0 0x100>; nvidia,snor-mux-mode; -- cgit v1.2.3 From d9e575127b4169061d94c9982c4f0e8aae208c78 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 7 Mar 2018 18:46:25 +0100 Subject: ASoC: Use proper DT compatible string for Hardkernel Odroid boards The Odroid boards are manufactured by Hardkernel, not Samsung. New compatible string entries are added, with "hardkernel," instead of "samsung," vendor prefix. Support for the old compatible strings is going to be removed after some time. Signed-off-by: Sylwester Nawrocki Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/samsung,odroid.txt | 6 +++--- sound/soc/samsung/odroid.c | 4 +++- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.txt b/Documentation/devicetree/bindings/sound/samsung,odroid.txt index 625b1b18fd02..f35a2694eb04 100644 --- a/Documentation/devicetree/bindings/sound/samsung,odroid.txt +++ b/Documentation/devicetree/bindings/sound/samsung,odroid.txt @@ -2,8 +2,8 @@ Samsung Exynos Odroid XU3/XU4 audio complex with MAX98090 codec Required properties: - - compatible - "samsung,odroidxu3-audio" - for Odroid XU3 board, - "samsung,odroidxu4-audio" - for Odroid XU4 board + - compatible - "hardkernel,odroid-xu3-audio" - for Odroid XU3 board, + "hardkernel,odroid-xu4-audio" - for Odroid XU4 board - model - the user-visible name of this sound complex - clocks - should contain entries matching clock names in the clock-names property @@ -35,7 +35,7 @@ Required sub-nodes: Example: sound { - compatible = "samsung,odroidxu3-audio"; + compatible = "hardkernel,odroid-xu3-audio"; model = "Odroid-XU3"; samsung,audio-routing = "Headphone Jack", "HPL", diff --git a/sound/soc/samsung/odroid.c b/sound/soc/samsung/odroid.c index 44b6de5a331a..92d750806d1d 100644 --- a/sound/soc/samsung/odroid.c +++ b/sound/soc/samsung/odroid.c @@ -213,8 +213,10 @@ static int odroid_audio_remove(struct platform_device *pdev) } static const struct of_device_id odroid_audio_of_match[] = { + { .compatible = "hardkernel,odroid-xu3-audio" }, + { .compatible = "hardkernel,odroid-xu4-audio" }, { .compatible = "samsung,odroid-xu3-audio" }, - { .compatible = "samsung,odroid-xu4-audio"}, + { .compatible = "samsung,odroid-xu4-audio" }, { }, }; MODULE_DEVICE_TABLE(of, odroid_audio_of_match); -- cgit v1.2.3 From 62f0f079b96d38b6c8a47a52477024b1197652f4 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 7 Mar 2018 11:56:55 -0800 Subject: Input: add RAVE SP Powerbutton driver Add driver that properly handles input event emitted by RAVE SP devices. Reviewed-by: Lucas Stach Signed-off-by: Andrey Smirnov Reviewed-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../bindings/input/zii,rave-sp-pwrbutton.txt | 22 +++++ drivers/input/misc/Kconfig | 9 +++ drivers/input/misc/Makefile | 1 + drivers/input/misc/rave-sp-pwrbutton.c | 94 ++++++++++++++++++++++ 4 files changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt create mode 100644 drivers/input/misc/rave-sp-pwrbutton.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt b/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt new file mode 100644 index 000000000000..43ef770dfeb9 --- /dev/null +++ b/Documentation/devicetree/bindings/input/zii,rave-sp-pwrbutton.txt @@ -0,0 +1,22 @@ +Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings + +RAVE SP input device is a "MFD cell" device corresponding to power +button functionality of RAVE Supervisory Processor. It is expected +that its Device Tree node is specified as a child of the node +corresponding to the parent RAVE SP device (as documented in +Documentation/devicetree/bindings/mfd/zii,rave-sp.txt) + +Required properties: + +- compatible: Should be "zii,rave-sp-pwrbutton" + +Example: + + rave-sp { + compatible = "zii,rave-sp-rdu1"; + current-speed = <38400>; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + } diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 62a1312a7387..6a3c753b093b 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -841,4 +841,13 @@ config INPUT_HISI_POWERKEY To compile this driver as a module, choose M here: the module will be called hisi_powerkey. +config INPUT_RAVE_SP_PWRBUTTON + tristate "RAVE SP Power button Driver" + depends on RAVE_SP_CORE + help + Say Y here if you want to enable power key reporting from RAVE SP + + To compile this driver as a module, choose M here: the + module will be called rave-sp-pwrbutton. + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index a8f61af865aa..8cc58f362bb8 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o obj-$(CONFIG_INPUT_POWERMATE) += powermate.o obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o obj-$(CONFIG_INPUT_PWM_VIBRA) += pwm-vibra.o +obj-$(CONFIG_INPUT_RAVE_SP_PWRBUTTON) += rave-sp-pwrbutton.o obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o obj-$(CONFIG_INPUT_REGULATOR_HAPTIC) += regulator-haptic.o obj-$(CONFIG_INPUT_RETU_PWRBUTTON) += retu-pwrbutton.o diff --git a/drivers/input/misc/rave-sp-pwrbutton.c b/drivers/input/misc/rave-sp-pwrbutton.c new file mode 100644 index 000000000000..bcab3cdb7ebd --- /dev/null +++ b/drivers/input/misc/rave-sp-pwrbutton.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Power Button driver for RAVE SP +// +// Copyright (C) 2017 Zodiac Inflight Innovations +// +// + +#include +#include +#include +#include +#include + +#define RAVE_SP_EVNT_BUTTON_PRESS (RAVE_SP_EVNT_BASE + 0x00) + +struct rave_sp_power_button { + struct input_dev *idev; + struct notifier_block nb; +}; + +static int rave_sp_power_button_event(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct rave_sp_power_button *pb = + container_of(nb, struct rave_sp_power_button, nb); + const u8 event = rave_sp_action_unpack_event(action); + const u8 value = rave_sp_action_unpack_value(action); + struct input_dev *idev = pb->idev; + + if (event == RAVE_SP_EVNT_BUTTON_PRESS) { + input_report_key(idev, KEY_POWER, value); + input_sync(idev); + + return NOTIFY_STOP; + } + + return NOTIFY_DONE; +} + +static int rave_sp_pwrbutton_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rave_sp_power_button *pb; + struct input_dev *idev; + int error; + + pb = devm_kzalloc(dev, sizeof(*pb), GFP_KERNEL); + if (!pb) + return -ENOMEM; + + idev = devm_input_allocate_device(dev); + if (!idev) + return -ENOMEM; + + idev->name = pdev->name; + + input_set_capability(idev, EV_KEY, KEY_POWER); + + error = input_register_device(idev); + if (error) + return error; + + pb->idev = idev; + pb->nb.notifier_call = rave_sp_power_button_event; + pb->nb.priority = 128; + + error = devm_rave_sp_register_event_notifier(dev, &pb->nb); + if (error) + return error; + + return 0; +} + +static const struct of_device_id rave_sp_pwrbutton_of_match[] = { + { .compatible = "zii,rave-sp-pwrbutton" }, + {} +}; + +static struct platform_driver rave_sp_pwrbutton_driver = { + .probe = rave_sp_pwrbutton_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = rave_sp_pwrbutton_of_match, + }, +}; +module_platform_driver(rave_sp_pwrbutton_driver); + +MODULE_DEVICE_TABLE(of, rave_sp_pwrbutton_of_match); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Andrey Vostrikov "); +MODULE_AUTHOR("Nikita Yushchenko "); +MODULE_AUTHOR("Andrey Smirnov "); +MODULE_DESCRIPTION("RAVE SP Power Button driver"); -- cgit v1.2.3 From 612123af86a4470d59bba5986c24eaa48611575f Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 22 Feb 2018 11:42:05 +0530 Subject: dt-bindings: arm: Document kryo385 cpu Document the compatible string for the Kryo385 cpus found in qualcomm SoCs. Signed-off-by: Rajendra Nayak Reviewed-by: Rob Herring Reviewed-by: Douglas Anderson Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index f4a777039f03..8b0328ff951d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -185,6 +185,7 @@ described below. "nvidia,tegra186-denver" "qcom,krait" "qcom,kryo" + "qcom,kryo385" "qcom,scorpion" - enable-method Value type: -- cgit v1.2.3 From d46bd5ce1b3936958e2139830642fda46dd61253 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 22 Feb 2018 11:42:06 +0530 Subject: dt-bindings: qcom: Add SDM845 bindings Add a SoC string 'sdm845' for the qualcomm SDM845 SoC Signed-off-by: Rajendra Nayak Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 0ed4d39d7fe1..ee532e705d6c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074 + sdm845 The 'board' element must be one of the following strings: -- cgit v1.2.3 From f59125248a691dfef62f0450ce7b0238b63b6dbd Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 8 Mar 2018 22:14:32 +0300 Subject: pinctrl: sh-pfc: Add R8A77980 PFC support Add the PFC support for the R8A77980 SoC including pin groups for some on-chip devices such as AVB, CAN-FD, GETHER, [H]SCIF, I2C, INTC-EX, MMC, MSIOF, PWM, and VIN... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Rob Herring Signed-off-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + drivers/pinctrl/sh-pfc/Kconfig | 5 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 2799 ++++++++++++++++++++ drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + 6 files changed, 2813 insertions(+) create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a77980.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index bd5370a71666..892d8fd7b700 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -26,6 +26,7 @@ Required Properties: - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. + - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller. - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 0621cb51c016..c11b789ec583 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -99,6 +99,11 @@ config PINCTRL_PFC_R8A77970 depends on ARCH_R8A77970 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A77980 + def_bool y + depends on ARCH_R8A77980 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A77995 def_bool y depends on ARCH_R8A77995 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 05b4379f0c98..463775f28cf1 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o +obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 7461af941659..74861b7b5b0d 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -569,6 +569,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a77970_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A77980 + { + .compatible = "renesas,pfc-r8a77980", + .data = &r8a77980_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A77995 { .compatible = "renesas,pfc-r8a77995", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c new file mode 100644 index 000000000000..84c8f1c2f1d1 --- /dev/null +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -0,0 +1,2799 @@ +// SPDX-Lincense-Identifier: GPL 2.0 +/* + * R8A77980 processor support - PFC hardware block. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * + * R-Car Gen3 processor support - PFC hardware block. + * + * Copyright (C) 2015 Renesas Electronics Corporation + */ + +#include +#include + +#include "core.h" +#include "sh_pfc.h" + +#define CPU_ALL_PORT(fn, sfx) \ + PORT_GP_22(0, fn, sfx), \ + PORT_GP_28(1, fn, sfx), \ + PORT_GP_30(2, fn, sfx), \ + PORT_GP_17(3, fn, sfx), \ + PORT_GP_25(4, fn, sfx), \ + PORT_GP_15(5, fn, sfx) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20) +#define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16) +#define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12) +#define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8) +#define GPSR0_17 F_(DU_DB7, IP2_7_4) +#define GPSR0_16 F_(DU_DB6, IP2_3_0) +#define GPSR0_15 F_(DU_DB5, IP1_31_28) +#define GPSR0_14 F_(DU_DB4, IP1_27_24) +#define GPSR0_13 F_(DU_DB3, IP1_23_20) +#define GPSR0_12 F_(DU_DB2, IP1_19_16) +#define GPSR0_11 F_(DU_DG7, IP1_15_12) +#define GPSR0_10 F_(DU_DG6, IP1_11_8) +#define GPSR0_9 F_(DU_DG5, IP1_7_4) +#define GPSR0_8 F_(DU_DG4, IP1_3_0) +#define GPSR0_7 F_(DU_DG3, IP0_31_28) +#define GPSR0_6 F_(DU_DG2, IP0_27_24) +#define GPSR0_5 F_(DU_DR7, IP0_23_20) +#define GPSR0_4 F_(DU_DR6, IP0_19_16) +#define GPSR0_3 F_(DU_DR5, IP0_15_12) +#define GPSR0_2 F_(DU_DR4, IP0_11_8) +#define GPSR0_1 F_(DU_DR3, IP0_7_4) +#define GPSR0_0 F_(DU_DR2, IP0_3_0) + +/* GPSR1 */ +#define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28) +#define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24) +#define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20) +#define GPSR1_24 F_(CANFD1_RX, IP8_19_16) +#define GPSR1_23 F_(CANFD1_TX, IP8_15_12) +#define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8) +#define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4) +#define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0) +#define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28) +#define GPSR1_18 FM(AVB_LINK) +#define GPSR1_17 FM(AVB_PHY_INT) +#define GPSR1_16 FM(AVB_MAGIC) +#define GPSR1_15 FM(AVB_MDC) +#define GPSR1_14 FM(AVB_MDIO) +#define GPSR1_13 FM(AVB_TXCREFCLK) +#define GPSR1_12 FM(AVB_TD3) +#define GPSR1_11 FM(AVB_TD2) +#define GPSR1_10 FM(AVB_TD1) +#define GPSR1_9 FM(AVB_TD0) +#define GPSR1_8 FM(AVB_TXC) +#define GPSR1_7 FM(AVB_TX_CTL) +#define GPSR1_6 FM(AVB_RD3) +#define GPSR1_5 FM(AVB_RD2) +#define GPSR1_4 FM(AVB_RD1) +#define GPSR1_3 FM(AVB_RD0) +#define GPSR1_2 FM(AVB_RXC) +#define GPSR1_1 FM(AVB_RX_CTL) +#define GPSR1_0 F_(IRQ0, IP2_27_24) + +/* GPSR2 */ +#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) +#define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) +#define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) +#define GPSR2_26 F_(SDA3, IP10_7_4) +#define GPSR2_25 F_(SCL3, IP10_3_0) +#define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28) +#define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24) +#define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20) +#define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16) +#define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12) +#define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8) +#define GPSR2_18 F_(IRQ5, IP9_7_4) +#define GPSR2_17 F_(IRQ4, IP9_3_0) +#define GPSR2_16 F_(VI0_FIELD, IP4_31_28) +#define GPSR2_15 F_(VI0_DATA11, IP4_27_24) +#define GPSR2_14 F_(VI0_DATA10, IP4_23_20) +#define GPSR2_13 F_(VI0_DATA9, IP4_19_16) +#define GPSR2_12 F_(VI0_DATA8, IP4_15_12) +#define GPSR2_11 F_(VI0_DATA7, IP4_11_8) +#define GPSR2_10 F_(VI0_DATA6, IP4_7_4) +#define GPSR2_9 F_(VI0_DATA5, IP4_3_0) +#define GPSR2_8 F_(VI0_DATA4, IP3_31_28) +#define GPSR2_7 F_(VI0_DATA3, IP3_27_24) +#define GPSR2_6 F_(VI0_DATA2, IP3_23_20) +#define GPSR2_5 F_(VI0_DATA1, IP3_19_16) +#define GPSR2_4 F_(VI0_DATA0, IP3_15_12) +#define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8) +#define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4) +#define GPSR2_1 F_(VI0_CLKENB, IP3_3_0) +#define GPSR2_0 F_(VI0_CLK, IP2_31_28) + +/* GPSR3 */ +#define GPSR3_16 F_(VI1_FIELD, IP7_3_0) +#define GPSR3_15 F_(VI1_DATA11, IP6_31_28) +#define GPSR3_14 F_(VI1_DATA10, IP6_27_24) +#define GPSR3_13 F_(VI1_DATA9, IP6_23_20) +#define GPSR3_12 F_(VI1_DATA8, IP6_19_16) +#define GPSR3_11 F_(VI1_DATA7, IP6_15_12) +#define GPSR3_10 F_(VI1_DATA6, IP6_11_8) +#define GPSR3_9 F_(VI1_DATA5, IP6_7_4) +#define GPSR3_8 F_(VI1_DATA4, IP6_3_0) +#define GPSR3_7 F_(VI1_DATA3, IP5_31_28) +#define GPSR3_6 F_(VI1_DATA2, IP5_27_24) +#define GPSR3_5 F_(VI1_DATA1, IP5_23_20) +#define GPSR3_4 F_(VI1_DATA0, IP5_19_16) +#define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12) +#define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8) +#define GPSR3_1 F_(VI1_CLKENB, IP5_7_4) +#define GPSR3_0 F_(VI1_CLK, IP5_3_0) + +/* GPSR4 */ +#define GPSR4_24 FM(GETHER_LINK_A) +#define GPSR4_23 FM(GETHER_PHY_INT_A) +#define GPSR4_22 FM(GETHER_MAGIC) +#define GPSR4_21 FM(GETHER_MDC_A) +#define GPSR4_20 FM(GETHER_MDIO_A) +#define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA) +#define GPSR4_18 FM(GETHER_TXCREFCLK) +#define GPSR4_17 FM(GETHER_TD3) +#define GPSR4_16 FM(GETHER_TD2) +#define GPSR4_15 FM(GETHER_TD1) +#define GPSR4_14 FM(GETHER_TD0) +#define GPSR4_13 FM(GETHER_TXC) +#define GPSR4_12 FM(GETHER_TX_CTL) +#define GPSR4_11 FM(GETHER_RD3) +#define GPSR4_10 FM(GETHER_RD2) +#define GPSR4_9 FM(GETHER_RD1) +#define GPSR4_8 FM(GETHER_RD0) +#define GPSR4_7 FM(GETHER_RXC) +#define GPSR4_6 FM(GETHER_RX_CTL) +#define GPSR4_5 F_(SDA2, IP7_27_24) +#define GPSR4_4 F_(SCL2, IP7_23_20) +#define GPSR4_3 F_(SDA1, IP7_19_16) +#define GPSR4_2 F_(SCL1, IP7_15_12) +#define GPSR4_1 F_(SDA0, IP7_11_8) +#define GPSR4_0 F_(SCL0, IP7_7_4) + +/* GPSR5 */ +#define GPSR5_14 FM(RPC_INT_N) +#define GPSR5_13 FM(RPC_WP_N) +#define GPSR5_12 FM(RPC_RESET_N) +#define GPSR5_11 FM(QSPI1_SSL) +#define GPSR5_10 FM(QSPI1_IO3) +#define GPSR5_9 FM(QSPI1_IO2) +#define GPSR5_8 FM(QSPI1_MISO_IO1) +#define GPSR5_7 FM(QSPI1_MOSI_IO0) +#define GPSR5_6 FM(QSPI1_SPCLK) +#define GPSR5_5 FM(QSPI0_SSL) +#define GPSR5_4 FM(QSPI0_IO3) +#define GPSR5_3 FM(QSPI0_IO2) +#define GPSR5_2 FM(QSPI0_MISO_IO1) +#define GPSR5_1 FM(QSPI0_MOSI_IO0) +#define GPSR5_0 FM(QSPI0_SPCLK) + + +/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ +#define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_19_16 FM(DU_DR6) FM(RTS4_N_TANS) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ +\ + GPSR2_29 \ + GPSR2_28 \ + GPSR1_27 GPSR2_27 \ + GPSR1_26 GPSR2_26 \ + GPSR1_25 GPSR2_25 \ + GPSR1_24 GPSR2_24 GPSR4_24 \ + GPSR1_23 GPSR2_23 GPSR4_23 \ + GPSR1_22 GPSR2_22 GPSR4_22 \ +GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \ +GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \ +GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \ +GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \ +GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \ +GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 + +#define PINMUX_IPSR \ +\ +FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ +FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ +FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ +FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ +FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ +FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ +FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ +FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ +\ +FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ +FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ +FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ +FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ +FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ +FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ +FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ +FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ +\ +FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \ +FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \ +FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \ +FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \ +FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \ +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 + +/* MOD_SEL0 */ /* 0 */ /* 1 */ +#define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) +#define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1) +#define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) +#define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1) +#define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1) +#define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1) +#define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1) +#define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1) +#define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1) +#define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) +#define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL0_11 \ +MOD_SEL0_10 \ +MOD_SEL0_9 \ +MOD_SEL0_8 \ +MOD_SEL0_7 \ +MOD_SEL0_6 \ +MOD_SEL0_5 \ +MOD_SEL0_4 \ +MOD_SEL0_2 \ +MOD_SEL0_1 \ +MOD_SEL0_0 + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(AVB_RX_CTL), + PINMUX_SINGLE(AVB_RXC), + PINMUX_SINGLE(AVB_RD0), + PINMUX_SINGLE(AVB_RD1), + PINMUX_SINGLE(AVB_RD2), + PINMUX_SINGLE(AVB_RD3), + PINMUX_SINGLE(AVB_TX_CTL), + PINMUX_SINGLE(AVB_TXC), + PINMUX_SINGLE(AVB_TD0), + PINMUX_SINGLE(AVB_TD1), + PINMUX_SINGLE(AVB_TD2), + PINMUX_SINGLE(AVB_TD3), + PINMUX_SINGLE(AVB_TXCREFCLK), + PINMUX_SINGLE(AVB_MDIO), + PINMUX_SINGLE(AVB_MDC), + PINMUX_SINGLE(AVB_MAGIC), + PINMUX_SINGLE(AVB_PHY_INT), + PINMUX_SINGLE(AVB_LINK), + + PINMUX_SINGLE(GETHER_RX_CTL), + PINMUX_SINGLE(GETHER_RXC), + PINMUX_SINGLE(GETHER_RD0), + PINMUX_SINGLE(GETHER_RD1), + PINMUX_SINGLE(GETHER_RD2), + PINMUX_SINGLE(GETHER_RD3), + PINMUX_SINGLE(GETHER_TX_CTL), + PINMUX_SINGLE(GETHER_TXC), + PINMUX_SINGLE(GETHER_TD0), + PINMUX_SINGLE(GETHER_TD1), + PINMUX_SINGLE(GETHER_TD2), + PINMUX_SINGLE(GETHER_TD3), + PINMUX_SINGLE(GETHER_TXCREFCLK), + PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA), + PINMUX_SINGLE(GETHER_MDIO_A), + PINMUX_SINGLE(GETHER_MDC_A), + PINMUX_SINGLE(GETHER_MAGIC), + PINMUX_SINGLE(GETHER_PHY_INT_A), + PINMUX_SINGLE(GETHER_LINK_A), + + PINMUX_SINGLE(QSPI0_SPCLK), + PINMUX_SINGLE(QSPI0_MOSI_IO0), + PINMUX_SINGLE(QSPI0_MISO_IO1), + PINMUX_SINGLE(QSPI0_IO2), + PINMUX_SINGLE(QSPI0_IO3), + PINMUX_SINGLE(QSPI0_SSL), + PINMUX_SINGLE(QSPI1_SPCLK), + PINMUX_SINGLE(QSPI1_MOSI_IO0), + PINMUX_SINGLE(QSPI1_MISO_IO1), + PINMUX_SINGLE(QSPI1_IO2), + PINMUX_SINGLE(QSPI1_IO3), + PINMUX_SINGLE(QSPI1_SSL), + PINMUX_SINGLE(RPC_RESET_N), + PINMUX_SINGLE(RPC_WP_N), + PINMUX_SINGLE(RPC_INT_N), + + /* IPSR0 */ + PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2), + PINMUX_IPSR_GPSR(IP0_3_0, SCK4), + PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV), + PINMUX_IPSR_GPSR(IP0_3_0, A0), + + PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3), + PINMUX_IPSR_GPSR(IP0_7_4, RX4), + PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER), + PINMUX_IPSR_GPSR(IP0_7_4, A1), + + PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4), + PINMUX_IPSR_GPSR(IP0_11_8, TX4), + PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0), + PINMUX_IPSR_GPSR(IP0_11_8, A2), + + PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5), + PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N), + PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1), + PINMUX_IPSR_GPSR(IP0_15_12, A3), + + PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6), + PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N_TANS), + PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN), + PINMUX_IPSR_GPSR(IP0_19_16, A4), + + PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7), + PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0), + PINMUX_IPSR_GPSR(IP0_23_20, A5), + + PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2), + PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1), + PINMUX_IPSR_GPSR(IP0_27_24, A6), + + PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3), + PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT), + PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK), + PINMUX_IPSR_GPSR(IP0_31_28, A7), + PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4), + PINMUX_IPSR_GPSR(IP1_3_0, SCL5), + PINMUX_IPSR_GPSR(IP1_3_0, A8), + + PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5), + PINMUX_IPSR_GPSR(IP1_7_4, SDA5), + PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1), + PINMUX_IPSR_GPSR(IP1_7_4, A9), + + PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6), + PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1), + PINMUX_IPSR_GPSR(IP1_11_8, A10), + + PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7), + PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP1_15_12, A11), + + PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2), + PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP1_19_16, A12), + PINMUX_IPSR_GPSR(IP1_19_16, IRQ1), + + PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3), + PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP1_23_20, A13), + PINMUX_IPSR_GPSR(IP1_23_20, IRQ2), + + PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4), + PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0), + PINMUX_IPSR_GPSR(IP1_27_24, A14), + PINMUX_IPSR_GPSR(IP1_27_24, IRQ3), + + PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5), + PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0), + PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0), + PINMUX_IPSR_GPSR(IP1_31_28, A15), + + /* IPSR2 */ + PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6), + PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD), + PINMUX_IPSR_GPSR(IP2_3_0, A16), + + PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7), + PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD), + PINMUX_IPSR_GPSR(IP2_7_4, A17), + + PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT), + PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1), + PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1), + PINMUX_IPSR_GPSR(IP2_11_8, A18), + + PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2), + PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1), + PINMUX_IPSR_GPSR(IP2_15_12, A19), + PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N), + + PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK), + PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N), + + PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), + + PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), + PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT), + + PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), + PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), + PINMUX_IPSR_GPSR(IP2_31_28, SCK3), + PINMUX_IPSR_GPSR(IP2_31_28, HSCK3), + + /* IPSR3 */ + PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB), + PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD), + PINMUX_IPSR_GPSR(IP3_3_0, RX3), + PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N), + PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N), + + PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N), + PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), + PINMUX_IPSR_GPSR(IP3_7_4, TX3), + PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N), + + PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N), + PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC), + PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N), + PINMUX_IPSR_GPSR(IP3_11_8, HTX3), + + PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), + PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), + PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP3_15_12, HRX3), + + PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), + PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2), + PINMUX_IPSR_GPSR(IP3_19_16, SCK1), + PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0), + + PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2), + PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS), + + PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3), + PINMUX_IPSR_GPSR(IP3_27_24, HSCK1), + + PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4), + PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N), + PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0), + + /* IPSR4 */ + PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5), + PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N), + PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0), + + PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6), + PINMUX_IPSR_GPSR(IP4_7_4, HTX1), + PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N), + + PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), + PINMUX_IPSR_GPSR(IP4_11_8, HRX1), + PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), + + PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), + PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), + + PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9), + PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N), + PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0), + + PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10), + PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N), + PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0), + + PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11), + PINMUX_IPSR_GPSR(IP4_27_24, HTX2), + PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0), + + PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD), + PINMUX_IPSR_GPSR(IP4_31_28, HRX2), + PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0), + PINMUX_IPSR_GPSR(IP4_31_28, CS1_N), + + /* IPSR5 */ + PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK), + PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP5_3_0, CS0_N), + + PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB), + PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP5_7_4, D0), + + PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N), + PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK), + PINMUX_IPSR_GPSR(IP5_11_8, D1), + + PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N), + PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP5_15_12, D2), + + PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0), + PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP5_19_16, D3), + PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP), + + PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1), + PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP5_23_20, D4), + PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD), + + PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2), + PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1), + PINMUX_IPSR_GPSR(IP5_27_24, D5), + PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS), + + PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3), + PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1), + PINMUX_IPSR_GPSR(IP5_31_28, D6), + PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD), + + /* IPSR6 */ + PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4), + PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1), + PINMUX_IPSR_GPSR(IP6_3_0, D7), + PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0), + + PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5), + PINMUX_IPSR_GPSR(IP6_7_4, D8), + PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1), + + PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6), + PINMUX_IPSR_GPSR(IP6_11_8, D9), + PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2), + + PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7), + PINMUX_IPSR_GPSR(IP6_15_12, D10), + PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3), + + PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8), + PINMUX_IPSR_GPSR(IP6_19_16, D11), + PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK), + + PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), + PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0), + PINMUX_IPSR_GPSR(IP6_23_20, D12), + PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4), + + PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10), + PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0), + PINMUX_IPSR_GPSR(IP6_27_24, D13), + PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5), + + PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11), + PINMUX_IPSR_GPSR(IP6_31_28, SCL4), + PINMUX_IPSR_GPSR(IP6_31_28, D14), + PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6), + + /* IPSR7 */ + PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD), + PINMUX_IPSR_GPSR(IP7_3_0, SDA4), + PINMUX_IPSR_GPSR(IP7_3_0, D15), + PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7), + + PINMUX_IPSR_GPSR(IP7_7_4, SCL0), + PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT), + + PINMUX_IPSR_GPSR(IP7_11_8, SDA0), + PINMUX_IPSR_GPSR(IP7_11_8, BS_N), + PINMUX_IPSR_GPSR(IP7_11_8, SCK0), + PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1), + + PINMUX_IPSR_GPSR(IP7_15_12, SCL1), + PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2), + PINMUX_IPSR_GPSR(IP7_15_12, RD_N), + PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N), + PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B), + + PINMUX_IPSR_GPSR(IP7_19_16, SDA1), + PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), + PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), + PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), + PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1), + + PINMUX_IPSR_GPSR(IP7_23_20, SCL2), + PINMUX_IPSR_GPSR(IP7_23_20, WE1_N), + PINMUX_IPSR_GPSR(IP7_23_20, RX0), + PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1), + + PINMUX_IPSR_GPSR(IP7_27_24, SDA2), + PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0), + PINMUX_IPSR_GPSR(IP7_27_24, TX0), + PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1), + + PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH), + PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0), + + /* IPSR8 */ + PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE), + PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1), + + PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0), + PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA), + PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1), + PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP), + + PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0), + PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR), + PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1), + PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE), + + PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX), + PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB), + PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1), + PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1), + + PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX), + PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR), + PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1), + PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1), + PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1), + + PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0), + PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR), + PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1), + PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1), + + PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN), + PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN), + + PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT), + PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT), + + /* IPSR9 */ + PINMUX_IPSR_GPSR(IP9_3_0, IRQ4), + PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12), + + PINMUX_IPSR_GPSR(IP9_7_4, IRQ5), + PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13), + + PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0), + PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14), + + PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1), + PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15), + + PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0), + PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16), + + PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1), + PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17), + + PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0), + PINMUX_IPSR_GPSR(IP9_27_24, TCLK3), + PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18), + + PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1), + PINMUX_IPSR_GPSR(IP9_31_28, TCLK4), + PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19), + + /* IPSR10 */ + PINMUX_IPSR_GPSR(IP10_3_0, SCL3), + PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20), + + PINMUX_IPSR_GPSR(IP10_7_4, SDA3), + PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21), + + PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N), + PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22), + + PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N), + PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23), + + PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - AVB -------------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + /* AVB_LINK */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + /* AVB_MAGIC */ + RCAR_GP_PIN(1, 16), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + /* AVB_PHY_INT */ + RCAR_GP_PIN(1, 17), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdio_pins[] = { + /* AVB_MDC, AVB_MDIO */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int avb_mdio_mux[] = { + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_rgmii_pins[] = { + /* + * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3, + * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3, + */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), +}; +static const unsigned int avb_rgmii_mux[] = { + AVB_TX_CTL_MARK, AVB_TXC_MARK, + AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, + AVB_RX_CTL_MARK, AVB_RXC_MARK, + AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, +}; +static const unsigned int avb_txcrefclk_pins[] = { + /* AVB_TXCREFCLK */ + RCAR_GP_PIN(1, 13), +}; +static const unsigned int avb_txcrefclk_mux[] = { + AVB_TXCREFCLK_MARK, +}; +static const unsigned int avb_avtp_pps_pins[] = { + /* AVB_AVTP_PPS */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int avb_avtp_pps_mux[] = { + AVB_AVTP_PPS_MARK, +}; +static const unsigned int avb_avtp_capture_pins[] = { + /* AVB_AVTP_CAPTURE */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int avb_avtp_capture_mux[] = { + AVB_AVTP_CAPTURE_MARK, +}; +static const unsigned int avb_avtp_match_pins[] = { + /* AVB_AVTP_MATCH */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int avb_avtp_match_mux[] = { + AVB_AVTP_MATCH_MARK, +}; + +/* - CANFD0 ----------------------------------------------------------------- */ +static const unsigned int canfd0_data_a_pins[] = { + /* CANFD0_TX, CANFD0_RX */ + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), +}; +static const unsigned int canfd0_data_a_mux[] = { + CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, +}; +static const unsigned int canfd0_data_b_pins[] = { + /* CANFD0_TX, CANFD0_RX */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int canfd0_data_b_mux[] = { + CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, +}; + +/* - CANFD1 ----------------------------------------------------------------- */ +static const unsigned int canfd1_data_pins[] = { + /* CANFD1_TX, CANFD1_RX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int canfd1_data_mux[] = { + CANFD1_TX_MARK, CANFD1_RX_MARK, +}; + +/* - CANFD Clock ------------------------------------------------------------ */ +static const unsigned int canfd_clk_a_pins[] = { + /* CANFD_CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int canfd_clk_a_mux[] = { + CANFD_CLK_A_MARK, +}; +static const unsigned int canfd_clk_b_pins[] = { + /* CANFD_CLK */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int canfd_clk_b_mux[] = { + CANFD_CLK_B_MARK, +}; + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), +}; +static const unsigned int du_rgb666_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, + DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, + DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, + DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_rgb888_pins[] = { + /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0), + RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21), + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12), + RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), +}; +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, + DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK, + DU_DR1_MARK, DU_DR0_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, + DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK, + DU_DG1_MARK, DU_DG0_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, + DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK, + DU_DB1_MARK, DU_DB0_MARK, +}; +static const unsigned int du_clk_out_pins[] = { + /* DU_DOTCLKOUT */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int du_clk_out_mux[] = { + DU_DOTCLKOUT_MARK, +}; +static const unsigned int du_sync_pins[] = { + /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */ + RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), +}; +static const unsigned int du_sync_mux[] = { + DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK, +}; +static const unsigned int du_oddf_pins[] = { + /* DU_EXODDF/DU_ODDF/DISP/CDE */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int du_oddf_mux[] = { + DU_EXODDF_DU_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du_cde_pins[] = { + /* DU_CDE */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int du_cde_mux[] = { + DU_CDE_MARK, +}; +static const unsigned int du_disp_pins[] = { + /* DU_DISP */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int du_disp_mux[] = { + DU_DISP_MARK, +}; + +/* - GETHER ----------------------------------------------------------------- */ +static const unsigned int gether_link_a_pins[] = { + /* GETHER_LINK */ + RCAR_GP_PIN(4, 24), +}; +static const unsigned int gether_link_a_mux[] = { + GETHER_LINK_A_MARK, +}; +static const unsigned int gether_phy_int_a_pins[] = { + /* GETHER_PHY_INT */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int gether_phy_int_a_mux[] = { + GETHER_PHY_INT_A_MARK, +}; +static const unsigned int gether_mdio_a_pins[] = { + /* GETHER_MDC, GETHER_MDIO */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), +}; +static const unsigned int gether_mdio_a_mux[] = { + GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK, +}; +static const unsigned int gether_link_b_pins[] = { + /* GETHER_LINK */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int gether_link_b_mux[] = { + GETHER_LINK_B_MARK, +}; +static const unsigned int gether_phy_int_b_pins[] = { + /* GETHER_PHY_INT */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int gether_phy_int_b_mux[] = { + GETHER_PHY_INT_B_MARK, +}; +static const unsigned int gether_mdio_b_mux[] = { + GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK, +}; +static const unsigned int gether_mdio_b_pins[] = { + /* GETHER_MDC, GETHER_MDIO */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int gether_magic_pins[] = { + /* GETHER_MAGIC */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int gether_magic_mux[] = { + GETHER_MAGIC_MARK, +}; +static const unsigned int gether_rgmii_pins[] = { + /* + * GETHER_TX_CTL, GETHER_TXC, + * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3, + * GETHER_RX_CTL, GETHER_RXC, + * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3, + */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), +}; +static const unsigned int gether_rgmii_mux[] = { + GETHER_TX_CTL_MARK, GETHER_TXC_MARK, + GETHER_TD0_MARK, GETHER_TD1_MARK, + GETHER_TD2_MARK, GETHER_TD3_MARK, + GETHER_RX_CTL_MARK, GETHER_RXC_MARK, + GETHER_RD0_MARK, AVB_RD1_MARK, + GETHER_RD2_MARK, AVB_RD3_MARK, +}; +static const unsigned int gether_txcrefclk_pins[] = { + /* GETHER_TXCREFCLK */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int gether_txcrefclk_mux[] = { + GETHER_TXCREFCLK_MARK, +}; +static const unsigned int gether_txcrefclk_mega_pins[] = { + /* GETHER_TXCREFCLK_MEGA */ + RCAR_GP_PIN(4, 19), +}; +static const unsigned int gether_txcrefclk_mega_mux[] = { + GETHER_TXCREFCLK_MEGA_MARK, +}; +static const unsigned int gether_rmii_pins[] = { + /* + * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER, + * GETHER_RMII_RXD0, GETHER_RMII_RXD1, + * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0, + * GETHER_RMII_TXD1, GETHER_RMII_REFCLK + */ + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int gether_rmii_mux[] = { + GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK, + GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK, + GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK, + GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK, +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_a_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15), +}; +static const unsigned int hscif0_data_a_mux[] = { + HRX0_A_MARK, HTX0_A_MARK, +}; +static const unsigned int hscif0_clk_a_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int hscif0_clk_a_mux[] = { + HSCK0_A_MARK, +}; +static const unsigned int hscif0_ctrl_a_pins[] = { + /* HRTS0#, HCTS0# */ + RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), +}; +static const unsigned int hscif0_ctrl_a_mux[] = { + HRTS0_N_A_MARK, HCTS0_N_A_MARK, +}; +static const unsigned int hscif0_data_b_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; +static const unsigned int hscif0_clk_b_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(4, 1), +}; +static const unsigned int hscif0_clk_b_mux[] = { + HSCK0_B_MARK, +}; +static const unsigned int hscif0_ctrl_b_pins[] = { + /* HRTS0#, HCTS0# */ + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), +}; +static const unsigned int hscif0_ctrl_b_mux[] = { + HRTS0_N_B_MARK, HCTS0_N_B_MARK, +}; + +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* HRX1, HTX1 */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* HSCK1 */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* HRTS1#, HCTS1# */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; + +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* HRX2, HTX2 */ + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* HSCK2 */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* HRTS2#, HCTS2# */ + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; + +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_pins[] = { + /* HRX3, HTX3 */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), +}; +static const unsigned int hscif3_data_mux[] = { + HRX3_MARK, HTX3_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* HSCK3 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* HRTS3#, HCTS3# */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SDA0, SCL0 */ + RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0), +}; +static const unsigned int i2c0_mux[] = { + SDA0_MARK, SCL0_MARK, +}; + +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SDA1, SCL1 */ + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), +}; +static const unsigned int i2c1_mux[] = { + SDA1_MARK, SCL1_MARK, +}; + +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SDA2, SCL2 */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4), +}; +static const unsigned int i2c2_mux[] = { + SDA2_MARK, SCL2_MARK, +}; + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SDA3, SCL3 */ + RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), +}; +static const unsigned int i2c3_mux[] = { + SDA3_MARK, SCL3_MARK, +}; + +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SDA4, SCL4 */ + RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15), +}; +static const unsigned int i2c4_mux[] = { + SDA4_MARK, SCL4_MARK, +}; + +/* - I2C5 ------------------------------------------------------------------- */ +static const unsigned int i2c5_pins[] = { + /* SDA5, SCL5 */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), +}; +static const unsigned int i2c5_mux[] = { + SDA5_MARK, SCL5_MARK, +}; + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 17), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 18), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data1_pins[] = { + /* MMC_D0 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* MMC_D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, + MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* MMC_D[0:7] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, + MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* MMC_CLK, MMC_CMD */ + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* MMC_CD */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int mmc_cd_mux[] = { + MMC_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* MMC_WP */ + RCAR_GP_PIN(3, 4), +}; +static const unsigned int mmc_wp_mux[] = { + MMC_WP_MARK, +}; +static const unsigned int mmc_ds_pins[] = { + /* MMC_DS */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int mmc_ds_mux[] = { + MMC_DS_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* MSIOF0_SCK */ + RCAR_GP_PIN(2, 21), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* MSIOF0_SYNC */ + RCAR_GP_PIN(2, 22), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* MSIOF0_SS1 */ + RCAR_GP_PIN(2, 23), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* MSIOF0_SS2 */ + RCAR_GP_PIN(2, 24), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* MSIOF0_TXD */ + RCAR_GP_PIN(2, 20), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* MSIOF0_RXD */ + RCAR_GP_PIN(2, 19), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* MSIOF1_SCK */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* MSIOF1_SYNC */ + RCAR_GP_PIN(3, 3), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* MSIOF1_SS1 */ + RCAR_GP_PIN(3, 4), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* MSIOF1_SS2 */ + RCAR_GP_PIN(3, 5), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* MSIOF1_TXD */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* MSIOF1_RXD */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* MSIOF2_SCK */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* MSIOF2_SYNC */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* MSIOF2_SS1 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* MSIOF2_SS2 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* MSIOF2_TXD */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_rxd_pins[] = { + /* MSIOF2_RXD */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int msiof2_rxd_mux[] = { + MSIOF2_RXD_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* MSIOF3_SCK */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* MSIOF3_SYNC */ + RCAR_GP_PIN(0, 21), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* MSIOF3_SS1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* MSIOF3_SS2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* MSIOF3_TXD */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int msiof3_txd_mux[] = { + MSIOF3_TXD_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* MSIOF3_RXD */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int msiof3_rxd_mux[] = { + MSIOF3_RXD_MARK, +}; + +/* - PWM0 ------------------------------------------------------------------- */ +static const unsigned int pwm0_a_pins[] = { + /* PWM0 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int pwm0_a_mux[] = { + PWM0_A_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + /* PWM0 */ + RCAR_GP_PIN(1, 21), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; + +/* - PWM1 ------------------------------------------------------------------- */ +static const unsigned int pwm1_a_pins[] = { + /* PWM1 */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + /* PWM1 */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; + +/* - PWM2 ------------------------------------------------------------------- */ +static const unsigned int pwm2_a_pins[] = { + /* PWM2 */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + /* PWM2 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; + +/* - PWM3 ------------------------------------------------------------------- */ +static const unsigned int pwm3_a_pins[] = { + /* PWM3 */ + RCAR_GP_PIN(2, 15), +}; +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; +static const unsigned int pwm3_b_pins[] = { + /* PWM3 */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; + +/* - PWM4 ------------------------------------------------------------------- */ +static const unsigned int pwm4_a_pins[] = { + /* PWM4 */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int pwm4_a_mux[] = { + PWM4_A_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + /* PWM4 */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX0, TX0 */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK0 */ + RCAR_GP_PIN(4, 1), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS0#/TANS, CTS0# */ + RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_TANS_MARK, CTS0_N_MARK, +}; + +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_a_pins[] = { + /* RX1, TX1 */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), +}; +static const unsigned int scif1_data_a_mux[] = { + RX1_A_MARK, TX1_A_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK1 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS1#/TANS, CTS1# */ + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_TANS_MARK, CTS1_N_MARK, +}; +static const unsigned int scif1_data_b_pins[] = { + /* RX1, TX1 */ + RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23), +}; +static const unsigned int scif1_data_b_mux[] = { + RX1_B_MARK, TX1_B_MARK, +}; + +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX3, TX3 */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK3 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS3#/TANS, CTS3# */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_TANS_MARK, CTS3_N_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX4, TX4 */ + RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK4 */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_ctrl_pins[] = { + /* RTS4#/TANS, CTS4# */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), +}; +static const unsigned int scif4_ctrl_mux[] = { + RTS4_N_TANS_MARK, CTS4_N_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_a_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif_clk_a_mux[] = { + SCIF_CLK_A_MARK, +}; +static const unsigned int scif_clk_b_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(1, 25), +}; +static const unsigned int scif_clk_b_mux[] = { + SCIF_CLK_B_MARK, +}; + +/* - TMU -------------------------------------------------------------------- */ +static const unsigned int tmu_tclk1_a_pins[] = { + /* TCLK1 */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int tmu_tclk1_a_mux[] = { + TCLK1_A_MARK, +}; +static const unsigned int tmu_tclk1_b_pins[] = { + /* TCLK1 */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int tmu_tclk1_b_mux[] = { + TCLK1_B_MARK, +}; +static const unsigned int tmu_tclk2_a_pins[] = { + /* TCLK2 */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int tmu_tclk2_a_mux[] = { + TCLK2_A_MARK, +}; +static const unsigned int tmu_tclk2_b_pins[] = { + /* TCLK2 */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int tmu_tclk2_b_mux[] = { + TCLK2_B_MARK, +}; + +/* - TPU ------------------------------------------------------------------- */ +static const unsigned int tpu_to0_pins[] = { + /* TPU0TO0 */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int tpu_to0_mux[] = { + TPU0TO0_MARK, +}; +static const unsigned int tpu_to1_pins[] = { + /* TPU0TO1 */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int tpu_to1_mux[] = { + TPU0TO1_MARK, +}; +static const unsigned int tpu_to2_pins[] = { + /* TPU0TO2 */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int tpu_to2_mux[] = { + TPU0TO2_MARK, +}; +static const unsigned int tpu_to3_pins[] = { + /* TPU0TO3 */ + RCAR_GP_PIN(4, 3), +}; +static const unsigned int tpu_to3_mux[] = { + TPU0TO3_MARK, +}; + +/* - VIN0 ------------------------------------------------------------------- */ +static const union vin_data vin0_data_pins = { + .data24 = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), + }, +}; +static const union vin_data vin0_data_mux = { + .data24 = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, + VI0_DATA12_MARK, VI0_DATA13_MARK, + VI0_DATA14_MARK, VI0_DATA15_MARK, + VI0_DATA16_MARK, VI0_DATA17_MARK, + VI0_DATA18_MARK, VI0_DATA19_MARK, + VI0_DATA20_MARK, VI0_DATA21_MARK, + VI0_DATA22_MARK, VI0_DATA23_MARK, + }, +}; +static const unsigned int vin0_data18_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), +}; +static const unsigned int vin0_data18_mux[] = { + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, + VI0_DATA12_MARK, VI0_DATA13_MARK, + VI0_DATA14_MARK, VI0_DATA15_MARK, + VI0_DATA18_MARK, VI0_DATA19_MARK, + VI0_DATA20_MARK, VI0_DATA21_MARK, + VI0_DATA22_MARK, VI0_DATA23_MARK, +}; +static const unsigned int vin0_sync_pins[] = { + /* VI0_VSYNC#, VI0_HSYNC# */ + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2), +}; +static const unsigned int vin0_sync_mux[] = { + VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK, +}; +static const unsigned int vin0_field_pins[] = { + /* VI0_FIELD */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int vin0_field_mux[] = { + VI0_FIELD_MARK, +}; +static const unsigned int vin0_clkenb_pins[] = { + /* VI0_CLKENB */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int vin0_clkenb_mux[] = { + VI0_CLKENB_MARK, +}; +static const unsigned int vin0_clk_pins[] = { + /* VI0_CLK */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int vin0_clk_mux[] = { + VI0_CLK_MARK, +}; + +/* - VIN1 ------------------------------------------------------------------- */ +static const unsigned int vin1_data8_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int vin1_data8_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, +}; +static const unsigned int vin1_data10_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), +}; +static const unsigned int vin1_data10_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, +}; +static const unsigned int vin1_data12_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; +static const unsigned int vin1_data12_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, +}; +static const unsigned int vin1_sync_pins[] = { + /* VI1_VSYNC#, VI1_HSYNC# */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2), +}; +static const unsigned int vin1_sync_mux[] = { + VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK, +}; +static const unsigned int vin1_field_pins[] = { + /* VI1_FIELD */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int vin1_field_mux[] = { + VI1_FIELD_MARK, +}; +static const unsigned int vin1_clkenb_pins[] = { + /* VI1_CLKENB */ + RCAR_GP_PIN(3, 1), +}; +static const unsigned int vin1_clkenb_mux[] = { + VI1_CLKENB_MARK, +}; +static const unsigned int vin1_clk_pins[] = { + /* VI1_CLK */ + RCAR_GP_PIN(3, 0), +}; +static const unsigned int vin1_clk_mux[] = { + VI1_CLK_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_rgmii), + SH_PFC_PIN_GROUP(avb_txcrefclk), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_capture), + SH_PFC_PIN_GROUP(avb_avtp_match), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), + SH_PFC_PIN_GROUP(canfd_clk_a), + SH_PFC_PIN_GROUP(canfd_clk_b), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(gether_link_a), + SH_PFC_PIN_GROUP(gether_phy_int_a), + SH_PFC_PIN_GROUP(gether_mdio_a), + SH_PFC_PIN_GROUP(gether_link_b), + SH_PFC_PIN_GROUP(gether_phy_int_b), + SH_PFC_PIN_GROUP(gether_mdio_b), + SH_PFC_PIN_GROUP(gether_magic), + SH_PFC_PIN_GROUP(gether_rgmii), + SH_PFC_PIN_GROUP(gether_txcrefclk), + SH_PFC_PIN_GROUP(gether_txcrefclk_mega), + SH_PFC_PIN_GROUP(gether_rmii), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_clk_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_clk_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif3_data), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), + SH_PFC_PIN_GROUP(mmc_ds), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_rxd), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), + SH_PFC_PIN_GROUP(pwm0_a), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data_a), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk_a), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(tmu_tclk1_a), + SH_PFC_PIN_GROUP(tmu_tclk1_b), + SH_PFC_PIN_GROUP(tmu_tclk2_a), + SH_PFC_PIN_GROUP(tmu_tclk2_b), + SH_PFC_PIN_GROUP(tpu_to0), + SH_PFC_PIN_GROUP(tpu_to1), + SH_PFC_PIN_GROUP(tpu_to2), + SH_PFC_PIN_GROUP(tpu_to3), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 16), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 20), + VIN_DATA_PIN_GROUP(vin0_data, 24), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_data10), + SH_PFC_PIN_GROUP(vin1_data12), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), +}; + +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdio", + "avb_rgmii", + "avb_txcrefclk", + "avb_avtp_pps", + "avb_avtp_capture", + "avb_avtp_match", +}; + +static const char * const canfd0_groups[] = { + "canfd0_data_a", + "canfd0_data_b", +}; + +static const char * const canfd1_groups[] = { + "canfd1_data", +}; + +static const char * const canfd_clk_groups[] = { + "canfd_clk_a", + "canfd_clk_b", +}; + +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_out", + "du_sync", + "du_oddf", + "du_cde", + "du_disp", +}; + +static const char * const gether_groups[] = { + "gether_link_a", + "gether_phy_int_a", + "gether_mdio_a", + "gether_link_b", + "gether_phy_int_b", + "gether_mdio_b", + "gether_magic", + "gether_rgmii", + "gether_txcrefclk", + "gether_txcrefclk_mega", + "gether_rmii", +}; + +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_clk_a", + "hscif0_ctrl_a", + "hscif0_data_b", + "hscif0_clk_b", + "hscif0_ctrl_b", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data", + "hscif3_clk", + "hscif3_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c4_groups[] = { + "i2c4", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", + "mmc_ds", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_txd", + "msiof3_rxd", +}; + +static const char * const pwm0_groups[] = { + "pwm0_a", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", +}; + +static const char * const pwm4_groups[] = { + "pwm4_a", + "pwm4_b", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data_a", + "scif1_clk", + "scif1_ctrl", + "scif1_data_b", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_ctrl", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_ctrl", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk_a", + "scif_clk_b", +}; + +static const char * const tmu_groups[] = { + "tmu_tclk1_a", + "tmu_tclk1_b", + "tmu_tclk2_a", + "tmu_tclk2_b", +}; + +static const char * const tpu_groups[] = { + "tpu_to0", + "tpu_to1", + "tpu_to2", + "tpu_to3", +}; + +static const char * const vin0_groups[] = { + "vin0_data8", + "vin0_data10", + "vin0_data12", + "vin0_data16", + "vin0_data18", + "vin0_data20", + "vin0_data24", + "vin0_sync", + "vin0_field", + "vin0_clkenb", + "vin0_clk", +}; + +static const char * const vin1_groups[] = { + "vin1_data8", + "vin1_data10", + "vin1_data12", + "vin1_sync", + "vin1_field", + "vin1_clkenb", + "vin1_clk", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), + SH_PFC_FUNCTION(canfd_clk), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(gether), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(tmu), + SH_PFC_FUNCTION(tpu), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_21_FN, GPSR0_21, + GP_0_20_FN, GPSR0_20, + GP_0_19_FN, GPSR0_19, + GP_0_18_FN, GPSR0_18, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_27_FN, GPSR1_27, + GP_1_26_FN, GPSR1_26, + GP_1_25_FN, GPSR1_25, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, } + }, + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, GPSR2_29, + GP_2_28_FN, GPSR2_28, + GP_2_27_FN, GPSR2_27, + GP_2_26_FN, GPSR2_26, + GP_2_25_FN, GPSR2_25, + GP_2_24_FN, GPSR2_24, + GP_2_23_FN, GPSR2_23, + GP_2_22_FN, GPSR2_22, + GP_2_21_FN, GPSR2_21, + GP_2_20_FN, GPSR2_20, + GP_2_19_FN, GPSR2_19, + GP_2_18_FN, GPSR2_18, + GP_2_17_FN, GPSR2_17, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, } + }, + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_16_FN, GPSR3_16, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, } + }, + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_24_FN, GPSR4_24, + GP_4_23_FN, GPSR4_23, + GP_4_22_FN, GPSR4_22, + GP_4_21_FN, GPSR4_21, + GP_4_20_FN, GPSR4_20, + GP_4_19_FN, GPSR4_19, + GP_4_18_FN, GPSR4_18, + GP_4_17_FN, GPSR4_17, + GP_4_16_FN, GPSR4_16, + GP_4_15_FN, GPSR4_15, + GP_4_14_FN, GPSR4_14, + GP_4_13_FN, GPSR4_13, + GP_4_12_FN, GPSR4_12, + GP_4_11_FN, GPSR4_11, + GP_4_10_FN, GPSR4_10, + GP_4_9_FN, GPSR4_9, + GP_4_8_FN, GPSR4_8, + GP_4_7_FN, GPSR4_7, + GP_4_6_FN, GPSR4_6, + GP_4_5_FN, GPSR4_5, + GP_4_4_FN, GPSR4_4, + GP_4_3_FN, GPSR4_3, + GP_4_2_FN, GPSR4_2, + GP_4_1_FN, GPSR4_1, + GP_4_0_FN, GPSR4_0, } + }, + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_14_FN, GPSR5_14, + GP_5_13_FN, GPSR5_13, + GP_5_12_FN, GPSR5_12, + GP_5_11_FN, GPSR5_11, + GP_5_10_FN, GPSR5_10, + GP_5_9_FN, GPSR5_9, + GP_5_8_FN, GPSR5_8, + GP_5_7_FN, GPSR5_7, + GP_5_6_FN, GPSR5_6, + GP_5_5_FN, GPSR5_5, + GP_5_4_FN, GPSR5_4, + GP_5_3_FN, GPSR5_3, + GP_5_2_FN, GPSR5_2, + GP_5_1_FN, GPSR5_1, + GP_5_0_FN, GPSR5_0, } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + IP0_31_28 + IP0_27_24 + IP0_23_20 + IP0_19_16 + IP0_15_12 + IP0_11_8 + IP0_7_4 + IP0_3_0 } + }, + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + IP1_31_28 + IP1_27_24 + IP1_23_20 + IP1_19_16 + IP1_15_12 + IP1_11_8 + IP1_7_4 + IP1_3_0 } + }, + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + IP2_31_28 + IP2_27_24 + IP2_23_20 + IP2_19_16 + IP2_15_12 + IP2_11_8 + IP2_7_4 + IP2_3_0 } + }, + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + IP3_31_28 + IP3_27_24 + IP3_23_20 + IP3_19_16 + IP3_15_12 + IP3_11_8 + IP3_7_4 + IP3_3_0 } + }, + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + IP4_31_28 + IP4_27_24 + IP4_23_20 + IP4_19_16 + IP4_15_12 + IP4_11_8 + IP4_7_4 + IP4_3_0 } + }, + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + IP5_31_28 + IP5_27_24 + IP5_23_20 + IP5_19_16 + IP5_15_12 + IP5_11_8 + IP5_7_4 + IP5_3_0 } + }, + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + IP6_31_28 + IP6_27_24 + IP6_23_20 + IP6_19_16 + IP6_15_12 + IP6_11_8 + IP6_7_4 + IP6_3_0 } + }, + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + IP7_31_28 + IP7_27_24 + IP7_23_20 + IP7_19_16 + IP7_15_12 + IP7_11_8 + IP7_7_4 + IP7_3_0 } + }, + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + IP8_31_28 + IP8_27_24 + IP8_23_20 + IP8_19_16 + IP8_15_12 + IP8_11_8 + IP8_7_4 + IP8_3_0 } + }, + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + IP9_31_28 + IP9_27_24 + IP9_23_20 + IP9_19_16 + IP9_15_12 + IP9_11_8 + IP9_7_4 + IP9_3_0 } + }, + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + IP10_31_28 + IP10_27_24 + IP10_23_20 + IP10_19_16 + IP10_15_12 + IP10_11_8 + IP10_7_4 + IP10_3_0 } + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, + 4, 4, 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* RESERVED 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL0_11 + MOD_SEL0_10 + MOD_SEL0_9 + MOD_SEL0_8 + MOD_SEL0_7 + MOD_SEL0_6 + MOD_SEL0_5 + MOD_SEL0_4 + 0, 0, + MOD_SEL0_2 + MOD_SEL0_1 + MOD_SEL0_0 } + }, + { }, +}; + +const struct sh_pfc_soc_info r8a77980_pinmux_info = { + .name = "r8a77980_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 05a3ff81e4a4..62d36804becc 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -285,6 +285,7 @@ extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; extern const struct sh_pfc_soc_info r8a7796_pinmux_info; extern const struct sh_pfc_soc_info r8a77965_pinmux_info; extern const struct sh_pfc_soc_info r8a77970_pinmux_info; +extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; -- cgit v1.2.3 From 2a254de29e995ea58d73f75b69016cf913a5447d Mon Sep 17 00:00:00 2001 From: Alexander Monakov Date: Fri, 9 Mar 2018 01:53:02 +0300 Subject: regulator: 88pg86x: add DT bindings document The only device-specific node names are "buck1" and "buck2" for the two regulators present on the device. Sleep mode GPIO and per-regulator GPIO enable pins are not exposed (the driver does not support them either). Signed-off-by: Alexander Monakov Signed-off-by: Mark Brown --- .../devicetree/bindings/regulator/88pg86x.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/88pg86x.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/88pg86x.txt b/Documentation/devicetree/bindings/regulator/88pg86x.txt new file mode 100644 index 000000000000..13b7f49a2ea8 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/88pg86x.txt @@ -0,0 +1,22 @@ +Marvell 88PG867/88PG868 voltage regulators + +Required properties: +- compatible: one of "marvell,88pg867", "marvell,88pg868"; +- reg: I2C slave address. + +Optional subnodes for regulators: "buck1", "buck2", using common regulator +bindings given in . + +Example: + + pg868@19 { + compatible = "marvell,88pg868"; + reg = <0x19>; + + vcpu: buck1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1350000>; + }; + }; -- cgit v1.2.3 From b166be0044913a4ce03564e7c81f172025d78867 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 28 Feb 2018 15:27:23 +0100 Subject: hwrng: omap - Fix clock resource by adding a register clock On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updating accordingly. Signed-off-by: Gregory CLEMENT Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/omap_rng.txt | 7 ++++++- drivers/char/hw_random/omap-rng.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt index 9cf7876ab434..ea434ce50f36 100644 --- a/Documentation/devicetree/bindings/rng/omap_rng.txt +++ b/Documentation/devicetree/bindings/rng/omap_rng.txt @@ -13,7 +13,12 @@ Required properties: - interrupts : the interrupt number for the RNG module. Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76" - clocks: the trng clock source. Only mandatory for the - "inside-secure,safexcel-eip76" compatible. + "inside-secure,safexcel-eip76" compatible, the second clock is + needed for the Armada 7K/8K SoCs +- clock-names: mandatory if there is a second clock, in this case the + name must be "core" for the first clock and "reg" for the second + one + Example: /* AM335x */ diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c index 159d4a1347b8..b65ff6962899 100644 --- a/drivers/char/hw_random/omap-rng.c +++ b/drivers/char/hw_random/omap-rng.c @@ -150,6 +150,7 @@ struct omap_rng_dev { const struct omap_rng_pdata *pdata; struct hwrng rng; struct clk *clk; + struct clk *clk_reg; }; static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg) @@ -480,6 +481,19 @@ static int omap_rng_probe(struct platform_device *pdev) } } + priv->clk_reg = devm_clk_get(&pdev->dev, "reg"); + if (IS_ERR(priv->clk_reg) && PTR_ERR(priv->clk_reg) == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (!IS_ERR(priv->clk_reg)) { + ret = clk_prepare_enable(priv->clk_reg); + if (ret) { + dev_err(&pdev->dev, + "Unable to enable the register clk: %d\n", + ret); + goto err_register; + } + } + ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) : get_omap_rng_device_details(priv); if (ret) @@ -499,6 +513,7 @@ err_register: pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); + clk_disable_unprepare(priv->clk_reg); clk_disable_unprepare(priv->clk); err_ioremap: dev_err(dev, "initialization failed.\n"); @@ -517,6 +532,7 @@ static int omap_rng_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); clk_disable_unprepare(priv->clk); + clk_disable_unprepare(priv->clk_reg); return 0; } -- cgit v1.2.3 From 8413b9e00aa33604aa661d7271c3c02c86beb994 Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Fri, 9 Mar 2018 22:21:16 +0900 Subject: ASoC: uniphier: add support for UniPhier PXs2 AIO This patch adds support for UniPhier AIO sound driver which is included in UniPhier PXs2 SoCs. Signed-off-by: Katsuhiro Suzuki Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/uniphier,aio.txt | 1 + sound/soc/uniphier/Kconfig | 11 + sound/soc/uniphier/Makefile | 2 + sound/soc/uniphier/aio-ld11.c | 2 +- sound/soc/uniphier/aio-pxs2.c | 320 +++++++++++++++++++++ sound/soc/uniphier/aio.h | 2 + 6 files changed, 337 insertions(+), 1 deletion(-) create mode 100644 sound/soc/uniphier/aio-pxs2.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/uniphier,aio.txt b/Documentation/devicetree/bindings/sound/uniphier,aio.txt index 73f6c27ae4f7..65d71cf6ef0f 100644 --- a/Documentation/devicetree/bindings/sound/uniphier,aio.txt +++ b/Documentation/devicetree/bindings/sound/uniphier,aio.txt @@ -7,6 +7,7 @@ Required properties: - compatible : should be one of the following: "socionext,uniphier-ld11-aio" "socionext,uniphier-ld20-aio" + "socionext,uniphier-pxs2-aio" - reg : offset and length of the register set for the device. - interrupts : should contain I2S or S/PDIF interrupt. - pinctrl-names : should be "default". diff --git a/sound/soc/uniphier/Kconfig b/sound/soc/uniphier/Kconfig index 5da545b9bf2a..aa3592ee1358 100644 --- a/sound/soc/uniphier/Kconfig +++ b/sound/soc/uniphier/Kconfig @@ -30,6 +30,17 @@ config SND_SOC_UNIPHIER_LD11 Select Y if you use such device. If unsure select "N". +config SND_SOC_UNIPHIER_PXS2 + tristate "UniPhier PXs2 Device Driver" + depends on SND_SOC_UNIPHIER + select SND_SOC_UNIPHIER_AIO + select SND_SOC_UNIPHIER_AIO_DMA + help + This adds ASoC driver for Socionext UniPhier PXs2 + input and output that can be used with other codecs. + Select Y if you use such device. + If unsure select "N". + config SND_SOC_UNIPHIER_EVEA_CODEC tristate "UniPhier SoC internal audio codec" depends on SND_SOC_UNIPHIER diff --git a/sound/soc/uniphier/Makefile b/sound/soc/uniphier/Makefile index 587a89700950..88169395f68a 100644 --- a/sound/soc/uniphier/Makefile +++ b/sound/soc/uniphier/Makefile @@ -1,9 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 snd-soc-uniphier-aio-cpu-objs := aio-core.o aio-dma.o aio-cpu.o aio-compress.o snd-soc-uniphier-aio-ld11-objs := aio-ld11.o +snd-soc-uniphier-aio-pxs2-objs := aio-pxs2.o obj-$(CONFIG_SND_SOC_UNIPHIER_AIO) += snd-soc-uniphier-aio-cpu.o obj-$(CONFIG_SND_SOC_UNIPHIER_LD11) += snd-soc-uniphier-aio-ld11.o +obj-$(CONFIG_SND_SOC_UNIPHIER_PXS2) += snd-soc-uniphier-aio-pxs2.o snd-soc-uniphier-evea-objs := evea.o obj-$(CONFIG_SND_SOC_UNIPHIER_EVEA_CODEC) += snd-soc-uniphier-evea.o diff --git a/sound/soc/uniphier/aio-ld11.c b/sound/soc/uniphier/aio-ld11.c index 8e40e6c2e42f..4c4dd3dd4dee 100644 --- a/sound/soc/uniphier/aio-ld11.c +++ b/sound/soc/uniphier/aio-ld11.c @@ -418,7 +418,7 @@ MODULE_DEVICE_TABLE(of, uniphier_aio_of_match); static struct platform_driver uniphier_aio_driver = { .driver = { - .name = "snd-uniphier-aio", + .name = "snd-uniphier-aio-ld11", .of_match_table = of_match_ptr(uniphier_aio_of_match), }, .probe = uniphier_aio_probe, diff --git a/sound/soc/uniphier/aio-pxs2.c b/sound/soc/uniphier/aio-pxs2.c new file mode 100644 index 000000000000..69cd5b0af948 --- /dev/null +++ b/sound/soc/uniphier/aio-pxs2.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Socionext UniPhier AIO ALSA driver for PXs2. +// +// Copyright (c) 2018 Socionext Inc. + +#include + +#include "aio.h" + +static const struct uniphier_aio_spec uniphier_aio_pxs2[] = { + /* for Line PCM In, Pin:AI1Dx */ + { + .name = AUD_NAME_PCMIN1, + .gname = AUD_GNAME_LINE, + .swm = { + .type = PORT_TYPE_I2S, + .dir = PORT_DIR_INPUT, + .rb = { 16, 11, }, + .ch = { 16, 11, }, + .iif = { 0, 0, }, + .iport = { 0, AUD_HW_PCMIN1, }, + }, + }, + + /* for Speaker/Headphone/Mic PCM In, Pin:AI2Dx */ + { + .name = AUD_NAME_PCMIN2, + .gname = AUD_GNAME_AUX, + .swm = { + .type = PORT_TYPE_I2S, + .dir = PORT_DIR_INPUT, + .rb = { 17, 12, }, + .ch = { 17, 12, }, + .iif = { 1, 1, }, + .iport = { 1, AUD_HW_PCMIN2, }, + }, + }, + + /* for HDMI PCM Out, Pin:AO1Dx (inner) */ + { + .name = AUD_NAME_HPCMOUT1, + .gname = AUD_GNAME_HDMI, + .swm = { + .type = PORT_TYPE_I2S, + .dir = PORT_DIR_OUTPUT, + .rb = { 0, 0, }, + .ch = { 0, 0, }, + .oif = { 0, 0, }, + .oport = { 3, AUD_HW_HPCMOUT1, }, + }, + }, + + /* for Line PCM Out, Pin:AO2Dx */ + { + .name = AUD_NAME_PCMOUT1, + .gname = AUD_GNAME_LINE, + .swm = { + .type = PORT_TYPE_I2S, + .dir = PORT_DIR_OUTPUT, + .rb = { 1, 1, }, + .ch = { 1, 1, }, + .oif = { 1, 1, }, + .oport = { 0, AUD_HW_PCMOUT1, }, + }, + }, + + /* for Speaker/Headphone/Mic PCM Out, Pin:AO3Dx */ + { + .name = AUD_NAME_PCMOUT2, + .gname = AUD_GNAME_AUX, + .swm = { + .type = PORT_TYPE_I2S, + .dir = PORT_DIR_OUTPUT, + .rb = { 2, 2, }, + .ch = { 2, 2, }, + .oif = { 2, 2, }, + .oport = { 1, AUD_HW_PCMOUT2, }, + }, + }, + + /* for HDMI Out, Pin:AO1IEC */ + { + .name = AUD_NAME_HIECOUT1, + .swm = { + .type = PORT_TYPE_SPDIF, + .dir = PORT_DIR_OUTPUT, + .rb = { 6, 4, }, + .ch = { 6, 4, }, + .oif = { 6, 4, }, + .oport = { 12, AUD_HW_HIECOUT1, }, + }, + }, + + /* for HDMI Out, Pin:AO1IEC, Compress */ + { + .name = AUD_NAME_HIECCOMPOUT1, + .swm = { + .type = PORT_TYPE_SPDIF, + .dir = PORT_DIR_OUTPUT, + .rb = { 6, 4, }, + .ch = { 6, 4, }, + .oif = { 6, 4, }, + .oport = { 12, AUD_HW_HIECOUT1, }, + }, + }, + + /* for S/PDIF Out, Pin:AO2IEC */ + { + .name = AUD_NAME_IECOUT1, + .swm = { + .type = PORT_TYPE_SPDIF, + .dir = PORT_DIR_OUTPUT, + .rb = { 7, 5, }, + .ch = { 7, 5, }, + .oif = { 7, 5, }, + .oport = { 13, AUD_HW_IECOUT1, }, + }, + }, + + /* for S/PDIF Out, Pin:AO2IEC */ + { + .name = AUD_NAME_IECCOMPOUT1, + .swm = { + .type = PORT_TYPE_SPDIF, + .dir = PORT_DIR_OUTPUT, + .rb = { 7, 5, }, + .ch = { 7, 5, }, + .oif = { 7, 5, }, + .oport = { 13, AUD_HW_IECOUT1, }, + }, + }, +}; + +static const struct uniphier_aio_pll uniphier_aio_pll_pxs2[] = { + [AUD_PLL_A1] = { .enable = true, }, + [AUD_PLL_F1] = { .enable = true, }, + [AUD_PLL_A2] = { .enable = true, }, + [AUD_PLL_F2] = { .enable = true, }, + [AUD_PLL_APLL] = { .enable = true, }, + [AUD_PLL_HSC0] = { .enable = true, }, +}; + +static int uniphier_aio_pxs2_probe(struct snd_soc_dai *dai) +{ + int ret; + + ret = uniphier_aio_dai_probe(dai); + if (ret < 0) + return ret; + + ret = snd_soc_dai_set_pll(dai, AUD_PLL_A1, 0, 0, 36864000); + if (ret < 0) + return ret; + ret = snd_soc_dai_set_pll(dai, AUD_PLL_F1, 0, 0, 36864000); + if (ret < 0) + return ret; + + ret = snd_soc_dai_set_pll(dai, AUD_PLL_A2, 0, 0, 33868800); + if (ret < 0) + return ret; + ret = snd_soc_dai_set_pll(dai, AUD_PLL_F2, 0, 0, 33868800); + if (ret < 0) + return ret; + + return 0; +} + +static struct snd_soc_dai_driver uniphier_aio_dai_pxs2[] = { + { + .name = AUD_GNAME_HDMI, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .playback = { + .stream_name = AUD_NAME_HPCMOUT1, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &uniphier_aio_i2s_ops, + }, + { + .name = AUD_GNAME_LINE, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .playback = { + .stream_name = AUD_NAME_PCMOUT1, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .capture = { + .stream_name = AUD_NAME_PCMIN1, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &uniphier_aio_i2s_ops, + }, + { + .name = AUD_GNAME_AUX, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .playback = { + .stream_name = AUD_NAME_PCMOUT2, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .capture = { + .stream_name = AUD_NAME_PCMIN2, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &uniphier_aio_i2s_ops, + }, + { + .name = AUD_NAME_HIECOUT1, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .playback = { + .stream_name = AUD_NAME_HIECOUT1, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &uniphier_aio_spdif_ops, + }, + { + .name = AUD_NAME_IECOUT1, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .playback = { + .stream_name = AUD_NAME_IECOUT1, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .rates = SNDRV_PCM_RATE_48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &uniphier_aio_spdif_ops, + }, + { + .name = AUD_NAME_HIECCOMPOUT1, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .compress_new = snd_soc_new_compress, + .playback = { + .stream_name = AUD_NAME_HIECCOMPOUT1, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &uniphier_aio_spdif_ops, + }, + { + .name = AUD_NAME_IECCOMPOUT1, + .probe = uniphier_aio_pxs2_probe, + .remove = uniphier_aio_dai_remove, + .suspend = uniphier_aio_dai_suspend, + .resume = uniphier_aio_dai_resume, + .compress_new = snd_soc_new_compress, + .playback = { + .stream_name = AUD_NAME_IECCOMPOUT1, + .channels_min = 1, + .channels_max = 1, + }, + .ops = &uniphier_aio_spdif_ops, + }, +}; + +static const struct uniphier_aio_chip_spec uniphier_aio_pxs2_spec = { + .specs = uniphier_aio_pxs2, + .num_specs = ARRAY_SIZE(uniphier_aio_pxs2), + .dais = uniphier_aio_dai_pxs2, + .num_dais = ARRAY_SIZE(uniphier_aio_dai_pxs2), + .plls = uniphier_aio_pll_pxs2, + .num_plls = ARRAY_SIZE(uniphier_aio_pll_pxs2), + .addr_ext = 0, +}; + +static const struct of_device_id uniphier_aio_of_match[] = { + { + .compatible = "socionext,uniphier-pxs2-aio", + .data = &uniphier_aio_pxs2_spec, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, uniphier_aio_of_match); + +static struct platform_driver uniphier_aio_driver = { + .driver = { + .name = "snd-uniphier-aio-pxs2", + .of_match_table = of_match_ptr(uniphier_aio_of_match), + }, + .probe = uniphier_aio_probe, + .remove = uniphier_aio_remove, +}; +module_platform_driver(uniphier_aio_driver); + +MODULE_AUTHOR("Katsuhiro Suzuki "); +MODULE_DESCRIPTION("UniPhier PXs2 AIO driver."); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/uniphier/aio.h b/sound/soc/uniphier/aio.h index 2cd64273fb5b..793334675cb3 100644 --- a/sound/soc/uniphier/aio.h +++ b/sound/soc/uniphier/aio.h @@ -110,9 +110,11 @@ enum IEC61937_PC { #define AUD_NAME_IECOUT1 "aio-iecout1" #define AUD_NAME_CMASTER "aio-cmaster" #define AUD_NAME_HIECCOMPOUT1 "aio-hieccompout1" +#define AUD_NAME_IECCOMPOUT1 "aio-ieccompout1" #define AUD_GNAME_HDMI "aio-hdmi" #define AUD_GNAME_LINE "aio-line" +#define AUD_GNAME_AUX "aio-aux" #define AUD_GNAME_IEC "aio-iec" #define AUD_CLK_IO 0 -- cgit v1.2.3 From 99cdb0a9f5ecae5c8accc0ee65326b6e9e793725 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 28 Feb 2018 11:35:59 +0100 Subject: dt-bindings: power: supply: axp20x: add AXP813 battery DT binding The AXP813 can have a battery as power supply, so let's add it to the list of compatibles. Signed-off-by: Quentin Schulz Reviewed-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/supply/axp20x_battery.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt index c24886676a60..41916f69902c 100644 --- a/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt +++ b/Documentation/devicetree/bindings/power/supply/axp20x_battery.txt @@ -4,12 +4,12 @@ Required Properties: - compatible, one of: "x-powers,axp209-battery-power-supply" "x-powers,axp221-battery-power-supply" + "x-powers,axp813-battery-power-supply" -This node is a subnode of the axp20x/axp22x PMIC. +This node is a subnode of its respective PMIC DT node. -The AXP20X and AXP22X can read the battery voltage, charge and discharge -currents of the battery by reading ADC channels from the AXP20X/AXP22X -ADC. +The supported devices can read the battery voltage, charge and discharge +currents of the battery by reading ADC channels from the ADC. Example: -- cgit v1.2.3 From 88f598725f42c8ad8c6c01c82bd3d667c250e1de Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Thu, 22 Feb 2018 15:17:13 -0800 Subject: dt-bindings: power: reset: gpio-poweroff: Add 'timeout-ms' property Add 'timeout-ms' property to support boards where the 3s timeout that the current driver defaults to is too short. Signed-off-by: Moritz Fischer Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt index e62d53d844cc..6d8980c18c34 100644 --- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt +++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt @@ -27,10 +27,13 @@ Optional properties: it to an output when the power-off handler is called. If this optional property is not specified, the GPIO is initialized as an output in its inactive state. +- timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is + specified, 3000 ms is used. Examples: gpio-poweroff { compatible = "gpio-poweroff"; gpios = <&gpio 4 0>; + timeout-ms = <3000>; }; -- cgit v1.2.3 From fc8f7ea2d6c074baaad202c9187962bfa493ef13 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Fri, 9 Mar 2018 16:25:43 +0000 Subject: ASoC: da7219: Add common clock usage for providing DAI clks There is a need to use DA7219 as DAI clock master for other codecs within a system, which means that the DAI clocks are required to remain, regardless of whether the codec is actually running playback/capture. To be able to expose control of the DAI clocking the common clock framework has been employed. The current implementation adds a simple clock gate for enabling and disabling the DAI clocks, with no rate control supported (this is still handled through standard hw_params() functions as before). If DT is enabled then the clock is added to the OF providers list, otherwise a clkdev lookup is used. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/da7219.txt | 6 + include/sound/da7219.h | 2 + sound/soc/codecs/da7219.c | 129 +++++++++++++++++++-- sound/soc/codecs/da7219.h | 9 ++ 4 files changed, 138 insertions(+), 8 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/da7219.txt b/Documentation/devicetree/bindings/sound/da7219.txt index 5b54d2d045c3..c3df92d31c4b 100644 --- a/Documentation/devicetree/bindings/sound/da7219.txt +++ b/Documentation/devicetree/bindings/sound/da7219.txt @@ -25,6 +25,9 @@ Optional properties: interrupt is to be used to wake system, otherwise "irq" should be used. - wakeup-source: Flag to indicate this device can wake system (suspend/resume). +- #clock-cells : Should be set to '<0>', only one clock source provided; +- clock-output-names : Name given for DAI clocks output; + - clocks : phandle and clock specifier for codec MCLK. - clock-names : Clock name string for 'clocks' attribute, should be "mclk". @@ -83,6 +86,9 @@ Example: VDDMIC-supply = <®_audio>; VDDIO-supply = <®_audio>; + #clock-cells = <0>; + clock-output-names = "dai-clks"; + clocks = <&clks 201>; clock-names = "mclk"; diff --git a/include/sound/da7219.h b/include/sound/da7219.h index 409ef1397fd3..1bfcb16f2d10 100644 --- a/include/sound/da7219.h +++ b/include/sound/da7219.h @@ -36,6 +36,8 @@ struct da7219_aad_pdata; struct da7219_pdata { bool wakeup_source; + const char *dai_clks_name; + /* Mic */ enum da7219_micbias_voltage micbias_lvl; enum da7219_mic_amp_in_sel mic_amp_in_sel; diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c index 5e043d082f4b..441215997273 100644 --- a/sound/soc/codecs/da7219.c +++ b/sound/soc/codecs/da7219.c @@ -13,6 +13,8 @@ #include #include +#include +#include #include #include #include @@ -772,16 +774,27 @@ static int da7219_dai_event(struct snd_soc_dapm_widget *w, struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component); u8 pll_ctrl, pll_status; - int i = 0; + int i = 0, ret; bool srm_lock = false; switch (event) { case SND_SOC_DAPM_PRE_PMU: - if (da7219->master) + if (da7219->master) { /* Enable DAI clks for master mode */ - snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE, - DA7219_DAI_CLK_EN_MASK, - DA7219_DAI_CLK_EN_MASK); + if (da7219->dai_clks) { + ret = clk_prepare_enable(da7219->dai_clks); + if (ret) { + dev_err(component->dev, + "Failed to enable dai_clks\n"); + return ret; + } + } else { + snd_soc_component_update_bits(component, + DA7219_DAI_CLK_MODE, + DA7219_DAI_CLK_EN_MASK, + DA7219_DAI_CLK_EN_MASK); + } + } /* PC synchronised to DAI */ snd_soc_component_update_bits(component, DA7219_PC_COUNT, @@ -814,9 +827,16 @@ static int da7219_dai_event(struct snd_soc_dapm_widget *w, DA7219_PC_FREERUN_MASK); /* Disable DAI clks if in master mode */ - if (da7219->master) - snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE, - DA7219_DAI_CLK_EN_MASK, 0); + if (da7219->master) { + if (da7219->dai_clks) + clk_disable_unprepare(da7219->dai_clks); + else + snd_soc_component_update_bits(component, + DA7219_DAI_CLK_MODE, + DA7219_DAI_CLK_EN_MASK, + 0); + } + return 0; default: return -EINVAL; @@ -1598,6 +1618,12 @@ static struct da7219_pdata *da7219_fw_to_pdata(struct snd_soc_component *compone pdata->wakeup_source = device_property_read_bool(dev, "wakeup-source"); + pdata->dai_clks_name = "da7219-dai-clks"; + if (device_property_read_string(dev, "clock-output-names", + &pdata->dai_clks_name)) + dev_warn(dev, "Using default clk name: %s\n", + pdata->dai_clks_name); + if (device_property_read_u32(dev, "dlg,micbias-lvl", &of_val32) >= 0) pdata->micbias_lvl = da7219_fw_micbias_lvl(dev, of_val32); else @@ -1712,6 +1738,88 @@ static int da7219_handle_supplies(struct snd_soc_component *component) return 0; } +#ifdef CONFIG_COMMON_CLK +static int da7219_dai_clks_prepare(struct clk_hw *hw) +{ + struct da7219_priv *da7219 = + container_of(hw, struct da7219_priv, dai_clks_hw); + struct snd_soc_component *component = da7219->aad->component; + + snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE, + DA7219_DAI_CLK_EN_MASK, + DA7219_DAI_CLK_EN_MASK); + + return 0; +} + +static void da7219_dai_clks_unprepare(struct clk_hw *hw) +{ + struct da7219_priv *da7219 = + container_of(hw, struct da7219_priv, dai_clks_hw); + struct snd_soc_component *component = da7219->aad->component; + + snd_soc_component_update_bits(component, DA7219_DAI_CLK_MODE, + DA7219_DAI_CLK_EN_MASK, 0); +} + +static int da7219_dai_clks_is_prepared(struct clk_hw *hw) +{ + struct da7219_priv *da7219 = + container_of(hw, struct da7219_priv, dai_clks_hw); + struct snd_soc_component *component = da7219->aad->component; + u8 clk_reg; + + clk_reg = snd_soc_component_read32(component, DA7219_DAI_CLK_MODE); + + return !!(clk_reg & DA7219_DAI_CLK_EN_MASK); +} + +const struct clk_ops da7219_dai_clks_ops = { + .prepare = da7219_dai_clks_prepare, + .unprepare = da7219_dai_clks_unprepare, + .is_prepared = da7219_dai_clks_is_prepared, +}; + +static void da7219_register_dai_clks(struct snd_soc_component *component) +{ + struct device *dev = component->dev; + struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component); + struct da7219_pdata *pdata = da7219->pdata; + struct clk_init_data init = {}; + struct clk *dai_clks; + struct clk_lookup *dai_clks_lookup; + + init.parent_names = NULL; + init.num_parents = 0; + init.name = pdata->dai_clks_name; + init.ops = &da7219_dai_clks_ops; + da7219->dai_clks_hw.init = &init; + + dai_clks = devm_clk_register(dev, &da7219->dai_clks_hw); + if (IS_ERR(dai_clks)) { + dev_warn(dev, "Failed to register DAI clocks: %ld\n", + PTR_ERR(dai_clks)); + return; + } + da7219->dai_clks = dai_clks; + + /* If we're using DT, then register as provider accordingly */ + if (dev->of_node) { + devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &da7219->dai_clks_hw); + } else { + dai_clks_lookup = clkdev_create(dai_clks, pdata->dai_clks_name, + "%s", dev_name(dev)); + if (!dai_clks_lookup) + dev_warn(dev, "Failed to create DAI clkdev"); + else + da7219->dai_clks_lookup = dai_clks_lookup; + } +} +#else +static inline void da7219_register_dai_clks(struct snd_soc_component *component) {} +#endif /* CONFIG_COMMON_CLK */ + static void da7219_handle_pdata(struct snd_soc_component *component) { struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component); @@ -1722,6 +1830,8 @@ static void da7219_handle_pdata(struct snd_soc_component *component) da7219->wakeup_source = pdata->wakeup_source; + da7219_register_dai_clks(component); + /* Mic Bias voltages */ switch (pdata->micbias_lvl) { case DA7219_MICBIAS_1_6V: @@ -1856,6 +1966,9 @@ static void da7219_remove(struct snd_soc_component *component) da7219_aad_exit(component); + if (da7219->dai_clks_lookup) + clkdev_drop(da7219->dai_clks_lookup); + /* Supplies */ regulator_bulk_disable(DA7219_NUM_SUPPLIES, da7219->supplies); } diff --git a/sound/soc/codecs/da7219.h b/sound/soc/codecs/da7219.h index 1acb34cd12ad..1b00023e33cd 100644 --- a/sound/soc/codecs/da7219.h +++ b/sound/soc/codecs/da7219.h @@ -14,6 +14,9 @@ #ifndef __DA7219_H #define __DA7219_H +#include +#include +#include #include #include #include @@ -813,6 +816,12 @@ struct da7219_priv { struct mutex ctrl_lock; struct mutex pll_lock; +#ifdef CONFIG_COMMON_CLK + struct clk_hw dai_clks_hw; +#endif + struct clk_lookup *dai_clks_lookup; + struct clk *dai_clks; + struct clk *mclk; unsigned int mclk_rate; int clk_src; -- cgit v1.2.3 From 05db0dcc70c61bb51d01845e558bd43add5d55bb Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 3 Mar 2018 22:43:02 +0100 Subject: dt-bindings: usb: add the documentation for USB HCDs A USB HCD may have several PHYs which need to be configured before the the HCD starts working. This adds the documentation for such a USB HCD as well as a reference to the new "usb-hcd.txt" from all bindings that implement a USB HCD which support one USB PHY per port. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Tested-by: Yixun Lan Tested-by: Neil Armstrong Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 5 ++++- Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 5 ++++- Documentation/devicetree/bindings/usb/usb-ehci.txt | 6 ++++-- Documentation/devicetree/bindings/usb/usb-hcd.txt | 9 +++++++++ Documentation/devicetree/bindings/usb/usb-ohci.txt | 6 ++++-- Documentation/devicetree/bindings/usb/usb-uhci.txt | 3 +++ Documentation/devicetree/bindings/usb/usb-xhci.txt | 5 +++++ 7 files changed, 33 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/usb/usb-hcd.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt index 88d9f4a4b280..266c2d917a28 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt @@ -32,7 +32,7 @@ Required properties: "mcu_ck": mcu_bus clock for register access, "dma_ck": dma_bus clock for data transfer by DMA - - phys : a list of phandle + phy specifier pairs + - phys : see usb-hcd.txt in the current directory Optional properties: - wakeup-source : enable USB remote wakeup; @@ -52,6 +52,9 @@ Optional properties: See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - imod-interval-ns: default interrupt moderation interval is 5000ns +additionally the properties from usb-hcd.txt (in the current directory) are +supported. + Example: usb30: usb@11270000 { compatible = "mediatek,mt8173-xhci"; diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt index d589a1ef96a1..3382b5cb471d 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt @@ -17,7 +17,7 @@ Required properties: - clock-names : must contain "sys_ck" for clock of controller, the following clocks are optional: "ref_ck", "mcu_ck" and "dam_ck"; - - phys : a list of phandle + phy specifier pairs + - phys : see usb-hcd.txt in the current directory - dr_mode : should be one of "host", "peripheral" or "otg", refer to usb/generic.txt @@ -53,6 +53,9 @@ Optional properties: - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, bit1 for u3port1, ... etc; +additionally the properties from usb-hcd.txt (in the current directory) are +supported. + Sub-nodes: The xhci should be added as subnode to mtu3 as shown in the following example if host mode is enabled. The DT binding details of xhci can be found in: diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt index 3efde12b5d68..0f1b75386207 100644 --- a/Documentation/devicetree/bindings/usb/usb-ehci.txt +++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt @@ -16,10 +16,12 @@ Optional properties: - has-transaction-translator : boolean, set this if EHCI have a Transaction Translator built into the root hub. - clocks : a list of phandle + clock specifier pairs - - phys : phandle + phy specifier pair - - phy-names : "usb" + - phys : see usb-hcd.txt in the current directory - resets : phandle + reset specifier pair +additionally the properties from usb-hcd.txt (in the current directory) are +supported. + Example (Sequoia 440EPx): ehci@e0000300 { compatible = "ibm,usb-ehci-440epx", "usb-ehci"; diff --git a/Documentation/devicetree/bindings/usb/usb-hcd.txt b/Documentation/devicetree/bindings/usb/usb-hcd.txt new file mode 100644 index 000000000000..50529b838c9c --- /dev/null +++ b/Documentation/devicetree/bindings/usb/usb-hcd.txt @@ -0,0 +1,9 @@ +Generic USB HCD (Host Controller Device) Properties + +Optional properties: +- phys: a list of all USB PHYs on this HCD + +Example: + &usb1 { + phys = <&usb2_phy1>, <&usb3_phy1>; + }; diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt index 09e70c875bc6..a8d2103d1f3d 100644 --- a/Documentation/devicetree/bindings/usb/usb-ohci.txt +++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt @@ -13,10 +13,12 @@ Optional properties: - remote-wakeup-connected: remote wakeup is wired on the platform - num-ports : u32, to override the detected port count - clocks : a list of phandle + clock specifier pairs -- phys : phandle + phy specifier pair -- phy-names : "usb" +- phys : see usb-hcd.txt in the current directory - resets : a list of phandle + reset specifier pairs +additionally the properties from usb-hcd.txt (in the current directory) are +supported. + Example: ohci0: usb@1c14400 { diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.txt b/Documentation/devicetree/bindings/usb/usb-uhci.txt index 298133416c97..cc2e6f7d602e 100644 --- a/Documentation/devicetree/bindings/usb/usb-uhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-uhci.txt @@ -6,6 +6,9 @@ Required properties: - reg : Should contain 1 register ranges(address and length) - interrupts : UHCI controller interrupt +additionally the properties from usb-hcd.txt (in the current directory) are +supported. + Example: uhci@d8007b00 { diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index e2ea59bbca93..2f7663bb69ff 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -32,6 +32,11 @@ Optional properties: - usb3-lpm-capable: determines if platform is USB3 LPM capable - quirk-broken-port-ped: set if the controller has broken port disable mechanism - imod-interval-ns: default interrupt moderation interval is 5000ns + - phys : see usb-hcd.txt in the current directory + +additionally the properties from usb-hcd.txt (in the current directory) are +supported. + Example: usb@f0931000 { -- cgit v1.2.3 From f597fbce38d230af95384f4a04e0a13a1d0ad45d Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 5 Mar 2018 22:17:38 +1030 Subject: serial: 8250: Add Nuvoton NPCM UART The Nuvoton UART is almost compatible with the 8250 driver when probed via the 8250_of driver, however it requires some extra configuration at startup. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley Cc: stable Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/8250.txt | 1 + drivers/tty/serial/8250/8250_of.c | 1 + drivers/tty/serial/8250/8250_port.c | 33 +++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 +++ 4 files changed, 38 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt index dad3b2ec66d4..aeb6db4e35c3 100644 --- a/Documentation/devicetree/bindings/serial/8250.txt +++ b/Documentation/devicetree/bindings/serial/8250.txt @@ -24,6 +24,7 @@ Required properties: - "ti,da830-uart" - "aspeed,ast2400-vuart" - "aspeed,ast2500-vuart" + - "nuvoton,npcm750-uart" - "serial" if the port type is unknown. - reg : offset and length of the register set for the device. - interrupts : should contain uart interrupt. diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c index 160b8906d9b9..9835b1c1cbe1 100644 --- a/drivers/tty/serial/8250/8250_of.c +++ b/drivers/tty/serial/8250/8250_of.c @@ -316,6 +316,7 @@ static const struct of_device_id of_platform_serial_table[] = { { .compatible = "mrvl,mmp-uart", .data = (void *)PORT_XSCALE, }, { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, + { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, }, { /* end of list */ }, }; MODULE_DEVICE_TABLE(of, of_platform_serial_table); diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index ffbb955d1c06..95833cbc4338 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -47,6 +47,10 @@ #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ #define UART_EXAR_DVID 0x8d /* Device identification */ +/* Nuvoton NPCM timeout register */ +#define UART_NPCM_TOR 7 +#define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */ + /* * Debugging. */ @@ -293,6 +297,15 @@ static const struct serial8250_config uart_config[] = { UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, .flags = UART_CAP_FIFO, }, + [PORT_NPCM] = { + .name = "Nuvoton 16550", + .fifo_size = 16, + .tx_loadsz = 16, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, + .rxtrig_bytes = {1, 4, 8, 14}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ @@ -2141,6 +2154,15 @@ int serial8250_do_startup(struct uart_port *port) UART_DA830_PWREMU_MGMT_FREE); } + if (port->type == PORT_NPCM) { + /* + * Nuvoton calls the scratch register 'UART_TOR' (timeout + * register). Enable it, and set TIOC (timeout interrupt + * comparator) to be 0x20 for correct operation. + */ + serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20); + } + #ifdef CONFIG_SERIAL_8250_RSA /* * If this is an RSA port, see if we can kick it up to the @@ -2463,6 +2485,15 @@ static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up, return quot_16 >> 4; } +/* Nuvoton NPCM UARTs have a custom divisor calculation */ +static unsigned int npcm_get_divisor(struct uart_8250_port *up, + unsigned int baud) +{ + struct uart_port *port = &up->port; + + return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2; +} + static unsigned int serial8250_get_divisor(struct uart_8250_port *up, unsigned int baud, unsigned int *frac) @@ -2483,6 +2514,8 @@ static unsigned int serial8250_get_divisor(struct uart_8250_port *up, quot = 0x8002; else if (up->port.type == PORT_XR17V35X) quot = xr17v35x_get_divisor(up, baud, frac); + else if (up->port.type == PORT_NPCM) + quot = npcm_get_divisor(up, baud); else quot = uart_get_divisor(port, baud); diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 1c8413f93e3d..dce5f9dae121 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -76,6 +76,9 @@ #define PORT_SUNZILOG 38 #define PORT_SUNSAB 39 +/* Nuvoton UART */ +#define PORT_NPCM 40 + /* Intel EG20 */ #define PORT_PCH_8LINE 44 #define PORT_PCH_2LINE 45 -- cgit v1.2.3 From 8591743f12636a247bdab56c8c355ea9686f2d97 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 8 Mar 2018 23:00:10 +0800 Subject: ARM: sunxi: mc-smp: Use DT enable-method for sun9i A80 SMP Instead of having an early init function check the machine compatible and installing multi-cluster SMP support for the A80 if it matches, use a new cpu enable-method string. This makes the platform support future proof in case anyone manages to add PSCI support. The original init code for the SMP support is changed into the .prepare_cpus callback in the smp_operations structure. Instead of panicing when resources are missing like on some platforms, our code merely guards against engaging SMP or CPU hotplug and returns an error. Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm/mach-sunxi/mc_smp.c | 21 ++++++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index f4a777039f03..76655d0d67c2 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -198,6 +198,7 @@ described below. "actions,s500-smp" "allwinner,sun6i-a31" "allwinner,sun8i-a23" + "allwinner,sun9i-a80-smp" "amlogic,meson8-smp" "amlogic,meson8b-smp" "arm,realview-smp" diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c index 9db6c4ed5861..86e90b038555 100644 --- a/arch/arm/mach-sunxi/mc_smp.c +++ b/arch/arm/mach-sunxi/mc_smp.c @@ -690,7 +690,26 @@ static int __init sunxi_mc_smp_init(void) struct resource res; int ret; - if (!of_machine_is_compatible("allwinner,sun9i-a80")) + /* + * Don't bother checking the "cpus" node, as an enable-method + * property in that node is undocumented. + */ + node = of_cpu_device_node_get(0); + if (!node) + return -ENODEV; + + /* + * We can't actually use the enable-method magic in the kernel. + * Our loopback / trampoline code uses the CPU suspend framework, + * which requires the identity mapping be available. It would not + * yet be available if we used the .init_cpus or .prepare_cpus + * callbacks in smp_operations, which we would use if we were to + * use CPU_METHOD_OF_DECLARE + */ + ret = of_property_match_string(node, "enable-method", + "allwinner,sun9i-a80-smp"); + of_node_put(node); + if (ret) return -ENODEV; if (!sunxi_mc_smp_cpu_table_init()) -- cgit v1.2.3 From 605add0c7bbf5ecb9eeef02c605e47dfd2980acb Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 8 Mar 2018 17:53:54 +0100 Subject: dt-bindings: Document STM32MP1 Reset Clock Controller (RCC) bindings The RCC block is responsible of the management of the clock and reset generation for the complete circuit. Signed-off-by: Gabriel Fernandez Reviewed-by: Rob Herring Signed-off-by: Michael Turquette --- .../devicetree/bindings/clock/st,stm32mp1-rcc.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt new file mode 100644 index 000000000000..fb9495ea582c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt @@ -0,0 +1,60 @@ +STMicroelectronics STM32 Peripheral Reset Clock Controller +========================================================== + +The RCC IP is both a reset and a clock controller. + +RCC makes also power management (resume/supend and wakeup interrupt). + +Please also refer to reset.txt for common reset controller binding usage. + +Please also refer to clock-bindings.txt for common clock controller +binding usage. + + +Required properties: +- compatible: "st,stm32mp1-rcc", "syscon" +- reg: should be register base and length as documented in the datasheet +- #clock-cells: 1, device nodes should specify the clock in their + "clocks" property, containing a phandle to the clock device node, + an index specifying the clock to use. +- #reset-cells: Shall be 1 +- interrupts: Should contain a general interrupt line and a interrupt line + to the wake-up of processor (CSTOP). + +Example: + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + interrupts = , + ; + }; + +Specifying clocks +================= + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/stm32mp1-clks.h header and can be used in device +tree sources. + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. +The index is the bit number within the RCC registers bank, starting from RCC +base address. +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register. + +For example on STM32MP1, for LTDC reset: + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset + = 0x180 / 4 * 32 + 0 = 3072 + +The list of valid indices for STM32MP1 is available in: +include/dt-bindings/reset-controller/stm32mp1-resets.h + +This file implements defines like: +#define LTDC_R 3072 -- cgit v1.2.3 From b6853f821658e660dc1f0d694f04d64c1bdbdb7e Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Wed, 7 Feb 2018 18:22:47 +0800 Subject: dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC document the binding for enabling SCPSYS on MediaTek MT7623 and MT7623A SoC. Where MT7623 SoC has the same definition about power domains with MT2701, so it's fine to using MT2701 ones as MT7623's fallback. Signed-off-by: Sean Wang Reviewed-by: Rob Herring Reviewed-by: Ulf Hansson Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/soc/mediatek/scpsys.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 76bf45b893fa..d6fe16f094af 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -21,6 +21,8 @@ Required properties: - "mediatek,mt2712-scpsys" - "mediatek,mt6797-scpsys" - "mediatek,mt7622-scpsys" + - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC + - "mediatek,mt7623a-scpsys": For MT7623A SoC - "mediatek,mt8173-scpsys" - #power-domain-cells: Must be 1 - reg: Address range of the SCPSYS unit @@ -28,10 +30,11 @@ Required properties: - clock, clock-names: clocks according to the common clock binding. These are clocks which hardware needs to be enabled before enabling certain power domains. - Required clocks for MT2701: "mm", "mfg", "ethif" + Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif" Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec" Required clocks for MT6797: "mm", "mfg", "vdec" Required clocks for MT7622: "hif_sel" + Required clocks for MT7622A: "ethif" Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" Optional properties: -- cgit v1.2.3 From 4e017f1419397473cf3db6e9fa020013998b1aa4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 10 Mar 2018 14:06:21 -0300 Subject: dt-bindings: ifc: Fix the unit address format in the examples DTC warnings will be seen if these examples are used in a real dts file due to a mismatch in the unit address notation. Align the unit address notation to what is done in the real dts files as per commit f81d7af79575 ("arm64: dts: fsl: fix ifc simple-bus unit address format warnings") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt index 89427b018ba7..a4d4b6a2ff0d 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt @@ -43,7 +43,7 @@ Example: 0x1 0x0 0x0 0xffa00000 0x00010000 0x3 0x0 0x0 0xffb00000 0x00020000>; - flash@0,0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; @@ -58,7 +58,7 @@ Example: }; }; - flash@1,0 { + flash@100000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,ifc-nand"; @@ -73,7 +73,7 @@ Example: }; }; - cpld@3,0 { + cpld@@300000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1010rdb-cpld"; -- cgit v1.2.3 From 3f4a9729c4f46198981a049bd8ad5a19764176c3 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Fri, 23 Feb 2018 18:16:24 +0800 Subject: dt-bindings: arm: mediatek: add support for more mt7623 reference boards Update binding document for more mt7623[A,N] reference boards being supported. Signed-off-by: Sean Wang Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.txt | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index 91d517849483..7d21ab37c19c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -50,6 +50,15 @@ Supported boards: - Reference board variant 1 for MT7622: Required root node properties: - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; +- Reference board for MT7623a with eMMC: + Required root node properties: + - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; +- Reference board for MT7623a with NAND: + Required root node properties: + - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623"; +- Reference board for MT7623n with eMMC: + Required root node properties: + - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623"; - Reference board for MT7623n with NAND: Required root node properties: - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623"; -- cgit v1.2.3 From 2a38f6da6014f1e1922361370dbe9a15a828386e Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Thu, 8 Mar 2018 20:58:29 +0100 Subject: dt-bindings: trivial: add various mcp4017/18/19 potentiometers They come in 5 kOhm, 10 kOhm, 50 kOhm and 100 kOhm variations. Signed-off-by: Peter Rosin Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/trivial-devices.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index 2e3740f98c41..763a2808a95c 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -75,6 +75,18 @@ maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface mcube,mc3230 mCube 3-axis 8-bit digital accelerometer memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer +microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k) +microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k) +microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k) +microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k) +microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k) +microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k) +microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k) +microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k) +microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k) +microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k) +microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k) +microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k) microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k) microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k) microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k) -- cgit v1.2.3 From b50c32bd28e399cd4672a1e43645399e5bd1eb85 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Fri, 9 Mar 2018 18:48:52 +0100 Subject: ASoC: max98090: Add #sound-dai-cells property documentation MAX98090 CODEC supports 1 input DAI, adding the #sound-dai-cells property helps to reference the DAI in DT in a standard way. Signed-off-by: Sylwester Nawrocki Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/max98090.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/max98090.txt b/Documentation/devicetree/bindings/sound/max98090.txt index 4e3be6682c98..7e1bbd5c27fd 100644 --- a/Documentation/devicetree/bindings/sound/max98090.txt +++ b/Documentation/devicetree/bindings/sound/max98090.txt @@ -16,6 +16,8 @@ Optional properties: - clock-names: Should be "mclk" +- #sound-dai-cells : should be 0. + - maxim,dmic-freq: Frequency at which to clock DMIC - maxim,micbias: Micbias voltage applies to the analog mic, valid voltages value are: -- cgit v1.2.3 From 6b2d99247b62d288b5b320fcea46c164ab733e49 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 12 Mar 2018 20:34:36 +0100 Subject: ASoC: rt5651: Fix jack-dectect typo in the dt-bindings documentation Fix the jack-dectect typo in the dt-bindings documentation. Signed-off-by: Hans de Goede Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rt5651.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rt5651.txt b/Documentation/devicetree/bindings/sound/rt5651.txt index 7890aa9477f8..b85221864cec 100644 --- a/Documentation/devicetree/bindings/sound/rt5651.txt +++ b/Documentation/devicetree/bindings/sound/rt5651.txt @@ -18,9 +18,9 @@ Optional properties: - realtek,jack-detect-source u32. Valid values: - 1: Use JD1_1 pin for jack-dectect - 2: Use JD1_2 pin for jack-dectect - 3: Use JD2 pin for jack-dectect + 1: Use JD1_1 pin for jack-detect + 2: Use JD1_2 pin for jack-detect + 3: Use JD2 pin for jack-detect - realtek,over-current-threshold-microamp u32, micbias over-current detection threshold in µA, valid values are -- cgit v1.2.3 From c4e50b1d87fbbeabb2d7f286af673666f507acb9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 12 Mar 2018 18:28:09 -0300 Subject: ASoC: sgtl5000: Pass the required '#sound-dai-cells' DTC now warns about missing #sound-dai-cells: arch/arm/boot/dts/imx6ul-geam.dtb: Warning (sound_dai_property): /sound/simple-audio-card,codec: Missing property '#sound-dai-cells' in node /soc/aips-bus@2100000/i2c@21a0000/codec@a or bad phandle (referred from sound-dai[0]) Pass the required '#sound-dai-cells' property to improve the documentation. Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/sgtl5000.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt index 060cb4a3b47e..9a36c7e2a143 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt @@ -5,6 +5,8 @@ Required properties: - reg : the I2C address of the device +- #sound-dai-cells: must be equal to 0 + - clocks : the clock provider of SYS_MCLK - VDDA-supply : the regulator provider of VDDA @@ -40,6 +42,7 @@ Example: codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks 150>; micbias-resistor-k-ohms = <2>; micbias-voltage-m-volts = <2250>; -- cgit v1.2.3 From 4c40db995eb54c3ee8cb5a8340640f49395d5f9e Mon Sep 17 00:00:00 2001 From: Xiaofei Tan Date: Wed, 7 Mar 2018 20:25:05 +0800 Subject: scsi: hisi_sas: dt-bindings: add an property of signal attenuation For some new boards with hip07 chipset we are required to set PHY config registers differently. The hw property which determines how to set these registers is in the PHY signal attenuation readings. This patch add an devicetree property, "hisilicon,signal-attenuation", which is used to describe the signal attenuation of an board. Cc: Rob Herring Cc: Mark Rutland Signed-off-by: Xiaofei Tan Signed-off-by: John Garry Reviewed-by: Rob Herring Signed-off-by: Martin K. Petersen --- Documentation/devicetree/bindings/scsi/hisilicon-sas.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt index df3bef7998fa..8c6659ed2cfc 100644 --- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -53,6 +53,13 @@ Main node required properties: Optional main node properties: - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the "am-max-transmissions" limitation. + - hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis, + preshoot, and boost attenuation readings for the board. They + are used to describe the signal attenuation of the board. These + values' range is 7600 to 12400, and used to represent -24dB to + 24dB. + The formula is "y = (x-10000)/10000". For example, 10478 + means 4.78dB. Example: sas0: sas@c1000000 { -- cgit v1.2.3 From a5d411962c444377d0de0dc89502dbaf2e2a34e2 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 11 Feb 2018 22:15:15 +0100 Subject: dt-bindings: usb: add support for dwc3 controller on Amlogic Meson GX Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB controller. This requires a clock to be enabled and a reset line to be pulsed to get the hardware into a known state. Add the documentation for this IP block, similar to "qcom,dwc3.txt". Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Tested-by: Yixun Lan Signed-off-by: Felipe Balbi --- .../devicetree/bindings/usb/amlogic,dwc3.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/amlogic,dwc3.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt new file mode 100644 index 000000000000..9a8b631904fd --- /dev/null +++ b/Documentation/devicetree/bindings/usb/amlogic,dwc3.txt @@ -0,0 +1,42 @@ +Amlogic Meson GX DWC3 USB SoC controller + +Required properties: +- compatible: depending on the SoC this should contain one of: + * amlogic,meson-axg-dwc3 + * amlogic,meson-gxl-dwc3 +- clocks: a handle for the "USB general" clock +- clock-names: must be "usb_general" +- resets: a handle for the shared "USB OTG" reset line +- reset-names: must be "usb_otg" + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +PHY documentation is provided in the following places: +- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt +- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt + +Example device nodes: + usb0: usb@ff500000 { + compatible = "amlogic,meson-axg-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc CLKID_USB>; + clock-names = "usb_general"; + resets = <&reset RESET_USB_OTG>; + reset-names = "usb_otg"; + + dwc3: dwc3@ff500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff500000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + phys = <&usb3_phy>, <&usb2_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; -- cgit v1.2.3 From ea3f79e2c40172b8c476260c1e33dbb419789d85 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Mon, 12 Mar 2018 19:49:38 +0100 Subject: ASoC: samsung: Snow DT bindings update The new DT bindings are introduced so sound on the HDMI interface can also be supported. The exisiting CPU and CODEC DAI phandle properties are marked as deprecated. Signed-off-by: Sylwester Nawrocki Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/snow.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/snow.txt b/Documentation/devicetree/bindings/sound/snow.txt index 6df74f15687f..80fd9a87bb3f 100644 --- a/Documentation/devicetree/bindings/sound/snow.txt +++ b/Documentation/devicetree/bindings/sound/snow.txt @@ -5,8 +5,17 @@ Required properties: "google,snow-audio-max98090" or "google,snow-audio-max98091" or "google,snow-audio-max98095" -- samsung,i2s-controller: The phandle of the Samsung I2S controller -- samsung,audio-codec: The phandle of the audio codec +- samsung,i2s-controller (deprecated): The phandle of the Samsung I2S controller +- samsung,audio-codec (deprecated): The phandle of the audio codec + +Required sub-nodes: + + - 'cpu' subnode with a 'sound-dai' property containing the phandle of the I2S + controller + - 'codec' subnode with a 'sound-dai' property containing list of phandles + to the CODEC nodes, first entry must be the phandle of the MAX98090, + MAX98091 or MAX98095 CODEC (exact device type is indicated by the compatible + string) and the second entry must be the phandle of the HDMI IP block node Optional: - samsung,model: The name of the sound-card -- cgit v1.2.3 From 1ae8862e27e2b68542294747ae473fb3e1024f74 Mon Sep 17 00:00:00 2001 From: Archana Sathyakumar Date: Wed, 28 Feb 2018 10:27:30 -0700 Subject: dt-bindings/interrupt-controller: pdc: Describe PDC device binding Add device binding documentation for the PDC Interrupt controller on QCOM SoC's like the SDM845. The interrupt-controller can be used to sense edge low interrupts and wakeup interrupts when the GIC is non-operational. Cc: devicetree@vger.kernel.org Signed-off-by: Archana Sathyakumar Signed-off-by: Lina Iyer Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/qcom,pdc.txt | 78 ++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt new file mode 100644 index 000000000000..0b2c97ddb520 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -0,0 +1,78 @@ +PDC interrupt controller + +Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a +Power Domain Controller (PDC) that is on always-on domain. In addition to +providing power control for the power domains, the hardware also has an +interrupt controller that can be used to help detect edge low interrupts as +well detect interrupts when the GIC is non-operational. + +GIC is parent interrupt controller at the highest level. Platform interrupt +controller PDC is next in hierarchy, followed by others. Drivers requiring +wakeup capabilities of their device interrupts routed through the PDC, must +specify PDC as their interrupt controller and request the PDC port associated +with the GIC interrupt. See example below. + +Properties: + +- compatible: + Usage: required + Value type: + Definition: Should contain "qcom,-pdc" + - "qcom,sdm845-pdc": For SDM845 + +- reg: + Usage: required + Value type: + Definition: Specifies the base physical address for PDC hardware. + +- interrupt-cells: + Usage: required + Value type: + Definition: Specifies the number of cells needed to encode an interrupt + source. + Must be 2. + The first element of the tuple is the PDC pin for the + interrupt. + The second element is the trigger type. + +- interrupt-parent: + Usage: required + Value type: + Definition: Specifies the interrupt parent necessary for hierarchical + domain to operate. + +- interrupt-controller: + Usage: required + Value type: + Definition: Identifies the node as an interrupt controller. + +- qcom,pdc-ranges: + Usage: required + Value type: + Definition: Specifies the PDC pin offset and the number of PDC ports. + The tuples indicates the valid mapping of valid PDC ports + and their hwirq mapping. + The first element of the tuple is the starting PDC port. + The second element is the GIC hwirq number for the PDC port. + The third element is the number of interrupts in sequence. + +Example: + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm845-pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + +DT binding of a device that wants to use the GIC SPI 514 as a wakeup +interrupt, must do - + + wake-device { + interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>; + }; + +In this case interrupt 514 would be mapped to port 2 on the PDC as defined by +the qcom,pdc-ranges property. -- cgit v1.2.3 From 68883dc0db43f4943d4dab3c5d31e703d4ebb435 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 9 Mar 2018 10:44:14 -0800 Subject: dt-bindings: soc: Add a binding for the Broadcom VCHIQ services. (v3) The VCHIQ communication channel can be provided by BCM283x and Capri SoCs, to communicate with the VPU-side OS services. Signed-off-by: Eric Anholt Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt new file mode 100644 index 000000000000..8dd7b3a7de65 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-vchiq.txt @@ -0,0 +1,16 @@ +Broadcom VCHIQ firmware services + +Required properties: + +- compatible: Should be "brcm,bcm2835-vchiq" +- reg: Physical base address and length of the doorbell register pair +- interrupts: The interrupt number + See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt + +Example: + +mailbox@7e00b840 { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; +}; -- cgit v1.2.3 From 241672cb4b166da3d2f4deb66bac335f44e04d4a Mon Sep 17 00:00:00 2001 From: Bich HEMON Date: Mon, 12 Mar 2018 09:50:04 +0000 Subject: dt-bindings: serial: stm32: add RS485 optional properties Add options for enabling RS485 hardware control and configuring Driver Enable signal: - rs485-rts-delay - rs485-rx-during-tx - rs485-rts-active-low - linux,rs485-enabled-at-boot-time Signed-off-by: Bich Hemon Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/st,stm32-usart.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt index d150b04a6229..9d3efed55deb 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-usart.txt +++ b/Documentation/devicetree/bindings/serial/st,stm32-usart.txt @@ -15,6 +15,8 @@ Required properties: Optional properties: - pinctrl: The reference on the pins configuration - st,hw-flow-ctrl: bool flag to enable hardware flow control. +- rs485-rts-delay, rs485-rx-during-tx, rs485-rts-active-low, + linux,rs485-enabled-at-boot-time: see rs485.txt. - dmas: phandle(s) to DMA controller node(s). Refer to stm32-dma.txt - dma-names: "rx" and/or "tx" -- cgit v1.2.3 From 6431243f1506d1cd964a6c54d3d95e87a30f8a93 Mon Sep 17 00:00:00 2001 From: Preetham Ramchandra Date: Mon, 12 Mar 2018 17:10:30 +0530 Subject: dt-bindings: Tegra210: add binding documentation This adds bindings documentation for the AHCI controller on Tegra210. Signed-off-by: Preetham Chandru R Acked-by: Thierry Reding Signed-off-by: Tejun Heo --- .../bindings/ata/nvidia,tegra124-ahci.txt | 36 ++++++++++++++-------- 1 file changed, 24 insertions(+), 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt index 66c83c3e8915..12ab2f723eb0 100644 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt @@ -1,9 +1,10 @@ -Tegra124 SoC SATA AHCI controller +Tegra SoC SATA AHCI controller Required properties : -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise, - must contain '"nvidia,-ahci", "nvidia,tegra124-ahci"', where - is tegra132. +- compatible : Must be one of: + - Tegra124 : "nvidia,tegra124-ahci" + - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci" + - Tegra210 : "nvidia,tegra210-ahci" - reg : Should contain 2 entries: - AHCI register set (SATA BAR5) - SATA register set @@ -13,8 +14,6 @@ Required properties : - clock-names : Must include the following entries: - sata - sata-oob - - cml1 - - pll_e - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names : Must include the following entries: @@ -24,9 +23,22 @@ Required properties : - phys : Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. - phy-names : Must include the following entries: - - sata-phy : XUSB PADCTL SATA PHY -- hvdd-supply : Defines the SATA HVDD regulator -- vddio-supply : Defines the SATA VDDIO regulator -- avdd-supply : Defines the SATA AVDD regulator -- target-5v-supply : Defines the SATA 5V power regulator -- target-12v-supply : Defines the SATA 12V power regulator + - For Tegra124 and Tegra132: + - sata-phy : XUSB PADCTL SATA PHY +- For Tegra124 and Tegra132: + - hvdd-supply : Defines the SATA HVDD regulator + - vddio-supply : Defines the SATA VDDIO regulator + - avdd-supply : Defines the SATA AVDD regulator + - target-5v-supply : Defines the SATA 5V power regulator + - target-12v-supply : Defines the SATA 12V power regulator + +Optional properties: +- reg : + - AUX register set +- clock-names : + - cml1 : + cml1 clock should be defined here if the PHY driver + doesn't manage them. If it does, they should not be. +- phy-names : + - For T210: + - sata-phy -- cgit v1.2.3 From 83fc580dcc2f0f36114477c4ac7adbe5c32329a3 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Thu, 8 Mar 2018 16:03:27 -0800 Subject: Input: gpio-keys - add support for wakeup event action Add support for specifying event actions to trigger wakeup when using the gpio-keys input device as a wakeup source. This would allow the device to configure when to wakeup the system. For example a gpio-keys input device for pen insert, may only want to wakeup the system when ejecting the pen. Suggested-by: Brian Norris Signed-off-by: Jeffy Chen Reviewed-by: Rob Herring Signed-off-by: Dmitry Torokhov --- .../devicetree/bindings/input/gpio-keys.txt | 8 ++ drivers/input/keyboard/gpio_keys.c | 145 +++++++++++++++++++-- include/dt-bindings/input/gpio-keys.h | 13 ++ include/linux/gpio_keys.h | 2 + 4 files changed, 154 insertions(+), 14 deletions(-) create mode 100644 include/dt-bindings/input/gpio-keys.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/input/gpio-keys.txt b/Documentation/devicetree/bindings/input/gpio-keys.txt index a94940481e55..996ce84352cb 100644 --- a/Documentation/devicetree/bindings/input/gpio-keys.txt +++ b/Documentation/devicetree/bindings/input/gpio-keys.txt @@ -26,6 +26,14 @@ Optional subnode-properties: If not specified defaults to 5. - wakeup-source: Boolean, button can wake-up the system. (Legacy property supported: "gpio-key,wakeup") + - wakeup-event-action: Specifies whether the key should wake the + system when asserted, when deasserted, or both. This property is + only valid for keys that wake up the system (e.g., when the + "wakeup-source" property is also provided). + Supported values are defined in linux-event-codes.h: + EV_ACT_ASSERTED - asserted + EV_ACT_DEASSERTED - deasserted + EV_ACT_ANY - both asserted and deasserted - linux,can-disable: Boolean, indicates that button is connected to dedicated (not shared) interrupt which can be disabled to suppress events from the button. diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c index 87e613dc33b8..052e37675086 100644 --- a/drivers/input/keyboard/gpio_keys.c +++ b/drivers/input/keyboard/gpio_keys.c @@ -30,6 +30,7 @@ #include #include #include +#include struct gpio_button_data { const struct gpio_keys_button *button; @@ -45,6 +46,7 @@ struct gpio_button_data { unsigned int software_debounce; /* in msecs, for GPIO-driven buttons */ unsigned int irq; + unsigned int wakeup_trigger_type; spinlock_t lock; bool disabled; bool key_pressed; @@ -540,6 +542,8 @@ static int gpio_keys_setup_key(struct platform_device *pdev, } if (bdata->gpiod) { + bool active_low = gpiod_is_active_low(bdata->gpiod); + if (button->debounce_interval) { error = gpiod_set_debounce(bdata->gpiod, button->debounce_interval * 1000); @@ -568,6 +572,24 @@ static int gpio_keys_setup_key(struct platform_device *pdev, isr = gpio_keys_gpio_isr; irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; + switch (button->wakeup_event_action) { + case EV_ACT_ASSERTED: + bdata->wakeup_trigger_type = active_low ? + IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; + break; + case EV_ACT_DEASSERTED: + bdata->wakeup_trigger_type = active_low ? + IRQ_TYPE_EDGE_RISING : IRQ_TYPE_EDGE_FALLING; + break; + case EV_ACT_ANY: + /* fall through */ + default: + /* + * For other cases, we are OK letting suspend/resume + * not reconfigure the trigger type. + */ + break; + } } else { if (!button->irq) { dev_err(dev, "Found button without gpio or irq\n"); @@ -586,6 +608,11 @@ static int gpio_keys_setup_key(struct platform_device *pdev, isr = gpio_keys_irq_isr; irqflags = 0; + + /* + * For IRQ buttons, there is no interrupt for release. + * So we don't need to reconfigure the trigger type for wakeup. + */ } bdata->code = &ddata->keymap[idx]; @@ -718,6 +745,9 @@ gpio_keys_get_devtree_pdata(struct device *dev) /* legacy name */ fwnode_property_read_bool(child, "gpio-key,wakeup"); + fwnode_property_read_u32(child, "wakeup-event-action", + &button->wakeup_event_action); + button->can_disable = fwnode_property_read_bool(child, "linux,can-disable"); @@ -845,19 +875,112 @@ static int gpio_keys_probe(struct platform_device *pdev) return 0; } +static int __maybe_unused +gpio_keys_button_enable_wakeup(struct gpio_button_data *bdata) +{ + int error; + + error = enable_irq_wake(bdata->irq); + if (error) { + dev_err(bdata->input->dev.parent, + "failed to configure IRQ %d as wakeup source: %d\n", + bdata->irq, error); + return error; + } + + if (bdata->wakeup_trigger_type) { + error = irq_set_irq_type(bdata->irq, + bdata->wakeup_trigger_type); + if (error) { + dev_err(bdata->input->dev.parent, + "failed to set wakeup trigger %08x for IRQ %d: %d\n", + bdata->wakeup_trigger_type, bdata->irq, error); + disable_irq_wake(bdata->irq); + return error; + } + } + + return 0; +} + +static void __maybe_unused +gpio_keys_button_disable_wakeup(struct gpio_button_data *bdata) +{ + int error; + + /* + * The trigger type is always both edges for gpio-based keys and we do + * not support changing wakeup trigger for interrupt-based keys. + */ + if (bdata->wakeup_trigger_type) { + error = irq_set_irq_type(bdata->irq, IRQ_TYPE_EDGE_BOTH); + if (error) + dev_warn(bdata->input->dev.parent, + "failed to restore interrupt trigger for IRQ %d: %d\n", + bdata->irq, error); + } + + error = disable_irq_wake(bdata->irq); + if (error) + dev_warn(bdata->input->dev.parent, + "failed to disable IRQ %d as wake source: %d\n", + bdata->irq, error); +} + +static int __maybe_unused +gpio_keys_enable_wakeup(struct gpio_keys_drvdata *ddata) +{ + struct gpio_button_data *bdata; + int error; + int i; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + bdata = &ddata->data[i]; + if (bdata->button->wakeup) { + error = gpio_keys_button_enable_wakeup(bdata); + if (error) + goto err_out; + } + bdata->suspended = true; + } + + return 0; + +err_out: + while (i--) { + bdata = &ddata->data[i]; + if (bdata->button->wakeup) + gpio_keys_button_disable_wakeup(bdata); + bdata->suspended = false; + } + + return error; +} + +static void __maybe_unused +gpio_keys_disable_wakeup(struct gpio_keys_drvdata *ddata) +{ + struct gpio_button_data *bdata; + int i; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + bdata = &ddata->data[i]; + bdata->suspended = false; + if (irqd_is_wakeup_set(irq_get_irq_data(bdata->irq))) + gpio_keys_button_disable_wakeup(bdata); + } +} + static int __maybe_unused gpio_keys_suspend(struct device *dev) { struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev); struct input_dev *input = ddata->input; - int i; + int error; if (device_may_wakeup(dev)) { - for (i = 0; i < ddata->pdata->nbuttons; i++) { - struct gpio_button_data *bdata = &ddata->data[i]; - if (bdata->button->wakeup) - enable_irq_wake(bdata->irq); - bdata->suspended = true; - } + error = gpio_keys_enable_wakeup(ddata); + if (error) + return error; } else { mutex_lock(&input->mutex); if (input->users) @@ -873,15 +996,9 @@ static int __maybe_unused gpio_keys_resume(struct device *dev) struct gpio_keys_drvdata *ddata = dev_get_drvdata(dev); struct input_dev *input = ddata->input; int error = 0; - int i; if (device_may_wakeup(dev)) { - for (i = 0; i < ddata->pdata->nbuttons; i++) { - struct gpio_button_data *bdata = &ddata->data[i]; - if (bdata->button->wakeup) - disable_irq_wake(bdata->irq); - bdata->suspended = false; - } + gpio_keys_disable_wakeup(ddata); } else { mutex_lock(&input->mutex); if (input->users) diff --git a/include/dt-bindings/input/gpio-keys.h b/include/dt-bindings/input/gpio-keys.h new file mode 100644 index 000000000000..8962df79e753 --- /dev/null +++ b/include/dt-bindings/input/gpio-keys.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for gpio keys bindings. + */ + +#ifndef _DT_BINDINGS_GPIO_KEYS_H +#define _DT_BINDINGS_GPIO_KEYS_H + +#define EV_ACT_ANY 0x00 /* asserted or deasserted */ +#define EV_ACT_ASSERTED 0x01 /* asserted */ +#define EV_ACT_DEASSERTED 0x02 /* deasserted */ + +#endif /* _DT_BINDINGS_GPIO_KEYS_H */ diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h index d06bf77400f1..7160df54a6fe 100644 --- a/include/linux/gpio_keys.h +++ b/include/linux/gpio_keys.h @@ -13,6 +13,7 @@ struct device; * @desc: label that will be attached to button's gpio * @type: input event type (%EV_KEY, %EV_SW, %EV_ABS) * @wakeup: configure the button as a wake-up source + * @wakeup_event_action: event action to trigger wakeup * @debounce_interval: debounce ticks interval in msecs * @can_disable: %true indicates that userspace is allowed to * disable button via sysfs @@ -26,6 +27,7 @@ struct gpio_keys_button { const char *desc; unsigned int type; int wakeup; + int wakeup_event_action; int debounce_interval; bool can_disable; int value; -- cgit v1.2.3 From 889ee9fe472af1a2407e3e604498a5edaf7f98ce Mon Sep 17 00:00:00 2001 From: Jeremy Kerr Date: Mon, 12 Feb 2018 15:45:44 +1030 Subject: dt-bindings: fsi: Add specification for FSI busses This change introduces a proposed layout for describing FSI busses in the device tree. While the bus is probe-able, we'd still like a method of describing subordinate (eg i2c) busses that are behind FSI devices. The FSI core will be responsible for matching probed slaves & engines to their device tree nodes, so the FSI device drivers' probe() functions will be passed a struct device with the appropriate of_node populated where a matching DT node is found. Signed-off-by: Jeremy Kerr Acked-by: Joel Stanley Acked-by: Brad Bishop Acked-by: Eddie James Acked-by: Rob Herring Signed-off-by: Joel Stanley Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/fsi/fsi.txt | 144 ++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/fsi.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/fsi/fsi.txt b/Documentation/devicetree/bindings/fsi/fsi.txt new file mode 100644 index 000000000000..4eaf488d4015 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi.txt @@ -0,0 +1,144 @@ +FSI bus & engine generic device tree bindings +============================================= + +The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and +engines within those slaves. However, we have a facility to match devicetree +nodes to probed engines. This allows for fsi engines to expose non-probeable +busses, which are then exposed by the device tree. For example, an FSI engine +that is an I2C master - the I2C bus can be described by the device tree under +the engine's device tree node. + +FSI masters may require their own DT nodes (to describe the master HW itself); +that requirement is defined by the master's implementation, and is described by +the fsi-master-* binding specifications. + +Under the masters' nodes, we can describe the bus topology using nodes to +represent the FSI slaves and their slave engines. As a basic outline: + + fsi-master { + /* top-level of FSI bus topology, bound to an FSI master driver and + * exposes an FSI bus */ + + fsi-slave@ { + /* this node defines the FSI slave device, and is handled + * entirely with FSI core code */ + + fsi-slave-engine@ { + /* this node defines the engine endpoint & address range, which + * is bound to the relevant fsi device driver */ + ... + }; + + fsi-slave-engine@ { + ... + }; + + }; + }; + +Note that since the bus is probe-able, some (or all) of the topology may +not be described; this binding only provides an optional facility for +adding subordinate device tree nodes as children of FSI engines. + +FSI masters +----------- + +FSI master nodes declare themselves as such with the "fsi-master" compatible +value. It's likely that an implementation-specific compatible value will +be needed as well, for example: + + compatible = "fsi-master-gpio", "fsi-master"; + +Since the master nodes describe the top-level of the FSI topology, they also +need to declare the FSI-standard addressing scheme. This requires two cells for +addresses (link index and slave ID), and no size: + + #address-cells = <2>; + #size-cells = <0>; + +FSI slaves +---------- + +Slaves are identified by a (link-index, slave-id) pair, so require two cells +for an address identifier. Since these are not a range, no size cells are +required. For an example, a slave on link 1, with ID 2, could be represented +as: + + cfam@1,2 { + reg = <1 2>; + [...]; + } + +Each slave provides an address-space, under which the engines are accessible. +That address space has a maximum of 23 bits, so we use one cell to represent +addresses and sizes in the slave address space: + + #address-cells = <1>; + #size-cells = <1>; + + +FSI engines (devices) +--------------------- + +Engines are identified by their address under the slaves' address spaces. We +use a single cell for address and size. Engine nodes represent the endpoint +FSI device, and are passed to those FSI device drivers' ->probe() functions. + +For example, for a slave using a single 0x400-byte page starting at address +0xc00: + + engine@c00 { + reg = <0xc00 0x400>; + }; + + +Full example +------------ + +Here's an example that illustrates: + - an FSI master + - connected to an FSI slave + - that contains an engine that is an I2C master + - connected to an I2C EEPROM + +The FSI master may be connected to additional slaves, and slaves may have +additional engines, but they don't necessarily need to be describe in the +device tree if no extra platform information is required. + + /* The GPIO-based FSI master node, describing the top level of the + * FSI bus + */ + gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + + /* A FSI slave (aka. CFAM) at link 0, ID 0. */ + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + + /* FSI engine at 0xc00, using a single page. In this example, + * it's an I2C master controller, so subnodes describe the + * I2C bus. + */ + i2c-controller@c00 { + reg = <0xc00 0x400>; + + /* Engine-specific data. In this case, we're describing an + * I2C bus, so we're conforming to the generic I2C binding + */ + compatible = "some-vendor,fsi-i2c-controller"; + #address-cells = <1>; + #size-cells = <1>; + + /* I2C endpoint device: an Atmel EEPROM */ + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; + }; + }; + }; -- cgit v1.2.3 From dd7987392324960cb0184a4564b06e15c66d3f55 Mon Sep 17 00:00:00 2001 From: Christopher Bostic Date: Mon, 12 Feb 2018 15:45:48 +1030 Subject: dt-bindings: fsi: Add optional property no-scan-on-init Add an optional FSI master property 'no-scan-on-init. This can be specified to indicate that a master should not be automatically scanned at init time. This is required in cases where a scan could interfere with another FSI master on the same bus. Signed-off-by: Christopher Bostic Acked-by: Jeremy Kerr Signed-off-by: Joel Stanley Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/fsi/fsi.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/fsi/fsi.txt b/Documentation/devicetree/bindings/fsi/fsi.txt index 4eaf488d4015..ab516c673a4b 100644 --- a/Documentation/devicetree/bindings/fsi/fsi.txt +++ b/Documentation/devicetree/bindings/fsi/fsi.txt @@ -56,6 +56,13 @@ addresses (link index and slave ID), and no size: #address-cells = <2>; #size-cells = <0>; +An optional boolean property can be added to indicate that a particular master +should not scan for connected devices at initialization time. This is +necessary in cases where a scan could cause arbitration issues with other +masters that may be present on the bus. + + no-scan-on-init; + FSI slaves ---------- -- cgit v1.2.3 From 80b820cae421a424c2a1cd37bb714c47519086cd Mon Sep 17 00:00:00 2001 From: Andrey Yurovsky Date: Fri, 9 Mar 2018 14:47:16 +0000 Subject: nvmem: add i.MX7 support to snvs-lpgpr The i.MX7 family has similar SNVS hardware so make the snvs-lpgpr support it along with the i.MX6 family. The register interface is the same except for the number and offset of the general purpose registers. Signed-off-by: Andrey Yurovsky Reviewed-by: Oleksij Rempel Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 3 ++- drivers/nvmem/Kconfig | 4 ++-- drivers/nvmem/snvs_lpgpr.c | 27 +++++++++++++++++----- 3 files changed, 25 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt index 20bc49b49799..3cb170896658 100644 --- a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt @@ -1,5 +1,5 @@ Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D -Secure Non-Volatile Storage. +and i.MX7 Secure Non-Volatile Storage. This DT node should be represented as a sub-node of a "syscon", "simple-mfd" node. @@ -8,6 +8,7 @@ Required properties: - compatible: should be one of the fallowing variants: "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL + "fsl,imx7d-snvs-lpgpr" for Freescale i.MX7D/S Example: snvs: snvs@020cc000 { diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index ff505af064ba..5f9bc787d634 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -167,10 +167,10 @@ config MESON_MX_EFUSE config NVMEM_SNVS_LPGPR tristate "Support for Low Power General Purpose Register" - depends on SOC_IMX6 || COMPILE_TEST + depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST help This is a driver for Low Power General Purpose Register (LPGPR) available on - i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. + i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. This driver can also be built as a module. If so, the module will be called nvmem-snvs-lpgpr. diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c index 92e1e41d128e..c050a23a9f2b 100644 --- a/drivers/nvmem/snvs_lpgpr.c +++ b/drivers/nvmem/snvs_lpgpr.c @@ -14,15 +14,21 @@ #include #define IMX6Q_SNVS_HPLR 0x00 -#define IMX6Q_GPR_SL BIT(5) #define IMX6Q_SNVS_LPLR 0x34 -#define IMX6Q_GPR_HL BIT(5) #define IMX6Q_SNVS_LPGPR 0x68 +#define IMX7D_SNVS_HPLR 0x00 +#define IMX7D_SNVS_LPLR 0x34 +#define IMX7D_SNVS_LPGPR 0x90 + +#define IMX_GPR_SL BIT(5) +#define IMX_GPR_HL BIT(5) + struct snvs_lpgpr_cfg { int offset; int offset_hplr; int offset_lplr; + int size; }; struct snvs_lpgpr_priv { @@ -36,6 +42,14 @@ static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = { .offset = IMX6Q_SNVS_LPGPR, .offset_hplr = IMX6Q_SNVS_HPLR, .offset_lplr = IMX6Q_SNVS_LPLR, + .size = 4, +}; + +static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx7d = { + .offset = IMX7D_SNVS_LPGPR, + .offset_hplr = IMX7D_SNVS_HPLR, + .offset_lplr = IMX7D_SNVS_LPLR, + .size = 16, }; static int snvs_lpgpr_write(void *context, unsigned int offset, void *val, @@ -50,14 +64,14 @@ static int snvs_lpgpr_write(void *context, unsigned int offset, void *val, if (ret < 0) return ret; - if (lock_reg & IMX6Q_GPR_SL) + if (lock_reg & IMX_GPR_SL) return -EPERM; ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); if (ret < 0) return ret; - if (lock_reg & IMX6Q_GPR_HL) + if (lock_reg & IMX_GPR_HL) return -EPERM; return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, @@ -112,7 +126,7 @@ static int snvs_lpgpr_probe(struct platform_device *pdev) cfg->dev = dev; cfg->stride = 4; cfg->word_size = 4; - cfg->size = 4; + cfg->size = dcfg->size, cfg->owner = THIS_MODULE; cfg->reg_read = snvs_lpgpr_read; cfg->reg_write = snvs_lpgpr_write; @@ -126,6 +140,7 @@ static const struct of_device_id snvs_lpgpr_dt_ids[] = { { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q }, { .compatible = "fsl,imx6ul-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q }, + { .compatible = "fsl,imx7d-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx7d }, { }, }; MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids); @@ -140,5 +155,5 @@ static struct platform_driver snvs_lpgpr_driver = { module_platform_driver(snvs_lpgpr_driver); MODULE_AUTHOR("Oleksij Rempel "); -MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 Secure Non-Volatile Storage"); +MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 and i.MX7 Secure Non-Volatile Storage"); MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From a1078b440fdf1b43024b1e2c9806bdd39ae6502a Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Fri, 9 Mar 2018 14:47:18 +0000 Subject: dt-bindings: nvmem: imx-ocotp: update the binding to reflect data cells imx-ocotp is implemented based on nvmem which can have data cells as child node. Update the binding doc to reflect it to be more easily understood by users. Cc: Srinivas Kandagatla Cc: Rob Herring Cc: Mark Rutland Cc: Shawn Guo Signed-off-by: Dong Aisheng Acked-by: Shawn Guo Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/nvmem/imx-ocotp.txt | 23 ++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt index f162c72b4e36..729f6747813b 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt @@ -11,17 +11,32 @@ Required properties: "fsl,imx6ul-ocotp" (i.MX6UL), "fsl,imx7d-ocotp" (i.MX7D/S), followed by "syscon". +- #address-cells : Should be 1 +- #size-cells : Should be 1 - reg: Should contain the register base and length. - clocks: Should contain a phandle pointing to the gated peripheral clock. Optional properties: - read-only: disable write access -Example: +Optional Child nodes: + +- Data cells of ocotp: + Detailed bindings are described in bindings/nvmem/nvmem.txt +Example: ocotp: ocotp@21bc000 { - compatible = "fsl,imx6q-ocotp", "syscon"; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6QDL_CLK_IIM>; - read-only; + clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; -- cgit v1.2.3 From 86b93a4825d8fa22f05e712a0e70b7406e1df1b5 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 23 Feb 2018 15:41:33 +0900 Subject: mmc: dw_mmc: remove the deprecated "clock-freq-min-max" property 'clock-freq-min-max' property had already deprecated. Remove the 'clock-freq-min-max' property that is kept to maintain the compatibility. Signed-off-by: Jaehoon Chung Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 4 ---- drivers/mmc/host/dw_mmc.c | 15 ++++----------- 2 files changed, 4 insertions(+), 15 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index ef3e5f14067a..75c9fdca4aaf 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -59,10 +59,6 @@ Optional properties: is specified and the ciu clock is specified then we'll try to set the ciu clock to this at probe time. -* clock-freq-min-max (DEPRECATED): Minimum and Maximum clock frequency for card output - clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default. - (Use the "max-frequency" instead of "clock-freq-min-max".) - * num-slots (DEPRECATED): specifies the number of slots supported by the controller. The number of physical slots actually used could be equal or less than the value specified by num-slots. If this property is not specified, the value diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 09ed242de464..b07135e6f74f 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2799,6 +2799,10 @@ static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) if (host->pdata->caps2) mmc->caps2 = host->pdata->caps2; + mmc->f_min = DW_MCI_FREQ_MIN; + if (!mmc->f_max) + mmc->f_max = DW_MCI_FREQ_MAX; + /* Process SDIO IRQs through the sdio_irq_work. */ if (mmc->caps & MMC_CAP_SDIO_IRQ) mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; @@ -2811,7 +2815,6 @@ static int dw_mci_init_slot(struct dw_mci *host) struct mmc_host *mmc; struct dw_mci_slot *slot; int ret; - u32 freq[2]; mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); if (!mmc) @@ -2825,16 +2828,6 @@ static int dw_mci_init_slot(struct dw_mci *host) host->slot = slot; mmc->ops = &dw_mci_ops; - if (device_property_read_u32_array(host->dev, "clock-freq-min-max", - freq, 2)) { - mmc->f_min = DW_MCI_FREQ_MIN; - mmc->f_max = DW_MCI_FREQ_MAX; - } else { - dev_info(host->dev, - "'clock-freq-min-max' property was deprecated.\n"); - mmc->f_min = freq[0]; - mmc->f_max = freq[1]; - } /*if there are external regulators, get them*/ ret = mmc_regulator_get_supply(mmc); -- cgit v1.2.3 From 01b653c2199b55ea798f9b4e224d055317524d8f Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 23 Feb 2018 15:41:34 +0900 Subject: mmc: dw_mmc: remove the deprecated "num-slots" 'num-slots' property had already deprecated. Remove the 'nom-slots' property that is kept to maintain the compatibility. Signed-off-by: Jaehoon Chung Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 5 ----- drivers/mmc/host/dw_mmc-pci.c | 1 - drivers/mmc/host/dw_mmc.c | 4 ---- drivers/mmc/host/dw_mmc.h | 2 -- 4 files changed, 12 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index 75c9fdca4aaf..7e5e427a22ce 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -59,11 +59,6 @@ Optional properties: is specified and the ciu clock is specified then we'll try to set the ciu clock to this at probe time. -* num-slots (DEPRECATED): specifies the number of slots supported by the controller. - The number of physical slots actually used could be equal or less than the - value specified by num-slots. If this property is not specified, the value - of num-slot property is assumed to be 1. - * fifo-depth: The maximum size of the tx/rx fifo's. If this property is not specified, the default value of the fifo size is determined from the controller registers. diff --git a/drivers/mmc/host/dw_mmc-pci.c b/drivers/mmc/host/dw_mmc-pci.c index ab8713297edb..3ad07d7b2c97 100644 --- a/drivers/mmc/host/dw_mmc-pci.c +++ b/drivers/mmc/host/dw_mmc-pci.c @@ -29,7 +29,6 @@ MMC_CAP_SDIO_IRQ) static struct dw_mci_board pci_board_data = { - .num_slots = 1, .caps = DW_MCI_CAPABILITIES, .bus_hz = 33 * 1000 * 1000, .detect_delay_ms = 200, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index b07135e6f74f..e7de83805e60 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -3126,10 +3126,6 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) return ERR_PTR(-EPROBE_DEFER); } - /* find out number of slots supported */ - if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots)) - dev_info(dev, "'num-slots' was deprecated.\n"); - if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) dev_info(dev, "fifo-depth property not found, using value of FIFOTH register as default\n"); diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 9c7085ab63df..950f194e1573 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -251,8 +251,6 @@ struct dma_pdata; /* Board platform data */ struct dw_mci_board { - u32 num_slots; - unsigned int bus_hz; /* Clock speed at the cclk_in pad */ u32 caps; /* Capabilities */ -- cgit v1.2.3 From 8a9cdf985258d3409e5647fbcb8a573da35ee4f8 Mon Sep 17 00:00:00 2001 From: tianshuliang Date: Thu, 8 Mar 2018 09:01:33 +0800 Subject: dt-bindings: mmc: add bindings for hi3798cv200-dw-mshc Hisilicon hi3798cv200 SoC extends the dw-mshc controller for additional clock control. Add device tree bindings for hi3798cv200-dw-mshc. Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo Reviewed-by: Rob Herring Signed-off-by: Ulf Hansson --- .../bindings/mmc/hi3798cv200-dw-mshc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt new file mode 100644 index 000000000000..a0693b7145f2 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt @@ -0,0 +1,40 @@ +* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +Read synopsys-dw-mshc.txt for more details + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200 +specific extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: +- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc". +- clocks: A list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names: Should contain the following: + "ciu" - The ciu clock described in synopsys-dw-mshc.txt. + "biu" - The biu clock described in synopsys-dw-mshc.txt. + "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling. + "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving. + +Example: + + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + }; -- cgit v1.2.3 From eb105eace9521063c2b8786e09879043ec643d26 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 19 Feb 2018 17:54:20 +1030 Subject: dt-bindings: aspeed-lpc: Document LPC Host Interface Controller The LPC Host Interface Controller is part of a BMC SoC that is used for communication with the host. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley Signed-off-by: Greg Kroah-Hartman --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..69aadee00d5f 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -109,9 +109,50 @@ lpc: lpc@1e789000 { }; }; +BMC Node Children +================== + + Host Node Children ================== +LPC Host Interface Controller +------------------- + +The LPC Host Interface Controller manages functions exposed to the host such as +LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART +management and bus snoop configuration. + +Required properties: + +- compatible: One of: + "aspeed,ast2400-lpc-ctrl"; + "aspeed,ast2500-lpc-ctrl"; + +- reg: contains offset/length values of the host interface controller + memory regions + +- clocks: contains a phandle to the syscon node describing the clocks. + There should then be one cell representing the clock to use + +- memory-region: A phandle to a reserved_memory region to be used for the LPC + to AHB mapping + +- flash: A phandle to the SPI flash controller containing the flash to + be exposed over the LPC to AHB mapping + +Example: + +lpc-host@80 { + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; +}; + LPC Host Controller ------------------- -- cgit v1.2.3 From c55fbcb8cf6b3653103f046232ada503e482b57d Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Mon, 12 Mar 2018 13:25:40 +0800 Subject: dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate Add two properties of ref_clk and coefficient used by U2 slew rate calibrate which may vary on different SoCs Signed-off-by: Chunfeng Yun Reviewed-by: Matthias Brugger Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 41e09ed2ca70..0d34b2b4a6b7 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): - reg : offset and length of register shared by multiple ports, exclude port's private register. It is needed on mt2701 and mt8173, but not on mt2712. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process Required properties (port (child) node): - reg : address and length of the register set for the port. -- cgit v1.2.3 From 324e46cee18739efbbed49b30a9100cb7bd0d35e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 3 Mar 2018 19:46:59 +0100 Subject: dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL SoCs Amlogic Meson GXL SoCs use a dwc3 controller with two (GXM - a variant for GXL, has three) USB2 ports. The first USB2 port supports host and peripheral (also called "device") mode. While the dwc3 controller has no USB3 port enabled we still need the USB3 PHY to be initialized. Otherwise high-speed USB transfers (for example with a USB flash drive) may time out (most often seen on boards with mainline u-boot, where the bootloader does not initialize the USB3 PHY registers). Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Tested-by: Yixun Lan Tested-by: Neil Armstrong Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt new file mode 100644 index 000000000000..114947e1de3d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt @@ -0,0 +1,31 @@ +* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding + +Required properties: +- compatible: Should be "amlogic,meson-gxl-usb3-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- interrupts: the interrupt specifier for the OTG detection +- clocks: phandles to the clocks for + - the USB3 PHY + - and peripheral mode/OTG detection +- clock-names: must contain "phy" and "peripheral" +- resets: phandle to the reset lines for: + - the USB3 PHY and + - peripheral mode/OTG detection +- reset-names: must contain "phy" and "peripheral" + +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + + +Example: + usb3_phy0: phy@78080 { + compatible = "amlogic,meson-gxl-usb3-phy"; + #phy-cells = <0>; + reg = <0x0 0x78080 0x0 0x20>; + interrupts = ; + clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>; + clock-names = "phy", "peripheral"; + resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; + reset-names = "phy", "peripheral"; + }; -- cgit v1.2.3 From 194303d60b68a8038979560e5f4ca493bbb3cf37 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 2 Mar 2018 15:56:24 +0100 Subject: dt-bindings: phy: add support for STM32 USB PHY Controller (USBPHYC) This patch adds the device tree bindings description for STM32 USBPHYC (USB PHY Controller). Signed-off-by: Amelie Delaunay Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-stm32-usbphyc.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt new file mode 100644 index 000000000000..725ae71ae653 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.txt @@ -0,0 +1,73 @@ +STMicroelectronics STM32 USB HS PHY controller + +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI +switch. It controls PHY configuration and status, and the UTMI+ switch that +selects either OTG or HOST controller for the second PHY port. It also sets +PLL configuration. + +USBPHYC + |_ PLL + | + |_ PHY port#1 _________________ HOST controller + | _ | + | / 1|________________| + |_ PHY port#2 ----| |________________ + | \_0| | + |_ UTMI switch_______| OTG controller + + +Phy provider node +================= + +Required properties: +- compatible: must be "st,stm32mp1-usbphyc" +- reg: address and length of the usb phy control register set +- clocks: phandle + clock specifier for the PLL phy clock +- #address-cells: number of address cells for phys sub-nodes, must be <1> +- #size-cells: number of size cells for phys sub-nodes, must be <0> + +Optional properties: +- assigned-clocks: phandle + clock specifier for the PLL phy clock +- assigned-clock-parents: the PLL phy clock parent +- resets: phandle + reset specifier + +Required nodes: one sub-node per port the controller provides. + +Phy sub-nodes +============== + +Required properties: +- reg: phy port index +- phy-supply: phandle to the regulator providing 3V3 power to the PHY, + see phy-bindings.txt in the same directory. +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY +- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY + port#1 and must be <1> for PHY port#2, to select USB controller + + +Example: + usbphyc: usb-phy@5a006000 { + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc_clk USBPHY_K>; + resets = <&rcc_rst USBPHY_R>; + #address-cells = <1>; + #size-cells = <0>; + + usbphyc_port0: usb-phy@0 { + reg = <0>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18> + #phy-cells = <0>; + }; + + usbphyc_port1: usb-phy@1 { + reg = <1>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18> + #phy-cells = <1>; + }; + }; -- cgit v1.2.3 From c690eddc2f3b44b24520f4a77cc3a4c9bde7d571 Mon Sep 17 00:00:00 2001 From: Jesper Nilsson Date: Sun, 11 Mar 2018 11:05:23 +0100 Subject: CRIS: Drop support for the CRIS port The port was added back in 2000 so it's no longer even a good source of inspiration for newer ports (if it ever was) The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008. Coupled with time and working developer board hardware being in low supply, it's time to drop the port from Linux. So long and thanks for all the fish! Signed-off-by: Jesper Nilsson Signed-off-by: Arnd Bergmann --- Documentation/00-INDEX | 2 - Documentation/cris/README | 195 - Documentation/devicetree/bindings/cris/axis.txt | 9 - Documentation/devicetree/bindings/cris/boards.txt | 8 - .../interrupt-controller/axis,crisv32-intc.txt | 23 - MAINTAINERS | 10 - arch/cris/Kconfig | 595 -- arch/cris/Kconfig.debug | 41 - arch/cris/Makefile | 104 - arch/cris/arch-v10/Kconfig | 399 -- arch/cris/arch-v10/README.mm | 244 - arch/cris/arch-v10/drivers/Kconfig | 561 -- arch/cris/arch-v10/drivers/Makefile | 11 - arch/cris/arch-v10/drivers/axisflashmap.c | 413 -- arch/cris/arch-v10/drivers/eeprom.c | 852 --- arch/cris/arch-v10/drivers/gpio.c | 857 --- arch/cris/arch-v10/drivers/i2c.c | 699 -- arch/cris/arch-v10/drivers/i2c.h | 18 - arch/cris/arch-v10/drivers/sync_serial.c | 1463 ---- arch/cris/arch-v10/kernel/Makefile | 18 - arch/cris/arch-v10/kernel/crisksyms.c | 17 - arch/cris/arch-v10/kernel/debugport.c | 560 -- arch/cris/arch-v10/kernel/dma.c | 288 - arch/cris/arch-v10/kernel/entry.S | 978 --- arch/cris/arch-v10/kernel/fasttimer.c | 835 --- arch/cris/arch-v10/kernel/head.S | 620 -- arch/cris/arch-v10/kernel/io_interface_mux.c | 1183 ---- arch/cris/arch-v10/kernel/irq.c | 236 - arch/cris/arch-v10/kernel/kgdb.c | 1128 --- arch/cris/arch-v10/kernel/process.c | 180 - arch/cris/arch-v10/kernel/ptrace.c | 204 - arch/cris/arch-v10/kernel/setup.c | 107 - arch/cris/arch-v10/kernel/shadows.c | 37 - arch/cris/arch-v10/kernel/signal.c | 440 -- arch/cris/arch-v10/kernel/time.c | 268 - arch/cris/arch-v10/kernel/traps.c | 134 - arch/cris/arch-v10/lib/Makefile | 6 - arch/cris/arch-v10/lib/checksum.S | 119 - arch/cris/arch-v10/lib/checksumcopy.S | 127 - arch/cris/arch-v10/lib/csumcpfruser.S | 65 - arch/cris/arch-v10/lib/dram_init.S | 147 - arch/cris/arch-v10/lib/hw_settings.S | 61 - arch/cris/arch-v10/lib/memset.c | 259 - arch/cris/arch-v10/lib/string.c | 236 - arch/cris/arch-v10/lib/usercopy.c | 511 -- arch/cris/arch-v10/mm/Makefile | 6 - arch/cris/arch-v10/mm/fault.c | 96 - arch/cris/arch-v10/mm/init.c | 256 - arch/cris/arch-v10/mm/tlb.c | 179 - arch/cris/arch-v10/output_arch.ld | 2 - arch/cris/arch-v32/Kconfig | 211 - arch/cris/arch-v32/drivers/Kconfig | 263 - arch/cris/arch-v32/drivers/Makefile | 12 - arch/cris/arch-v32/drivers/axisflashmap.c | 592 -- arch/cris/arch-v32/drivers/cryptocop.c | 3522 ---------- arch/cris/arch-v32/drivers/iop_fw_load.c | 230 - arch/cris/arch-v32/drivers/mach-a3/Makefile | 5 - arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 177 - arch/cris/arch-v32/drivers/mach-fs/Makefile | 5 - arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 171 - arch/cris/arch-v32/drivers/pci/Makefile | 5 - arch/cris/arch-v32/drivers/pci/bios.c | 74 - arch/cris/arch-v32/drivers/sync_serial.c | 1715 ----- arch/cris/arch-v32/kernel/Makefile | 18 - arch/cris/arch-v32/kernel/cache.c | 34 - arch/cris/arch-v32/kernel/cacheflush.S | 100 - arch/cris/arch-v32/kernel/crisksyms.c | 26 - arch/cris/arch-v32/kernel/debugport.c | 232 - arch/cris/arch-v32/kernel/entry.S | 909 --- arch/cris/arch-v32/kernel/fasttimer.c | 793 --- arch/cris/arch-v32/kernel/head.S | 439 -- arch/cris/arch-v32/kernel/irq.c | 520 -- arch/cris/arch-v32/kernel/kgdb.c | 1593 ----- arch/cris/arch-v32/kernel/kgdb_asm.S | 552 -- arch/cris/arch-v32/kernel/process.c | 180 - arch/cris/arch-v32/kernel/ptrace.c | 492 -- arch/cris/arch-v32/kernel/setup.c | 163 - arch/cris/arch-v32/kernel/signal.c | 541 -- arch/cris/arch-v32/kernel/time.c | 345 - arch/cris/arch-v32/kernel/traps.c | 196 - arch/cris/arch-v32/lib/Makefile | 7 - arch/cris/arch-v32/lib/checksum.S | 89 - arch/cris/arch-v32/lib/checksumcopy.S | 95 - arch/cris/arch-v32/lib/csumcpfruser.S | 70 - arch/cris/arch-v32/lib/delay.c | 29 - arch/cris/arch-v32/lib/memset.c | 259 - arch/cris/arch-v32/lib/strcmp.S | 21 - arch/cris/arch-v32/lib/string.c | 236 - arch/cris/arch-v32/lib/usercopy.c | 458 -- arch/cris/arch-v32/mach-a3/Kconfig | 111 - arch/cris/arch-v32/mach-a3/Makefile | 8 - arch/cris/arch-v32/mach-a3/arbiter.c | 635 -- arch/cris/arch-v32/mach-a3/dma.c | 184 - arch/cris/arch-v32/mach-a3/dram_init.S | 119 - arch/cris/arch-v32/mach-a3/hw_settings.S | 54 - arch/cris/arch-v32/mach-a3/pinmux.c | 389 -- arch/cris/arch-v32/mach-fs/Kconfig | 198 - arch/cris/arch-v32/mach-fs/Makefile | 8 - arch/cris/arch-v32/mach-fs/arbiter.c | 405 -- arch/cris/arch-v32/mach-fs/dma.c | 229 - arch/cris/arch-v32/mach-fs/dram_init.S | 117 - arch/cris/arch-v32/mach-fs/hw_settings.S | 71 - arch/cris/arch-v32/mach-fs/pinmux.c | 328 - arch/cris/arch-v32/mm/Makefile | 4 - arch/cris/arch-v32/mm/init.c | 163 - arch/cris/arch-v32/mm/intmem.c | 157 - arch/cris/arch-v32/mm/l2cache.c | 30 - arch/cris/arch-v32/mm/mmu.S | 211 - arch/cris/arch-v32/mm/tlb.c | 209 - arch/cris/arch-v32/output_arch.ld | 2 - arch/cris/boot/.gitignore | 2 - arch/cris/boot/Makefile | 25 - arch/cris/boot/compressed/Makefile | 36 - arch/cris/boot/compressed/README | 24 - arch/cris/boot/compressed/decompress_v10.lds | 31 - arch/cris/boot/compressed/decompress_v32.lds | 31 - arch/cris/boot/compressed/head_v10.S | 127 - arch/cris/boot/compressed/head_v32.S | 146 - arch/cris/boot/compressed/misc.c | 377 - arch/cris/boot/dts/Makefile | 5 - arch/cris/boot/dts/artpec3.dtsi | 47 - arch/cris/boot/dts/dev88.dts | 68 - arch/cris/boot/dts/etraxfs.dtsi | 47 - arch/cris/boot/dts/p1343.dts | 77 - arch/cris/boot/rescue/Makefile | 53 - arch/cris/boot/rescue/head_v10.S | 358 - arch/cris/boot/rescue/head_v32.S | 27 - arch/cris/boot/rescue/kimagerescue.S | 142 - arch/cris/boot/rescue/rescue_v10.lds | 21 - arch/cris/boot/rescue/rescue_v32.lds | 44 - arch/cris/boot/rescue/testrescue.S | 25 - arch/cris/boot/tools/build.c | 288 - arch/cris/configs/artpec_3_defconfig | 40 - arch/cris/configs/dev88_defconfig | 48 - arch/cris/configs/etrax-100lx_defconfig | 23 - arch/cris/configs/etrax-100lx_v2_defconfig | 42 - arch/cris/configs/etraxfs_defconfig | 40 - arch/cris/include/arch-v10/arch/bitops.h | 74 - arch/cris/include/arch-v10/arch/bug.h | 74 - arch/cris/include/arch-v10/arch/cache.h | 9 - arch/cris/include/arch-v10/arch/checksum.h | 30 - arch/cris/include/arch-v10/arch/delay.h | 21 - arch/cris/include/arch-v10/arch/dma.h | 75 - arch/cris/include/arch-v10/arch/io.h | 173 - arch/cris/include/arch-v10/arch/io_interface_mux.h | 76 - arch/cris/include/arch-v10/arch/irq.h | 162 - arch/cris/include/arch-v10/arch/irqflags.h | 46 - arch/cris/include/arch-v10/arch/memmap.h | 23 - arch/cris/include/arch-v10/arch/mmu.h | 108 - arch/cris/include/arch-v10/arch/offset.h | 34 - arch/cris/include/arch-v10/arch/page.h | 31 - arch/cris/include/arch-v10/arch/pgtable.h | 18 - arch/cris/include/arch-v10/arch/processor.h | 70 - arch/cris/include/arch-v10/arch/swab.h | 31 - arch/cris/include/arch-v10/arch/system.h | 40 - arch/cris/include/arch-v10/arch/thread_info.h | 13 - arch/cris/include/arch-v10/arch/timex.h | 31 - arch/cris/include/arch-v10/arch/tlb.h | 14 - arch/cris/include/arch-v10/arch/uaccess.h | 651 -- arch/cris/include/arch-v10/arch/unistd.h | 149 - arch/cris/include/arch-v32/arch/bitops.h | 65 - arch/cris/include/arch-v32/arch/bug.h | 41 - arch/cris/include/arch-v32/arch/cache.h | 22 - arch/cris/include/arch-v32/arch/checksum.h | 30 - arch/cris/include/arch-v32/arch/cryptocop.h | 159 - arch/cris/include/arch-v32/arch/delay.h | 29 - arch/cris/include/arch-v32/arch/dma.h | 1 - arch/cris/include/arch-v32/arch/hwregs/Makefile | 187 - .../arch-v32/arch/hwregs/asm/ata_defs_asm.h | 223 - .../arch-v32/arch/hwregs/asm/bif_core_defs_asm.h | 320 - .../arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h | 496 -- .../arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h | 250 - .../arch-v32/arch/hwregs/asm/config_defs_asm.h | 132 - .../include/arch-v32/arch/hwregs/asm/cpu_vect.h | 41 - .../arch-v32/arch/hwregs/asm/cris_defs_asm.h | 115 - .../arch-v32/arch/hwregs/asm/cris_supp_reg.h | 11 - .../arch-v32/arch/hwregs/asm/dma_defs_asm.h | 369 - .../arch-v32/arch/hwregs/asm/eth_defs_asm.h | 499 -- .../arch-v32/arch/hwregs/asm/gio_defs_asm.h | 277 - .../include/arch-v32/arch/hwregs/asm/intr_vect.h | 39 - .../arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h | 356 - .../arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h | 70 - .../arch-v32/arch/hwregs/asm/marb_defs_asm.h | 580 -- .../arch-v32/arch/hwregs/asm/mmu_defs_asm.h | 213 - .../arch-v32/arch/hwregs/asm/mmu_supp_reg.h | 8 - .../arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h | 143 - .../arch-v32/arch/hwregs/asm/ser_defs_asm.h | 360 - .../arch-v32/arch/hwregs/asm/sser_defs_asm.h | 463 -- .../arch-v32/arch/hwregs/asm/strcop_defs_asm.h | 85 - .../arch-v32/arch/hwregs/asm/strmux_defs_asm.h | 101 - .../arch-v32/arch/hwregs/asm/timer_defs_asm.h | 230 - arch/cris/include/arch-v32/arch/hwregs/ata_defs.h | 223 - .../include/arch-v32/arch/hwregs/bif_core_defs.h | 285 - .../include/arch-v32/arch/hwregs/bif_dma_defs.h | 474 -- .../include/arch-v32/arch/hwregs/bif_slave_defs.h | 250 - .../include/arch-v32/arch/hwregs/config_defs.h | 143 - arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h | 42 - arch/cris/include/arch-v32/arch/hwregs/dma.h | 128 - arch/cris/include/arch-v32/arch/hwregs/dma_defs.h | 437 -- arch/cris/include/arch-v32/arch/hwregs/eth_defs.h | 379 - .../include/arch-v32/arch/hwregs/extmem_defs.h | 370 - .../cris/include/arch-v32/arch/hwregs/iop/Makefile | 147 - .../arch/hwregs/iop/asm/iop_crc_par_defs_asm.h | 172 - .../arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h | 322 - .../arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h | 350 - .../arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h | 235 - .../hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h | 156 - .../arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h | 255 - .../hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h | 159 - .../arch/hwregs/iop/asm/iop_mpu_defs_asm.h | 178 - .../arch/hwregs/iop/asm/iop_reg_space_asm.h | 45 - .../arch/hwregs/iop/asm/iop_sap_in_defs_asm.h | 183 - .../arch/hwregs/iop/asm/iop_sap_out_defs_asm.h | 347 - .../arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h | 112 - .../arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h | 106 - .../arch/hwregs/iop/asm/iop_spu_defs_asm.h | 574 -- .../arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h | 1053 --- .../arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h | 1759 ----- .../arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h | 1777 ----- .../arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h | 692 -- .../arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h | 238 - .../arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h | 158 - .../arch/hwregs/iop/asm/iop_version_defs_asm.h | 65 - .../arch-v32/arch/hwregs/iop/iop_crc_par_defs.h | 233 - .../arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h | 326 - .../arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h | 327 - .../arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h | 256 - .../arch/hwregs/iop/iop_fifo_in_extra_defs.h | 165 - .../arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h | 279 - .../arch/hwregs/iop/iop_fifo_out_extra_defs.h | 165 - .../arch-v32/arch/hwregs/iop/iop_mpu_defs.h | 191 - .../arch-v32/arch/hwregs/iop/iop_mpu_macros.h | 765 -- .../arch-v32/arch/hwregs/iop/iop_reg_space.h | 45 - .../arch-v32/arch/hwregs/iop/iop_sap_in_defs.h | 180 - .../arch-v32/arch/hwregs/iop/iop_sap_out_defs.h | 307 - .../arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h | 161 - .../arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h | 147 - .../arch-v32/arch/hwregs/iop/iop_spu_defs.h | 454 -- .../arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h | 1043 --- .../arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h | 854 --- .../arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h | 894 --- .../arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h | 553 -- .../arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h | 250 - .../arch/hwregs/iop/iop_trigger_grp_defs.h | 171 - .../arch-v32/arch/hwregs/iop/iop_version_defs.h | 100 - .../include/arch-v32/arch/hwregs/irq_nmi_defs.h | 105 - .../include/arch-v32/arch/hwregs/marb_bp_defs.h | 206 - arch/cris/include/arch-v32/arch/hwregs/marb_defs.h | 476 -- arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h | 18 - .../include/arch-v32/arch/hwregs/rt_trace_defs.h | 174 - arch/cris/include/arch-v32/arch/hwregs/ser_defs.h | 309 - arch/cris/include/arch-v32/arch/hwregs/sser_defs.h | 332 - arch/cris/include/arch-v32/arch/hwregs/strcop.h | 58 - .../include/arch-v32/arch/hwregs/strcop_defs.h | 110 - arch/cris/include/arch-v32/arch/hwregs/supp_reg.h | 79 - arch/cris/include/arch-v32/arch/intmem.h | 10 - arch/cris/include/arch-v32/arch/irq.h | 125 - arch/cris/include/arch-v32/arch/irqflags.h | 47 - arch/cris/include/arch-v32/arch/memmap.h | 1 - arch/cris/include/arch-v32/arch/mmu.h | 111 - arch/cris/include/arch-v32/arch/offset.h | 36 - arch/cris/include/arch-v32/arch/page.h | 23 - arch/cris/include/arch-v32/arch/pgtable.h | 18 - arch/cris/include/arch-v32/arch/processor.h | 54 - arch/cris/include/arch-v32/arch/swab.h | 25 - arch/cris/include/arch-v32/arch/system.h | 38 - arch/cris/include/arch-v32/arch/thread_info.h | 14 - arch/cris/include/arch-v32/arch/timex.h | 32 - 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delete mode 100644 arch/cris/kernel/sys_cris.c delete mode 100644 arch/cris/kernel/time.c delete mode 100644 arch/cris/kernel/traps.c delete mode 100644 arch/cris/kernel/vmlinux.lds.S delete mode 100644 arch/cris/mm/Makefile delete mode 100644 arch/cris/mm/fault.c delete mode 100644 arch/cris/mm/init.c delete mode 100644 arch/cris/mm/ioremap.c delete mode 100644 arch/cris/mm/tlb.c (limited to 'Documentation/devicetree') diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX index ee2808415f64..708dc4c166e4 100644 --- a/Documentation/00-INDEX +++ b/Documentation/00-INDEX @@ -112,8 +112,6 @@ cputopology.txt - documentation on how CPU topology info is exported via sysfs. crc32.txt - brief tutorial on CRC computation -cris/ - - directory with info about Linux on CRIS architecture. crypto/ - directory with info on the Crypto API. dcdbas.txt diff --git a/Documentation/cris/README b/Documentation/cris/README deleted file mode 100644 index 8dbdb1a44429..000000000000 --- a/Documentation/cris/README +++ /dev/null @@ -1,195 +0,0 @@ -Linux on the CRIS architecture -============================== - -This is a port of Linux to Axis Communications ETRAX 100LX, -ETRAX FS and ARTPEC-3 embedded network CPUs. - -For more information about CRIS and ETRAX please see further below. - -In order to compile this you need a version of gcc with support for the -ETRAX chip family. Please see this link for more information on how to -download the compiler and other tools useful when building and booting -software for the ETRAX platform: - -http://developer.axis.com/wiki/doku.php?id=axis:install-howto-2_20 - -What is CRIS ? --------------- - -CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU -architecture in Axis Communication AB's range of embedded network CPU's, -called ETRAX. - -The ETRAX 100LX chip --------------------- - -For reference, please see the following link: - -http://www.axis.com/products/dev_etrax_100lx/index.htm - -The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad -range of built-in interfaces, all with modern scatter/gather DMA. - -Memory interfaces: - - * SRAM - * NOR-flash/ROM - * EDO or page-mode DRAM - * SDRAM - -I/O interfaces: - - * one 10/100 Mbit/s ethernet controller - * four serial-ports (up to 6 Mbit/s) - * two synchronous serial-ports for multimedia codec's etc. - * USB host controller and USB slave - * ATA - * SCSI - * two parallel-ports - * two generic 8-bit ports - - (not all interfaces are available at the same time due to chip pin - multiplexing) - -ETRAX 100LX is CRISv10 architecture. - - -The ETRAX FS and ARTPEC-3 chips -------------------------------- - -The ETRAX FS is a 200MHz 32-bit RISC processor with on-chip 16kB -I-cache and 16kB D-cache and with a wide range of device interfaces -including multiple high speed serial ports and an integrated USB 1.1 PHY. - -The ARTPEC-3 is a variant of the ETRAX FS with additional IO-units -used by the Axis Communications network cameras. - -See below link for more information: - -http://www.axis.com/products/dev_etrax_fs/index.htm - -ETRAX FS and ARTPEC-3 are both CRISv32 architectures. - -Bootlog -------- - -Just as an example, this is the debug-output from a boot of Linux 2.4 on -a board with ETRAX 100LX. The displayed BogoMIPS value is 5 times too small :) -At the end you see some user-mode programs booting like telnet and ftp daemons. - -Linux version 2.4.1 (bjornw@godzilla.axis.se) (gcc version 2.96 20000427 (experimental)) #207 Wed Feb 21 15:48:15 CET 2001 -ROM fs in RAM, size 1376256 bytes -Setting up paging and the MMU. -On node 0 totalpages: 2048 -zone(0): 2048 pages. -zone(1): 0 pages. -zone(2): 0 pages. -Linux/CRIS port on ETRAX 100LX (c) 2001 Axis Communications AB -Kernel command line: -Calibrating delay loop... 19.91 BogoMIPS -Memory: 13872k/16384k available (587k kernel code, 2512k reserved, 44k data, 24k init) -kmem_create: Forcing size word alignment - vm_area_struct -kmem_create: Forcing size word alignment - filp -Dentry-cache hash table entries: 2048 (order: 1, 16384 bytes) -Buffer-cache hash table entries: 2048 (order: 0, 8192 bytes) -Page-cache hash table entries: 2048 (order: 0, 8192 bytes) -kmem_create: Forcing size word alignment - kiobuf -kmem_create: Forcing size word alignment - bdev_cache -Inode-cache hash table entries: 1024 (order: 0, 8192 bytes) -kmem_create: Forcing size word alignment - inode_cache -POSIX conformance testing by UNIFIX -Linux NET4.0 for Linux 2.4 -Based upon Swansea University Computer Society NET3.039 -Starting kswapd v1.8 -kmem_create: Forcing size word alignment - file lock cache -kmem_create: Forcing size word alignment - blkdev_requests -block: queued sectors max/low 9109kB/3036kB, 64 slots per queue -ETRAX 100LX 10/100MBit ethernet v2.0 (c) 2000 Axis Communications AB -eth0 initialized -eth0: changed MAC to 00:40:8C:CD:00:00 -ETRAX 100LX serial-driver $Revision: 1.7 $, (c) 2000 Axis Communications AB -ttyS0 at 0xb0000060 is a builtin UART with DMA -ttyS1 at 0xb0000068 is a builtin UART with DMA -ttyS2 at 0xb0000070 is a builtin UART with DMA -ttyS3 at 0xb0000078 is a builtin UART with DMA -Axis flash mapping: 200000 at 50000000 -Axis flash: Found 1 x16 CFI device at 0x0 in 16 bit mode - Amd/Fujitsu Extended Query Table v1.0 at 0x0040 -Axis flash: JEDEC Device ID is 0xC4. Assuming broken CFI table. -Axis flash: Swapping erase regions for broken CFI table. -number of CFI chips: 1 - Using default partition table -I2C driver v2.2, (c) 1999-2001 Axis Communications AB -ETRAX 100LX GPIO driver v2.1, (c) 2001 Axis Communications AB -NET4: Linux TCP/IP 1.0 for NET4.0 -IP Protocols: ICMP, UDP, TCP -kmem_create: Forcing size word alignment - ip_dst_cache -IP: routing cache hash table of 1024 buckets, 8Kbytes -TCP: Hash tables configured (established 2048 bind 2048) -NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. -VFS: Mounted root (cramfs filesystem) readonly. -Init starts up... -Mounted none on /proc ok. -Setting up eth0 with ip 10.13.9.116 and mac 00:40:8c:18:04:60 -eth0: changed MAC to 00:40:8C:18:04:60 -Setting up lo with ip 127.0.0.1 -Default gateway is 10.13.9.1 -Hostname is bbox1 -Telnetd starting, using port 23. - using /bin/sash as shell. -sftpd[15]: sftpd $Revision: 1.7 $ starting up - - - -And here is how some /proc entries look: - -17# cd /proc -17# cat cpuinfo -cpu : CRIS -cpu revision : 10 -cpu model : ETRAX 100LX -cache size : 8 kB -fpu : no -mmu : yes -ethernet : 10/100 Mbps -token ring : no -scsi : yes -ata : yes -usb : yes -bogomips : 99.84 - -17# cat meminfo - total: used: free: shared: buffers: cached: -Mem: 7028736 925696 6103040 114688 0 229376 -Swap: 0 0 0 -MemTotal: 6864 kB -MemFree: 5960 kB -MemShared: 112 kB -Buffers: 0 kB -Cached: 224 kB -Active: 224 kB -Inact_dirty: 0 kB -Inact_clean: 0 kB -Inact_target: 0 kB -HighTotal: 0 kB -HighFree: 0 kB -LowTotal: 6864 kB -LowFree: 5960 kB -SwapTotal: 0 kB -SwapFree: 0 kB -17# ls -l /bin --rwxr-xr-x 1 342 100 10356 Jan 01 00:00 ifconfig --rwxr-xr-x 1 342 100 17548 Jan 01 00:00 init --rwxr-xr-x 1 342 100 9488 Jan 01 00:00 route --rwxr-xr-x 1 342 100 46036 Jan 01 00:00 sftpd --rwxr-xr-x 1 342 100 48104 Jan 01 00:00 sh --rwxr-xr-x 1 342 100 16252 Jan 01 00:00 telnetd - - - - - - - - - diff --git a/Documentation/devicetree/bindings/cris/axis.txt b/Documentation/devicetree/bindings/cris/axis.txt deleted file mode 100644 index d209ca2a47c0..000000000000 --- a/Documentation/devicetree/bindings/cris/axis.txt +++ /dev/null @@ -1,9 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - - -CRISv32 based SoCs are ETRAX FS and ARTPEC-3: - - - compatible = "axis,crisv32"; - - diff --git a/Documentation/devicetree/bindings/cris/boards.txt b/Documentation/devicetree/bindings/cris/boards.txt deleted file mode 100644 index 533dd273ccf7..000000000000 --- a/Documentation/devicetree/bindings/cris/boards.txt +++ /dev/null @@ -1,8 +0,0 @@ -Boards based on the CRIS SoCs: - -Required root node properties: - - compatible = should be one or more of the following: - - "axis,dev88" - for Axis devboard 88 with ETRAX FS - -Optional: - diff --git a/Documentation/devicetree/bindings/interrupt-controller/axis,crisv32-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/axis,crisv32-intc.txt deleted file mode 100644 index e8b123b0a5e6..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/axis,crisv32-intc.txt +++ /dev/null @@ -1,23 +0,0 @@ -* CRISv32 Interrupt Controller - -Interrupt controller for the CRISv32 SoCs. - -Main node required properties: - -- compatible : should be: - "axis,crisv32-intc" -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The type shall be a and the value shall be 1. -- reg: physical base address and size of the intc registers map. - -Example: - - intc: interrupt-controller { - compatible = "axis,crisv32-intc"; - reg = <0xb001c000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - diff --git a/MAINTAINERS b/MAINTAINERS index ac6083ae4f94..c06fcd0e1514 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3704,16 +3704,6 @@ S: Maintained F: Documentation/filesystems/cramfs.txt F: fs/cramfs/ -CRIS PORT -M: Mikael Starvik -M: Jesper Nilsson -L: linux-cris-kernel@axis.com -W: http://developer.axis.com -T: git git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris.git -S: Maintained -F: arch/cris/ -F: drivers/tty/serial/crisv10.* - CRYPTO API M: Herbert Xu M: "David S. Miller" diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig deleted file mode 100644 index cd5a0865c97f..000000000000 --- a/arch/cris/Kconfig +++ /dev/null @@ -1,595 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config MMU - bool - default y - -config ZONE_DMA - bool - default y - -config RWSEM_GENERIC_SPINLOCK - bool - default y - -config RWSEM_XCHGADD_ALGORITHM - bool - -config ARCH_HAS_ILOG2_U32 - bool - default n - -config ARCH_HAS_ILOG2_U64 - bool - default n - -config GENERIC_HWEIGHT - bool - default y - -config GENERIC_CALIBRATE_DELAY - bool - default y - -config NO_IOPORT_MAP - def_bool y if !PCI - -config NO_DMA - def_bool y if !PCI - -config FORCE_MAX_ZONEORDER - int - default 6 - -config TRACE_IRQFLAGS_SUPPORT - depends on ETRAX_ARCH_V32 - def_bool y - -config STACKTRACE_SUPPORT - def_bool y - -config LOCKDEP_SUPPORT - depends on ETRAX_ARCH_V32 - def_bool y - -config CRIS - bool - default y - select HAVE_IDE - select GENERIC_ATOMIC64 - select HAVE_UID16 - select VIRT_TO_BUS - select ARCH_WANT_IPC_PARSE_VERSION - select GENERIC_IRQ_SHOW - select GENERIC_IOMAP - select MODULES_USE_ELF_RELA - select CLONE_BACKWARDS2 - select HAVE_EXIT_THREAD if ETRAX_ARCH_V32 - select OLD_SIGSUSPEND - select OLD_SIGACTION - select GPIOLIB - select IRQ_DOMAIN if ETRAX_ARCH_V32 - select OF if ETRAX_ARCH_V32 - select OF_EARLY_FLATTREE if ETRAX_ARCH_V32 - select CLKSRC_MMIO if ETRAX_ARCH_V32 - select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32 - select GENERIC_SCHED_CLOCK if ETRAX_ARCH_V32 - select HAVE_DEBUG_BUGVERBOSE if ETRAX_ARCH_V32 - select HAVE_NMI - select DMA_DIRECT_OPS if PCI - -config HZ - int - default 100 - -config NR_CPUS - int - default "1" - -config BUILTIN_DTB - string "DTB to build into the kernel image" - depends on OF - -source "init/Kconfig" - -source "kernel/Kconfig.freezer" - -menu "General setup" - -source "fs/Kconfig.binfmt" - -config ETRAX_CMDLINE - string "Kernel command line" - default "root=/dev/mtdblock3" - help - Pass additional commands to the kernel. - -config ETRAX_WATCHDOG - bool "Enable ETRAX watchdog" - help - Enable the built-in watchdog timer support on ETRAX based embedded - network computers. - -config ETRAX_WATCHDOG_NICE_DOGGY - bool "Disable watchdog during Oops printouts" - depends on ETRAX_WATCHDOG - help - By enabling this you make sure that the watchdog does not bite while - printing oopses. Recommended for development systems but not for - production releases. - -config ETRAX_FAST_TIMER - bool "Enable ETRAX fast timer API" - help - This options enables the API to a fast timer implementation using - timer1 to get sub jiffie resolution timers (primarily one-shot - timers). - This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled. - -config ETRAX_KMALLOCED_MODULES - bool "Enable module allocation with kmalloc" - help - Enable module allocation with kmalloc instead of vmalloc. - -source "kernel/Kconfig.preempt" - -source mm/Kconfig - -endmenu - -menu "Hardware setup" - -choice - prompt "Processor type" - default ETRAX100LX - -config ETRAX100LX - bool "ETRAX-100LX-v1" - select ARCH_USES_GETTIMEOFFSET - help - Support version 1 of the ETRAX 100LX. - -config ETRAX100LX_V2 - bool "ETRAX-100LX-v2" - select ARCH_USES_GETTIMEOFFSET - help - Support version 2 of the ETRAX 100LX. - -config ETRAXFS - bool "ETRAX-FS-V32" - help - Support CRIS V32. - -config CRIS_MACH_ARTPEC3 - bool "ARTPEC-3" - help - Support Axis ARTPEC-3. - -endchoice - -config ETRAX_ARCH_V10 - bool - default y if ETRAX100LX || ETRAX100LX_V2 - default n if !(ETRAX100LX || ETRAX100LX_V2) - select TTY - -config ETRAX_ARCH_V32 - bool - default y if (ETRAXFS || CRIS_MACH_ARTPEC3) - default n if !(ETRAXFS || CRIS_MACH_ARTPEC3) - -config ETRAX_DRAM_SIZE - int "DRAM size (dec, in MB)" - default "8" - help - Size of DRAM (decimal in MB) typically 2, 8 or 16. - -config ETRAX_VMEM_SIZE - int "Video memory size (dec, in MB)" - depends on ETRAX_ARCH_V32 && !ETRAXFS - default 8 if !ETRAXFS - help - Size of Video accessible memory (decimal, in MB). - -config ETRAX_FLASH_BUSWIDTH - int "Buswidth of NOR flash in bytes" - default "2" - help - Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2. - -config ETRAX_FLASH1_SIZE - int "FLASH1 size (dec, in MB. 0 = Unknown)" - default "0" - -choice - prompt "Product debug-port" - default ETRAX_DEBUG_PORT0 - -config ETRAX_DEBUG_PORT0 - bool "Serial-0" - help - Choose a serial port for the ETRAX debug console. Default to - port 0. - -config ETRAX_DEBUG_PORT1 - bool "Serial-1" - help - Use serial port 1 for the console. - -config ETRAX_DEBUG_PORT2 - bool "Serial-2" - help - Use serial port 2 for the console. - -config ETRAX_DEBUG_PORT3 - bool "Serial-3" - help - Use serial port 3 for the console. - -config ETRAX_DEBUG_PORT_NULL - bool "disabled" - help - Disable serial-port debugging. - -endchoice - -choice - prompt "Kernel GDB port" - depends on ETRAX_KGDB - default ETRAX_KGDB_PORT0 - help - Choose a serial port for kernel debugging. NOTE: This port should - not be enabled under Drivers for built-in interfaces (as it has its - own initialization code) and should not be the same as the debug port. - -config ETRAX_KGDB_PORT0 - bool "Serial-0" - help - Use serial port 0 for kernel debugging. - -config ETRAX_KGDB_PORT1 - bool "Serial-1" - help - Use serial port 1 for kernel debugging. - -config ETRAX_KGDB_PORT2 - bool "Serial-2" - help - Use serial port 2 for kernel debugging. - -config ETRAX_KGDB_PORT3 - bool "Serial-3" - help - Use serial port 3 for kernel debugging. - -endchoice - -source arch/cris/arch-v10/Kconfig -source arch/cris/arch-v32/Kconfig - -endmenu - -source "net/Kconfig" - -# bring in ETRAX built-in drivers -menu "Drivers for built-in interfaces" -source arch/cris/arch-v10/drivers/Kconfig -source arch/cris/arch-v32/drivers/Kconfig - -config ETRAX_AXISFLASHMAP - bool "Axis flash-map support" - select MTD - select MTD_CFI - select MTD_CFI_AMDSTD - select MTD_JEDECPROBE if ETRAX_ARCH_V32 - select MTD_BLOCK - select MTD_COMPLEX_MAPPINGS - help - This option enables MTD mapping of flash devices. Needed to use - flash memories. If unsure, say Y. - -config ETRAX_SYNCHRONOUS_SERIAL - bool "Synchronous serial-port support" - help - Select this to enable the synchronous serial port driver. - -config ETRAX_SYNCHRONOUS_SERIAL_PORT0 - bool "Synchronous serial port 0 enabled" - depends on ETRAX_SYNCHRONOUS_SERIAL - help - Enabled synchronous serial port 0. - -config ETRAX_SYNCHRONOUS_SERIAL0_DMA - bool "Enable DMA on synchronous serial port 0." - depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0 - help - A synchronous serial port can run in manual or DMA mode. - Selecting this option will make it run in DMA mode. - -config ETRAX_SYNCHRONOUS_SERIAL_PORT1 - bool "Synchronous serial port 1 enabled" - depends on ETRAX_SYNCHRONOUS_SERIAL && (ETRAXFS || ETRAX_ARCH_V10) - help - Enabled synchronous serial port 1. - -config ETRAX_SYNCHRONOUS_SERIAL1_DMA - bool "Enable DMA on synchronous serial port 1." - depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1 - help - A synchronous serial port can run in manual or DMA mode. - Selecting this option will make it run in DMA mode. - -choice - prompt "Network LED behavior" - depends on ETRAX_ETHERNET - default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY - -config ETRAX_NETWORK_LED_ON_WHEN_LINK - bool "LED_on_when_link" - help - Selecting LED_on_when_link will light the LED when there is a - connection and will flash off when there is activity. - - Selecting LED_on_when_activity will light the LED only when - there is activity. - - This setting will also affect the behaviour of other activity LEDs - e.g. Bluetooth. - -config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY - bool "LED_on_when_activity" - help - Selecting LED_on_when_link will light the LED when there is a - connection and will flash off when there is activity. - - Selecting LED_on_when_activity will light the LED only when - there is activity. - - This setting will also affect the behaviour of other activity LEDs - e.g. Bluetooth. - -endchoice - -choice - prompt "Ser0 DMA out channel" - depends on ETRAX_SERIAL_PORT0 - default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10 - -config ETRAX_SERIAL_PORT0_NO_DMA_OUT - bool "Ser0 uses no DMA for output" - help - Do not use DMA for ser0 output. - -config ETRAX_SERIAL_PORT0_DMA6_OUT - bool "Ser0 uses DMA6 for output" - depends on ETRAXFS - help - Enables the DMA6 output channel for ser0 (ttyS0). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -config ETRAX_SERIAL_PORT0_DMA0_OUT - bool "Ser0 uses DMA0 for output" - depends on CRIS_MACH_ARTPEC3 - help - Enables the DMA0 output channel for ser0 (ttyS0). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser0 DMA in channel " - depends on ETRAX_SERIAL_PORT0 - default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10 - help - What DMA channel to use for ser0. - -config ETRAX_SERIAL_PORT0_NO_DMA_IN - bool "Ser0 uses no DMA for input" - help - Do not use DMA for ser0 input. - -config ETRAX_SERIAL_PORT0_DMA7_IN - bool "Ser0 uses DMA7 for input" - depends on ETRAXFS - help - Enables the DMA7 input channel for ser0 (ttyS0). - If you do not enable DMA, an interrupt for each character will be - used when receiving data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -config ETRAX_SERIAL_PORT0_DMA1_IN - bool "Ser0 uses DMA1 for input" - depends on CRIS_MACH_ARTPEC3 - help - Enables the DMA1 input channel for ser0 (ttyS0). - If you do not enable DMA, an interrupt for each character will be - used when receiving data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser1 DMA in channel " - depends on ETRAX_SERIAL_PORT1 - default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10 - help - What DMA channel to use for ser1. - -config ETRAX_SERIAL_PORT1_NO_DMA_IN - bool "Ser1 uses no DMA for input" - help - Do not use DMA for ser1 input. - -config ETRAX_SERIAL_PORT1_DMA5_IN - bool "Ser1 uses DMA5 for input" - depends on ETRAX_ARCH_V32 - help - Enables the DMA5 input channel for ser1 (ttyS1). - If you do not enable DMA, an interrupt for each character will be - used when receiving data. - Normally you want this on, unless you use the DMA channel for - something else. - -config ETRAX_SERIAL_PORT1_DMA9_IN - depends on ETRAX_ARCH_V10 - bool "Ser1 uses DMA9 for input" - -endchoice - - -choice - prompt "Ser1 DMA out channel" - depends on ETRAX_SERIAL_PORT1 - default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10 - help - What DMA channel to use for ser1. - -config ETRAX_SERIAL_PORT1_NO_DMA_OUT - bool "Ser1 uses no DMA for output" - help - Do not use DMA for ser1 output. - -config ETRAX_SERIAL_PORT1_DMA8_OUT - depends on ETRAX_ARCH_V10 - bool "Ser1 uses DMA8 for output" - -config ETRAX_SERIAL_PORT1_DMA4_OUT - depends on ETRAX_ARCH_V32 - bool "Ser1 uses DMA4 for output" - help - Enables the DMA4 output channel for ser1 (ttyS1). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want this on, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser2 DMA out channel" - depends on ETRAX_SERIAL_PORT2 - default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10 - -config ETRAX_SERIAL_PORT2_NO_DMA_OUT - bool "Ser2 uses no DMA for output" - help - Do not use DMA for ser2 output. - -config ETRAX_SERIAL_PORT2_DMA2_OUT - bool "Ser2 uses DMA2 for output" - depends on ETRAXFS || ETRAX_ARCH_V10 - help - Enables the DMA2 output channel for ser2 (ttyS2). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -config ETRAX_SERIAL_PORT2_DMA6_OUT - bool "Ser2 uses DMA6 for output" - depends on CRIS_MACH_ARTPEC3 - help - Enables the DMA6 output channel for ser2 (ttyS2). - If you do not enable DMA, an interrupt for each character will be - used when transmitting data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser2 DMA in channel" - depends on ETRAX_SERIAL_PORT2 - default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10 - help - What DMA channel to use for ser2. - -config ETRAX_SERIAL_PORT2_NO_DMA_IN - bool "Ser2 uses no DMA for input" - help - Do not use DMA for ser2 input. - -config ETRAX_SERIAL_PORT2_DMA3_IN - bool "Ser2 uses DMA3 for input" - depends on ETRAXFS || ETRAX_ARCH_V10 - help - Enables the DMA3 input channel for ser2 (ttyS2). - If you do not enable DMA, an interrupt for each character will be - used when receiving data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -config ETRAX_SERIAL_PORT2_DMA7_IN - bool "Ser2 uses DMA7 for input" - depends on CRIS_MACH_ARTPEC3 - help - Enables the DMA7 input channel for ser2 (ttyS2). - If you do not enable DMA, an interrupt for each character will be - used when receiving data. - Normally you want to use DMA, unless you use the DMA channel for - something else. - -endchoice - -choice - prompt "Ser3 DMA in channel" - depends on ETRAX_SERIAL_PORT3 - default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10 - help - What DMA channel to use for ser3. - -config ETRAX_SERIAL_PORT3_NO_DMA_IN - bool "Ser3 uses no DMA for input" - help - Do not use DMA for ser3 input. - -config ETRAX_SERIAL_PORT3_DMA5_IN - depends on ETRAX_ARCH_V10 - bool "DMA 5" - -endchoice - -choice - prompt "Ser3 DMA out channel" - depends on ETRAX_SERIAL_PORT3 - default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32 - default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10 - -config ETRAX_SERIAL_PORT3_NO_DMA_OUT - bool "Ser3 uses no DMA for output" - help - Do not use DMA for ser3 output. - -config ETRAX_SERIAL_PORT3_DMA4_OUT - depends on ETRAX_ARCH_V10 - bool "DMA 4" - -endchoice - -endmenu - -source "drivers/Kconfig" - -source "fs/Kconfig" - -source "arch/cris/Kconfig.debug" - -source "security/Kconfig" - -source "crypto/Kconfig" - -source "lib/Kconfig" diff --git a/arch/cris/Kconfig.debug b/arch/cris/Kconfig.debug deleted file mode 100644 index 6084d5e0c512..000000000000 --- a/arch/cris/Kconfig.debug +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menu "Kernel hacking" - -config PROFILING - bool "Kernel profiling support" - -config SYSTEM_PROFILER - bool "System profiling support" - -source "lib/Kconfig.debug" - -config ETRAX_KGDB - bool "Use kernel GDB debugger" - depends on DEBUG_KERNEL - ---help--- - The CRIS version of gdb can be used to remotely debug a running - Linux kernel via the serial debug port. Provided you have gdb-cris - installed, run gdb-cris vmlinux, then type - - (gdb) set remotebaud 115200 <- kgdb uses 115200 as default - (gdb) target remote /dev/ttyS0 <- maybe you use another port - - This should connect you to your booted kernel (or boot it now if you - didn't before). The kernel halts when it boots, waiting for gdb if - this option is turned on! - - -config DEBUG_NMI_OOPS - bool "NMI causes oops printout" - depends on DEBUG_KERNEL - help - If the system locks up without any debug information you can say Y - here to make it possible to dump an OOPS with an external NMI. - -config NO_SEGFAULT_TERMINATION - bool "Keep segfaulting processes" - help - Place segfaulting user mode processes on a wait queue instead of - delivering a terminating SIGSEGV to allow debugging with gdb. - -endmenu diff --git a/arch/cris/Makefile b/arch/cris/Makefile deleted file mode 100644 index 4a5404b3d0e4..000000000000 --- a/arch/cris/Makefile +++ /dev/null @@ -1,104 +0,0 @@ -# -# cris/Makefile -# -# This file is included by the global makefile so that you can add your own -# architecture-specific flags and dependencies. Remember to do have actions -# for "archclean" and "archdep" for cleaning up and making dependencies for -# this architecture -# -# This file is subject to the terms and conditions of the GNU General Public -# License. See the file "COPYING" in the main directory of this archive -# for more details. - -KBUILD_DEFCONFIG := etrax-100lx_v2_defconfig - -arch-y := v10 -arch-$(CONFIG_ETRAX_ARCH_V10) := v10 -arch-$(CONFIG_ETRAX_ARCH_V32) := v32 - -# No config available for make clean etc -mach-y := fs -mach-$(CONFIG_CRIS_MACH_ARTPEC3) := a3 -mach-$(CONFIG_ETRAXFS) := fs - -ifneq ($(arch-y),) -SARCH := arch-$(arch-y) -inc := -Iarch/cris/include/uapi/$(SARCH) -inc += -Iarch/cris/include/$(SARCH) -inc += -Iarch/cris/include/uapi/$(SARCH)/arch -inc += -Iarch/cris/include/$(SARCH)/arch -else -SARCH := -inc := -endif - -ifneq ($(mach-y),) -MACH := mach-$(mach-y) -inc += -Iarch/cris/include/$(SARCH)/$(MACH)/ -inc += -Iarch/cris/include/$(SARCH)/$(MACH)/mach -else -MACH := -endif - -ifneq ($(CONFIG_BUILTIN_DTB),"") -core-$(CONFIG_OF) += arch/cris/boot/dts/ -endif - -LD = $(CROSS_COMPILE)ld -mcrislinux - -OBJCOPYFLAGS := -O binary -R .note -R .comment -S - -KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) -KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) -KBUILD_CPPFLAGS += $(inc) - -ifdef CONFIG_FRAME_POINTER -KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g -KBUILD_CFLAGS += -fno-omit-frame-pointer -endif - -head-y := arch/cris/$(SARCH)/kernel/head.o - -LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libgcc.a) - -core-y += arch/cris/kernel/ arch/cris/mm/ -core-y += arch/cris/$(SARCH)/kernel/ arch/cris/$(SARCH)/mm/ -ifdef CONFIG_ETRAX_ARCH_V32 -core-y += arch/cris/$(SARCH)/$(MACH)/ -endif -drivers-y += arch/cris/$(SARCH)/drivers/ -libs-y += arch/cris/$(SARCH)/lib/ $(LIBGCC) - -# cris source path -SRC_ARCH = $(srctree)/arch/cris -# cris object files path -OBJ_ARCH = $(objtree)/arch/cris - -boot := arch/cris/boot -MACHINE := arch/cris/$(SARCH) - -all: zImage - -zImage Image: vmlinux - $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ - -archprepare: - -archclean: - $(Q)if [ -e arch/cris/boot ]; then \ - $(MAKE) $(clean)=arch/cris/boot; \ - fi - -CLEAN_FILES += \ - $(boot)/zImage \ - $(boot)/compressed/decompress.bin \ - $(boot)/compressed/piggy.gz \ - $(boot)/rescue/rescue.bin - - -# MRPROPER_FILES += - -define archhelp - echo '* zImage - Compressed kernel image (arch/cris/boot/zImage)' - echo '* Image - Uncompressed kernel image (arch/cris/boot/Image)' -endef diff --git a/arch/cris/arch-v10/Kconfig b/arch/cris/arch-v10/Kconfig deleted file mode 100644 index d4015a931374..000000000000 --- a/arch/cris/arch-v10/Kconfig +++ /dev/null @@ -1,399 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ETRAX_ARCH_V10 - -menu "CRIS v10 options" - -# ETRAX 100LX v1 has a MMU "feature" requiring a low mapping -config CRIS_LOW_MAP - bool - depends on ETRAX_ARCH_V10 && ETRAX100LX - default y - -config ETRAX_DRAM_VIRTUAL_BASE - hex - depends on ETRAX_ARCH_V10 - default "c0000000" if !ETRAX100LX - default "60000000" if ETRAX100LX - -choice - prompt "Product LED port" - depends on ETRAX_ARCH_V10 - default ETRAX_PA_LEDS - -config ETRAX_PA_LEDS - bool "Port-PA-LEDs" - help - The ETRAX network driver is responsible for flashing LED's when - packets arrive and are sent. It uses macros defined in - , and those macros are defined after - what YOU choose in this option. The actual bits used are configured - separately. Select this if the LEDs are on port PA. Some products - put the leds on PB or a memory-mapped latch (CSP0) instead. - -config ETRAX_PB_LEDS - bool "Port-PB-LEDs" - help - The ETRAX network driver is responsible for flashing LED's when - packets arrive and are sent. It uses macros defined in - , and those macros are defined after - what YOU choose in this option. The actual bits used are configured - separately. Select this if the LEDs are on port PB. Some products - put the leds on PA or a memory-mapped latch (CSP0) instead. - -config ETRAX_CSP0_LEDS - bool "Port-CSP0-LEDs" - help - The ETRAX network driver is responsible for flashing LED's when - packets arrive and are sent. It uses macros defined in - , and those macros are defined after - what YOU choose in this option. The actual bits used are configured - separately. Select this if the LEDs are on a memory-mapped latch - using chip select CSP0, this is mapped at 0x90000000. - Some products put the leds on PA or PB instead. - -config ETRAX_NO_LEDS - bool "None" - help - Select this option if you don't have any LED at all. - -endchoice - -config ETRAX_LED1G - int "First green LED bit" - depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS - default "2" - help - Bit to use for the first green LED. - Most Axis products use bit 2 here. - -config ETRAX_LED1R - int "First red LED bit" - depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS - default "3" - help - Bit to use for the first red LED. - Most Axis products use bit 3 here. - For products with only one controllable LED, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED2G - int "Second green LED bit" - depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS - default "4" - help - Bit to use for the second green LED. The "Active" LED. - Most Axis products use bit 4 here. - For products with only one controllable LED, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED2R - int "Second red LED bit" - depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS - default "5" - help - Bit to use for the second red LED. - Most Axis products use bit 5 here. - For products with only one controllable LED, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED3G - int "Third green LED bit" - depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS - default "2" - help - Bit to use for the third green LED. The "Drive" LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED3R - int "Third red LED bit" - depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS - default "2" - help - Bit to use for the third red LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED4R - int "Fourth red LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the fourth red LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED4G - int "Fourth green LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the fourth green LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED5R - int "Fifth red LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the fifth red LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED5G - int "Fifth green LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the fifth green LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED6R - int "Sixth red LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the sixth red LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED6G - int "Sixth green LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the sixth green LED. The "Drive" LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED7R - int "Seventh red LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the seventh red LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED7G - int "Seventh green LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the seventh green LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED8Y - int "Eighth yellow LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the eighth yellow LED. The "Drive" LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED9Y - int "Ninth yellow LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the ninth yellow LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED10Y - int "Tenth yellow LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the tenth yellow LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED11Y - int "Eleventh yellow LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the eleventh yellow LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - -config ETRAX_LED12R - int "Twelfth red LED bit" - depends on ETRAX_CSP0_LEDS - default "2" - help - Bit to use for the twelfth red LED. - For products with only one or two controllable LEDs, - set this to same as CONFIG_ETRAX_LED1G (normally 2). - - -choice - prompt "Product rescue-port" - depends on ETRAX_ARCH_V10 - default ETRAX_RESCUE_SER0 - -config ETRAX_RESCUE_SER0 - bool "Serial-0" - help - Select one of the four serial ports as a rescue port. The default - is port 0. - -config ETRAX_RESCUE_SER1 - bool "Serial-1" - help - Use serial port 1 as the rescue port. - -config ETRAX_RESCUE_SER2 - bool "Serial-2" - help - Use serial port 2 as the rescue port. - -config ETRAX_RESCUE_SER3 - bool "Serial-3" - help - Use serial port 3 as the rescue port. - -endchoice - -config ETRAX_DEF_R_WAITSTATES - hex "R_WAITSTATES" - depends on ETRAX_ARCH_V10 - default "95a6" - help - Waitstates for SRAM, Flash and peripherals (not DRAM). 95f8 is a - good choice for most Axis products... - -config ETRAX_DEF_R_BUS_CONFIG - hex "R_BUS_CONFIG" - depends on ETRAX_ARCH_V10 - default "104" - help - Assorted bits controlling write mode, DMA burst length etc. 104 is - a good choice for most Axis products... - -config ETRAX_SDRAM - bool "SDRAM support" - depends on ETRAX_ARCH_V10 - help - Enable this if you use SDRAM chips and configure - R_SDRAM_CONFIG and R_SDRAM_TIMING as well. - -config ETRAX_DEF_R_DRAM_CONFIG - hex "R_DRAM_CONFIG" - depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM - default "1a200040" - help - The R_DRAM_CONFIG register specifies everything on how the DRAM - chips in the system are connected to the ETRAX CPU. This is - different depending on the manufacturer, chip type and number of - chips. So this value often needs to be different for each Axis - product. - -config ETRAX_DEF_R_DRAM_TIMING - hex "R_DRAM_TIMING" - depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM - default "5611" - help - Different DRAM chips have different speeds. Current Axis products - use 50ns DRAM chips which can use the timing: 5611. - -config ETRAX_DEF_R_SDRAM_CONFIG - hex "R_SDRAM_CONFIG" - depends on ETRAX_ARCH_V10 && ETRAX_SDRAM - default "d2fa7878" - help - The R_SDRAM_CONFIG register specifies everything on how the SDRAM - chips in the system are connected to the ETRAX CPU. This is - different depending on the manufacturer, chip type and number of - chips. So this value often needs to be different for each Axis - product. - -config ETRAX_DEF_R_SDRAM_TIMING - hex "R_SDRAM_TIMING" - depends on ETRAX_ARCH_V10 && ETRAX_SDRAM - default "80004801" - help - Different SDRAM chips have different timing. - -config ETRAX_DEF_R_PORT_PA_DIR - hex "R_PORT_PA_DIR" - depends on ETRAX_ARCH_V10 - default "1c" - help - Configures the direction of general port A bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_R_PORT_PA_DATA - hex "R_PORT_PA_DATA" - depends on ETRAX_ARCH_V10 - default "00" - help - Configures the initial data for the general port A bits. Most - products should use 00 here. - -config ETRAX_DEF_R_PORT_PB_CONFIG - hex "R_PORT_PB_CONFIG" - depends on ETRAX_ARCH_V10 - default "00" - help - Configures the type of the general port B bits. 1 is chip select, - 0 is port. Most products should use 00 here. - -config ETRAX_DEF_R_PORT_PB_DIR - hex "R_PORT_PB_DIR" - depends on ETRAX_ARCH_V10 - default "00" - help - Configures the direction of general port B bits. 1 is out, 0 is in. - This is often totally different depending on the product used. Bits - 0 and 1 on port PB are usually used for I2C communication, but the - kernel I2C driver sets the appropriate directions itself so you - don't need to take that into consideration when setting this option. - If you don't know what to use, it is always safe to put all as - inputs. - -config ETRAX_DEF_R_PORT_PB_DATA - hex "R_PORT_PB_DATA" - depends on ETRAX_ARCH_V10 - default "ff" - help - Configures the initial data for the general port A bits. Most - products should use FF here. - -config ETRAX_SOFT_SHUTDOWN - bool "Software Shutdown Support" - depends on ETRAX_ARCH_V10 - help - Enable this if ETRAX is used with a power-supply that can be turned - off and on with PS_ON signal. Gives the possibility to detect - powerbutton and then do a power off after unmounting disks. - -config ETRAX_SHUTDOWN_BIT - int "Shutdown bit on port CSP0" - depends on ETRAX_SOFT_SHUTDOWN - default "12" - help - Configure what pin on CSPO-port that is used for controlling power - supply. - -config ETRAX_POWERBUTTON_BIT - int "Power button bit on port G" - depends on ETRAX_SOFT_SHUTDOWN - default "25" - help - Configure where power button is connected. - -endmenu - -endif diff --git a/arch/cris/arch-v10/README.mm b/arch/cris/arch-v10/README.mm deleted file mode 100644 index 67731d75cb51..000000000000 --- a/arch/cris/arch-v10/README.mm +++ /dev/null @@ -1,244 +0,0 @@ -Memory management for CRIS/MMU ------------------------------- -HISTORY: - -$Log: README.mm,v $ -Revision 1.1 2001/12/17 13:59:27 bjornw -Initial revision - -Revision 1.1 2000/07/10 16:25:21 bjornw -Initial revision - -Revision 1.4 2000/01/17 02:31:59 bjornw -Added discussion of paging and VM. - -Revision 1.3 1999/12/03 16:43:23 hp -Blurb about that the 3.5G-limitation is not a MMU limitation - -Revision 1.2 1999/12/03 16:04:21 hp -Picky comment about not mapping the first page - -Revision 1.1 1999/12/03 15:41:30 bjornw -First version of CRIS/MMU memory layout specification. - - - - - ------------------------------- - -See the ETRAX-NG HSDD for reference. - -We use the page-size of 8 kbytes, as opposed to the i386 page-size of 4 kbytes. - -The MMU can, apart from the normal mapping of pages, also do a top-level -segmentation of the kernel memory space. We use this feature to avoid having -to use page-tables to map the physical memory into the kernel's address -space. We also use it to keep the user-mode virtual mapping in the same -map during kernel-mode, so that the kernel easily can access the corresponding -user-mode process' data. - -As a comparison, the Linux/i386 2.0 puts the kernel and physical RAM at -address 0, overlapping with the user-mode virtual space, so that descriptor -registers are needed for each memory access to specify which MMU space to -map through. That changed in 2.2, putting the kernel/physical RAM at -0xc0000000, to co-exist with the user-mode mapping. We will do something -quite similar, but with the additional complexity of having to map the -internal chip I/O registers and the flash memory area (including SRAM -and peripherial chip-selets). - -The kernel-mode segmentation map: - - ------------------------ ------------------------ -FFFFFFFF| | => cached | | - | kernel seg_f | flash | | -F0000000|______________________| | | -EFFFFFFF| | => uncached | | - | kernel seg_e | flash | | -E0000000|______________________| | DRAM | -DFFFFFFF| | paged to any | Un-cached | - | kernel seg_d | =======> | | -D0000000|______________________| | | -CFFFFFFF| | | | - | kernel seg_c |==\ | | -C0000000|______________________| \ |______________________| -BFFFFFFF| | uncached | | - | kernel seg_b |=====\=========>| Registers | -B0000000|______________________| \c |______________________| -AFFFFFFF| | \a | | - | | \c | FLASH/SRAM/Peripheral| - | | \h |______________________| - | | \e | | - | | \d | | - | kernel seg_0 - seg_a | \==>| DRAM | - | | | Cached | - | | paged to any | | - | | =======> |______________________| - | | | | - | | | Illegal | - | | |______________________| - | | | | - | | | FLASH/SRAM/Peripheral| -00000000|______________________| |______________________| - -In user-mode it looks the same except that only the space 0-AFFFFFFF is -available. Therefore, in this model, the virtual address space per process -is limited to 0xb0000000 bytes (minus 8192 bytes, since the first page, -0..8191, is never mapped, in order to trap NULL references). - -It also means that the total physical RAM that can be mapped is 256 MB -(kseg_c above). More RAM can be mapped by choosing a different segmentation -and shrinking the user-mode memory space. - -The MMU can map all 4 GB in user mode, but doing that would mean that a -few extra instructions would be needed for each access to user mode -memory. - -The kernel needs access to both cached and uncached flash. Uncached is -necessary because of the special write/erase sequences. Also, the -peripherial chip-selects are decoded from that region. - -The kernel also needs its own virtual memory space. That is kseg_d. It -is used by the vmalloc() kernel function to allocate virtual contiguous -chunks of memory not possible using the normal kmalloc physical RAM -allocator. - -The setting of the actual MMU control registers to use this layout would -be something like this: - -R_MMU_KSEG = ( ( seg_f, seg ) | // Flash cached - ( seg_e, seg ) | // Flash uncached - ( seg_d, page ) | // kernel vmalloc area - ( seg_c, seg ) | // kernel linear segment - ( seg_b, seg ) | // kernel linear segment - ( seg_a, page ) | - ( seg_9, page ) | - ( seg_8, page ) | - ( seg_7, page ) | - ( seg_6, page ) | - ( seg_5, page ) | - ( seg_4, page ) | - ( seg_3, page ) | - ( seg_2, page ) | - ( seg_1, page ) | - ( seg_0, page ) ); - -R_MMU_KBASE_HI = ( ( base_f, 0x0 ) | // flash/sram/periph cached - ( base_e, 0x8 ) | // flash/sram/periph uncached - ( base_d, 0x0 ) | // don't care - ( base_c, 0x4 ) | // physical RAM cached area - ( base_b, 0xb ) | // uncached on-chip registers - ( base_a, 0x0 ) | // don't care - ( base_9, 0x0 ) | // don't care - ( base_8, 0x0 ) ); // don't care - -R_MMU_KBASE_LO = ( ( base_7, 0x0 ) | // don't care - ( base_6, 0x0 ) | // don't care - ( base_5, 0x0 ) | // don't care - ( base_4, 0x0 ) | // don't care - ( base_3, 0x0 ) | // don't care - ( base_2, 0x0 ) | // don't care - ( base_1, 0x0 ) | // don't care - ( base_0, 0x0 ) ); // don't care - -NOTE: while setting up the MMU, we run in a non-mapped mode in the DRAM (0x40 -segment) and need to setup the seg_4 to a unity mapping, so that we don't get -a fault before we have had time to jump into the real kernel segment (0xc0). This -is done in head.S temporarily, but fixed by the kernel later in paging_init. - - -Paging - PTE's, PMD's and PGD's -------------------------------- - -[ References: asm/pgtable.h, asm/page.h, asm/mmu.h ] - -The paging mechanism uses virtual addresses to split a process memory-space into -pages, a page being the smallest unit that can be freely remapped in memory. On -Linux/CRIS, a page is 8192 bytes (for technical reasons not equal to 4096 as in -most other 32-bit architectures). It would be inefficient to let a virtual memory -mapping be controlled by a long table of page mappings, so it is broken down into -a 2-level structure with a Page Directory containing pointers to Page Tables which -each have maps of up to 2048 pages (8192 / sizeof(void *)). Linux can actually -handle 3-level structures as well, with a Page Middle Directory in between, but -in many cases, this is folded into a two-level structure by excluding the Middle -Directory. - -We'll take a look at how an address is translated while we discuss how it's handled -in the Linux kernel. - -The example address is 0xd004000c; in binary this is: - -31 23 15 7 0 -11010000 00000100 00000000 00001100 - -|______| |__________||____________| - PGD PTE page offset - -Given the top-level Page Directory, the offset in that directory is calculated -using the upper 8 bits: - -static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) -{ - return mm->pgd + (address >> PGDIR_SHIFT); -} - -PGDIR_SHIFT is the log2 of the amount of memory an entry in the PGD can map; in our -case it is 24, corresponding to 16 MB. This means that each entry in the PGD -corresponds to 16 MB of virtual memory. - -The pgd_t from our example will therefore be the 208'th (0xd0) entry in mm->pgd. - -Since the Middle Directory does not exist, it is a unity mapping: - -static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) -{ - return (pmd_t *) dir; -} - -The Page Table provides the final lookup by using bits 13 to 23 as index: - -static inline pte_t * pte_offset(pmd_t * dir, unsigned long address) -{ - return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & - (PTRS_PER_PTE - 1)); -} - -PAGE_SHIFT is the log2 of the size of a page; 13 in our case. PTRS_PER_PTE is -the number of pointers that fit in a Page Table and is used to mask off the -PGD-part of the address. - -The so-far unused bits 0 to 12 are used to index inside a page linearily. - -The VM system -------------- - -The kernels own page-directory is the swapper_pg_dir, cleared in paging_init, -and contains the kernels virtual mappings (the kernel itself is not paged - it -is mapped linearily using kseg_c as described above). Architectures without -kernel segments like the i386, need to setup swapper_pg_dir directly in head.S -to map the kernel itself. swapper_pg_dir is pointed to by init_mm.pgd as the -init-task's PGD. - -To see what support functions are used to setup a page-table, let's look at the -kernel's internal paged memory system, vmalloc/vfree. - -void * vmalloc(unsigned long size) - -The vmalloc-system keeps a paged segment in kernel-space at 0xd0000000. What -happens first is that a virtual address chunk is allocated to the request using -get_vm_area(size). After that, physical RAM pages are allocated and put into -the kernel's page-table using alloc_area_pages(addr, size). - -static int alloc_area_pages(unsigned long address, unsigned long size) - -First the PGD entry is found using init_mm.pgd. This is passed to -alloc_area_pmd (remember the 3->2 folding). It uses pte_alloc_kernel to -check if the PGD entry points anywhere - if not, a page table page is -allocated and the PGD entry updated. Then the alloc_area_pte function is -used just like alloc_area_pmd to check which page table entry is desired, -and a physical page is allocated and the table entry updated. All of this -is repeated at the top-level until the entire address range specified has -been mapped. - - - diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig deleted file mode 100644 index 8792af63c049..000000000000 --- a/arch/cris/arch-v10/drivers/Kconfig +++ /dev/null @@ -1,561 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ETRAX_ARCH_V10 - -config ETRAX_ETHERNET - bool "Ethernet support" - depends on ETRAX_ARCH_V10 && NETDEVICES - select MII - help - This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet - controller. - -config ETRAX_SERIAL - bool "Serial-port support" - depends on ETRAX_ARCH_V10 - help - Enables the ETRAX 100 serial driver for ser0 (ttyS0) - You probably want this enabled. - -config ETRAX_SERIAL_FAST_TIMER - bool "Use fast timers for serial DMA flush (experimental)" - depends on ETRAX_SERIAL - help - Select this to have the serial DMAs flushed at a higher rate than - normally, possible by using the fast timer API, the timeout is - approx. 4 character times. - If unsure, say N. - -config ETRAX_SERIAL_FLUSH_DMA_FAST - bool "Fast serial port DMA flush" - depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER - help - Select this to have the serial DMAs flushed at a higher rate than - normally possible through a fast timer interrupt (currently at - 15360 Hz). - If unsure, say N. - -config ETRAX_SERIAL_RX_TIMEOUT_TICKS - int "Receive flush timeout (ticks) " - depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER && !ETRAX_SERIAL_FLUSH_DMA_FAST - default "5" - help - Number of timer ticks between flush of receive fifo (1 tick = 10ms). - Try 0-3 for low latency applications. Approx 5 for high load - applications (e.g. PPP). Maybe this should be more adaptive some - day... - -config ETRAX_SERIAL_PORT0 - bool "Serial port 0 enabled" - depends on ETRAX_SERIAL - help - Enables the ETRAX 100 serial driver for ser0 (ttyS0) - Normally you want this on, unless you use external DMA 1 that uses - the same DMA channels. - -choice - prompt "Ser0 DTR, RI, DSR and CD assignment" - depends on ETRAX_SERIAL_PORT0 - default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE - -config ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE - bool "No_DTR_RI_DSR_CD" - -config ETRAX_SER0_DTR_RI_DSR_CD_ON_PA - bool "DTR_RI_DSR_CD_on_PA" - -config ETRAX_SER0_DTR_RI_DSR_CD_ON_PB - bool "DTR_RI_DSR_CD_on_PB" - help - Enables the status and control signals DTR, RI, DSR and CD on PB for - ser0. - -config ETRAX_SER0_DTR_RI_DSR_CD_MIXED - bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" - -endchoice - -config ETRAX_SER0_DTR_ON_PA_BIT - int "Ser0 DTR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER0_RI_ON_PA_BIT - int "Ser0 RI on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER0_DSR_ON_PA_BIT - int "Ser0 DSR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER0_CD_ON_PA_BIT - int "Ser0 CD on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER0_DTR_ON_PB_BIT - int "Ser0 DTR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the DTR signal for serial - port 0. - -config ETRAX_SER0_RI_ON_PB_BIT - int "Ser0 RI on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the RI signal for serial - port 0. - -config ETRAX_SER0_DSR_ON_PB_BIT - int "Ser0 DSR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the DSR signal for serial - port 0. - -config ETRAX_SER0_CD_ON_PB_BIT - int "Ser0 CD on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT0 - default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED - default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the CD signal for serial - port 0. - -config ETRAX_SERIAL_PORT1 - bool "Serial port 1 enabled" - depends on ETRAX_SERIAL - help - Enables the ETRAX 100 serial driver for ser1 (ttyS1). - -choice - prompt "Ser1 DTR, RI, DSR and CD assignment" - depends on ETRAX_SERIAL_PORT1 - default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE - -config ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE - bool "No_DTR_RI_DSR_CD" - -config ETRAX_SER1_DTR_RI_DSR_CD_ON_PA - bool "DTR_RI_DSR_CD_on_PA" - -config ETRAX_SER1_DTR_RI_DSR_CD_ON_PB - bool "DTR_RI_DSR_CD_on_PB" - help - Enables the status and control signals DTR, RI, DSR and CD on PB for - ser1. - -config ETRAX_SER1_DTR_RI_DSR_CD_MIXED - bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" - -endchoice - -config ETRAX_SER1_DTR_ON_PA_BIT - int "Ser1 DTR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER1_RI_ON_PA_BIT - int "Ser1 RI on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER1_DSR_ON_PA_BIT - int "Ser1 DSR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER1_CD_ON_PA_BIT - int "Ser1 CD on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER1_DTR_ON_PB_BIT - int "Ser1 DTR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the DTR signal for serial - port 1. - -config ETRAX_SER1_RI_ON_PB_BIT - int "Ser1 RI on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the RI signal for serial - port 1. - -config ETRAX_SER1_DSR_ON_PB_BIT - int "Ser1 DSR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the DSR signal for serial - port 1. - -config ETRAX_SER1_CD_ON_PB_BIT - int "Ser1 CD on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT1 - default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED - default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PB port to carry the CD signal for serial - port 1. - -comment "Make sure you do not have the same PB bits more than once!" - depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB - -config ETRAX_SERIAL_PORT2 - bool "Serial port 2 enabled" - depends on ETRAX_SERIAL - help - Enables the ETRAX 100 serial driver for ser2 (ttyS2). - -choice - prompt "Ser2 DTR, RI, DSR and CD assignment" - depends on ETRAX_SERIAL_PORT2 - default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE - -config ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE - bool "No_DTR_RI_DSR_CD" - -config ETRAX_SER2_DTR_RI_DSR_CD_ON_PA - bool "DTR_RI_DSR_CD_on_PA" - help - Enables the status and control signals DTR, RI, DSR and CD on PA for - ser2. - -config ETRAX_SER2_DTR_RI_DSR_CD_ON_PB - bool "DTR_RI_DSR_CD_on_PB" - -config ETRAX_SER2_DTR_RI_DSR_CD_MIXED - bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" - -endchoice - -config ETRAX_SER2_DTR_ON_PA_BIT - int "Ser2 DTR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PA port to carry the DTR signal for serial - port 2. - -config ETRAX_SER2_RI_ON_PA_BIT - int "Ser2 RI on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PA port to carry the RI signal for serial - port 2. - -config ETRAX_SER2_DSR_ON_PA_BIT - int "Ser2 DSR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PA port to carry the DTR signal for serial - port 2. - -config ETRAX_SER2_CD_ON_PA_BIT - int "Ser2 CD on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - help - Specify the pin of the PA port to carry the CD signal for serial - port 2. - -config ETRAX_SER2_DTR_ON_PB_BIT - int "Ser2 DTR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER2_RI_ON_PB_BIT - int "Ser2 RI on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER2_DSR_ON_PB_BIT - int "Ser2 DSR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - -config ETRAX_SER2_CD_ON_PB_BIT - int "Ser2 CD on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT2 - default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED - default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED - -config ETRAX_SERIAL_PORT3 - bool "Serial port 3 enabled" - depends on ETRAX_SERIAL - help - Enables the ETRAX 100 serial driver for ser3 (ttyS3). - -choice - prompt "Ser3 DTR, RI, DSR and CD assignment" - depends on ETRAX_SERIAL_PORT3 - default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE - -config ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE - bool "No_DTR_RI_DSR_CD" - -config ETRAX_SER3_DTR_RI_DSR_CD_ON_PA - bool "DTR_RI_DSR_CD_on_PA" - -config ETRAX_SER3_DTR_RI_DSR_CD_ON_PB - bool "DTR_RI_DSR_CD_on_PB" - -config ETRAX_SER3_DTR_RI_DSR_CD_MIXED - bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB" - -endchoice - -config ETRAX_SER3_DTR_ON_PA_BIT - int "Ser3 DTR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_RI_ON_PA_BIT - int "Ser3 RI on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_DSR_ON_PA_BIT - int "Ser3 DSR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_CD_ON_PA_BIT - int "Ser3 CD on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_DTR_ON_PB_BIT - int "Ser3 DTR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_RI_ON_PB_BIT - int "Ser3 RI on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_DSR_ON_PB_BIT - int "Ser3 DSR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_SER3_CD_ON_PB_BIT - int "Ser3 CD on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED - depends on ETRAX_SERIAL_PORT3 - default "-1" - -config ETRAX_RS485 - bool "RS-485 support" - depends on ETRAX_SERIAL - help - Enables support for RS-485 serial communication. For a primer on - RS-485, see - -config ETRAX_RS485_ON_PA - bool "RS-485 mode on PA" - depends on ETRAX_RS485 - help - Control Driver Output Enable on RS485 transceiver using a pin on PA - port: - Axis 2400/2401 uses PA 3. - -config ETRAX_RS485_ON_PA_BIT - int "RS-485 mode on PA bit" - depends on ETRAX_RS485_ON_PA - default "3" - help - Control Driver Output Enable on RS485 transceiver using a this bit - on PA port. - -config ETRAX_RS485_DISABLE_RECEIVER - bool "Disable serial receiver" - depends on ETRAX_RS485 - help - It's necessary to disable the serial receiver to avoid serial - loopback. Not all products are able to do this in software only. - Axis 2400/2401 must disable receiver. - -config ETRAX_USB_HOST - bool "USB host" - select USB - help - This option enables the host functionality of the ETRAX 100LX - built-in USB controller. In host mode the controller is designed - for CTRL and BULK traffic only, INTR traffic may work as well - however (depending on the requirements of timeliness). - -config ETRAX_PTABLE_SECTOR - int "Byte-offset of partition table sector" - depends on ETRAX_AXISFLASHMAP - default "65536" - help - Byte-offset of the partition table in the first flash chip. - The default value is 64kB and should not be changed unless - you know exactly what you are doing. The only valid reason - for changing this is when the flash block size is bigger - than 64kB (e.g. when using two parallel 16 bit flashes). - -config ETRAX_I2C - bool "I2C support" - depends on ETRAX_ARCH_V10 - help - Enables an I2C driver on ETRAX100. - EXAMPLE usage: - i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); - ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); - i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); - val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); - -# this is true for most products since PB-I2C seems to be somewhat -# flawed.. -config ETRAX_I2C_USES_PB_NOT_PB_I2C - bool "I2C uses PB not PB-I2C" - depends on ETRAX_I2C - help - Select whether to use the special I2C mode in the PB I/O register or - not. This option needs to be selected in order to use some drivers - that access the I2C I/O pins directly instead of going through the - I2C driver, like the DS1302 realtime-clock driver. If you are - uncertain, choose Y here. - -config ETRAX_I2C_DATA_PORT - int "I2C SDA bit number" - depends on ETRAX_I2C_USES_PB_NOT_PB_I2C - default "0" - help - Selects the pin on Port B where the data pin is connected - -config ETRAX_I2C_CLK_PORT - int "I2C SCL bit number" - depends on ETRAX_I2C_USES_PB_NOT_PB_I2C - default "1" - help - Select the pin on Port B where the clock pin is connected - -config ETRAX_I2C_EEPROM - bool "I2C EEPROM (non-volatile RAM) support" - depends on ETRAX_I2C - help - Enables I2C EEPROM (non-volatile RAM) on PB0 and PB1 using the I2C - driver. Select size option: Probed, 2k, 8k, 16k. - (Probing works for 2k and 8k but not that well for 16k) - -choice - prompt "EEPROM size" - depends on ETRAX_I2C_EEPROM - default ETRAX_I2C_EEPROM_PROBE - -config ETRAX_I2C_EEPROM_PROBE - bool "Probed" - help - Specifies size or auto probe of the EEPROM size. - Options: Probed, 2k, 8k, 16k. - (Probing works for 2k and 8k but not that well for 16k) - -config ETRAX_I2C_EEPROM_2KB - bool "2kB" - help - Use a 2kB EEPROM. - -config ETRAX_I2C_EEPROM_8KB - bool "8kB" - help - Use a 8kB EEPROM. - -config ETRAX_I2C_EEPROM_16KB - bool "16kB" - help - Use a 16kB EEPROM. - -endchoice - -config ETRAX_GPIO - bool "GPIO support" - depends on ETRAX_ARCH_V10 - ---help--- - Enables the ETRAX general port device (major 120, minors 0 and 1). - You can use this driver to access the general port bits. It supports - these ioctl's: - #include - fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob - ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set); - ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear); - val = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READBITS), NULL); - Remember that you need to setup the port directions appropriately in - the General configuration. - -config ETRAX_PA_CHANGEABLE_DIR - hex "PA user changeable dir mask" - depends on ETRAX_GPIO - default "00" - help - This is a bitmask with information of what bits in PA that a user - can change direction on using ioctl's. - Bit set = changeable. - You probably want 00 here. - -config ETRAX_PA_CHANGEABLE_BITS - hex "PA user changeable bits mask" - depends on ETRAX_GPIO - default "FF" - help - This is a bitmask with information of what bits in PA that a user - can change the value on using ioctl's. - Bit set = changeable. - You probably want 00 here. - -config ETRAX_PB_CHANGEABLE_DIR - hex "PB user changeable dir mask" - depends on ETRAX_GPIO - default "00" - help - This is a bitmask with information of what bits in PB that a user - can change direction on using ioctl's. - Bit set = changeable. - You probably want 00 here. - -config ETRAX_PB_CHANGEABLE_BITS - hex "PB user changeable bits mask" - depends on ETRAX_GPIO - default "FF" - help - This is a bitmask with information of what bits in PB that a user - can change the value on using ioctl's. - Bit set = changeable. - You probably want 00 here. - -endif diff --git a/arch/cris/arch-v10/drivers/Makefile b/arch/cris/arch-v10/drivers/Makefile deleted file mode 100644 index d5549dca81bf..000000000000 --- a/arch/cris/arch-v10/drivers/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for Etrax-specific drivers -# - -obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o -obj-$(CONFIG_ETRAX_I2C) += i2c.o -obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o -obj-$(CONFIG_ETRAX_GPIO) += gpio.o -obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o - diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c deleted file mode 100644 index 28292da49664..000000000000 --- a/arch/cris/arch-v10/drivers/axisflashmap.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Physical mapping layer for MTD using the Axis partitiontable format - * - * Copyright (c) 2001, 2002 Axis Communications AB - * - * This file is under the GPL. - * - * First partition is always sector 0 regardless of if we find a partitiontable - * or not. In the start of the next sector, there can be a partitiontable that - * tells us what other partitions to define. If there isn't, we use a default - * partition split defined below. - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_CRIS_LOW_MAP -#define FLASH_UNCACHED_ADDR KSEG_8 -#define FLASH_CACHED_ADDR KSEG_5 -#else -#define FLASH_UNCACHED_ADDR KSEG_E -#define FLASH_CACHED_ADDR KSEG_F -#endif - -#if CONFIG_ETRAX_FLASH_BUSWIDTH==1 -#define flash_data __u8 -#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2 -#define flash_data __u16 -#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4 -#define flash_data __u32 -#endif - -/* From head.S */ -extern unsigned long romfs_start, romfs_length, romfs_in_flash; - -/* The master mtd for the entire flash. */ -struct mtd_info* axisflash_mtd = NULL; - -/* Map driver functions. */ - -static map_word flash_read(struct map_info *map, unsigned long ofs) -{ - map_word tmp; - tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs); - return tmp; -} - -static void flash_copy_from(struct map_info *map, void *to, - unsigned long from, ssize_t len) -{ - memcpy(to, (void *)(map->map_priv_1 + from), len); -} - -static void flash_write(struct map_info *map, map_word d, unsigned long adr) -{ - *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0]; -} - -/* - * The map for chip select e0. - * - * We run into tricky coherence situations if we mix cached with uncached - * accesses to we only use the uncached version here. - * - * The size field is the total size where the flash chips may be mapped on the - * chip select. MTD probes should find all devices there and it does not matter - * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD - * probes will ignore them. - * - * The start address in map_priv_1 is in virtual memory so we cannot use - * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start - * address of cse0. - */ -static struct map_info map_cse0 = { - .name = "cse0", - .size = MEM_CSE0_SIZE, - .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, - .read = flash_read, - .copy_from = flash_copy_from, - .write = flash_write, - .map_priv_1 = FLASH_UNCACHED_ADDR -}; - -/* - * The map for chip select e1. - * - * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong - * address, but there isn't. - */ -static struct map_info map_cse1 = { - .name = "cse1", - .size = MEM_CSE1_SIZE, - .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, - .read = flash_read, - .copy_from = flash_copy_from, - .write = flash_write, - .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE -}; - -/* If no partition-table was found, we use this default-set. */ -#define MAX_PARTITIONS 7 -#define NUM_DEFAULT_PARTITIONS 3 - -/* - * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the - * size of one flash block and "filesystem"-partition needs 5 blocks to be able - * to use JFFS. - */ -static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { - { - .name = "boot firmware", - .size = CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0 - }, - { - .name = "kernel", - .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), - .offset = CONFIG_ETRAX_PTABLE_SECTOR - }, - { - .name = "filesystem", - .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) - } -}; - -/* Initialize the ones normally used. */ -static struct mtd_partition axis_partitions[MAX_PARTITIONS] = { - { - .name = "part0", - .size = CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0 - }, - { - .name = "part1", - .size = 0, - .offset = 0 - }, - { - .name = "part2", - .size = 0, - .offset = 0 - }, - { - .name = "part3", - .size = 0, - .offset = 0 - }, - { - .name = "part4", - .size = 0, - .offset = 0 - }, - { - .name = "part5", - .size = 0, - .offset = 0 - }, - { - .name = "part6", - .size = 0, - .offset = 0 - }, -}; - -/* - * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash - * chips in that order (because the amd_flash-driver is faster). - */ -static struct mtd_info *probe_cs(struct map_info *map_cs) -{ - struct mtd_info *mtd_cs = NULL; - - printk(KERN_INFO - "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n", - map_cs->name, map_cs->size, map_cs->map_priv_1); - -#ifdef CONFIG_MTD_CFI - mtd_cs = do_map_probe("cfi_probe", map_cs); -#endif -#ifdef CONFIG_MTD_JEDECPROBE - if (!mtd_cs) - mtd_cs = do_map_probe("jedec_probe", map_cs); -#endif - - return mtd_cs; -} - -/* - * Probe each chip select individually for flash chips. If there are chips on - * both cse0 and cse1, the mtd_info structs will be concatenated to one struct - * so that MTD partitions can cross chip boundaries. - * - * The only known restriction to how you can mount your chips is that each - * chip select must hold similar flash chips. But you need external hardware - * to do that anyway and you can put totally different chips on cse0 and cse1 - * so it isn't really much of a restriction. - */ -static struct mtd_info *flash_probe(void) -{ - struct mtd_info *mtd_cse0; - struct mtd_info *mtd_cse1; - struct mtd_info *mtd_cse; - - mtd_cse0 = probe_cs(&map_cse0); - mtd_cse1 = probe_cs(&map_cse1); - - if (!mtd_cse0 && !mtd_cse1) { - /* No chip found. */ - return NULL; - } - - if (mtd_cse0 && mtd_cse1) { - struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 }; - - /* Since the concatenation layer adds a small overhead we - * could try to figure out if the chips in cse0 and cse1 are - * identical and reprobe the whole cse0+cse1 window. But since - * flash chips are slow, the overhead is relatively small. - * So we use the MTD concatenation layer instead of further - * complicating the probing procedure. - */ - mtd_cse = mtd_concat_create(mtds, ARRAY_SIZE(mtds), - "cse0+cse1"); - if (!mtd_cse) { - printk(KERN_ERR "%s and %s: Concatenation failed!\n", - map_cse0.name, map_cse1.name); - - /* The best we can do now is to only use what we found - * at cse0. - */ - mtd_cse = mtd_cse0; - map_destroy(mtd_cse1); - } - } else { - mtd_cse = mtd_cse0? mtd_cse0 : mtd_cse1; - } - - return mtd_cse; -} - -/* - * Probe the flash chip(s) and, if it succeeds, read the partition-table - * and register the partitions with MTD. - */ -static int __init init_axis_flash(void) -{ - struct mtd_info *mymtd; - int err = 0; - int pidx = 0; - struct partitiontable_head *ptable_head = NULL; - struct partitiontable_entry *ptable; - int use_default_ptable = 1; /* Until proven otherwise. */ - const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n"; - - if (!(mymtd = flash_probe())) { - /* There's no reason to use this module if no flash chip can - * be identified. Make sure that's understood. - */ - printk(KERN_INFO "axisflashmap: Found no flash chip.\n"); - } else { - printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n", - mymtd->name, mymtd->size); - axisflash_mtd = mymtd; - } - - if (mymtd) { - mymtd->owner = THIS_MODULE; - ptable_head = (struct partitiontable_head *)(FLASH_CACHED_ADDR + - CONFIG_ETRAX_PTABLE_SECTOR + - PARTITION_TABLE_OFFSET); - } - pidx++; /* First partition is always set to the default. */ - - if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC) - && (ptable_head->size < - (MAX_PARTITIONS * sizeof(struct partitiontable_entry) + - PARTITIONTABLE_END_MARKER_SIZE)) - && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) + - ptable_head->size - - PARTITIONTABLE_END_MARKER_SIZE) - == PARTITIONTABLE_END_MARKER)) { - /* Looks like a start, sane length and end of a - * partition table, lets check csum etc. - */ - int ptable_ok = 0; - struct partitiontable_entry *max_addr = - (struct partitiontable_entry *) - ((unsigned long)ptable_head + sizeof(*ptable_head) + - ptable_head->size); - unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR; - unsigned char *p; - unsigned long csum = 0; - - ptable = (struct partitiontable_entry *) - ((unsigned long)ptable_head + sizeof(*ptable_head)); - - /* Lets be PARANOID, and check the checksum. */ - p = (unsigned char*) ptable; - - while (p <= (unsigned char*)max_addr) { - csum += *p++; - csum += *p++; - csum += *p++; - csum += *p++; - } - ptable_ok = (csum == ptable_head->checksum); - - /* Read the entries and use/show the info. */ - printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n", - (ptable_ok ? " valid" : "n invalid"), ptable_head, - max_addr); - - /* We have found a working bootblock. Now read the - * partition table. Scan the table. It ends when - * there is 0xffffffff, that is, empty flash. - */ - while (ptable_ok - && ptable->offset != 0xffffffff - && ptable < max_addr - && pidx < MAX_PARTITIONS) { - - axis_partitions[pidx].offset = offset + ptable->offset; - axis_partitions[pidx].size = ptable->size; - - printk(pmsg, pidx, axis_partitions[pidx].offset, - axis_partitions[pidx].size); - pidx++; - ptable++; - } - use_default_ptable = !ptable_ok; - } - - if (romfs_in_flash) { - /* Add an overlapping device for the root partition (romfs). */ - - axis_partitions[pidx].name = "romfs"; - axis_partitions[pidx].size = romfs_length; - axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; - axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; - - printk(KERN_INFO - " Adding readonly flash partition for romfs image:\n"); - printk(pmsg, pidx, axis_partitions[pidx].offset, - axis_partitions[pidx].size); - pidx++; - } - - if (mymtd) { - if (use_default_ptable) { - printk(KERN_INFO " Using default partition table.\n"); - err = mtd_device_register(mymtd, - axis_default_partitions, - NUM_DEFAULT_PARTITIONS); - } else { - err = mtd_device_register(mymtd, axis_partitions, - pidx); - } - - if (err) - panic("axisflashmap could not add MTD partitions!\n"); - } - - if (!romfs_in_flash) { - /* Create an RAM device for the root partition (romfs). */ - -#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) - /* No use trying to boot this kernel from RAM. Panic! */ - printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " - "device due to kernel (mis)configuration!\n"); - panic("This kernel cannot boot from RAM!\n"); -#else - struct mtd_info *mtd_ram; - - mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); - if (!mtd_ram) - panic("axisflashmap couldn't allocate memory for " - "mtd_info!\n"); - - printk(KERN_INFO " Adding RAM partition for romfs image:\n"); - printk(pmsg, pidx, (unsigned)romfs_start, - (unsigned)romfs_length); - - err = mtdram_init_device(mtd_ram, - (void *)romfs_start, - romfs_length, - "romfs"); - if (err) - panic("axisflashmap could not initialize MTD RAM " - "device!\n"); -#endif - } - return err; -} - -/* This adds the above to the kernels init-call chain. */ -module_init(init_axis_flash); - -EXPORT_SYMBOL(axisflash_mtd); diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c deleted file mode 100644 index 2d312c8a4dd5..000000000000 --- a/arch/cris/arch-v10/drivers/eeprom.c +++ /dev/null @@ -1,852 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*!***************************************************************************** -*! -*! Implements an interface for i2c compatible eeproms to run under Linux. -*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by -*! Johan.Adolfsson@axis.com -*! -*! Probing results: -*! 8k or not is detected (the assumes 2k or 16k) -*! 2k or 16k detected using test reads and writes. -*! -*!------------------------------------------------------------------------ -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! Aug 28 1999 Edgar Iglesias Initial Version -*! Aug 31 1999 Edgar Iglesias Allow simultaneous users. -*! Sep 03 1999 Edgar Iglesias Updated probe. -*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted -*! in the spin-lock. -*! -*! (c) 1999 Axis Communications AB, Lund, Sweden -*!*****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "i2c.h" - -#define D(x) - -/* If we should use adaptive timing or not: */ -/* #define EEPROM_ADAPTIVE_TIMING */ - -#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */ -#define EEPROM_MINOR_NR 0 - -/* Empirical sane initial value of the delay, the value will be adapted to - * what the chip needs when using EEPROM_ADAPTIVE_TIMING. - */ -#define INITIAL_WRITEDELAY_US 4000 -#define MAX_WRITEDELAY_US 10000 /* 10 ms according to spec for 2KB EEPROM */ - -/* This one defines how many times to try when eeprom fails. */ -#define EEPROM_RETRIES 10 - -#define EEPROM_2KB (2 * 1024) -/*#define EEPROM_4KB (4 * 1024)*/ /* Exists but not used in Axis products */ -#define EEPROM_8KB (8 * 1024 - 1 ) /* Last byte has write protection bit */ -#define EEPROM_16KB (16 * 1024) - -#define i2c_delay(x) udelay(x) - -/* - * This structure describes the attached eeprom chip. - * The values are probed for. - */ - -struct eeprom_type -{ - unsigned long size; - unsigned long sequential_write_pagesize; - unsigned char select_cmd; - unsigned long usec_delay_writecycles; /* Min time between write cycles - (up to 10ms for some models) */ - unsigned long usec_delay_step; /* For adaptive algorithm */ - int adapt_state; /* 1 = To high , 0 = Even, -1 = To low */ - - /* this one is to keep the read/write operations atomic */ - struct mutex lock; - int retry_cnt_addr; /* Used to keep track of number of retries for - adaptive timing adjustments */ - int retry_cnt_read; -}; - -static int eeprom_open(struct inode * inode, struct file * file); -static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig); -static ssize_t eeprom_read(struct file * file, char * buf, size_t count, - loff_t *off); -static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, - loff_t *off); -static int eeprom_close(struct inode * inode, struct file * file); - -static int eeprom_address(unsigned long addr); -static int read_from_eeprom(char * buf, int count); -static int eeprom_write_buf(loff_t addr, const char * buf, int count); -static int eeprom_read_buf(loff_t addr, char * buf, int count); - -static void eeprom_disable_write_protect(void); - - -static const char eeprom_name[] = "eeprom"; - -/* chip description */ -static struct eeprom_type eeprom; - -/* This is the exported file-operations structure for this device. */ -const struct file_operations eeprom_fops = -{ - .llseek = eeprom_lseek, - .read = eeprom_read, - .write = eeprom_write, - .open = eeprom_open, - .release = eeprom_close -}; - -/* eeprom init call. Probes for different eeprom models. */ - -int __init eeprom_init(void) -{ - mutex_init(&eeprom.lock); - -#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE -#define EETEXT "Found" -#else -#define EETEXT "Assuming" -#endif - if (register_chrdev(EEPROM_MAJOR_NR, eeprom_name, &eeprom_fops)) - { - printk(KERN_INFO "%s: unable to get major %d for eeprom device\n", - eeprom_name, EEPROM_MAJOR_NR); - return -1; - } - - printk("EEPROM char device v0.3, (c) 2000 Axis Communications AB\n"); - - /* - * Note: Most of this probing method was taken from the printserver (5470e) - * codebase. It did not contain a way of finding the 16kB chips - * (M24128 or variants). The method used here might not work - * for all models. If you encounter problems the easiest way - * is probably to define your model within #ifdef's, and hard- - * code it. - */ - - eeprom.size = 0; - eeprom.usec_delay_writecycles = INITIAL_WRITEDELAY_US; - eeprom.usec_delay_step = 128; - eeprom.adapt_state = 0; - -#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE - i2c_start(); - i2c_outbyte(0x80); - if(!i2c_getack()) - { - /* It's not 8k.. */ - int success = 0; - unsigned char buf_2k_start[16]; - - /* Im not sure this will work... :) */ - /* assume 2kB, if failure go for 16kB */ - /* Test with 16kB settings.. */ - /* If it's a 2kB EEPROM and we address it outside it's range - * it will mirror the address space: - * 1. We read two locations (that are mirrored), - * if the content differs * it's a 16kB EEPROM. - * 2. if it doesn't differ - write different value to one of the locations, - * check the other - if content still is the same it's a 2k EEPROM, - * restore original data. - */ -#define LOC1 8 -#define LOC2 (0x1fb) /*1fb, 3ed, 5df, 7d1 */ - - /* 2k settings */ - i2c_stop(); - eeprom.size = EEPROM_2KB; - eeprom.select_cmd = 0xA0; - eeprom.sequential_write_pagesize = 16; - if( eeprom_read_buf( 0, buf_2k_start, 16 ) == 16 ) - { - D(printk("2k start: '%16.16s'\n", buf_2k_start)); - } - else - { - printk(KERN_INFO "%s: Failed to read in 2k mode!\n", eeprom_name); - } - - /* 16k settings */ - eeprom.size = EEPROM_16KB; - eeprom.select_cmd = 0xA0; - eeprom.sequential_write_pagesize = 64; - - { - unsigned char loc1[4], loc2[4], tmp[4]; - if( eeprom_read_buf(LOC2, loc2, 4) == 4) - { - if( eeprom_read_buf(LOC1, loc1, 4) == 4) - { - D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", - LOC1, loc1, LOC2, loc2)); -#if 0 - if (memcmp(loc1, loc2, 4) != 0 ) - { - /* It's 16k */ - printk(KERN_INFO "%s: 16k detected in step 1\n", eeprom_name); - eeprom.size = EEPROM_16KB; - success = 1; - } - else -#endif - { - /* Do step 2 check */ - /* Invert value */ - loc1[0] = ~loc1[0]; - if (eeprom_write_buf(LOC1, loc1, 1) == 1) - { - /* If 2k EEPROM this write will actually write 10 bytes - * from pos 0 - */ - D(printk("1 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", - LOC1, loc1, LOC2, loc2)); - if( eeprom_read_buf(LOC1, tmp, 4) == 4) - { - D(printk("2 loc1: (%i) '%4.4s' tmp '%4.4s'\n", - LOC1, loc1, tmp)); - if (memcmp(loc1, tmp, 4) != 0 ) - { - printk(KERN_INFO "%s: read and write differs! Not 16kB\n", - eeprom_name); - loc1[0] = ~loc1[0]; - - if (eeprom_write_buf(LOC1, loc1, 1) == 1) - { - success = 1; - } - else - { - printk(KERN_INFO "%s: Restore 2k failed during probe," - " EEPROM might be corrupt!\n", eeprom_name); - - } - i2c_stop(); - /* Go to 2k mode and write original data */ - eeprom.size = EEPROM_2KB; - eeprom.select_cmd = 0xA0; - eeprom.sequential_write_pagesize = 16; - if( eeprom_write_buf(0, buf_2k_start, 16) == 16) - { - } - else - { - printk(KERN_INFO "%s: Failed to write back 2k start!\n", - eeprom_name); - } - - eeprom.size = EEPROM_2KB; - } - } - - if(!success) - { - if( eeprom_read_buf(LOC2, loc2, 1) == 1) - { - D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n", - LOC1, loc1, LOC2, loc2)); - if (memcmp(loc1, loc2, 4) == 0 ) - { - /* Data the same, must be mirrored -> 2k */ - /* Restore data */ - printk(KERN_INFO "%s: 2k detected in step 2\n", eeprom_name); - loc1[0] = ~loc1[0]; - if (eeprom_write_buf(LOC1, loc1, 1) == 1) - { - success = 1; - } - else - { - printk(KERN_INFO "%s: Restore 2k failed during probe," - " EEPROM might be corrupt!\n", eeprom_name); - - } - - eeprom.size = EEPROM_2KB; - } - else - { - printk(KERN_INFO "%s: 16k detected in step 2\n", - eeprom_name); - loc1[0] = ~loc1[0]; - /* Data differs, assume 16k */ - /* Restore data */ - if (eeprom_write_buf(LOC1, loc1, 1) == 1) - { - success = 1; - } - else - { - printk(KERN_INFO "%s: Restore 16k failed during probe," - " EEPROM might be corrupt!\n", eeprom_name); - } - - eeprom.size = EEPROM_16KB; - } - } - } - } - } /* read LOC1 */ - } /* address LOC1 */ - if (!success) - { - printk(KERN_INFO "%s: Probing failed!, using 2KB!\n", eeprom_name); - eeprom.size = EEPROM_2KB; - } - } /* read */ - } - } - else - { - i2c_outbyte(0x00); - if(!i2c_getack()) - { - /* No 8k */ - eeprom.size = EEPROM_2KB; - } - else - { - i2c_start(); - i2c_outbyte(0x81); - if (!i2c_getack()) - { - eeprom.size = EEPROM_2KB; - } - else - { - /* It's a 8kB */ - i2c_inbyte(); - eeprom.size = EEPROM_8KB; - } - } - } - i2c_stop(); -#elif defined(CONFIG_ETRAX_I2C_EEPROM_16KB) - eeprom.size = EEPROM_16KB; -#elif defined(CONFIG_ETRAX_I2C_EEPROM_8KB) - eeprom.size = EEPROM_8KB; -#elif defined(CONFIG_ETRAX_I2C_EEPROM_2KB) - eeprom.size = EEPROM_2KB; -#endif - - switch(eeprom.size) - { - case (EEPROM_2KB): - printk("%s: " EETEXT " i2c compatible 2kB eeprom.\n", eeprom_name); - eeprom.sequential_write_pagesize = 16; - eeprom.select_cmd = 0xA0; - break; - case (EEPROM_8KB): - printk("%s: " EETEXT " i2c compatible 8kB eeprom.\n", eeprom_name); - eeprom.sequential_write_pagesize = 16; - eeprom.select_cmd = 0x80; - break; - case (EEPROM_16KB): - printk("%s: " EETEXT " i2c compatible 16kB eeprom.\n", eeprom_name); - eeprom.sequential_write_pagesize = 64; - eeprom.select_cmd = 0xA0; - break; - default: - eeprom.size = 0; - printk("%s: Did not find a supported eeprom\n", eeprom_name); - break; - } - - - - eeprom_disable_write_protect(); - - return 0; -} - -/* Opens the device. */ -static int eeprom_open(struct inode * inode, struct file * file) -{ - if(iminor(inode) != EEPROM_MINOR_NR) - return -ENXIO; - if(imajor(inode) != EEPROM_MAJOR_NR) - return -ENXIO; - - if( eeprom.size > 0 ) - { - /* OK */ - return 0; - } - - /* No EEprom found */ - return -EFAULT; -} - -/* Changes the current file position. */ - -static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig) -{ -/* - * orig 0: position from beginning of eeprom - * orig 1: relative from current position - * orig 2: position from last eeprom address - */ - - switch (orig) - { - case 0: - file->f_pos = offset; - break; - case 1: - file->f_pos += offset; - break; - case 2: - file->f_pos = eeprom.size - offset; - break; - default: - return -EINVAL; - } - - /* truncate position */ - if (file->f_pos < 0) - { - file->f_pos = 0; - return(-EOVERFLOW); - } - - if (file->f_pos >= eeprom.size) - { - file->f_pos = eeprom.size - 1; - return(-EOVERFLOW); - } - - return ( file->f_pos ); -} - -/* Reads data from eeprom. */ - -static int eeprom_read_buf(loff_t addr, char * buf, int count) -{ - return eeprom_read(NULL, buf, count, &addr); -} - - - -/* Reads data from eeprom. */ - -static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t *off) -{ - int read=0; - unsigned long p = *off; - - unsigned char page; - - if(p >= eeprom.size) /* Address i 0 - (size-1) */ - { - return -EFAULT; - } - - if (mutex_lock_interruptible(&eeprom.lock)) - return -EINTR; - - page = (unsigned char) (p >> 8); - - if(!eeprom_address(p)) - { - printk(KERN_INFO "%s: Read failed to address the eeprom: " - "0x%08X (%i) page: %i\n", eeprom_name, (int)p, (int)p, page); - i2c_stop(); - - /* don't forget to wake them up */ - mutex_unlock(&eeprom.lock); - return -EFAULT; - } - - if( (p + count) > eeprom.size) - { - /* truncate count */ - count = eeprom.size - p; - } - - /* stop dummy write op and initiate the read op */ - i2c_start(); - - /* special case for small eeproms */ - if(eeprom.size < EEPROM_16KB) - { - i2c_outbyte( eeprom.select_cmd | 1 | (page << 1) ); - } - - /* go on with the actual read */ - read = read_from_eeprom( buf, count); - - if(read > 0) - { - *off += read; - } - - mutex_unlock(&eeprom.lock); - return read; -} - -/* Writes data to eeprom. */ - -static int eeprom_write_buf(loff_t addr, const char * buf, int count) -{ - return eeprom_write(NULL, buf, count, &addr); -} - - -/* Writes data to eeprom. */ - -static ssize_t eeprom_write(struct file * file, const char * buf, size_t count, - loff_t *off) -{ - int i, written, restart=1; - unsigned long p; - - if (!access_ok(VERIFY_READ, buf, count)) - { - return -EFAULT; - } - - /* bail out if we get interrupted */ - if (mutex_lock_interruptible(&eeprom.lock)) - return -EINTR; - for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++) - { - restart = 0; - written = 0; - p = *off; - - - while( (written < count) && (p < eeprom.size)) - { - /* address the eeprom */ - if(!eeprom_address(p)) - { - printk(KERN_INFO "%s: Write failed to address the eeprom: " - "0x%08X (%i) \n", eeprom_name, (int)p, (int)p); - i2c_stop(); - - /* don't forget to wake them up */ - mutex_unlock(&eeprom.lock); - return -EFAULT; - } -#ifdef EEPROM_ADAPTIVE_TIMING - /* Adaptive algorithm to adjust timing */ - if (eeprom.retry_cnt_addr > 0) - { - /* To Low now */ - D(printk(">D=%i d=%i\n", - eeprom.usec_delay_writecycles, eeprom.usec_delay_step)); - - if (eeprom.usec_delay_step < 4) - { - eeprom.usec_delay_step++; - eeprom.usec_delay_writecycles += eeprom.usec_delay_step; - } - else - { - - if (eeprom.adapt_state > 0) - { - /* To Low before */ - eeprom.usec_delay_step *= 2; - if (eeprom.usec_delay_step > 2) - { - eeprom.usec_delay_step--; - } - eeprom.usec_delay_writecycles += eeprom.usec_delay_step; - } - else if (eeprom.adapt_state < 0) - { - /* To High before (toggle dir) */ - eeprom.usec_delay_writecycles += eeprom.usec_delay_step; - if (eeprom.usec_delay_step > 1) - { - eeprom.usec_delay_step /= 2; - eeprom.usec_delay_step--; - } - } - } - - eeprom.adapt_state = 1; - } - else - { - /* To High (or good) now */ - D(printk(" 1) - { - eeprom.usec_delay_step *= 2; - eeprom.usec_delay_step--; - - if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step) - { - eeprom.usec_delay_writecycles -= eeprom.usec_delay_step; - } - } - } - else if (eeprom.adapt_state > 0) - { - /* To Low before (toggle dir) */ - if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step) - { - eeprom.usec_delay_writecycles -= eeprom.usec_delay_step; - } - if (eeprom.usec_delay_step > 1) - { - eeprom.usec_delay_step /= 2; - eeprom.usec_delay_step--; - } - - eeprom.adapt_state = -1; - } - - if (eeprom.adapt_state > -100) - { - eeprom.adapt_state--; - } - else - { - /* Restart adaption */ - D(printk("#Restart\n")); - eeprom.usec_delay_step++; - } - } -#endif /* EEPROM_ADAPTIVE_TIMING */ - /* write until we hit a page boundary or count */ - do - { - i2c_outbyte(buf[written]); - if(!i2c_getack()) - { - restart=1; - printk(KERN_INFO "%s: write error, retrying. %d\n", eeprom_name, i); - i2c_stop(); - break; - } - written++; - p++; - } while( written < count && ( p % eeprom.sequential_write_pagesize )); - - /* end write cycle */ - i2c_stop(); - i2c_delay(eeprom.usec_delay_writecycles); - } /* while */ - } /* for */ - - mutex_unlock(&eeprom.lock); - if (written == 0 && p >= eeprom.size){ - return -ENOSPC; - } - *off = p; - return written; -} - -/* Closes the device. */ - -static int eeprom_close(struct inode * inode, struct file * file) -{ - /* do nothing for now */ - return 0; -} - -/* Sets the current address of the eeprom. */ - -static int eeprom_address(unsigned long addr) -{ - int i; - unsigned char page, offset; - - page = (unsigned char) (addr >> 8); - offset = (unsigned char) addr; - - for(i = 0; i < EEPROM_RETRIES; i++) - { - /* start a dummy write for addressing */ - i2c_start(); - - if(eeprom.size == EEPROM_16KB) - { - i2c_outbyte( eeprom.select_cmd ); - i2c_getack(); - i2c_outbyte(page); - } - else - { - i2c_outbyte( eeprom.select_cmd | (page << 1) ); - } - if(!i2c_getack()) - { - /* retry */ - i2c_stop(); - /* Must have a delay here.. 500 works, >50, 100->works 5th time*/ - i2c_delay(MAX_WRITEDELAY_US / EEPROM_RETRIES * i); - /* The chip needs up to 10 ms from write stop to next start */ - - } - else - { - i2c_outbyte(offset); - - if(!i2c_getack()) - { - /* retry */ - i2c_stop(); - } - else - break; - } - } - - - eeprom.retry_cnt_addr = i; - D(printk("%i\n", eeprom.retry_cnt_addr)); - if(eeprom.retry_cnt_addr == EEPROM_RETRIES) - { - /* failed */ - return 0; - } - return 1; -} - -/* Reads from current address. */ - -static int read_from_eeprom(char * buf, int count) -{ - int i, read=0; - - for(i = 0; i < EEPROM_RETRIES; i++) - { - if(eeprom.size == EEPROM_16KB) - { - i2c_outbyte( eeprom.select_cmd | 1 ); - } - - if(i2c_getack()) - { - break; - } - } - - if(i == EEPROM_RETRIES) - { - printk(KERN_INFO "%s: failed to read from eeprom\n", eeprom_name); - i2c_stop(); - - return -EFAULT; - } - - while( (read < count)) - { - if (put_user(i2c_inbyte(), &buf[read++])) - { - i2c_stop(); - - return -EFAULT; - } - - /* - * make sure we don't ack last byte or you will get very strange - * results! - */ - if(read < count) - { - i2c_sendack(); - } - } - - /* stop the operation */ - i2c_stop(); - - return read; -} - -/* Disables write protection if applicable. */ - -#define DBP_SAVE(x) -#define ax_printf printk -static void eeprom_disable_write_protect(void) -{ - /* Disable write protect */ - if (eeprom.size == EEPROM_8KB) - { - /* Step 1 Set WEL = 1 (write 00000010 to address 1FFFh */ - i2c_start(); - i2c_outbyte(0xbe); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false\n")); - } - i2c_outbyte(0xFF); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 2\n")); - } - i2c_outbyte(0x02); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 3\n")); - } - i2c_stop(); - - i2c_delay(1000); - - /* Step 2 Set RWEL = 1 (write 00000110 to address 1FFFh */ - i2c_start(); - i2c_outbyte(0xbe); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 55\n")); - } - i2c_outbyte(0xFF); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 52\n")); - } - i2c_outbyte(0x06); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 53\n")); - } - i2c_stop(); - - /* Step 3 Set BP1, BP0, and/or WPEN bits (write 00000110 to address 1FFFh */ - i2c_start(); - i2c_outbyte(0xbe); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 56\n")); - } - i2c_outbyte(0xFF); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 57\n")); - } - i2c_outbyte(0x06); - if(!i2c_getack()) - { - DBP_SAVE(ax_printf("Get ack returns false 58\n")); - } - i2c_stop(); - - /* Write protect disabled */ - } -} -device_initcall(eeprom_init); diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c deleted file mode 100644 index cd0e05d89d42..000000000000 --- a/arch/cris/arch-v10/drivers/gpio.c +++ /dev/null @@ -1,857 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Etrax general port I/O device - * - * Copyright (c) 1999-2007 Axis Communications AB - * - * Authors: Bjorn Wesen (initial version) - * Ola Knutsson (LED handling) - * Johan Adolfsson (read/set directions, write, port G) - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define GPIO_MAJOR 120 /* experimental MAJOR number */ - -#define D(x) - -#if 0 -static int dp_cnt; -#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0) -#else -#define DP(x) -#endif - -static char gpio_name[] = "etrax gpio"; - -#if 0 -static wait_queue_head_t *gpio_wq; -#endif - -static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg); -static ssize_t gpio_write(struct file *file, const char __user *buf, - size_t count, loff_t *off); -static int gpio_open(struct inode *inode, struct file *filp); -static int gpio_release(struct inode *inode, struct file *filp); -static __poll_t gpio_poll(struct file *filp, struct poll_table_struct *wait); - -/* private data per open() of this driver */ - -struct gpio_private { - struct gpio_private *next; - /* These fields are for PA and PB only */ - volatile unsigned char *port, *shadow; - volatile unsigned char *dir, *dir_shadow; - unsigned char changeable_dir; - unsigned char changeable_bits; - unsigned char clk_mask; - unsigned char data_mask; - unsigned char write_msb; - unsigned char pad1, pad2, pad3; - /* These fields are generic */ - unsigned long highalarm, lowalarm; - wait_queue_head_t alarm_wq; - int minor; -}; - -/* linked list of alarms to check for */ - -static struct gpio_private *alarmlist; - -static int gpio_some_alarms; /* Set if someone uses alarm */ -static unsigned long gpio_pa_irq_enabled_mask; - -static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */ - -/* Port A and B use 8 bit access, but Port G is 32 bit */ -#define NUM_PORTS (GPIO_MINOR_B+1) - -static volatile unsigned char *ports[NUM_PORTS] = { - R_PORT_PA_DATA, - R_PORT_PB_DATA, -}; -static volatile unsigned char *shads[NUM_PORTS] = { - &port_pa_data_shadow, - &port_pb_data_shadow -}; - -/* What direction bits that are user changeable 1=changeable*/ -#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR -#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00 -#endif -#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR -#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00 -#endif - -#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS -#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF -#endif -#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS -#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF -#endif - - -static unsigned char changeable_dir[NUM_PORTS] = { - CONFIG_ETRAX_PA_CHANGEABLE_DIR, - CONFIG_ETRAX_PB_CHANGEABLE_DIR -}; -static unsigned char changeable_bits[NUM_PORTS] = { - CONFIG_ETRAX_PA_CHANGEABLE_BITS, - CONFIG_ETRAX_PB_CHANGEABLE_BITS -}; - -static volatile unsigned char *dir[NUM_PORTS] = { - R_PORT_PA_DIR, - R_PORT_PB_DIR -}; - -static volatile unsigned char *dir_shadow[NUM_PORTS] = { - &port_pa_dir_shadow, - &port_pb_dir_shadow -}; - -/* All bits in port g that can change dir. */ -static const unsigned long int changeable_dir_g_mask = 0x01FFFF01; - -/* Port G is 32 bit, handle it special, some bits are both inputs - and outputs at the same time, only some of the bits can change direction - and some of them in groups of 8 bit. */ -static unsigned long changeable_dir_g; -static unsigned long dir_g_in_bits; -static unsigned long dir_g_out_bits; -static unsigned long dir_g_shadow; /* 1=output */ - -#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B) - - -static __poll_t gpio_poll(struct file *file, poll_table *wait) -{ - __poll_t mask = 0; - struct gpio_private *priv = file->private_data; - unsigned long data; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); - - poll_wait(file, &priv->alarm_wq, wait); - if (priv->minor == GPIO_MINOR_A) { - unsigned long tmp; - data = *R_PORT_PA_DATA; - /* PA has support for high level interrupt - - * lets activate for those low and with highalarm set - */ - tmp = ~data & priv->highalarm & 0xFF; - tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR); - - gpio_pa_irq_enabled_mask |= tmp; - *R_IRQ_MASK1_SET = tmp; - } else if (priv->minor == GPIO_MINOR_B) - data = *R_PORT_PB_DATA; - else if (priv->minor == GPIO_MINOR_G) - data = *R_PORT_G_DATA; - else { - mask = 0; - goto out; - } - - if ((data & priv->highalarm) || - (~data & priv->lowalarm)) { - mask = EPOLLIN|EPOLLRDNORM; - } - -out: - spin_unlock_irqrestore(&gpio_lock, flags); - DP(printk("gpio_poll ready: mask 0x%08X\n", mask)); - - return mask; -} - -int etrax_gpio_wake_up_check(void) -{ - struct gpio_private *priv; - unsigned long data = 0; - int ret = 0; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); - priv = alarmlist; - while (priv) { - if (USE_PORTS(priv)) - data = *priv->port; - else if (priv->minor == GPIO_MINOR_G) - data = *R_PORT_G_DATA; - - if ((data & priv->highalarm) || - (~data & priv->lowalarm)) { - DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor)); - wake_up_interruptible(&priv->alarm_wq); - ret = 1; - } - priv = priv->next; - } - spin_unlock_irqrestore(&gpio_lock, flags); - return ret; -} - -static irqreturn_t -gpio_poll_timer_interrupt(int irq, void *dev_id) -{ - if (gpio_some_alarms) { - etrax_gpio_wake_up_check(); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -static irqreturn_t -gpio_interrupt(int irq, void *dev_id) -{ - unsigned long tmp; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); - - /* Find what PA interrupts are active */ - tmp = (*R_IRQ_READ1); - - /* Find those that we have enabled */ - tmp &= gpio_pa_irq_enabled_mask; - - /* Clear them.. */ - *R_IRQ_MASK1_CLR = tmp; - gpio_pa_irq_enabled_mask &= ~tmp; - - spin_unlock_irqrestore(&gpio_lock, flags); - - if (gpio_some_alarms) - return IRQ_RETVAL(etrax_gpio_wake_up_check()); - - return IRQ_NONE; -} - -static void gpio_write_bit(struct gpio_private *priv, - unsigned char data, int bit) -{ - *priv->port = *priv->shadow &= ~(priv->clk_mask); - if (data & 1 << bit) - *priv->port = *priv->shadow |= priv->data_mask; - else - *priv->port = *priv->shadow &= ~(priv->data_mask); - - /* For FPGA: min 5.0ns (DCC) before CCLK high */ - *priv->port = *priv->shadow |= priv->clk_mask; -} - -static void gpio_write_byte(struct gpio_private *priv, unsigned char data) -{ - int i; - - if (priv->write_msb) - for (i = 7; i >= 0; i--) - gpio_write_bit(priv, data, i); - else - for (i = 0; i <= 7; i++) - gpio_write_bit(priv, data, i); -} - -static ssize_t gpio_write(struct file *file, const char __user *buf, - size_t count, loff_t *off) -{ - struct gpio_private *priv = file->private_data; - unsigned long flags; - ssize_t retval = count; - - if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) - return -EFAULT; - - if (!access_ok(VERIFY_READ, buf, count)) - return -EFAULT; - - spin_lock_irqsave(&gpio_lock, flags); - - /* It must have been configured using the IO_CFG_WRITE_MODE */ - /* Perhaps a better error code? */ - if (priv->clk_mask == 0 || priv->data_mask == 0) { - retval = -EPERM; - goto out; - } - - D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X " - "clk 0x%02X msb: %i\n", - count, priv->data_mask, priv->clk_mask, priv->write_msb)); - - while (count--) - gpio_write_byte(priv, *buf++); - -out: - spin_unlock_irqrestore(&gpio_lock, flags); - return retval; -} - - - -static int -gpio_open(struct inode *inode, struct file *filp) -{ - struct gpio_private *priv; - int p = iminor(inode); - unsigned long flags; - - if (p > GPIO_MINOR_LAST) - return -EINVAL; - - priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL); - - if (!priv) - return -ENOMEM; - - priv->minor = p; - - /* initialize the io/alarm struct */ - - if (USE_PORTS(priv)) { /* A and B */ - priv->port = ports[p]; - priv->shadow = shads[p]; - priv->dir = dir[p]; - priv->dir_shadow = dir_shadow[p]; - priv->changeable_dir = changeable_dir[p]; - priv->changeable_bits = changeable_bits[p]; - } else { - priv->port = NULL; - priv->shadow = NULL; - priv->dir = NULL; - priv->dir_shadow = NULL; - priv->changeable_dir = 0; - priv->changeable_bits = 0; - } - - priv->highalarm = 0; - priv->lowalarm = 0; - priv->clk_mask = 0; - priv->data_mask = 0; - init_waitqueue_head(&priv->alarm_wq); - - filp->private_data = priv; - - /* link it into our alarmlist */ - spin_lock_irqsave(&gpio_lock, flags); - priv->next = alarmlist; - alarmlist = priv; - spin_unlock_irqrestore(&gpio_lock, flags); - - return 0; -} - -static int -gpio_release(struct inode *inode, struct file *filp) -{ - struct gpio_private *p; - struct gpio_private *todel; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); - - p = alarmlist; - todel = filp->private_data; - - /* unlink from alarmlist and free the private structure */ - - if (p == todel) { - alarmlist = todel->next; - } else { - while (p->next != todel) - p = p->next; - p->next = todel->next; - } - - kfree(todel); - /* Check if there are still any alarms set */ - p = alarmlist; - while (p) { - if (p->highalarm | p->lowalarm) { - gpio_some_alarms = 1; - goto out; - } - p = p->next; - } - gpio_some_alarms = 0; -out: - spin_unlock_irqrestore(&gpio_lock, flags); - return 0; -} - -/* Main device API. ioctl's to read/set/clear bits, as well as to - * set alarms to wait for using a subsequent select(). - */ -inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg) -{ - /* Set direction 0=unchanged 1=input, - * return mask with 1=input */ - if (USE_PORTS(priv)) { - *priv->dir = *priv->dir_shadow &= - ~((unsigned char)arg & priv->changeable_dir); - return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */ - } - - if (priv->minor != GPIO_MINOR_G) - return 0; - - /* We must fiddle with R_GEN_CONFIG to change dir */ - if (((arg & dir_g_in_bits) != arg) && - (arg & changeable_dir_g)) { - arg &= changeable_dir_g; - /* Clear bits in genconfig to set to input */ - if (arg & (1<<0)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir); - dir_g_in_bits |= (1<<0); - dir_g_out_bits &= ~(1<<0); - } - if ((arg & 0x0000FF00) == 0x0000FF00) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir); - dir_g_in_bits |= 0x0000FF00; - dir_g_out_bits &= ~0x0000FF00; - } - if ((arg & 0x00FF0000) == 0x00FF0000) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir); - dir_g_in_bits |= 0x00FF0000; - dir_g_out_bits &= ~0x00FF0000; - } - if (arg & (1<<24)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir); - dir_g_in_bits |= (1<<24); - dir_g_out_bits &= ~(1<<24); - } - D(printk(KERN_DEBUG "gpio: SETINPUT on port G set " - "genconfig to 0x%08lX " - "in_bits: 0x%08lX " - "out_bits: 0x%08lX\n", - (unsigned long)genconfig_shadow, - dir_g_in_bits, dir_g_out_bits)); - *R_GEN_CONFIG = genconfig_shadow; - /* Must be a >120 ns delay before writing this again */ - - } - return dir_g_in_bits; -} /* setget_input */ - -inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg) -{ - if (USE_PORTS(priv)) { - *priv->dir = *priv->dir_shadow |= - ((unsigned char)arg & priv->changeable_dir); - return *priv->dir_shadow; - } - if (priv->minor != GPIO_MINOR_G) - return 0; - - /* We must fiddle with R_GEN_CONFIG to change dir */ - if (((arg & dir_g_out_bits) != arg) && - (arg & changeable_dir_g)) { - /* Set bits in genconfig to set to output */ - if (arg & (1<<0)) { - genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir); - dir_g_out_bits |= (1<<0); - dir_g_in_bits &= ~(1<<0); - } - if ((arg & 0x0000FF00) == 0x0000FF00) { - genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir); - dir_g_out_bits |= 0x0000FF00; - dir_g_in_bits &= ~0x0000FF00; - } - if ((arg & 0x00FF0000) == 0x00FF0000) { - genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir); - dir_g_out_bits |= 0x00FF0000; - dir_g_in_bits &= ~0x00FF0000; - } - if (arg & (1<<24)) { - genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir); - dir_g_out_bits |= (1<<24); - dir_g_in_bits &= ~(1<<24); - } - D(printk(KERN_INFO "gpio: SETOUTPUT on port G set " - "genconfig to 0x%08lX " - "in_bits: 0x%08lX " - "out_bits: 0x%08lX\n", - (unsigned long)genconfig_shadow, - dir_g_in_bits, dir_g_out_bits)); - *R_GEN_CONFIG = genconfig_shadow; - /* Must be a >120 ns delay before writing this again */ - } - return dir_g_out_bits & 0x7FFFFFFF; -} /* setget_output */ - -static int -gpio_leds_ioctl(unsigned int cmd, unsigned long arg); - -static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - unsigned long flags; - unsigned long val; - int ret = 0; - - struct gpio_private *priv = file->private_data; - if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) - return -EINVAL; - - switch (_IOC_NR(cmd)) { - case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */ - // read the port - spin_lock_irqsave(&gpio_lock, flags); - if (USE_PORTS(priv)) { - ret = *priv->port; - } else if (priv->minor == GPIO_MINOR_G) { - ret = (*R_PORT_G_DATA) & 0x7FFFFFFF; - } - spin_unlock_irqrestore(&gpio_lock, flags); - - break; - case IO_SETBITS: - // set changeable bits with a 1 in arg - spin_lock_irqsave(&gpio_lock, flags); - - if (USE_PORTS(priv)) { - *priv->port = *priv->shadow |= - ((unsigned char)arg & priv->changeable_bits); - } else if (priv->minor == GPIO_MINOR_G) { - *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits); - } - spin_unlock_irqrestore(&gpio_lock, flags); - - break; - case IO_CLRBITS: - // clear changeable bits with a 1 in arg - spin_lock_irqsave(&gpio_lock, flags); - if (USE_PORTS(priv)) { - *priv->port = *priv->shadow &= - ~((unsigned char)arg & priv->changeable_bits); - } else if (priv->minor == GPIO_MINOR_G) { - *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits); - } - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_HIGHALARM: - // set alarm when bits with 1 in arg go high - spin_lock_irqsave(&gpio_lock, flags); - priv->highalarm |= arg; - gpio_some_alarms = 1; - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_LOWALARM: - // set alarm when bits with 1 in arg go low - spin_lock_irqsave(&gpio_lock, flags); - priv->lowalarm |= arg; - gpio_some_alarms = 1; - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_CLRALARM: - /* clear alarm for bits with 1 in arg */ - spin_lock_irqsave(&gpio_lock, flags); - priv->highalarm &= ~arg; - priv->lowalarm &= ~arg; - { - /* Must update gpio_some_alarms */ - struct gpio_private *p = alarmlist; - int some_alarms; - p = alarmlist; - some_alarms = 0; - while (p) { - if (p->highalarm | p->lowalarm) { - some_alarms = 1; - break; - } - p = p->next; - } - gpio_some_alarms = some_alarms; - } - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */ - /* Read direction 0=input 1=output */ - spin_lock_irqsave(&gpio_lock, flags); - if (USE_PORTS(priv)) { - ret = *priv->dir_shadow; - } else if (priv->minor == GPIO_MINOR_G) { - /* Note: Some bits are both in and out, - * Those that are dual is set here as well. - */ - ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF; - } - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */ - /* Set direction 0=unchanged 1=input, - * return mask with 1=input - */ - spin_lock_irqsave(&gpio_lock, flags); - ret = setget_input(priv, arg) & 0x7FFFFFFF; - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */ - /* Set direction 0=unchanged 1=output, - * return mask with 1=output - */ - spin_lock_irqsave(&gpio_lock, flags); - ret = setget_output(priv, arg) & 0x7FFFFFFF; - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_SHUTDOWN: - spin_lock_irqsave(&gpio_lock, flags); - SOFT_SHUTDOWN(); - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_GET_PWR_BT: - spin_lock_irqsave(&gpio_lock, flags); -#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN) - ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT)); -#else - ret = 0; -#endif - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_CFG_WRITE_MODE: - spin_lock_irqsave(&gpio_lock, flags); - priv->clk_mask = arg & 0xFF; - priv->data_mask = (arg >> 8) & 0xFF; - priv->write_msb = (arg >> 16) & 0x01; - /* Check if we're allowed to change the bits and - * the direction is correct - */ - if (!((priv->clk_mask & priv->changeable_bits) && - (priv->data_mask & priv->changeable_bits) && - (priv->clk_mask & *priv->dir_shadow) && - (priv->data_mask & *priv->dir_shadow))) - { - priv->clk_mask = 0; - priv->data_mask = 0; - ret = -EPERM; - } - spin_unlock_irqrestore(&gpio_lock, flags); - break; - case IO_READ_INBITS: - /* *arg is result of reading the input pins */ - spin_lock_irqsave(&gpio_lock, flags); - if (USE_PORTS(priv)) { - val = *priv->port; - } else if (priv->minor == GPIO_MINOR_G) { - val = *R_PORT_G_DATA; - } - spin_unlock_irqrestore(&gpio_lock, flags); - if (copy_to_user((void __user *)arg, &val, sizeof(val))) - ret = -EFAULT; - break; - case IO_READ_OUTBITS: - /* *arg is result of reading the output shadow */ - spin_lock_irqsave(&gpio_lock, flags); - if (USE_PORTS(priv)) { - val = *priv->shadow; - } else if (priv->minor == GPIO_MINOR_G) { - val = port_g_data_shadow; - } - spin_unlock_irqrestore(&gpio_lock, flags); - if (copy_to_user((void __user *)arg, &val, sizeof(val))) - ret = -EFAULT; - break; - case IO_SETGET_INPUT: - /* bits set in *arg is set to input, - * *arg updated with current input pins. - */ - if (copy_from_user(&val, (void __user *)arg, sizeof(val))) - { - ret = -EFAULT; - break; - } - spin_lock_irqsave(&gpio_lock, flags); - val = setget_input(priv, val); - spin_unlock_irqrestore(&gpio_lock, flags); - if (copy_to_user((void __user *)arg, &val, sizeof(val))) - ret = -EFAULT; - break; - case IO_SETGET_OUTPUT: - /* bits set in *arg is set to output, - * *arg updated with current output pins. - */ - if (copy_from_user(&val, (void __user *)arg, sizeof(val))) { - ret = -EFAULT; - break; - } - spin_lock_irqsave(&gpio_lock, flags); - val = setget_output(priv, val); - spin_unlock_irqrestore(&gpio_lock, flags); - if (copy_to_user((void __user *)arg, &val, sizeof(val))) - ret = -EFAULT; - break; - default: - spin_lock_irqsave(&gpio_lock, flags); - if (priv->minor == GPIO_MINOR_LEDS) - ret = gpio_leds_ioctl(cmd, arg); - else - ret = -EINVAL; - spin_unlock_irqrestore(&gpio_lock, flags); - } /* switch */ - - return ret; -} - -static int -gpio_leds_ioctl(unsigned int cmd, unsigned long arg) -{ - unsigned char green; - unsigned char red; - - switch (_IOC_NR(cmd)) { - case IO_LEDACTIVE_SET: - green = ((unsigned char)arg) & 1; - red = (((unsigned char)arg) >> 1) & 1; - CRIS_LED_ACTIVE_SET_G(green); - CRIS_LED_ACTIVE_SET_R(red); - break; - - case IO_LED_SETBIT: - CRIS_LED_BIT_SET(arg); - break; - - case IO_LED_CLRBIT: - CRIS_LED_BIT_CLR(arg); - break; - - default: - return -EINVAL; - } /* switch */ - - return 0; -} - -static const struct file_operations gpio_fops = { - .owner = THIS_MODULE, - .poll = gpio_poll, - .unlocked_ioctl = gpio_ioctl, - .write = gpio_write, - .open = gpio_open, - .release = gpio_release, - .llseek = noop_llseek, -}; - -static void ioif_watcher(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available) -{ - unsigned long int flags; - - D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n")); - D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x " - "PA: 0x%02x PB: 0x%02x\n", - gpio_in_available, gpio_out_available, - pa_available, pb_available)); - - spin_lock_irqsave(&gpio_lock, flags); - - dir_g_in_bits = gpio_in_available; - dir_g_out_bits = gpio_out_available; - - /* Initialise the dir_g_shadow etc. depending on genconfig */ - /* 0=input 1=output */ - if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) - dir_g_shadow |= (1 << 0); - if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out)) - dir_g_shadow |= 0x0000FF00; - if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out)) - dir_g_shadow |= 0x00FF0000; - if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out)) - dir_g_shadow |= (1 << 24); - - changeable_dir_g = changeable_dir_g_mask; - changeable_dir_g &= dir_g_out_bits; - changeable_dir_g &= dir_g_in_bits; - - /* Correct the bits that can change direction */ - dir_g_out_bits &= ~changeable_dir_g; - dir_g_out_bits |= dir_g_shadow; - dir_g_in_bits &= ~changeable_dir_g; - dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g); - - spin_unlock_irqrestore(&gpio_lock, flags); - - printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX " - "val: %08lX\n", - dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA); - printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n", - dir_g_shadow, changeable_dir_g); -} - -/* main driver initialization routine, called from mem.c */ - -static int __init gpio_init(void) -{ - int res; -#if defined (CONFIG_ETRAX_CSP0_LEDS) - int i; -#endif - - res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops); - if (res < 0) { - printk(KERN_ERR "gpio: couldn't get a major number.\n"); - return res; - } - - /* Clear all leds */ -#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) - CRIS_LED_NETWORK_SET(0); - CRIS_LED_ACTIVE_SET(0); - CRIS_LED_DISK_READ(0); - CRIS_LED_DISK_WRITE(0); - -#if defined (CONFIG_ETRAX_CSP0_LEDS) - for (i = 0; i < 32; i++) - CRIS_LED_BIT_SET(i); -#endif - -#endif - /* The I/O interface allocation watcher will be called when - * registering it. */ - if (cris_io_interface_register_watcher(ioif_watcher)){ - printk(KERN_WARNING "gpio_init: Failed to install IO " - "if allocator watcher\n"); - } - - printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 " - "Axis Communications AB\n"); - /* We call etrax_gpio_wake_up_check() from timer interrupt and - * from default_idle() in kernel/process.c - * The check in default_idle() reduces latency from ~15 ms to ~6 ms - * in some tests. - */ - res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt, - IRQF_SHARED, "gpio poll", gpio_name); - if (res) { - printk(KERN_CRIT "err: timer0 irq for gpio\n"); - return res; - } - res = request_irq(PA_IRQ_NBR, gpio_interrupt, - IRQF_SHARED, "gpio PA", gpio_name); - if (res) - printk(KERN_CRIT "err: PA irq for gpio\n"); - - return res; -} - -/* this makes sure that gpio_init is called during kernel boot */ -module_init(gpio_init); - diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c deleted file mode 100644 index ec35d62e8e63..000000000000 --- a/arch/cris/arch-v10/drivers/i2c.c +++ /dev/null @@ -1,699 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*!*************************************************************************** -*! -*! FILE NAME : i2c.c -*! -*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other -*! kernel modules (i2c_writereg/readreg) and from userspace using -*! ioctl()'s -*! -*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN -*! -*!***************************************************************************/ - -/****************** INCLUDE FILES SECTION ***********************************/ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include "i2c.h" - -/****************** I2C DEFINITION SECTION *************************/ - -#define D(x) - -#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */ -static const char i2c_name[] = "i2c"; - -#define CLOCK_LOW_TIME 8 -#define CLOCK_HIGH_TIME 8 -#define START_CONDITION_HOLD_TIME 8 -#define STOP_CONDITION_HOLD_TIME 8 -#define ENABLE_OUTPUT 0x01 -#define ENABLE_INPUT 0x00 -#define I2C_CLOCK_HIGH 1 -#define I2C_CLOCK_LOW 0 -#define I2C_DATA_HIGH 1 -#define I2C_DATA_LOW 0 - -#ifdef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C -/* Use PB and not PB_I2C */ -#ifndef CONFIG_ETRAX_I2C_DATA_PORT -#define CONFIG_ETRAX_I2C_DATA_PORT 0 -#endif -#ifndef CONFIG_ETRAX_I2C_CLK_PORT -#define CONFIG_ETRAX_I2C_CLK_PORT 1 -#endif - -#define SDABIT CONFIG_ETRAX_I2C_DATA_PORT -#define SCLBIT CONFIG_ETRAX_I2C_CLK_PORT -#define i2c_enable() -#define i2c_disable() - -/* enable or disable output-enable, to select output or input on the i2c bus */ - -#define i2c_dir_out() \ - REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 1) -#define i2c_dir_in() \ - REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 0) - -/* control the i2c clock and data signals */ - -#define i2c_clk(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SCLBIT, x) -#define i2c_data(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SDABIT, x) - -/* read a bit from the i2c interface */ - -#define i2c_getbit() (((*R_PORT_PB_READ & (1 << SDABIT))) >> SDABIT) - -#else -/* enable or disable the i2c interface */ - -#define i2c_enable() *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_en)) -#define i2c_disable() *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_en)) - -/* enable or disable output-enable, to select output or input on the i2c bus */ - -#define i2c_dir_out() \ - *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \ - REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 1); -#define i2c_dir_in() \ - *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \ - REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 0); - -/* control the i2c clock and data signals */ - -#define i2c_clk(x) \ - *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \ - ~IO_MASK(R_PORT_PB_I2C, i2c_clk)) | IO_FIELD(R_PORT_PB_I2C, i2c_clk, (x))); \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 1, x); - -#define i2c_data(x) \ - *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \ - ~IO_MASK(R_PORT_PB_I2C, i2c_d)) | IO_FIELD(R_PORT_PB_I2C, i2c_d, (x))); \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 0, x); - -/* read a bit from the i2c interface */ - -#define i2c_getbit() (*R_PORT_PB_READ & 0x1) -#endif - -/* use the kernels delay routine */ - -#define i2c_delay(usecs) udelay(usecs) - -static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */ - -/****************** FUNCTION DEFINITION SECTION *************************/ - - -/* generate i2c start condition */ - -void -i2c_start(void) -{ - /* - * SCL=1 SDA=1 - */ - i2c_dir_out(); - i2c_delay(CLOCK_HIGH_TIME/6); - i2c_data(I2C_DATA_HIGH); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - /* - * SCL=1 SDA=0 - */ - i2c_data(I2C_DATA_LOW); - i2c_delay(START_CONDITION_HOLD_TIME); - /* - * SCL=0 SDA=0 - */ - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME); -} - -/* generate i2c stop condition */ - -void -i2c_stop(void) -{ - i2c_dir_out(); - - /* - * SCL=0 SDA=0 - */ - i2c_clk(I2C_CLOCK_LOW); - i2c_data(I2C_DATA_LOW); - i2c_delay(CLOCK_LOW_TIME*2); - /* - * SCL=1 SDA=0 - */ - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME*2); - /* - * SCL=1 SDA=1 - */ - i2c_data(I2C_DATA_HIGH); - i2c_delay(STOP_CONDITION_HOLD_TIME); - - i2c_dir_in(); -} - -/* write a byte to the i2c interface */ - -void -i2c_outbyte(unsigned char x) -{ - int i; - - i2c_dir_out(); - - for (i = 0; i < 8; i++) { - if (x & 0x80) { - i2c_data(I2C_DATA_HIGH); - } else { - i2c_data(I2C_DATA_LOW); - } - - i2c_delay(CLOCK_LOW_TIME/2); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME/2); - x <<= 1; - } - i2c_data(I2C_DATA_LOW); - i2c_delay(CLOCK_LOW_TIME/2); - - /* - * enable input - */ - i2c_dir_in(); -} - -/* read a byte from the i2c interface */ - -unsigned char -i2c_inbyte(void) -{ - unsigned char aBitByte = 0; - int i; - - /* Switch off I2C to get bit */ - i2c_disable(); - i2c_dir_in(); - i2c_delay(CLOCK_HIGH_TIME/2); - - /* Get bit */ - aBitByte |= i2c_getbit(); - - /* Enable I2C */ - i2c_enable(); - i2c_delay(CLOCK_LOW_TIME/2); - - for (i = 1; i < 8; i++) { - aBitByte <<= 1; - /* Clock pulse */ - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME); - - /* Switch off I2C to get bit */ - i2c_disable(); - i2c_dir_in(); - i2c_delay(CLOCK_HIGH_TIME/2); - - /* Get bit */ - aBitByte |= i2c_getbit(); - - /* Enable I2C */ - i2c_enable(); - i2c_delay(CLOCK_LOW_TIME/2); - } - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - - /* - * we leave the clock low, getbyte is usually followed - * by sendack/nack, they assume the clock to be low - */ - i2c_clk(I2C_CLOCK_LOW); - return aBitByte; -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_getack -*# -*# DESCRIPTION : checks if ack was received from ic2 -*# -*#--------------------------------------------------------------------------*/ - -int -i2c_getack(void) -{ - int ack = 1; - /* - * enable output - */ - i2c_dir_out(); - /* - * Release data bus by setting - * data high - */ - i2c_data(I2C_DATA_HIGH); - /* - * enable input - */ - i2c_dir_in(); - i2c_delay(CLOCK_HIGH_TIME/4); - /* - * generate ACK clock pulse - */ - i2c_clk(I2C_CLOCK_HIGH); - /* - * Use PORT PB instead of I2C - * for input. (I2C not working) - */ - i2c_clk(1); - i2c_data(1); - /* - * switch off I2C - */ - i2c_data(1); - i2c_disable(); - i2c_dir_in(); - /* - * now wait for ack - */ - i2c_delay(CLOCK_HIGH_TIME/2); - /* - * check for ack - */ - if(i2c_getbit()) - ack = 0; - i2c_delay(CLOCK_HIGH_TIME/2); - if(!ack){ - if(!i2c_getbit()) /* receiver pulld SDA low */ - ack = 1; - i2c_delay(CLOCK_HIGH_TIME/2); - } - - /* - * our clock is high now, make sure data is low - * before we enable our output. If we keep data high - * and enable output, we would generate a stop condition. - */ - i2c_data(I2C_DATA_LOW); - - /* - * end clock pulse - */ - i2c_enable(); - i2c_dir_out(); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_HIGH_TIME/4); - /* - * enable output - */ - i2c_dir_out(); - /* - * remove ACK clock pulse - */ - i2c_data(I2C_DATA_HIGH); - i2c_delay(CLOCK_LOW_TIME/2); - return ack; -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: I2C::sendAck -*# -*# DESCRIPTION : Send ACK on received data -*# -*#--------------------------------------------------------------------------*/ -void -i2c_sendack(void) -{ - /* - * enable output - */ - i2c_delay(CLOCK_LOW_TIME); - i2c_dir_out(); - /* - * set ack pulse high - */ - i2c_data(I2C_DATA_LOW); - /* - * generate clock pulse - */ - i2c_delay(CLOCK_HIGH_TIME/6); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME/6); - /* - * reset data out - */ - i2c_data(I2C_DATA_HIGH); - i2c_delay(CLOCK_LOW_TIME); - - i2c_dir_in(); -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_sendnack -*# -*# DESCRIPTION : Sends NACK on received data -*# -*#--------------------------------------------------------------------------*/ -void -i2c_sendnack(void) -{ - /* - * enable output - */ - i2c_delay(CLOCK_LOW_TIME); - i2c_dir_out(); - /* - * set data high - */ - i2c_data(I2C_DATA_HIGH); - /* - * generate clock pulse - */ - i2c_delay(CLOCK_HIGH_TIME/6); - i2c_clk(I2C_CLOCK_HIGH); - i2c_delay(CLOCK_HIGH_TIME); - i2c_clk(I2C_CLOCK_LOW); - i2c_delay(CLOCK_LOW_TIME); - - i2c_dir_in(); -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_writereg -*# -*# DESCRIPTION : Writes a value to an I2C device -*# -*#--------------------------------------------------------------------------*/ -int -i2c_writereg(unsigned char theSlave, unsigned char theReg, - unsigned char theValue) -{ - int error, cntr = 3; - unsigned long flags; - - spin_lock(&i2c_lock); - - do { - error = 0; - /* - * we don't like to be interrupted - */ - local_irq_save(flags); - - i2c_start(); - /* - * send slave address - */ - i2c_outbyte((theSlave & 0xfe)); - /* - * wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * now select register - */ - i2c_dir_out(); - i2c_outbyte(theReg); - /* - * now it's time to wait for ack - */ - if(!i2c_getack()) - error |= 2; - /* - * send register register data - */ - i2c_outbyte(theValue); - /* - * now it's time to wait for ack - */ - if(!i2c_getack()) - error |= 4; - /* - * end byte stream - */ - i2c_stop(); - /* - * enable interrupt again - */ - local_irq_restore(flags); - - } while(error && cntr--); - - i2c_delay(CLOCK_LOW_TIME); - - spin_unlock(&i2c_lock); - - return -error; -} - -/*#--------------------------------------------------------------------------- -*# -*# FUNCTION NAME: i2c_readreg -*# -*# DESCRIPTION : Reads a value from the decoder registers. -*# -*#--------------------------------------------------------------------------*/ -unsigned char -i2c_readreg(unsigned char theSlave, unsigned char theReg) -{ - unsigned char b = 0; - int error, cntr = 3; - unsigned long flags; - - spin_lock(&i2c_lock); - - do { - error = 0; - /* - * we don't like to be interrupted - */ - local_irq_save(flags); - /* - * generate start condition - */ - i2c_start(); - - /* - * send slave address - */ - i2c_outbyte((theSlave & 0xfe)); - /* - * wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * now select register - */ - i2c_dir_out(); - i2c_outbyte(theReg); - /* - * now it's time to wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * repeat start condition - */ - i2c_delay(CLOCK_LOW_TIME); - i2c_start(); - /* - * send slave address - */ - i2c_outbyte(theSlave | 0x01); - /* - * wait for ack - */ - if(!i2c_getack()) - error = 1; - /* - * fetch register - */ - b = i2c_inbyte(); - /* - * last received byte needs to be nacked - * instead of acked - */ - i2c_sendnack(); - /* - * end sequence - */ - i2c_stop(); - /* - * enable interrupt again - */ - local_irq_restore(flags); - - } while(error && cntr--); - - spin_unlock(&i2c_lock); - - return b; -} - -static int -i2c_open(struct inode *inode, struct file *filp) -{ - return 0; -} - -static int -i2c_release(struct inode *inode, struct file *filp) -{ - return 0; -} - -/* Main device API. ioctl's to write or read to/from i2c registers. - */ - -static long i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) { - return -EINVAL; - } - - switch (_IOC_NR(cmd)) { - case I2C_WRITEREG: - /* write to an i2c slave */ - D(printk(KERN_DEBUG "i2cw %d %d %d\n", - I2C_ARGSLAVE(arg), - I2C_ARGREG(arg), - I2C_ARGVALUE(arg))); - - return i2c_writereg(I2C_ARGSLAVE(arg), - I2C_ARGREG(arg), - I2C_ARGVALUE(arg)); - case I2C_READREG: - { - unsigned char val; - /* read from an i2c slave */ - D(printk(KERN_DEBUG "i2cr %d %d ", - I2C_ARGSLAVE(arg), - I2C_ARGREG(arg))); - val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg)); - D(printk(KERN_DEBUG "= %d\n", val)); - return val; - } - default: - return -EINVAL; - - } - return 0; -} - -static const struct file_operations i2c_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = i2c_ioctl, - .open = i2c_open, - .release = i2c_release, - .llseek = noop_llseek, -}; - -int __init -i2c_init(void) -{ - static int res = 0; - static int first = 1; - - if (!first) { - return res; - } - first = 0; - - /* Setup and enable the Port B I2C interface */ - -#ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C - if ((res = cris_request_io_interface(if_i2c, "I2C"))) { - printk(KERN_CRIT "i2c_init: Failed to get IO interface\n"); - return res; - } - - *R_PORT_PB_I2C = port_pb_i2c_shadow |= - IO_STATE(R_PORT_PB_I2C, i2c_en, on) | - IO_FIELD(R_PORT_PB_I2C, i2c_d, 1) | - IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1) | - IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable); - - port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0); - port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1); - - *R_PORT_PB_DIR = (port_pb_dir_shadow |= - IO_STATE(R_PORT_PB_DIR, dir0, input) | - IO_STATE(R_PORT_PB_DIR, dir1, output)); -#else - if ((res = cris_io_interface_allocate_pins(if_i2c, - 'b', - CONFIG_ETRAX_I2C_DATA_PORT, - CONFIG_ETRAX_I2C_DATA_PORT))) { - printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C data port\n"); - return res; - } else if ((res = cris_io_interface_allocate_pins(if_i2c, - 'b', - CONFIG_ETRAX_I2C_CLK_PORT, - CONFIG_ETRAX_I2C_CLK_PORT))) { - cris_io_interface_free_pins(if_i2c, - 'b', - CONFIG_ETRAX_I2C_DATA_PORT, - CONFIG_ETRAX_I2C_DATA_PORT); - printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C clk port\n"); - } -#endif - - return res; -} - -static int __init -i2c_register(void) -{ - int res; - - res = i2c_init(); - if (res < 0) - return res; - res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops); - if(res < 0) { - printk(KERN_ERR "i2c: couldn't get a major number.\n"); - return res; - } - - printk(KERN_INFO "I2C driver v2.2, (c) 1999-2004 Axis Communications AB\n"); - - return 0; -} - -/* this makes sure that i2c_register is called during boot */ - -module_init(i2c_register); - -/****************** END OF FILE i2c.c ********************************/ diff --git a/arch/cris/arch-v10/drivers/i2c.h b/arch/cris/arch-v10/drivers/i2c.h deleted file mode 100644 index de45c1ffbd7b..000000000000 --- a/arch/cris/arch-v10/drivers/i2c.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* i2c.h */ -int i2c_init(void); - -/* High level I2C actions */ -int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); -unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg); - -/* Low level I2C */ -void i2c_start(void); -void i2c_stop(void); -void i2c_outbyte(unsigned char x); -unsigned char i2c_inbyte(void); -int i2c_getack(void); -void i2c_sendack(void); - - - diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c deleted file mode 100644 index ed1a568a7217..000000000000 --- a/arch/cris/arch-v10/drivers/sync_serial.c +++ /dev/null @@ -1,1463 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Simple synchronous serial port driver for ETRAX 100LX. - * - * Synchronous serial ports are used for continuous streamed data like audio. - * The default setting for this driver is compatible with the STA 013 MP3 - * decoder. The driver can easily be tuned to fit other audio encoder/decoders - * and SPI - * - * Copyright (c) 2001-2008 Axis Communications AB - * - * Author: Mikael Starvik, Johan Adolfsson - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* The receiver is a bit tricky because of the continuous stream of data.*/ -/* */ -/* Three DMA descriptors are linked together. Each DMA descriptor is */ -/* responsible for port->bufchunk of a common buffer. */ -/* */ -/* +---------------------------------------------+ */ -/* | +----------+ +----------+ +----------+ | */ -/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ -/* +----------+ +----------+ +----------+ */ -/* | | | */ -/* v v v */ -/* +-------------------------------------+ */ -/* | BUFFER | */ -/* +-------------------------------------+ */ -/* |<- data_avail ->| */ -/* readp writep */ -/* */ -/* If the application keeps up the pace readp will be right after writep.*/ -/* If the application can't keep the pace we have to throw away data. */ -/* The idea is that readp should be ready with the data pointed out by */ -/* Descr[i] when the DMA has filled in Descr[i+1]. */ -/* Otherwise we will discard */ -/* the rest of the data pointed out by Descr1 and set readp to the start */ -/* of Descr2 */ - -#define SYNC_SERIAL_MAJOR 125 - -/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ -/* words can be handled */ -#define IN_BUFFER_SIZE 12288 -#define IN_DESCR_SIZE 256 -#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) -#define OUT_BUFFER_SIZE 4096 - -#define DEFAULT_FRAME_RATE 0 -#define DEFAULT_WORD_RATE 7 - -/* NOTE: Enabling some debug will likely cause overrun or underrun, - * especially if manual mode is use. - */ -#define DEBUG(x) -#define DEBUGREAD(x) -#define DEBUGWRITE(x) -#define DEBUGPOLL(x) -#define DEBUGRXINT(x) -#define DEBUGTXINT(x) - -/* Define some macros to access ETRAX 100 registers */ -#define SETF(var, reg, field, val) \ - do { \ - var = (var & ~IO_MASK_(reg##_, field##_)) | \ - IO_FIELD_(reg##_, field##_, val); \ - } while (0) - -#define SETS(var, reg, field, val) \ - do { \ - var = (var & ~IO_MASK_(reg##_, field##_)) | \ - IO_STATE_(reg##_, field##_, _##val); \ - } while (0) - -struct sync_port { - /* Etrax registers and bits*/ - const volatile unsigned *const status; - volatile unsigned *const ctrl_data; - volatile unsigned *const output_dma_first; - volatile unsigned char *const output_dma_cmd; - volatile unsigned char *const output_dma_clr_irq; - volatile unsigned *const input_dma_first; - volatile unsigned char *const input_dma_cmd; - volatile unsigned *const input_dma_descr; - /* 8*4 */ - volatile unsigned char *const input_dma_clr_irq; - volatile unsigned *const data_out; - const volatile unsigned *const data_in; - char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ - char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ - char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */ - - char output_dma_bit; /* In R_IRQ_MASK2_RD */ - /* End of fields initialised in array */ - char started; /* 1 if port has been started */ - char port_nbr; /* Port 0 or 1 */ - char busy; /* 1 if port is busy */ - - char enabled; /* 1 if port is enabled */ - char use_dma; /* 1 if port uses dma */ - char tr_running; - - char init_irqs; - - /* Register shadow */ - unsigned int ctrl_data_shadow; - /* Remaining bytes for current transfer */ - volatile unsigned int out_count; - /* Current position in out_buffer */ - unsigned char *outp; - /* 16*4 */ - /* Next byte to be read by application */ - volatile unsigned char *volatile readp; - /* Next byte to be written by etrax */ - volatile unsigned char *volatile writep; - - unsigned int in_buffer_size; - unsigned int inbufchunk; - struct etrax_dma_descr out_descr __attribute__ ((aligned(32))); - struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32))); - unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); - unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); - unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); - struct etrax_dma_descr *next_rx_desc; - struct etrax_dma_descr *prev_rx_desc; - int full; - - wait_queue_head_t out_wait_q; - wait_queue_head_t in_wait_q; -}; - - -static DEFINE_MUTEX(sync_serial_mutex); -static int etrax_sync_serial_init(void); -static void initialize_port(int portnbr); -static inline int sync_data_avail(struct sync_port *port); - -static int sync_serial_open(struct inode *inode, struct file *file); -static int sync_serial_release(struct inode *inode, struct file *file); -static __poll_t sync_serial_poll(struct file *filp, poll_table *wait); - -static long sync_serial_ioctl(struct file *file, - unsigned int cmd, unsigned long arg); -static ssize_t sync_serial_write(struct file *file, const char *buf, - size_t count, loff_t *ppos); -static ssize_t sync_serial_read(struct file *file, char *buf, - size_t count, loff_t *ppos); - -#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) -#define SYNC_SER_DMA -#endif - -static void send_word(struct sync_port *port); -static void start_dma(struct sync_port *port, const char *data, int count); -static void start_dma_in(struct sync_port *port); -#ifdef SYNC_SER_DMA -static irqreturn_t tr_interrupt(int irq, void *dev_id); -static irqreturn_t rx_interrupt(int irq, void *dev_id); -#endif -#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ - !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ - !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) -#define SYNC_SER_MANUAL -#endif -#ifdef SYNC_SER_MANUAL -static irqreturn_t manual_interrupt(int irq, void *dev_id); -#endif - -/* The ports */ -static struct sync_port ports[] = { - { - .status = R_SYNC_SERIAL1_STATUS, - .ctrl_data = R_SYNC_SERIAL1_CTRL, - .output_dma_first = R_DMA_CH8_FIRST, - .output_dma_cmd = R_DMA_CH8_CMD, - .output_dma_clr_irq = R_DMA_CH8_CLR_INTR, - .input_dma_first = R_DMA_CH9_FIRST, - .input_dma_cmd = R_DMA_CH9_CMD, - .input_dma_descr = R_DMA_CH9_DESCR, - .input_dma_clr_irq = R_DMA_CH9_CLR_INTR, - .data_out = R_SYNC_SERIAL1_TR_DATA, - .data_in = R_SYNC_SERIAL1_REC_DATA, - .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data), - .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready), - .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr), - .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop), - .init_irqs = 1, -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) - .use_dma = 1, -#else - .use_dma = 0, -#endif - }, - { - .status = R_SYNC_SERIAL3_STATUS, - .ctrl_data = R_SYNC_SERIAL3_CTRL, - .output_dma_first = R_DMA_CH4_FIRST, - .output_dma_cmd = R_DMA_CH4_CMD, - .output_dma_clr_irq = R_DMA_CH4_CLR_INTR, - .input_dma_first = R_DMA_CH5_FIRST, - .input_dma_cmd = R_DMA_CH5_CMD, - .input_dma_descr = R_DMA_CH5_DESCR, - .input_dma_clr_irq = R_DMA_CH5_CLR_INTR, - .data_out = R_SYNC_SERIAL3_TR_DATA, - .data_in = R_SYNC_SERIAL3_REC_DATA, - .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data), - .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready), - .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr), - .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop), - .init_irqs = 1, -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) - .use_dma = 1, -#else - .use_dma = 0, -#endif - } -}; - -/* Register shadows */ -static unsigned sync_serial_prescale_shadow; - -#define NUMBER_OF_PORTS 2 - -static const struct file_operations sync_serial_fops = { - .owner = THIS_MODULE, - .write = sync_serial_write, - .read = sync_serial_read, - .poll = sync_serial_poll, - .unlocked_ioctl = sync_serial_ioctl, - .open = sync_serial_open, - .release = sync_serial_release, - .llseek = noop_llseek, -}; - -static int __init etrax_sync_serial_init(void) -{ - ports[0].enabled = 0; - ports[1].enabled = 0; - -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) - if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) { - printk(KERN_CRIT "ETRAX100LX sync_serial: " - "Could not allocate IO group for port %d\n", 0); - return -EBUSY; - } -#endif -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) - if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) { -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) - cris_free_io_interface(if_sync_serial_1); -#endif - printk(KERN_CRIT "ETRAX100LX sync_serial: " - "Could not allocate IO group for port %d\n", 1); - return -EBUSY; - } -#endif - - if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial", - &sync_serial_fops) < 0) { -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) - cris_free_io_interface(if_sync_serial_3); -#endif -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) - cris_free_io_interface(if_sync_serial_1); -#endif - printk("unable to get major for synchronous serial port\n"); - return -EBUSY; - } - - /* Deselect synchronous serial ports while configuring. */ - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); - *R_GEN_CONFIG_II = gen_config_ii_shadow; - - /* Initialize Ports */ -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) - ports[0].enabled = 1; - SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra); - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) - ports[0].use_dma = 1; -#else - ports[0].use_dma = 0; -#endif - initialize_port(0); -#endif - -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) - ports[1].enabled = 1; - SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra); - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) - ports[1].use_dma = 1; -#else - ports[1].use_dma = 0; -#endif - initialize_port(1); -#endif - - *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */ - - /* Set up timing */ - *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = ( - IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | - IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | - IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | - IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | - IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | - IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, - DEFAULT_FRAME_RATE) | - IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) | - IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal)); - - /* Select synchronous ports */ - *R_GEN_CONFIG_II = gen_config_ii_shadow; - - printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n"); - return 0; -} - -static void __init initialize_port(int portnbr) -{ - struct sync_port *port = &ports[portnbr]; - - DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr)); - - port->started = 0; - port->port_nbr = portnbr; - port->busy = 0; - port->tr_running = 0; - - port->out_count = 0; - port->outp = port->out_buffer; - - port->readp = port->flip; - port->writep = port->flip; - port->in_buffer_size = IN_BUFFER_SIZE; - port->inbufchunk = IN_DESCR_SIZE; - port->next_rx_desc = &port->in_descr[0]; - port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1]; - port->prev_rx_desc->ctrl = d_eol; - - init_waitqueue_head(&port->out_wait_q); - init_waitqueue_head(&port->in_wait_q); - - port->ctrl_data_shadow = - IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) | - IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) | - IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) | - IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) | - IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) | - IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) | - IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) | - IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) | - IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) | - IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) | - IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) | - IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) | - IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) | - IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) | - IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) | - IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) | - IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)| - IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)| - IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) | - IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) | - IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)| - IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high); - - if (port->use_dma) - port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, - dma_enable, on); - else - port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, - dma_enable, off); - - *port->ctrl_data = port->ctrl_data_shadow; -} - -static inline int sync_data_avail(struct sync_port *port) -{ - int avail; - unsigned char *start; - unsigned char *end; - - start = (unsigned char *)port->readp; /* cast away volatile */ - end = (unsigned char *)port->writep; /* cast away volatile */ - /* 0123456789 0123456789 - * ----- - ----- - * ^rp ^wp ^wp ^rp - */ - if (end >= start) - avail = end - start; - else - avail = port->in_buffer_size - (start - end); - return avail; -} - -static inline int sync_data_avail_to_end(struct sync_port *port) -{ - int avail; - unsigned char *start; - unsigned char *end; - - start = (unsigned char *)port->readp; /* cast away volatile */ - end = (unsigned char *)port->writep; /* cast away volatile */ - /* 0123456789 0123456789 - * ----- ----- - * ^rp ^wp ^wp ^rp - */ - - if (end >= start) - avail = end - start; - else - avail = port->flip + port->in_buffer_size - start; - return avail; -} - - -static int sync_serial_open(struct inode *inode, struct file *file) -{ - int dev = MINOR(inode->i_rdev); - struct sync_port *port; - int mode; - int err = -EBUSY; - - mutex_lock(&sync_serial_mutex); - DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { - DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); - err = -ENODEV; - goto out; - } - port = &ports[dev]; - /* Allow open this device twice (assuming one reader and one writer) */ - if (port->busy == 2) { - DEBUG(printk(KERN_DEBUG "Device is busy.. \n")); - goto out; - } - if (port->init_irqs) { - if (port->use_dma) { - if (port == &ports[0]) { -#ifdef SYNC_SER_DMA - if (request_irq(24, tr_interrupt, 0, - "synchronous serial 1 dma tr", - &ports[0])) { - printk(KERN_CRIT "Can't alloc " - "sync serial port 1 IRQ"); - goto out; - } else if (request_irq(25, rx_interrupt, 0, - "synchronous serial 1 dma rx", - &ports[0])) { - free_irq(24, &port[0]); - printk(KERN_CRIT "Can't alloc " - "sync serial port 1 IRQ"); - goto out; - } else if (cris_request_dma(8, - "synchronous serial 1 dma tr", - DMA_VERBOSE_ON_ERROR, - dma_ser1)) { - free_irq(24, &port[0]); - free_irq(25, &port[0]); - printk(KERN_CRIT "Can't alloc " - "sync serial port 1 " - "TX DMA channel"); - goto out; - } else if (cris_request_dma(9, - "synchronous serial 1 dma rec", - DMA_VERBOSE_ON_ERROR, - dma_ser1)) { - cris_free_dma(8, NULL); - free_irq(24, &port[0]); - free_irq(25, &port[0]); - printk(KERN_CRIT "Can't alloc " - "sync serial port 1 " - "RX DMA channel"); - goto out; - } -#endif - RESET_DMA(8); WAIT_DMA(8); - RESET_DMA(9); WAIT_DMA(9); - *R_DMA_CH8_CLR_INTR = - IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, - do) | - IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, - do); - *R_DMA_CH9_CLR_INTR = - IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, - do) | - IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, - do); - *R_IRQ_MASK2_SET = - IO_STATE(R_IRQ_MASK2_SET, dma8_eop, - set) | - IO_STATE(R_IRQ_MASK2_SET, dma9_descr, - set); - } else if (port == &ports[1]) { -#ifdef SYNC_SER_DMA - if (request_irq(20, tr_interrupt, 0, - "synchronous serial 3 dma tr", - &ports[1])) { - printk(KERN_CRIT "Can't alloc " - "sync serial port 3 IRQ"); - goto out; - } else if (request_irq(21, rx_interrupt, 0, - "synchronous serial 3 dma rx", - &ports[1])) { - free_irq(20, &ports[1]); - printk(KERN_CRIT "Can't alloc " - "sync serial port 3 IRQ"); - goto out; - } else if (cris_request_dma(4, - "synchronous serial 3 dma tr", - DMA_VERBOSE_ON_ERROR, - dma_ser3)) { - free_irq(21, &ports[1]); - free_irq(20, &ports[1]); - printk(KERN_CRIT "Can't alloc " - "sync serial port 3 " - "TX DMA channel"); - goto out; - } else if (cris_request_dma(5, - "synchronous serial 3 dma rec", - DMA_VERBOSE_ON_ERROR, - dma_ser3)) { - cris_free_dma(4, NULL); - free_irq(21, &ports[1]); - free_irq(20, &ports[1]); - printk(KERN_CRIT "Can't alloc " - "sync serial port 3 " - "RX DMA channel"); - goto out; - } -#endif - RESET_DMA(4); WAIT_DMA(4); - RESET_DMA(5); WAIT_DMA(5); - *R_DMA_CH4_CLR_INTR = - IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, - do) | - IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, - do); - *R_DMA_CH5_CLR_INTR = - IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, - do) | - IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, - do); - *R_IRQ_MASK2_SET = - IO_STATE(R_IRQ_MASK2_SET, dma4_eop, - set) | - IO_STATE(R_IRQ_MASK2_SET, dma5_descr, - set); - } - start_dma_in(port); - port->init_irqs = 0; - } else { /* !port->use_dma */ -#ifdef SYNC_SER_MANUAL - if (port == &ports[0]) { - if (request_irq(8, - manual_interrupt, - IRQF_SHARED, - "synchronous serial manual irq", - &ports[0])) { - printk(KERN_CRIT "Can't alloc " - "sync serial manual irq"); - goto out; - } - } else if (port == &ports[1]) { - if (request_irq(8, - manual_interrupt, - IRQF_SHARED, - "synchronous serial manual irq", - &ports[1])) { - printk(KERN_CRIT "Can't alloc " - "sync serial manual irq"); - goto out; - } - } - port->init_irqs = 0; -#else - panic("sync_serial: Manual mode not supported.\n"); -#endif /* SYNC_SER_MANUAL */ - } - } /* port->init_irqs */ - - port->busy++; - /* Start port if we use it as input */ - mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow); - if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) || - mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) || - mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) || - mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) { - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, - running); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, - enable); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, - enable); - port->started = 1; - *port->ctrl_data = port->ctrl_data_shadow; - if (!port->use_dma) - *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; - DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev)); - } - err = 0; - -out: - mutex_unlock(&sync_serial_mutex); - return err; -} - -static int sync_serial_release(struct inode *inode, struct file *file) -{ - int dev = MINOR(inode->i_rdev); - struct sync_port *port; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { - DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - if (port->busy) - port->busy--; - if (!port->busy) - *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) | - (1 << port->transmitter_ready_bit)); - - return 0; -} - - - -static __poll_t sync_serial_poll(struct file *file, poll_table *wait) -{ - int dev = MINOR(file_inode(file)->i_rdev); - __poll_t mask = 0; - struct sync_port *port; - DEBUGPOLL(static __poll_t prev_mask = 0); - - port = &ports[dev]; - poll_wait(file, &port->out_wait_q, wait); - poll_wait(file, &port->in_wait_q, wait); - /* Some room to write */ - if (port->out_count < OUT_BUFFER_SIZE) - mask |= EPOLLOUT | EPOLLWRNORM; - /* At least an inbufchunk of data */ - if (sync_data_avail(port) >= port->inbufchunk) - mask |= EPOLLIN | EPOLLRDNORM; - - DEBUGPOLL(if (mask != prev_mask) - printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n", - mask, - mask & EPOLLOUT ? "POLLOUT" : "", - mask & EPOLLIN ? "POLLIN" : ""); - prev_mask = mask; - ); - return mask; -} - -static int sync_serial_ioctl_unlocked(struct file *file, - unsigned int cmd, unsigned long arg) -{ - int return_val = 0; - unsigned long flags; - - int dev = MINOR(file_inode(file)->i_rdev); - struct sync_port *port; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { - DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); - return -1; - } - port = &ports[dev]; - - local_irq_save(flags); - /* Disable port while changing config */ - if (dev) { - if (port->use_dma) { - RESET_DMA(4); WAIT_DMA(4); - port->tr_running = 0; - port->out_count = 0; - port->outp = port->out_buffer; - *R_DMA_CH4_CLR_INTR = - IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) | - IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); - } - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); - } else { - if (port->use_dma) { - RESET_DMA(8); WAIT_DMA(8); - port->tr_running = 0; - port->out_count = 0; - port->outp = port->out_buffer; - *R_DMA_CH8_CLR_INTR = - IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) | - IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); - } - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); - } - *R_GEN_CONFIG_II = gen_config_ii_shadow; - local_irq_restore(flags); - - switch (cmd) { - case SSP_SPEED: - if (GET_SPEED(arg) == CODEC) { - if (dev) - SETS(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, clk_sel_u3, - codec); - else - SETS(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, clk_sel_u1, - codec); - - SETF(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, prescaler, - GET_FREQ(arg)); - SETF(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, frame_rate, - GET_FRAME_RATE(arg)); - SETF(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, word_rate, - GET_WORD_RATE(arg)); - } else { - SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - tr_baud, GET_SPEED(arg)); - if (dev) - SETS(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, clk_sel_u3, - baudrate); - else - SETS(sync_serial_prescale_shadow, - R_SYNC_SERIAL_PRESCALE, clk_sel_u1, - baudrate); - } - break; - case SSP_MODE: - if (arg > 5) - return -EINVAL; - if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT) - *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit; - else if (!port->use_dma) - *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; - SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg); - break; - case SSP_FRAME_SYNC: - if (arg & NORMAL_SYNC) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_synctype, normal); - else if (arg & EARLY_SYNC) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_synctype, early); - - if (arg & BIT_SYNC) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_syncsize, bit); - else if (arg & WORD_SYNC) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_syncsize, word); - else if (arg & EXTENDED_SYNC) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_syncsize, extended); - - if (arg & SYNC_ON) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_sync, on); - else if (arg & SYNC_OFF) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - f_sync, off); - - if (arg & WORD_SIZE_8) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - wordsize, size8bit); - else if (arg & WORD_SIZE_12) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - wordsize, size12bit); - else if (arg & WORD_SIZE_16) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - wordsize, size16bit); - else if (arg & WORD_SIZE_24) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - wordsize, size24bit); - else if (arg & WORD_SIZE_32) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - wordsize, size32bit); - - if (arg & BIT_ORDER_MSB) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - bitorder, msb); - else if (arg & BIT_ORDER_LSB) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - bitorder, lsb); - - if (arg & FLOW_CONTROL_ENABLE) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - flow_ctrl, enabled); - else if (arg & FLOW_CONTROL_DISABLE) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - flow_ctrl, disabled); - - if (arg & CLOCK_NOT_GATED) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_mode, normal); - else if (arg & CLOCK_GATED) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_mode, gated); - - break; - case SSP_IPOLARITY: - /* NOTE!! negedge is considered NORMAL */ - if (arg & CLOCK_NORMAL) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_polarity, neg); - else if (arg & CLOCK_INVERT) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_polarity, pos); - - if (arg & FRAME_NORMAL) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - frame_polarity, normal); - else if (arg & FRAME_INVERT) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - frame_polarity, inverted); - - if (arg & STATUS_NORMAL) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - status_polarity, normal); - else if (arg & STATUS_INVERT) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - status_polarity, inverted); - break; - case SSP_OPOLARITY: - if (arg & CLOCK_NORMAL) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_driver, normal); - else if (arg & CLOCK_INVERT) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_driver, inverted); - - if (arg & FRAME_NORMAL) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - frame_driver, normal); - else if (arg & FRAME_INVERT) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - frame_driver, inverted); - - if (arg & STATUS_NORMAL) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - status_driver, normal); - else if (arg & STATUS_INVERT) - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - status_driver, inverted); - break; - case SSP_SPI: - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, - disabled); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, - msb); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, - size8bit); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, - word); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, - normal); - if (arg & SPI_SLAVE) { - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - frame_polarity, inverted); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_polarity, neg); - SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - mode, SLAVE_INPUT); - } else { - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - frame_driver, inverted); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - clk_driver, inverted); - SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, - mode, MASTER_OUTPUT); - } - break; - case SSP_INBUFCHUNK: -#if 0 - if (arg > port->in_buffer_size/NUM_IN_DESCR) - return -EINVAL; - port->inbufchunk = arg; - /* Make sure in_buffer_size is a multiple of inbufchunk */ - port->in_buffer_size = - (port->in_buffer_size/port->inbufchunk) * - port->inbufchunk; - DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n", - port->inbufchunk, port->in_buffer_size)); - if (port->use_dma) { - if (port->port_nbr == 0) { - RESET_DMA(9); - WAIT_DMA(9); - } else { - RESET_DMA(5); - WAIT_DMA(5); - } - start_dma_in(port); - } -#endif - break; - default: - return_val = -1; - } - /* Make sure we write the config without interruption */ - local_irq_save(flags); - /* Set config and enable port */ - *port->ctrl_data = port->ctrl_data_shadow; - nop(); nop(); nop(); nop(); - *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow; - nop(); nop(); nop(); nop(); - if (dev) - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); - else - SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); - - *R_GEN_CONFIG_II = gen_config_ii_shadow; - /* Reset DMA. At readout from serial port the data could be shifted - * one byte if not resetting DMA. - */ - if (port->use_dma) { - if (port->port_nbr == 0) { - RESET_DMA(9); - WAIT_DMA(9); - } else { - RESET_DMA(5); - WAIT_DMA(5); - } - start_dma_in(port); - } - local_irq_restore(flags); - return return_val; -} - -static long sync_serial_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - long ret; - - mutex_lock(&sync_serial_mutex); - ret = sync_serial_ioctl_unlocked(file, cmd, arg); - mutex_unlock(&sync_serial_mutex); - - return ret; -} - - -static ssize_t sync_serial_write(struct file *file, const char *buf, - size_t count, loff_t *ppos) -{ - int dev = MINOR(file_inode(file)->i_rdev); - DECLARE_WAITQUEUE(wait, current); - struct sync_port *port; - unsigned long flags; - unsigned long c, c1; - unsigned long free_outp; - unsigned long outp; - unsigned long out_buffer; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { - DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - - DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n", - port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE)); - /* Space to end of buffer */ - /* - * out_buffer 012345<- c ->OUT_BUFFER_SIZE - * outp^ +out_count - * ^free_outp - * out_buffer 45<- c ->0123OUT_BUFFER_SIZE - * +out_count outp^ - * free_outp - * - */ - - /* Read variables that may be updated by interrupts */ - local_irq_save(flags); - if (count > OUT_BUFFER_SIZE - port->out_count) - count = OUT_BUFFER_SIZE - port->out_count; - - outp = (unsigned long)port->outp; - free_outp = outp + port->out_count; - local_irq_restore(flags); - out_buffer = (unsigned long)port->out_buffer; - - /* Find out where and how much to write */ - if (free_outp >= out_buffer + OUT_BUFFER_SIZE) - free_outp -= OUT_BUFFER_SIZE; - if (free_outp >= outp) - c = out_buffer + OUT_BUFFER_SIZE - free_outp; - else - c = outp - free_outp; - if (c > count) - c = count; - - DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n", - outp, free_outp, c)); - if (copy_from_user((void *)free_outp, buf, c)) - return -EFAULT; - - if (c != count) { - buf += c; - c1 = count - c; - DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n", - free_outp-out_buffer, c, c1)); - if (copy_from_user((void *)out_buffer, buf, c1)) - return -EFAULT; - } - local_irq_save(flags); - port->out_count += count; - local_irq_restore(flags); - - /* Make sure transmitter/receiver is running */ - if (!port->started) { - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, - running); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, - enable); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, - enable); - port->started = 1; - } - - *port->ctrl_data = port->ctrl_data_shadow; - - if (file->f_flags & O_NONBLOCK) { - local_irq_save(flags); - if (!port->tr_running) { - if (!port->use_dma) { - /* Start sender by writing data */ - send_word(port); - /* and enable transmitter ready IRQ */ - *R_IRQ_MASK1_SET = 1 << - port->transmitter_ready_bit; - } else - start_dma(port, - (unsigned char *volatile)port->outp, c); - } - local_irq_restore(flags); - DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n", - port->port_nbr, count)); - return count; - } - - /* Sleep until all sent */ - add_wait_queue(&port->out_wait_q, &wait); - set_current_state(TASK_INTERRUPTIBLE); - local_irq_save(flags); - if (!port->tr_running) { - if (!port->use_dma) { - /* Start sender by writing data */ - send_word(port); - /* and enable transmitter ready IRQ */ - *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit; - } else - start_dma(port, port->outp, c); - } - local_irq_restore(flags); - schedule(); - remove_wait_queue(&port->out_wait_q, &wait); - if (signal_pending(current)) - return -EINTR; - - DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count)); - return count; -} - -static ssize_t sync_serial_read(struct file *file, char *buf, - size_t count, loff_t *ppos) -{ - int dev = MINOR(file_inode(file)->i_rdev); - int avail; - struct sync_port *port; - unsigned char *start; - unsigned char *end; - unsigned long flags; - - if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { - DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - - DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n", - dev, count, port->readp - port->flip, - port->writep - port->flip, port->in_buffer_size)); - - if (!port->started) { - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, - running); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, - enable); - SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, - enable); - port->started = 1; - } - *port->ctrl_data = port->ctrl_data_shadow; - - /* Calculate number of available bytes */ - /* Save pointers to avoid that they are modified by interrupt */ - local_irq_save(flags); - start = (unsigned char *)port->readp; /* cast away volatile */ - end = (unsigned char *)port->writep; /* cast away volatile */ - local_irq_restore(flags); - while (start == end && !port->full) { - /* No data */ - if (file->f_flags & O_NONBLOCK) - return -EAGAIN; - - wait_event_interruptible(port->in_wait_q, - !(start == end && !port->full)); - if (signal_pending(current)) - return -EINTR; - - local_irq_save(flags); - start = (unsigned char *)port->readp; /* cast away volatile */ - end = (unsigned char *)port->writep; /* cast away volatile */ - local_irq_restore(flags); - } - - /* Lazy read, never return wrapped data. */ - if (port->full) - avail = port->in_buffer_size; - else if (end > start) - avail = end - start; - else - avail = port->flip + port->in_buffer_size - start; - - count = count > avail ? avail : count; - if (copy_to_user(buf, start, count)) - return -EFAULT; - /* Disable interrupts while updating readp */ - local_irq_save(flags); - port->readp += count; - if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ - port->readp = port->flip; - port->full = 0; - local_irq_restore(flags); - DEBUGREAD(printk(KERN_DEBUG "r %d\n", count)); - return count; -} - -static void send_word(struct sync_port *port) -{ - switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize, - port->ctrl_data_shadow)) { - case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): - port->out_count--; - *port->data_out = *port->outp++; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): - { - int data = (*port->outp++) << 8; - data |= *port->outp++; - port->out_count -= 2; - *port->data_out = data; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - } - case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): - port->out_count -= 2; - *port->data_out = *(unsigned short *)port->outp; - port->outp += 2; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): - port->out_count -= 3; - *port->data_out = *(unsigned int *)port->outp; - port->outp += 3; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): - port->out_count -= 4; - *port->data_out = *(unsigned int *)port->outp; - port->outp += 4; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - break; - } -} - - -static void start_dma(struct sync_port *port, const char *data, int count) -{ - port->tr_running = 1; - port->out_descr.hw_len = 0; - port->out_descr.next = 0; - port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */ - port->out_descr.sw_len = count; - port->out_descr.buf = virt_to_phys(data); - port->out_descr.status = 0; - - *port->output_dma_first = virt_to_phys(&port->out_descr); - *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); - DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n", - (unsigned long)data, count)); -} - -static void start_dma_in(struct sync_port *port) -{ - int i; - unsigned long buf; - port->writep = port->flip; - - if (port->writep > port->flip + port->in_buffer_size) { - panic("Offset too large in sync serial driver\n"); - return; - } - buf = virt_to_phys(port->in_buffer); - for (i = 0; i < NUM_IN_DESCR; i++) { - port->in_descr[i].sw_len = port->inbufchunk; - port->in_descr[i].ctrl = d_int; - port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]); - port->in_descr[i].buf = buf; - port->in_descr[i].hw_len = 0; - port->in_descr[i].status = 0; - port->in_descr[i].fifo_len = 0; - buf += port->inbufchunk; - prepare_rx_descriptor(&port->in_descr[i]); - } - /* Link the last descriptor to the first */ - port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]); - port->in_descr[i-1].ctrl |= d_eol; - port->next_rx_desc = &port->in_descr[0]; - port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1]; - *port->input_dma_first = virt_to_phys(port->next_rx_desc); - *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); -} - -#ifdef SYNC_SER_DMA -static irqreturn_t tr_interrupt(int irq, void *dev_id) -{ - unsigned long ireg = *R_IRQ_MASK2_RD; - struct etrax_dma_descr *descr; - unsigned int sentl; - int handled = 0; - int i; - - for (i = 0; i < NUMBER_OF_PORTS; i++) { - struct sync_port *port = &ports[i]; - if (!port->enabled || !port->use_dma) - continue; - - /* IRQ active for the port? */ - if (!(ireg & (1 << port->output_dma_bit))) - continue; - - handled = 1; - - /* Clear IRQ */ - *port->output_dma_clr_irq = - IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) | - IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do); - - descr = &port->out_descr; - if (!(descr->status & d_stop)) - sentl = descr->sw_len; - else - /* Otherwise find amount of data sent here */ - sentl = descr->hw_len; - - port->out_count -= sentl; - port->outp += sentl; - if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) - port->outp = port->out_buffer; - if (port->out_count) { - int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp; - if (c > port->out_count) - c = port->out_count; - DEBUGTXINT(printk(KERN_DEBUG - "tx_int DMAWRITE %i %i\n", sentl, c)); - start_dma(port, port->outp, c); - } else { - DEBUGTXINT(printk(KERN_DEBUG - "tx_int DMA stop %i\n", sentl)); - port->tr_running = 0; - } - /* wake up the waiting process */ - wake_up_interruptible(&port->out_wait_q); - } - return IRQ_RETVAL(handled); -} /* tr_interrupt */ - -static irqreturn_t rx_interrupt(int irq, void *dev_id) -{ - unsigned long ireg = *R_IRQ_MASK2_RD; - int i; - int handled = 0; - - for (i = 0; i < NUMBER_OF_PORTS; i++) { - struct sync_port *port = &ports[i]; - - if (!port->enabled || !port->use_dma) - continue; - - if (!(ireg & (1 << port->input_dma_descr_bit))) - continue; - - /* Descriptor interrupt */ - handled = 1; - while (*port->input_dma_descr != - virt_to_phys(port->next_rx_desc)) { - if (port->writep + port->inbufchunk > port->flip + - port->in_buffer_size) { - int first_size = port->flip + - port->in_buffer_size - port->writep; - memcpy(port->writep, - phys_to_virt(port->next_rx_desc->buf), - first_size); - memcpy(port->flip, - phys_to_virt(port->next_rx_desc->buf + - first_size), - port->inbufchunk - first_size); - port->writep = port->flip + - port->inbufchunk - first_size; - } else { - memcpy(port->writep, - phys_to_virt(port->next_rx_desc->buf), - port->inbufchunk); - port->writep += port->inbufchunk; - if (port->writep >= port->flip - + port->in_buffer_size) - port->writep = port->flip; - } - if (port->writep == port->readp) - port->full = 1; - prepare_rx_descriptor(port->next_rx_desc); - port->next_rx_desc->ctrl |= d_eol; - port->prev_rx_desc->ctrl &= ~d_eol; - port->prev_rx_desc = phys_to_virt((unsigned) - port->next_rx_desc); - port->next_rx_desc = phys_to_virt((unsigned) - port->next_rx_desc->next); - /* Wake up the waiting process */ - wake_up_interruptible(&port->in_wait_q); - *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD, - cmd, restart); - /* DMA has reached end of descriptor */ - *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR, - clr_descr, do); - } - } - return IRQ_RETVAL(handled); -} /* rx_interrupt */ -#endif /* SYNC_SER_DMA */ - -#ifdef SYNC_SER_MANUAL -static irqreturn_t manual_interrupt(int irq, void *dev_id) -{ - int i; - int handled = 0; - - for (i = 0; i < NUMBER_OF_PORTS; i++) { - struct sync_port *port = &ports[i]; - - if (!port->enabled || port->use_dma) - continue; - - /* Data received? */ - if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) { - handled = 1; - /* Read data */ - switch (port->ctrl_data_shadow & - IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) { - case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): - *port->writep++ = - *(volatile char *)port->data_in; - break; - case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): - { - int data = *(unsigned short *)port->data_in; - *port->writep = (data & 0x0ff0) >> 4; - *(port->writep + 1) = data & 0x0f; - port->writep += 2; - break; - } - case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): - *(unsigned short *)port->writep = - *(volatile unsigned short *)port->data_in; - port->writep += 2; - break; - case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): - *(unsigned int *)port->writep = *port->data_in; - port->writep += 3; - break; - case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): - *(unsigned int *)port->writep = *port->data_in; - port->writep += 4; - break; - } - - /* Wrap? */ - if (port->writep >= port->flip + port->in_buffer_size) - port->writep = port->flip; - if (port->writep == port->readp) { - /* Receive buffer overrun, discard oldest */ - port->readp++; - /* Wrap? */ - if (port->readp >= port->flip + - port->in_buffer_size) - port->readp = port->flip; - } - if (sync_data_avail(port) >= port->inbufchunk) { - /* Wake up application */ - wake_up_interruptible(&port->in_wait_q); - } - } - - /* Transmitter ready? */ - if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) { - if (port->out_count > 0) { - /* More data to send */ - send_word(port); - } else { - /* Transmission finished */ - /* Turn off IRQ */ - *R_IRQ_MASK1_CLR = 1 << - port->transmitter_ready_bit; - /* Wake up application */ - wake_up_interruptible(&port->out_wait_q); - } - } - } - return IRQ_RETVAL(handled); -} -#endif - -module_init(etrax_sync_serial_init); diff --git a/arch/cris/arch-v10/kernel/Makefile b/arch/cris/arch-v10/kernel/Makefile deleted file mode 100644 index 7ec04b4a285e..000000000000 --- a/arch/cris/arch-v10/kernel/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -extra-y := head.o - - -obj-y := entry.o traps.o shadows.o debugport.o irq.o \ - process.o setup.o signal.o traps.o time.o ptrace.o \ - dma.o io_interface_mux.o - -obj-$(CONFIG_ETRAX_KGDB) += kgdb.o -obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o -obj-$(CONFIG_MODULES) += crisksyms.o - -clean: - diff --git a/arch/cris/arch-v10/kernel/crisksyms.c b/arch/cris/arch-v10/kernel/crisksyms.c deleted file mode 100644 index e1d897ed5b37..000000000000 --- a/arch/cris/arch-v10/kernel/crisksyms.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -/* Export shadow registers for the CPU I/O pins */ -EXPORT_SYMBOL(genconfig_shadow); -EXPORT_SYMBOL(port_pa_data_shadow); -EXPORT_SYMBOL(port_pa_dir_shadow); -EXPORT_SYMBOL(port_pb_data_shadow); -EXPORT_SYMBOL(port_pb_dir_shadow); -EXPORT_SYMBOL(port_pb_config_shadow); -EXPORT_SYMBOL(port_g_data_shadow); - -/* Cache flush functions */ -EXPORT_SYMBOL(flush_etrax_cache); -EXPORT_SYMBOL(prepare_rx_descriptor); diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c deleted file mode 100644 index d30834d4dd7e..000000000000 --- a/arch/cris/arch-v10/kernel/debugport.c +++ /dev/null @@ -1,560 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Serialport functions for debugging - * - * Copyright (c) 2000-2007 Axis Communications AB - * - * Authors: Bjorn Wesen - * - * Exports: - * console_print_etrax(char *buf) - * int getDebugChar() - * putDebugChar(int) - * enableDebugIRQ() - * init_etrax_debug() - * - */ - -#include -#include -#include -#include -#include -#include - -extern void reset_watchdog(void); - -struct dbg_port -{ - unsigned int index; - const volatile unsigned* read; - volatile char* write; - volatile unsigned* xoff; - volatile char* baud; - volatile char* tr_ctrl; - volatile char* rec_ctrl; - unsigned long irq; - unsigned int started; - unsigned long baudrate; - unsigned char parity; - unsigned int bits; -}; - -struct dbg_port ports[]= -{ - { - 0, - R_SERIAL0_READ, - R_SERIAL0_TR_DATA, - R_SERIAL0_XOFF, - R_SERIAL0_BAUD, - R_SERIAL0_TR_CTRL, - R_SERIAL0_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser0_data, set), - 0, - 115200, - 'N', - 8 - }, - { - 1, - R_SERIAL1_READ, - R_SERIAL1_TR_DATA, - R_SERIAL1_XOFF, - R_SERIAL1_BAUD, - R_SERIAL1_TR_CTRL, - R_SERIAL1_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser1_data, set), - 0, - 115200, - 'N', - 8 - }, - { - 2, - R_SERIAL2_READ, - R_SERIAL2_TR_DATA, - R_SERIAL2_XOFF, - R_SERIAL2_BAUD, - R_SERIAL2_TR_CTRL, - R_SERIAL2_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser2_data, set), - 0, - 115200, - 'N', - 8 - }, - { - 3, - R_SERIAL3_READ, - R_SERIAL3_TR_DATA, - R_SERIAL3_XOFF, - R_SERIAL3_BAUD, - R_SERIAL3_TR_CTRL, - R_SERIAL3_REC_CTRL, - IO_STATE(R_IRQ_MASK1_SET, ser3_data, set), - 0, - 115200, - 'N', - 8 - } -}; - -#ifdef CONFIG_ETRAX_SERIAL -extern struct tty_driver *serial_driver; -#endif - -struct dbg_port* port = -#if defined(CONFIG_ETRAX_DEBUG_PORT0) - &ports[0]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) - &ports[1]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) - &ports[2]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) - &ports[3]; -#else - NULL; -#endif - -static struct dbg_port* kgdb_port = -#if defined(CONFIG_ETRAX_KGDB_PORT0) - &ports[0]; -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - &ports[1]; -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - &ports[2]; -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - &ports[3]; -#else - NULL; -#endif - -static void -start_port(struct dbg_port* p) -{ - unsigned long rec_ctrl = 0; - unsigned long tr_ctrl = 0; - - if (!p) - return; - - if (p->started) - return; - p->started = 1; - - if (p->index == 0) - { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); - } - else if (p->index == 1) - { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); - } - else if (p->index == 2) - { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select); - } - else - { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select); - } - - *R_GEN_CONFIG = genconfig_shadow; - - *p->xoff = - IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) | - IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) | - IO_FIELD(R_SERIAL0_XOFF, xoff_char, 0); - - switch (p->baudrate) - { - case 0: - case 115200: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); - break; - case 1200: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz); - break; - case 2400: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz); - break; - case 4800: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz); - break; - case 9600: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz); - break; - case 19200: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz); - break; - case 38400: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz); - break; - case 57600: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz); - break; - default: - *p->baud = - IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | - IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); - break; - } - - if (p->parity == 'E') { - rec_ctrl = - IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | - IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); - tr_ctrl = - IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | - IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); - } else if (p->parity == 'O') { - rec_ctrl = - IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) | - IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); - tr_ctrl = - IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd) | - IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); - } else { - rec_ctrl = - IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | - IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, disable); - tr_ctrl = - IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | - IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable); - } - if (p->bits == 7) - { - rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); - tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); - } - else - { - rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit); - tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit); - } - - *p->rec_ctrl = - IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) | - IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) | - IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) | - IO_STATE(R_SERIAL0_REC_CTRL, sampling, middle) | - IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) | - rec_ctrl; - - *p->tr_ctrl = - IO_FIELD(R_SERIAL0_TR_CTRL, txd, 0) | - IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) | - IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) | - IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, one_bit) | - IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, normal) | - tr_ctrl; -} - -static void -console_write_direct(struct console *co, const char *buf, unsigned int len) -{ - int i; - unsigned long flags; - - if (!port) - return; - - local_irq_save(flags); - - /* Send data */ - for (i = 0; i < len; i++) { - /* LF -> CRLF */ - if (buf[i] == '\n') { - while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) - ; - *port->write = '\r'; - } - /* Wait until transmitter is ready and send.*/ - while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) - ; - *port->write = buf[i]; - } - - /* - * Feed the watchdog, otherwise it will reset the chip during boot. - * The time to send an ordinary boot message line (10-90 chars) - * varies between 1-8ms at 115200. What makes up for the additional - * 90ms that allows the watchdog to bite? - */ - reset_watchdog(); - - local_irq_restore(flags); -} - -static void -console_write(struct console *co, const char *buf, unsigned int len) -{ - if (!port) - return; - - console_write_direct(co, buf, len); -} - -/* legacy function */ - -void -console_print_etrax(const char *buf) -{ - console_write(NULL, buf, strlen(buf)); -} - -/* Use polling to get a single character FROM the debug port */ - -int -getDebugChar(void) -{ - unsigned long readval; - - if (!kgdb_port) - return 0; - - do { - readval = *kgdb_port->read; - } while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail))); - - return (readval & IO_MASK(R_SERIAL0_READ, data_in)); -} - -/* Use polling to put a single character to the debug port */ - -void -putDebugChar(int val) -{ - if (!kgdb_port) - return; - - while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready))) - ; - *kgdb_port->write = val; -} - -/* Enable irq for receiving chars on the debug port, used by kgdb */ - -void -enableDebugIRQ(void) -{ - if (!kgdb_port) - return; - - *R_IRQ_MASK1_SET = kgdb_port->irq; - /* use R_VECT_MASK directly, since we really bypass Linux normal - * IRQ handling in kgdb anyway, we don't need to use enable_irq - */ - *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); - - *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); -} - -static int __init -console_setup(struct console *co, char *options) -{ - char* s; - - if (options) { - port = &ports[co->index]; - port->baudrate = 115200; - port->parity = 'N'; - port->bits = 8; - port->baudrate = simple_strtoul(options, NULL, 10); - s = options; - while(*s >= '0' && *s <= '9') - s++; - if (*s) port->parity = *s++; - if (*s) port->bits = *s++ - '0'; - port->started = 0; - start_port(0); - } - return 0; -} - - -/* This is a dummy serial device that throws away anything written to it. - * This is used when no debug output is wanted. - */ -static struct tty_driver dummy_driver; - -static int dummy_open(struct tty_struct *tty, struct file * filp) -{ - return 0; -} - -static void dummy_close(struct tty_struct *tty, struct file * filp) -{ -} - -static int dummy_write(struct tty_struct * tty, - const unsigned char *buf, int count) -{ - return count; -} - -static int dummy_write_room(struct tty_struct *tty) -{ - return 8192; -} - -static const struct tty_operations dummy_ops = { - .open = dummy_open, - .close = dummy_close, - .write = dummy_write, - .write_room = dummy_write_room, -}; - -void __init -init_dummy_console(void) -{ - memset(&dummy_driver, 0, sizeof(struct tty_driver)); - dummy_driver.driver_name = "serial"; - dummy_driver.name = "ttyS"; - dummy_driver.major = TTY_MAJOR; - dummy_driver.minor_start = 68; - dummy_driver.num = 1; /* etrax100 has 4 serial ports */ - dummy_driver.type = TTY_DRIVER_TYPE_SERIAL; - dummy_driver.subtype = SERIAL_TYPE_NORMAL; - dummy_driver.init_termios = tty_std_termios; - /* Normally B9600 default... */ - dummy_driver.init_termios.c_cflag = - B115200 | CS8 | CREAD | HUPCL | CLOCAL; - dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; - dummy_driver.init_termios.c_ispeed = 115200; - dummy_driver.init_termios.c_ospeed = 115200; - - dummy_driver.ops = &dummy_ops; - if (tty_register_driver(&dummy_driver)) - panic("Couldn't register dummy serial driver\n"); -} - -static struct tty_driver* -etrax_console_device(struct console* co, int *index) -{ - if (port) - *index = port->index; - else - *index = 0; -#ifdef CONFIG_ETRAX_SERIAL - return port ? serial_driver : &dummy_driver; -#else - return &dummy_driver; -#endif -} - -static struct console ser_console = { - name : "ttyS", - write: console_write, - read : NULL, - device : etrax_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : -1, - cflag : 0, - next : NULL -}; -static struct console ser0_console = { - name : "ttyS", - write: console_write, - read : NULL, - device : etrax_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 0, - cflag : 0, - next : NULL -}; - -static struct console ser1_console = { - name : "ttyS", - write: console_write, - read : NULL, - device : etrax_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 1, - cflag : 0, - next : NULL -}; -static struct console ser2_console = { - name : "ttyS", - write: console_write, - read : NULL, - device : etrax_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 2, - cflag : 0, - next : NULL -}; -static struct console ser3_console = { - name : "ttyS", - write: console_write, - read : NULL, - device : etrax_console_device, - unblank : NULL, - setup : console_setup, - flags : CON_PRINTBUFFER, - index : 3, - cflag : 0, - next : NULL -}; -/* - * Register console (for printk's etc) - */ - -int __init -init_etrax_debug(void) -{ - static int first = 1; - - if (!first) { - unregister_console(&ser_console); - register_console(&ser0_console); - register_console(&ser1_console); - register_console(&ser2_console); - register_console(&ser3_console); - init_dummy_console(); - return 0; - } - - first = 0; - register_console(&ser_console); - start_port(port); -#ifdef CONFIG_ETRAX_KGDB - start_port(kgdb_port); -#endif - return 0; -} -__initcall(init_etrax_debug); diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c deleted file mode 100644 index c68e978def05..000000000000 --- a/arch/cris/arch-v10/kernel/dma.c +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Wrapper for DMA channel allocator that updates DMA client muxing. - * Copyright 2004-2007, Axis Communications AB - */ - -#include -#include -#include - -#include -#include -#include - -/* Macro to access ETRAX 100 registers */ -#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ - IO_STATE_(reg##_, field##_, _##val) - - -static char used_dma_channels[MAX_DMA_CHANNELS]; -static const char * used_dma_channels_users[MAX_DMA_CHANNELS]; - -int cris_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, enum dma_owner owner) -{ - unsigned long flags; - unsigned long int gens; - int fail = -EINVAL; - - if (dmanr >= MAX_DMA_CHANNELS) { - printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr); - return -EINVAL; - } - - local_irq_save(flags); - if (used_dma_channels[dmanr]) { - local_irq_restore(flags); - if (options & DMA_VERBOSE_ON_ERROR) { - printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]); - } - if (options & DMA_PANIC_ON_ERROR) { - panic("request_dma error!"); - } - return -EBUSY; - } - - gens = genconfig_shadow; - - switch(owner) - { - case dma_eth: - if ((dmanr != NETWORK_TX_DMA_NBR) && - (dmanr != NETWORK_RX_DMA_NBR)) { - printk(KERN_CRIT "Invalid DMA channel for eth\n"); - goto bail; - } - break; - case dma_ser0: - if (dmanr == SER0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma6, serial0); - } else if (dmanr == SER0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma7, serial0); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser0\n"); - goto bail; - } - break; - case dma_ser1: - if (dmanr == SER1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma8, serial1); - } else if (dmanr == SER1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma9, serial1); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser1\n"); - goto bail; - } - break; - case dma_ser2: - if (dmanr == SER2_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, serial2); - } else if (dmanr == SER2_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, serial2); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser2\n"); - goto bail; - } - break; - case dma_ser3: - if (dmanr == SER3_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, serial3); - } else if (dmanr == SER3_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, serial3); - } else { - printk(KERN_CRIT "Invalid DMA channel for ser3\n"); - goto bail; - } - break; - case dma_ata: - if (dmanr == ATA_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, ata); - } else if (dmanr == ATA_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, ata); - } else { - printk(KERN_CRIT "Invalid DMA channel for ata\n"); - goto bail; - } - break; - case dma_ext0: - if (dmanr == EXTDMA0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, extdma0); - } else if (dmanr == EXTDMA0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, extdma0); - } else { - printk(KERN_CRIT "Invalid DMA channel for ext0\n"); - goto bail; - } - break; - case dma_ext1: - if (dmanr == EXTDMA1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma6, extdma1); - } else if (dmanr == EXTDMA1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma7, extdma1); - } else { - printk(KERN_CRIT "Invalid DMA channel for ext1\n"); - goto bail; - } - break; - case dma_int6: - if (dmanr == MEM2MEM_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma7, intdma6); - } else { - printk(KERN_CRIT "Invalid DMA channel for int6\n"); - goto bail; - } - break; - case dma_int7: - if (dmanr == MEM2MEM_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma6, intdma7); - } else { - printk(KERN_CRIT "Invalid DMA channel for int7\n"); - goto bail; - } - break; - case dma_usb: - if (dmanr == USB_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma8, usb); - } else if (dmanr == USB_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma9, usb); - } else { - printk(KERN_CRIT "Invalid DMA channel for usb\n"); - goto bail; - } - break; - case dma_scsi0: - if (dmanr == SCSI0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, scsi0); - } else if (dmanr == SCSI0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, scsi0); - } else { - printk(KERN_CRIT "Invalid DMA channel for scsi0\n"); - goto bail; - } - break; - case dma_scsi1: - if (dmanr == SCSI1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, scsi1); - } else if (dmanr == SCSI1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, scsi1); - } else { - printk(KERN_CRIT "Invalid DMA channel for scsi1\n"); - goto bail; - } - break; - case dma_par0: - if (dmanr == PAR0_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma2, par0); - } else if (dmanr == PAR0_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma3, par0); - } else { - printk(KERN_CRIT "Invalid DMA channel for par0\n"); - goto bail; - } - break; - case dma_par1: - if (dmanr == PAR1_TX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma4, par1); - } else if (dmanr == PAR1_RX_DMA_NBR) { - SETS(gens, R_GEN_CONFIG, dma5, par1); - } else { - printk(KERN_CRIT "Invalid DMA channel for par1\n"); - goto bail; - } - break; - default: - printk(KERN_CRIT "Invalid DMA owner.\n"); - goto bail; - } - - used_dma_channels[dmanr] = 1; - used_dma_channels_users[dmanr] = device_id; - - { - volatile int i; - genconfig_shadow = gens; - *R_GEN_CONFIG = genconfig_shadow; - /* Wait 12 cycles before doing any DMA command */ - for(i = 6; i > 0; i--) - nop(); - } - fail = 0; - bail: - local_irq_restore(flags); - return fail; -} - -void cris_free_dma(unsigned int dmanr, const char * device_id) -{ - unsigned long flags; - if (dmanr >= MAX_DMA_CHANNELS) { - printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr); - return; - } - - local_irq_save(flags); - if (!used_dma_channels[dmanr]) { - printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr); - } else if (device_id != used_dma_channels_users[dmanr]) { - printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr); - } else { - switch(dmanr) - { - case 0: - *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) == - IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset)); - break; - case 1: - *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) == - IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset)); - break; - case 2: - *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) == - IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset)); - break; - case 3: - *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) == - IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset)); - break; - case 4: - *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) == - IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset)); - break; - case 5: - *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) == - IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset)); - break; - case 6: - *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) == - IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); - break; - case 7: - *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) == - IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset)); - break; - case 8: - *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) == - IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset)); - break; - case 9: - *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) == - IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset)); - break; - } - used_dma_channels[dmanr] = 0; - } - local_irq_restore(flags); -} - -EXPORT_SYMBOL(cris_request_dma); -EXPORT_SYMBOL(cris_free_dma); diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S deleted file mode 100644 index 1f066eebbd2b..000000000000 --- a/arch/cris/arch-v10/kernel/entry.S +++ /dev/null @@ -1,978 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/cris/entry.S - * - * Copyright (C) 2000, 2001, 2002 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - */ - -/* - * entry.S contains the system-call and fault low-level handling routines. - * - * NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - * - * Stack layout in 'ret_from_system_call': - * ptrace needs to have all regs on the stack. - * if the order here is changed, it needs to be - * updated in fork.c:copy_process, signal.c:do_signal, - * ptrace.c and ptrace.h - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - - ;; functions exported from this file - - .globl system_call - .globl ret_from_intr - .globl ret_from_fork - .globl ret_from_kernel_thread - .globl resume - .globl multiple_interrupt - .globl hwbreakpoint - .globl IRQ1_interrupt - .globl spurious_interrupt - .globl hw_bp_trigs - .globl mmu_bus_fault - .globl do_sigtrap - .globl gdb_handle_breakpoint - .globl sys_call_table - - ;; below are various parts of system_call which are not in the fast-path - -#ifdef CONFIG_PREEMPT - ; Check if preemptive kernel scheduling should be done -_resume_kernel: - di - ; Load current task struct - movs.w -8192, $r0 ; THREAD_SIZE = 8192 - and.d $sp, $r0 - move.d [$r0+TI_preempt_count], $r10 ; Preemption disabled? - bne _Rexit - nop -_need_resched: - move.d [$r0+TI_flags], $r10 - btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set - bpl _Rexit - nop - ; Ok, lets's do some preemptive kernel scheduling - jsr preempt_schedule_irq - ; Load new task struct - movs.w -8192, $r0 ; THREAD_SIZE = 8192 - and.d $sp, $r0 - ; One more time (with new task) - ba _need_resched - nop -#else -#define _resume_kernel _Rexit -#endif - - ; Called at exit from fork. schedule_tail must be called to drop - ; spinlock if CONFIG_PREEMPT -ret_from_fork: - jsr schedule_tail - ba ret_from_sys_call - nop - -ret_from_kernel_thread: - jsr schedule_tail - move.d $r2, $r10 ; argument is here - jsr $r1 ; call the payload - moveq 0, $r9 ; no syscall restarts, TYVM... - ba ret_from_sys_call - -ret_from_intr: - ;; check for resched if preemptive kernel or if we're going back to user-mode - ;; this test matches the user_regs(regs) macro - ;; we cannot simply test $dccr, because that does not necessarily - ;; reflect what mode we'll return into. - - move.d [$sp + PT_dccr], $r0; regs->dccr - btstq 8, $r0 ; U-flag - bpl _resume_kernel - ; Note that di below is in delay slot - -_resume_userspace: - di ; so need_resched and sigpending don't change - - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - move.d [$r0+TI_flags], $r10 ; current->work - and.d _TIF_WORK_MASK, $r10 ; is there any work to be done on return - bne _work_pending - nop - ba _Rexit - nop - - ;; The system_call is called by a BREAK instruction, which works like - ;; an interrupt call but it stores the return PC in BRP instead of IRP. - ;; Since we dont really want to have two epilogues (one for system calls - ;; and one for interrupts) we push the contents of BRP instead of IRP in the - ;; system call prologue, to make it look like an ordinary interrupt on the - ;; stackframe. - ;; - ;; Since we can't have system calls inside interrupts, it should not matter - ;; that we don't stack IRP. - ;; - ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,r13,mof,srp - ;; - ;; This function looks on the _surface_ like spaghetti programming, but it's - ;; really designed so that the fast-path does not force cache-loading of non-used - ;; instructions. Only the non-common cases cause the outlined code to run.. - -system_call: - ;; stack-frame similar to the irq heads, which is reversed in ret_from_sys_call - move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame - push $srp - push $dccr - push $mof - subq 14*4, $sp ; make room for r0-r13 - movem $r13, [$sp] ; push r0-r13 - push $r10 ; push orig_r10 - clear.d [$sp=$sp-4] ; frametype == 0, normal stackframe - - movs.w -ENOSYS, $r0 - move.d $r0, [$sp+PT_r10] ; put the default return value in r10 in the frame - - ;; check if this process is syscall-traced - - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - move.d [$r0+TI_flags], $r0 - btstq TIF_SYSCALL_TRACE, $r0 - bmi _syscall_trace_entry - nop - -_syscall_traced: - - ;; check for sanity in the requested syscall number - - cmpu.w NR_syscalls, $r9 - bcc ret_from_sys_call - lslq 2, $r9 ; multiply by 4, in the delay slot - - ;; as a bonus 7th parameter, we give the location on the stack - ;; of the register structure itself. some syscalls need this. - - push $sp - - ;; the parameter carrying registers r10, r11, r12 and 13 are intact. - ;; the fifth and sixth parameters (if any) was in mof and srp - ;; respectively, and we need to put them on the stack. - - push $srp - push $mof - - jsr [$r9+sys_call_table] ; actually do the system call - addq 3*4, $sp ; pop the mof, srp and regs parameters - move.d $r10, [$sp+PT_r10] ; save the return value - - moveq 1, $r9 ; "parameter" to ret_from_sys_call to show it was a sys call - - ;; fall through into ret_from_sys_call to return - -ret_from_sys_call: - ;; r9 is a parameter - if >=1 we came from a syscall, if 0, from an irq - - ;; get the current task-struct pointer (see top for defs) - - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - di ; make sure need_resched and sigpending don't change - move.d [$r0+TI_flags],$r1 - and.d _TIF_ALLWORK_MASK, $r1 - bne _syscall_exit_work - nop - -_Rexit: - ;; this epilogue MUST match the prologues in multiple_interrupt, irq.h and ptregs.h - pop $r10 ; frametype - bne _RBFexit ; was not CRIS_FRAME_NORMAL, handle otherwise - addq 4, $sp ; skip orig_r10, in delayslot - movem [$sp+], $r13 ; registers r0-r13 - pop $mof ; multiply overflow register - pop $dccr ; condition codes - pop $srp ; subroutine return pointer - ;; now we have a 4-word SBFS frame which we do not want to restore - ;; using RBF since it was not stacked with SBFS. instead we would like to - ;; just get the PC value to restart it with, and skip the rest of - ;; the frame. - ;; Also notice that it's important to use instructions here that - ;; keep the interrupts disabled (since we've already popped DCCR) - move [$sp=$sp+16], $p8; pop the SBFS frame from the sp - jmpu [$sp-16] ; return through the irp field in the sbfs frame - -_RBFexit: - movem [$sp+], $r13 ; registers r0-r13, in delay slot - pop $mof ; multiply overflow register - pop $dccr ; condition codes - pop $srp ; subroutine return pointer - rbf [$sp+] ; return by popping the CPU status - - ;; We get here after doing a syscall if extra work might need to be done - ;; perform syscall exit tracing if needed - -_syscall_exit_work: - ;; $r0 contains current at this point and irq's are disabled - - move.d [$r0+TI_flags], $r1 - btstq TIF_SYSCALL_TRACE, $r1 - bpl _work_pending - nop - - ei - - move.d $r9, $r1 ; preserve r9 - jsr do_syscall_trace - move.d $r1, $r9 - - ba _resume_userspace - nop - -_work_pending: - move.d [$r0+TI_flags], $r1 - btstq TIF_NEED_RESCHED, $r1 - bpl _work_notifysig ; was neither trace nor sched, must be signal/notify - nop - -_work_resched: - move.d $r9, $r1 ; preserve r9 - jsr schedule - move.d $r1, $r9 - di - - move.d [$r0+TI_flags], $r1 - and.d _TIF_WORK_MASK, $r1; ignore the syscall trace counter - beq _Rexit - nop - btstq TIF_NEED_RESCHED, $r1 - bmi _work_resched ; current->work.need_resched - nop - -_work_notifysig: - ;; deal with pending signals and notify-resume requests - - move.d $r9, $r10 ; do_notify_resume syscall/irq param - move.d $sp, $r11 ; the regs param - move.d $r1, $r12 ; the thread_info_flags parameter - jsr do_notify_resume - - ba _Rexit - nop - - ;; We get here as a sidetrack when we've entered a syscall with the - ;; trace-bit set. We need to call do_syscall_trace and then continue - ;; with the call. - -_syscall_trace_entry: - ;; PT_r10 in the frame contains -ENOSYS as required, at this point - - jsr do_syscall_trace - - ;; now re-enter the syscall code to do the syscall itself - ;; we need to restore $r9 here to contain the wanted syscall, and - ;; the other parameter-bearing registers - - move.d [$sp+PT_r9], $r9 - move.d [$sp+PT_orig_r10], $r10 ; PT_r10 is already filled with -ENOSYS. - move.d [$sp+PT_r11], $r11 - move.d [$sp+PT_r12], $r12 - move.d [$sp+PT_r13], $r13 - move [$sp+PT_mof], $mof - move [$sp+PT_srp], $srp - - ba _syscall_traced - nop - - ;; resume performs the actual task-switching, by switching stack pointers - ;; input arguments: r10 = prev, r11 = next, r12 = thread offset in task struct - ;; returns old current in r10 - ;; - ;; TODO: see the i386 version. The switch_to which calls resume in our version - ;; could really be an inline asm of this. - -resume: - push $srp ; we keep the old/new PC on the stack - add.d $r12, $r10 ; r10 = current tasks tss - move $dccr, [$r10+THREAD_dccr]; save irq enable state - di - - move $usp, [$r10+ THREAD_usp] ; save user-mode stackpointer - - ;; See copy_thread for the reason why register R9 is saved. - subq 10*4, $sp - movem $r9, [$sp] ; save non-scratch registers and R9. - - move.d $sp, [$r10+THREAD_ksp] ; save the kernel stack pointer for the old task - move.d $sp, $r10 ; return last running task in r10 - and.d -8192, $r10 ; get thread_info from stackpointer - move.d [$r10+TI_task], $r10 ; get task - add.d $r12, $r11 ; find the new tasks tss - move.d [$r11+THREAD_ksp], $sp ; switch into the new stackframe by restoring kernel sp - - movem [$sp+], $r9 ; restore non-scratch registers and R9. - - move [$r11+THREAD_usp], $usp ; restore user-mode stackpointer - - move [$r11+THREAD_dccr], $dccr ; restore irq enable status - jump [$sp+] ; restore PC - - ;; This is the MMU bus fault handler. - ;; It needs to stack the CPU status and overall is different - ;; from the other interrupt handlers. - -mmu_bus_fault: - ;; For refills we try to do a quick page table lookup. If it is - ;; a real fault we let the mm subsystem handle it. - - ;; the first longword in the sbfs frame was the interrupted PC - ;; which fits nicely with the "IRP" slot in pt_regs normally used to - ;; contain the return address. used by Oops to print kernel errors. - sbfs [$sp=$sp-16] ; push the internal CPU status - push $dccr - di - subq 2*4, $sp - movem $r1, [$sp] - move.d [R_MMU_CAUSE], $r1 - ;; ETRAX 100LX TR89 bugfix: if the second half of an unaligned - ;; write causes a MMU-fault, it will not be restarted correctly. - ;; This could happen if a write crosses a page-boundary and the - ;; second page is not yet COW'ed or even loaded. The workaround - ;; is to clear the unaligned bit in the CPU status record, so - ;; that the CPU will rerun both the first and second halves of - ;; the instruction. This will not have any sideeffects unless - ;; the first half goes to any device or memory that can't be - ;; written twice, and which is mapped through the MMU. - ;; - ;; We only need to do this for writes. - btstq 8, $r1 ; Write access? - bpl 1f - nop - move.d [$sp+16], $r0 ; Clear unaligned bit in csrinstr - and.d ~(1<<5), $r0 - move.d $r0, [$sp+16] -1: btstq 12, $r1 ; Refill? - bpl 2f - lsrq 24, $r1 ; Get PGD index (bit 24-31) - move.d [current_pgd], $r0 ; PGD for the current process - move.d [$r0+$r1.d], $r0 ; Get PMD - beq 2f - nop - and.w PAGE_MASK, $r0 ; Remove PMD flags - move.d [R_MMU_CAUSE], $r1 - lsrq PAGE_SHIFT, $r1 - and.d 0x7ff, $r1 ; Get PTE index into PGD (bit 13-23) - move.d [$r0+$r1.d], $r1 ; Get PTE - beq 2f - nop - ;; Store in TLB - move.d $r1, [R_TLB_LO] - ;; Return - movem [$sp+], $r1 - pop $dccr - rbf [$sp+] ; return by popping the CPU status - -2: ; PMD or PTE missing, let the mm subsystem fix it up. - movem [$sp+], $r1 - pop $dccr - - ; Ok, not that easy, pass it on to the mm subsystem - ; The MMU status record is now on the stack - push $srp ; make a stackframe similar to pt_regs - push $dccr - push $mof - di - subq 14*4, $sp - movem $r13, [$sp] - push $r10 ; dummy orig_r10 - moveq 1, $r10 - push $r10 ; frametype == 1, BUSFAULT frame type - - move.d $sp, $r10 ; pt_regs argument to handle_mmu_bus_fault - - jsr handle_mmu_bus_fault ; in arch/cris/arch-v10/mm/fault.c - - ;; now we need to return through the normal path, we cannot just - ;; do the RBFexit since we might have killed off the running - ;; process due to a SEGV, scheduled due to a page blocking or - ;; whatever. - - moveq 0, $r9 ; busfault is equivalent to an irq - - ba ret_from_intr - nop - - ;; special handlers for breakpoint and NMI -hwbreakpoint: - push $dccr - di - push $r10 - push $r11 - move.d [hw_bp_trig_ptr],$r10 - move $brp,$r11 - move.d $r11,[$r10+] - move.d $r10,[hw_bp_trig_ptr] -1: pop $r11 - pop $r10 - pop $dccr - retb - nop - -IRQ1_interrupt: - ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!! - move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame - push $srp - push $dccr - push $mof - di - subq 14*4, $sp - movem $r13, [$sp] - push $r10 ; push orig_r10 - clear.d [$sp=$sp-4] ; frametype == 0, normal frame - - ;; If there is a glitch on the NMI pin shorter than ~100ns - ;; (i.e. non-active by the time we get here) then the nmi_pin bit - ;; in R_IRQ_MASK0_RD will already be cleared. The watchdog_nmi bit - ;; is cleared by us however (when feeding the watchdog), which is why - ;; we use that bit to determine what brought us here. - - move.d [R_IRQ_MASK0_RD], $r1 ; External NMI or watchdog? - and.d (1<<30), $r1 - bne wdog - move.d $sp, $r10 - jsr handle_nmi - setf m ; Enable NMI again - ba _Rexit ; Return the standard way - nop -wdog: -#if defined(CONFIG_ETRAX_WATCHDOG) -;; Check if we're waiting for reset to happen, as signalled by -;; hard_reset_now setting cause_of_death to a magic value. If so, just -;; get stuck until reset happens. - .comm cause_of_death, 4 ;; Don't declare this anywhere. - move.d [cause_of_death], $r10 - cmp.d 0xbedead, $r10 -_killed_by_death: - beq _killed_by_death - nop - -;; We'll see this in ksymoops dumps. -Watchdog_bite: - -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - ;; We just restart the watchdog here to be sure we dont get - ;; hit while printing the watchdogmsg below - ;; This restart is compatible with the rest of the C-code, so - ;; the C-code can keep restarting the watchdog after this point. - ;; The non-NICE_DOGGY code below though, disables the possibility - ;; to restart since it changes the watchdog key, to avoid any - ;; buggy loops etc. keeping the watchdog alive after this. - jsr reset_watchdog -#else - -;; We need to extend the 3.3ms after the NMI at watchdog bite, so we have -;; time for an oops-dump over a 115k2 serial wire. Another 100ms should do. - -;; Change the watchdog key to an arbitrary 3-bit value and restart the -;; watchdog. -#define WD_INIT 2 - moveq IO_FIELD (R_WATCHDOG, key, WD_INIT), $r10 - move.d R_WATCHDOG, $r11 - - move.d $r10, [$r11] - moveq IO_FIELD (R_WATCHDOG, key, \ - IO_EXTRACT (R_WATCHDOG, key, \ - IO_MASK (R_WATCHDOG, key)) \ - ^ WD_INIT) \ - | IO_STATE (R_WATCHDOG, enable, start), $r10 - move.d $r10, [$r11] - -#endif - -;; Note that we don't do "setf m" here (or after two necessary NOPs), -;; since *not* doing that saves us from re-entrancy checks. We don't want -;; to get here again due to possible subsequent NMIs; we want the watchdog -;; to reset us. - - move.d _watchdogmsg,$r10 - jsr printk - - move.d $sp, $r10 - jsr watchdog_bite_hook - -;; This nop is here so we see the "Watchdog_bite" label in ksymoops dumps -;; rather than "spurious_interrupt". - nop -;; At this point we drop down into spurious_interrupt, which will do a -;; hard reset. - - .section .rodata,"a" -_watchdogmsg: - .ascii "Oops: bitten by watchdog\n\0" - .previous - -#endif /* CONFIG_ETRAX_WATCHDOG */ - -spurious_interrupt: - di - jump hard_reset_now - - ;; this handles the case when multiple interrupts arrive at the same time - ;; we jump to the first set interrupt bit in a priority fashion - ;; the hardware will call the unserved interrupts after the handler finishes - -multiple_interrupt: - ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!! - move $irp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame - push $srp - push $dccr - push $mof - di - subq 14*4, $sp - movem $r13, [$sp] - push $r10 ; push orig_r10 - clear.d [$sp=$sp-4] ; frametype == 0, normal frame - - move.d $sp, $r10 - jsr do_multiple_IRQ - - jump ret_from_intr - -do_sigtrap: - ;; - ;; SIGTRAP the process that executed the break instruction. - ;; Make a frame that Rexit in entry.S expects. - ;; - move $brp, [$sp=$sp-16] ; Push BRP while faking a cpu status record. - push $srp ; Push subroutine return pointer. - push $dccr ; Push condition codes. - push $mof ; Push multiply overflow reg. - di ; Need to disable irq's at this point. - subq 14*4, $sp ; Make room for r0-r13. - movem $r13, [$sp] ; Push the r0-r13 registers. - push $r10 ; Push orig_r10. - clear.d [$sp=$sp-4] ; Frametype - this is a normal stackframe. - - movs.w -8192,$r9 ; THREAD_SIZE == 8192 - and.d $sp, $r9 - move.d [$r9+TI_task], $r10 - move.d [$r10+TASK_pid], $r10 ; current->pid as arg1. - moveq 5, $r11 ; SIGTRAP as arg2. - jsr sys_kill - jump ret_from_intr ; Use the return routine for interrupts. - -gdb_handle_breakpoint: - push $dccr - push $r0 -#ifdef CONFIG_ETRAX_KGDB - move $dccr, $r0 ; U-flag not affected by previous insns. - btstq 8, $r0 ; Test the U-flag. - bmi _ugdb_handle_breakpoint ; Go to user mode debugging. - nop ; Empty delay slot (cannot pop r0 here). - pop $r0 ; Restore r0. - ba kgdb_handle_breakpoint ; Go to kernel debugging. - pop $dccr ; Restore dccr in delay slot. -#endif - -_ugdb_handle_breakpoint: - move $brp, $r0 ; Use r0 temporarily for calculation. - subq 2, $r0 ; Set to address of previous instruction. - move $r0, $brp - pop $r0 ; Restore r0. - ba do_sigtrap ; SIGTRAP the offending process. - pop $dccr ; Restore dccr in delay slot. - - .data - -hw_bp_trigs: - .space 64*4 -hw_bp_trig_ptr: - .dword hw_bp_trigs - - .section .rodata,"a" -sys_call_table: - .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */ - .long sys_exit - .long sys_fork - .long sys_read - .long sys_write - .long sys_open /* 5 */ - .long sys_close - .long sys_waitpid - .long sys_creat - .long sys_link - .long sys_unlink /* 10 */ - .long sys_execve - .long sys_chdir - .long sys_time - .long sys_mknod - .long sys_chmod /* 15 */ - .long sys_lchown16 - .long sys_ni_syscall /* old break syscall holder */ - .long sys_stat - .long sys_lseek - .long sys_getpid /* 20 */ - .long sys_mount - .long sys_oldumount - .long sys_setuid16 - .long sys_getuid16 - .long sys_stime /* 25 */ - .long sys_ptrace - .long sys_alarm - .long sys_fstat - .long sys_pause - .long sys_utime /* 30 */ - .long sys_ni_syscall /* old stty syscall holder */ - .long sys_ni_syscall /* old gtty syscall holder */ - .long sys_access - .long sys_nice - .long sys_ni_syscall /* 35 old ftime syscall holder */ - .long sys_sync - .long sys_kill - .long sys_rename - .long sys_mkdir - .long sys_rmdir /* 40 */ - .long sys_dup - .long sys_pipe - .long sys_times - .long sys_ni_syscall /* old prof syscall holder */ - .long sys_brk /* 45 */ - .long sys_setgid16 - .long sys_getgid16 - .long sys_signal - .long sys_geteuid16 - .long sys_getegid16 /* 50 */ - .long sys_acct - .long sys_umount /* recycled never used phys( */ - .long sys_ni_syscall /* old lock syscall holder */ - .long sys_ioctl - .long sys_fcntl /* 55 */ - .long sys_ni_syscall /* old mpx syscall holder */ - .long sys_setpgid - .long sys_ni_syscall /* old ulimit syscall holder */ - .long sys_ni_syscall /* old sys_olduname holder */ - .long sys_umask /* 60 */ - .long sys_chroot - .long sys_ustat - .long sys_dup2 - .long sys_getppid - .long sys_getpgrp /* 65 */ - .long sys_setsid - .long sys_sigaction - .long sys_sgetmask - .long sys_ssetmask - .long sys_setreuid16 /* 70 */ - .long sys_setregid16 - .long sys_sigsuspend - .long sys_sigpending - .long sys_sethostname - .long sys_setrlimit /* 75 */ - .long sys_old_getrlimit - .long sys_getrusage - .long sys_gettimeofday - .long sys_settimeofday - .long sys_getgroups16 /* 80 */ - .long sys_setgroups16 - .long sys_select /* was old_select in Linux/E100 */ - .long sys_symlink - .long sys_lstat - .long sys_readlink /* 85 */ - .long sys_uselib - .long sys_swapon - .long sys_reboot - .long sys_old_readdir - .long sys_old_mmap /* 90 */ - .long sys_munmap - .long sys_truncate - .long sys_ftruncate - .long sys_fchmod - .long sys_fchown16 /* 95 */ - .long sys_getpriority - .long sys_setpriority - .long sys_ni_syscall /* old profil syscall holder */ - .long sys_statfs - .long sys_fstatfs /* 100 */ - .long sys_ni_syscall /* sys_ioperm in i386 */ - .long sys_socketcall - .long sys_syslog - .long sys_setitimer - .long sys_getitimer /* 105 */ - .long sys_newstat - .long sys_newlstat - .long sys_newfstat - .long sys_ni_syscall /* old sys_uname holder */ - .long sys_ni_syscall /* 110 */ /* sys_iopl in i386 */ - .long sys_vhangup - .long sys_ni_syscall /* old "idle" system call */ - .long sys_ni_syscall /* vm86old in i386 */ - .long sys_wait4 - .long sys_swapoff /* 115 */ - .long sys_sysinfo - .long sys_ipc - .long sys_fsync - .long sys_sigreturn - .long sys_clone /* 120 */ - .long sys_setdomainname - .long sys_newuname - .long sys_ni_syscall /* sys_modify_ldt */ - .long sys_adjtimex - .long sys_mprotect /* 125 */ - .long sys_sigprocmask - .long sys_ni_syscall /* old "create_module" */ - .long sys_init_module - .long sys_delete_module - .long sys_ni_syscall /* 130: old "get_kernel_syms" */ - .long sys_quotactl - .long sys_getpgid - .long sys_fchdir - .long sys_bdflush - .long sys_sysfs /* 135 */ - .long sys_personality - .long sys_ni_syscall /* for afs_syscall */ - .long sys_setfsuid16 - .long sys_setfsgid16 - .long sys_llseek /* 140 */ - .long sys_getdents - .long sys_select - .long sys_flock - .long sys_msync - .long sys_readv /* 145 */ - .long sys_writev - .long sys_getsid - .long sys_fdatasync - .long sys_sysctl - .long sys_mlock /* 150 */ - .long sys_munlock - .long sys_mlockall - .long sys_munlockall - .long sys_sched_setparam - .long sys_sched_getparam /* 155 */ - .long sys_sched_setscheduler - .long sys_sched_getscheduler - .long sys_sched_yield - .long sys_sched_get_priority_max - .long sys_sched_get_priority_min /* 160 */ - .long sys_sched_rr_get_interval - .long sys_nanosleep - .long sys_mremap - .long sys_setresuid16 - .long sys_getresuid16 /* 165 */ - .long sys_ni_syscall /* sys_vm86 */ - .long sys_ni_syscall /* Old sys_query_module */ - .long sys_poll - .long sys_ni_syscall /* old nfsservctl */ - .long sys_setresgid16 /* 170 */ - .long sys_getresgid16 - .long sys_prctl - .long sys_rt_sigreturn - .long sys_rt_sigaction - .long sys_rt_sigprocmask /* 175 */ - .long sys_rt_sigpending - .long sys_rt_sigtimedwait - .long sys_rt_sigqueueinfo - .long sys_rt_sigsuspend - .long sys_pread64 /* 180 */ - .long sys_pwrite64 - .long sys_chown16 - .long sys_getcwd - .long sys_capget - .long sys_capset /* 185 */ - .long sys_sigaltstack - .long sys_sendfile - .long sys_ni_syscall /* streams1 */ - .long sys_ni_syscall /* streams2 */ - .long sys_vfork /* 190 */ - .long sys_getrlimit - .long sys_mmap2 /* mmap_pgoff */ - .long sys_truncate64 - .long sys_ftruncate64 - .long sys_stat64 /* 195 */ - .long sys_lstat64 - .long sys_fstat64 - .long sys_lchown - .long sys_getuid - .long sys_getgid /* 200 */ - .long sys_geteuid - .long sys_getegid - .long sys_setreuid - .long sys_setregid - .long sys_getgroups /* 205 */ - .long sys_setgroups - .long sys_fchown - .long sys_setresuid - .long sys_getresuid - .long sys_setresgid /* 210 */ - .long sys_getresgid - .long sys_chown - .long sys_setuid - .long sys_setgid - .long sys_setfsuid /* 215 */ - .long sys_setfsgid - .long sys_pivot_root - .long sys_mincore - .long sys_madvise - .long sys_getdents64 /* 220 */ - .long sys_fcntl64 - .long sys_ni_syscall /* reserved for TUX */ - .long sys_ni_syscall - .long sys_gettid - .long sys_readahead /* 225 */ - .long sys_setxattr - .long sys_lsetxattr - .long sys_fsetxattr - .long sys_getxattr - .long sys_lgetxattr /* 230 */ - .long sys_fgetxattr - .long sys_listxattr - .long sys_llistxattr - .long sys_flistxattr - .long sys_removexattr /* 235 */ - .long sys_lremovexattr - .long sys_fremovexattr - .long sys_tkill - .long sys_sendfile64 - .long sys_futex /* 240 */ - .long sys_sched_setaffinity - .long sys_sched_getaffinity - .long sys_ni_syscall /* sys_set_thread_area */ - .long sys_ni_syscall /* sys_get_thread_area */ - .long sys_io_setup /* 245 */ - .long sys_io_destroy - .long sys_io_getevents - .long sys_io_submit - .long sys_io_cancel - .long sys_fadvise64 /* 250 */ - .long sys_ni_syscall - .long sys_exit_group - .long sys_lookup_dcookie - .long sys_epoll_create - .long sys_epoll_ctl /* 255 */ - .long sys_epoll_wait - .long sys_remap_file_pages - .long sys_set_tid_address - .long sys_timer_create - .long sys_timer_settime /* 260 */ - .long sys_timer_gettime - .long sys_timer_getoverrun - .long sys_timer_delete - .long sys_clock_settime - .long sys_clock_gettime /* 265 */ - .long sys_clock_getres - .long sys_clock_nanosleep - .long sys_statfs64 - .long sys_fstatfs64 - .long sys_tgkill /* 270 */ - .long sys_utimes - .long sys_fadvise64_64 - .long sys_ni_syscall /* sys_vserver */ - .long sys_ni_syscall /* sys_mbind */ - .long sys_ni_syscall /* 275 sys_get_mempolicy */ - .long sys_ni_syscall /* sys_set_mempolicy */ - .long sys_mq_open - .long sys_mq_unlink - .long sys_mq_timedsend - .long sys_mq_timedreceive /* 280 */ - .long sys_mq_notify - .long sys_mq_getsetattr - .long sys_ni_syscall - .long sys_waitid - .long sys_ni_syscall /* 285 */ /* available */ - .long sys_add_key - .long sys_request_key - .long sys_keyctl - .long sys_ioprio_set - .long sys_ioprio_get /* 290 */ - .long sys_inotify_init - .long sys_inotify_add_watch - .long sys_inotify_rm_watch - .long sys_migrate_pages - .long sys_openat /* 295 */ - .long sys_mkdirat - .long sys_mknodat - .long sys_fchownat - .long sys_futimesat - .long sys_fstatat64 /* 300 */ - .long sys_unlinkat - .long sys_renameat - .long sys_linkat - .long sys_symlinkat - .long sys_readlinkat /* 305 */ - .long sys_fchmodat - .long sys_faccessat - .long sys_pselect6 - .long sys_ppoll - .long sys_unshare /* 310 */ - .long sys_set_robust_list - .long sys_get_robust_list - .long sys_splice - .long sys_sync_file_range - .long sys_tee /* 315 */ - .long sys_vmsplice - .long sys_move_pages - .long sys_getcpu - .long sys_epoll_pwait - .long sys_utimensat /* 320 */ - .long sys_signalfd - .long sys_timerfd_create - .long sys_eventfd - .long sys_fallocate - .long sys_timerfd_settime /* 325 */ - .long sys_timerfd_gettime - .long sys_signalfd4 - .long sys_eventfd2 - .long sys_epoll_create1 - .long sys_dup3 /* 330 */ - .long sys_pipe2 - .long sys_inotify_init1 - .long sys_preadv - .long sys_pwritev - .long sys_setns /* 335 */ - .long sys_name_to_handle_at - .long sys_open_by_handle_at - .long sys_rt_tgsigqueueinfo - .long sys_perf_event_open - .long sys_recvmmsg /* 340 */ - .long sys_accept4 - .long sys_fanotify_init - .long sys_fanotify_mark - .long sys_prlimit64 - .long sys_clock_adjtime /* 345 */ - .long sys_syncfs - .long sys_sendmmsg - .long sys_process_vm_readv - .long sys_process_vm_writev - .long sys_kcmp /* 350 */ - .long sys_finit_module - .long sys_sched_setattr - .long sys_sched_getattr - .long sys_renameat2 - .long sys_seccomp /* 355 */ - .long sys_getrandom - .long sys_memfd_create - .long sys_bpf - .long sys_execveat - - /* - * NOTE!! This doesn't have to be exact - we just have - * to make sure we have _enough_ of the "sys_ni_syscall" - * entries. Don't panic if you notice that this hasn't - * been shrunk every time we add a new system call. - */ - - .rept NR_syscalls-(.-sys_call_table)/4 - .long sys_ni_syscall - .endr - diff --git a/arch/cris/arch-v10/kernel/fasttimer.c b/arch/cris/arch-v10/kernel/fasttimer.c deleted file mode 100644 index 94abbff557ff..000000000000 --- a/arch/cris/arch-v10/kernel/fasttimer.c +++ /dev/null @@ -1,835 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/fasttimer.c - * - * Fast timers for ETRAX100/ETRAX100LX - * - * Copyright (C) 2000-2007 Axis Communications AB, Lund, Sweden - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - - -#define DEBUG_LOG_INCLUDED -#define FAST_TIMER_LOG -/* #define FAST_TIMER_TEST */ - -#define FAST_TIMER_SANITY_CHECKS - -#ifdef FAST_TIMER_SANITY_CHECKS -static int sanity_failed; -#endif - -#define D1(x) -#define D2(x) -#define DP(x) - -static unsigned int fast_timer_running; -static unsigned int fast_timers_added; -static unsigned int fast_timers_started; -static unsigned int fast_timers_expired; -static unsigned int fast_timers_deleted; -static unsigned int fast_timer_is_init; -static unsigned int fast_timer_ints; - -struct fast_timer *fast_timer_list = NULL; - -#ifdef DEBUG_LOG_INCLUDED -#define DEBUG_LOG_MAX 128 -static const char * debug_log_string[DEBUG_LOG_MAX]; -static unsigned long debug_log_value[DEBUG_LOG_MAX]; -static unsigned int debug_log_cnt; -static unsigned int debug_log_cnt_wrapped; - -#define DEBUG_LOG(string, value) \ -{ \ - unsigned long log_flags; \ - local_irq_save(log_flags); \ - debug_log_string[debug_log_cnt] = (string); \ - debug_log_value[debug_log_cnt] = (unsigned long)(value); \ - if (++debug_log_cnt >= DEBUG_LOG_MAX) \ - { \ - debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \ - debug_log_cnt_wrapped = 1; \ - } \ - local_irq_restore(log_flags); \ -} -#else -#define DEBUG_LOG(string, value) -#endif - - -/* The frequencies for index = clkselx number in R_TIMER_CTRL */ -#define NUM_TIMER_FREQ 15 -#define MAX_USABLE_TIMER_FREQ 7 -#define MAX_DELAY_US 853333L -const unsigned long timer_freq_100[NUM_TIMER_FREQ] = -{ - 3, /* 0 3333 - 853333 us */ - 6, /* 1 1666 - 426666 us */ - 12, /* 2 833 - 213333 us */ - 24, /* 3 416 - 106666 us */ - 48, /* 4 208 - 53333 us */ - 96, /* 5 104 - 26666 us */ - 192, /* 6 52 - 13333 us */ - 384, /* 7 26 - 6666 us */ - 576, - 1152, - 2304, - 4608, - 9216, - 18432, - 62500, - /* 15 = cascade */ -}; -#define NUM_TIMER_STATS 16 -#ifdef FAST_TIMER_LOG -struct fast_timer timer_added_log[NUM_TIMER_STATS]; -struct fast_timer timer_started_log[NUM_TIMER_STATS]; -struct fast_timer timer_expired_log[NUM_TIMER_STATS]; -#endif - -int timer_div_settings[NUM_TIMER_STATS]; -int timer_freq_settings[NUM_TIMER_STATS]; -int timer_delay_settings[NUM_TIMER_STATS]; - -/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */ -inline void do_gettimeofday_fast(struct fasttime_t *tv) -{ - tv->tv_jiff = jiffies; - tv->tv_usec = GET_JIFFIES_USEC(); -} - -inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1) -{ - /* Compare jiffies. Takes care of wrapping */ - if (time_before(t0->tv_jiff, t1->tv_jiff)) - return -1; - else if (time_after(t0->tv_jiff, t1->tv_jiff)) - return 1; - - /* Compare us */ - if (t0->tv_usec < t1->tv_usec) - return -1; - else if (t0->tv_usec > t1->tv_usec) - return 1; - return 0; -} - -inline void start_timer1(unsigned long delay_us) -{ - int freq_index = 0; /* This is the lowest resolution */ - unsigned long upper_limit = MAX_DELAY_US; - - unsigned long div; - /* Start/Restart the timer to the new shorter value */ - /* t = 1/freq = 1/19200 = 53us - * T=div*t, div = T/t = delay_us*freq/1000000 - */ -#if 1 /* Adaptive timer settings */ - while (delay_us < upper_limit && freq_index < MAX_USABLE_TIMER_FREQ) - { - freq_index++; - upper_limit >>= 1; /* Divide by 2 using shift */ - } - if (freq_index > 0) - { - freq_index--; - } -#else - freq_index = 6; -#endif - div = delay_us * timer_freq_100[freq_index]/10000; - if (div < 2) - { - /* Maybe increase timer freq? */ - div = 2; - } - if (div > 255) - { - div = 0; /* This means 256, the max the timer takes */ - /* If a longer timeout than the timer can handle is used, - * then we must restart it when it goes off. - */ - } - - timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = div; - timer_freq_settings[fast_timers_started % NUM_TIMER_STATS] = freq_index; - timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us; - - D1(printk(KERN_DEBUG "start_timer1 : %d us freq: %i div: %i\n", - delay_us, freq_index, div)); - /* Clear timer1 irq */ - *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); - - /* Set timer values */ - *R_TIMER_CTRL = r_timer_ctrl_shadow = - (r_timer_ctrl_shadow & - ~IO_MASK(R_TIMER_CTRL, timerdiv1) & - ~IO_MASK(R_TIMER_CTRL, tm1) & - ~IO_MASK(R_TIMER_CTRL, clksel1)) | - IO_FIELD(R_TIMER_CTRL, timerdiv1, div) | - IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | - IO_FIELD(R_TIMER_CTRL, clksel1, freq_index ); /* 6=c19k2Hz */ - - /* Ack interrupt */ - *R_TIMER_CTRL = r_timer_ctrl_shadow | - IO_STATE(R_TIMER_CTRL, i1, clr); - - /* Start timer */ - *R_TIMER_CTRL = r_timer_ctrl_shadow = - (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) | - IO_STATE(R_TIMER_CTRL, tm1, run); - - /* Enable timer1 irq */ - *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer1, set); - fast_timers_started++; - fast_timer_running = 1; -} - -/* In version 1.4 this function takes 27 - 50 us */ -void start_one_shot_timer(struct fast_timer *t, - fast_timer_function_type *function, - unsigned long data, - unsigned long delay_us, - const char *name) -{ - unsigned long flags; - struct fast_timer *tmp; - - D1(printk("sft %s %d us\n", name, delay_us)); - - local_irq_save(flags); - - do_gettimeofday_fast(&t->tv_set); - tmp = fast_timer_list; - -#ifdef FAST_TIMER_SANITY_CHECKS - /* Check so this is not in the list already... */ - while (tmp != NULL) { - if (tmp == t) { - printk(KERN_WARNING "timer name: %s data: " - "0x%08lX already in list!\n", name, data); - sanity_failed++; - goto done; - } else - tmp = tmp->next; - } - tmp = fast_timer_list; -#endif - - t->delay_us = delay_us; - t->function = function; - t->data = data; - t->name = name; - - t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000; - t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ; - if (t->tv_expires.tv_usec > 1000000) - { - t->tv_expires.tv_usec -= 1000000; - t->tv_expires.tv_jiff += HZ; - } -#ifdef FAST_TIMER_LOG - timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t; -#endif - fast_timers_added++; - - /* Check if this should timeout before anything else */ - if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) - { - /* Put first in list and modify the timer value */ - t->prev = NULL; - t->next = fast_timer_list; - if (fast_timer_list) - { - fast_timer_list->prev = t; - } - fast_timer_list = t; -#ifdef FAST_TIMER_LOG - timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; -#endif - start_timer1(delay_us); - } else { - /* Put in correct place in list */ - while (tmp->next && fasttime_cmp(&t->tv_expires, - &tmp->next->tv_expires) > 0) - { - tmp = tmp->next; - } - /* Insert t after tmp */ - t->prev = tmp; - t->next = tmp->next; - if (tmp->next) - { - tmp->next->prev = t; - } - tmp->next = t; - } - - D2(printk("start_one_shot_timer: %d us done\n", delay_us)); - -done: - local_irq_restore(flags); -} /* start_one_shot_timer */ - -static inline int fast_timer_pending (const struct fast_timer * t) -{ - return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list); -} - -static inline int detach_fast_timer (struct fast_timer *t) -{ - struct fast_timer *next, *prev; - if (!fast_timer_pending(t)) - return 0; - next = t->next; - prev = t->prev; - if (next) - next->prev = prev; - if (prev) - prev->next = next; - else - fast_timer_list = next; - fast_timers_deleted++; - return 1; -} - -int del_fast_timer(struct fast_timer * t) -{ - unsigned long flags; - int ret; - - local_irq_save(flags); - ret = detach_fast_timer(t); - t->next = t->prev = NULL; - local_irq_restore(flags); - return ret; -} /* del_fast_timer */ - - -/* Interrupt routines or functions called in interrupt context */ - -/* Timer 1 interrupt handler */ - -static irqreturn_t -timer1_handler(int irq, void *dev_id) -{ - struct fast_timer *t; - unsigned long flags; - - /* We keep interrupts disabled not only when we modify the - * fast timer list, but any time we hold a reference to a - * timer in the list, since del_fast_timer may be called - * from (another) interrupt context. Thus, the only time - * when interrupts are enabled is when calling the timer - * callback function. - */ - local_irq_save(flags); - - /* Clear timer1 irq */ - *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); - - /* First stop timer, then ack interrupt */ - /* Stop timer */ - *R_TIMER_CTRL = r_timer_ctrl_shadow = - (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) | - IO_STATE(R_TIMER_CTRL, tm1, stop_ld); - - /* Ack interrupt */ - *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i1, clr); - - fast_timer_running = 0; - fast_timer_ints++; - - t = fast_timer_list; - while (t) - { - struct fasttime_t tv; - fast_timer_function_type *f; - unsigned long d; - - /* Has it really expired? */ - do_gettimeofday_fast(&tv); - D1(printk(KERN_DEBUG "t: %is %06ius\n", - tv.tv_jiff, tv.tv_usec)); - - if (fasttime_cmp(&t->tv_expires, &tv) <= 0) - { - /* Yes it has expired */ -#ifdef FAST_TIMER_LOG - timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t; -#endif - fast_timers_expired++; - - /* Remove this timer before call, since it may reuse the timer */ - if (t->prev) - { - t->prev->next = t->next; - } - else - { - fast_timer_list = t->next; - } - if (t->next) - { - t->next->prev = t->prev; - } - t->prev = NULL; - t->next = NULL; - - /* Save function callback data before enabling - * interrupts, since the timer may be removed and - * we don't know how it was allocated - * (e.g. ->function and ->data may become overwritten - * after deletion if the timer was stack-allocated). - */ - f = t->function; - d = t->data; - - if (f != NULL) { - /* Run callback with interrupts enabled. */ - local_irq_restore(flags); - f(d); - local_irq_save(flags); - } else - DEBUG_LOG("!timer1 %i function==NULL!\n", fast_timer_ints); - } - else - { - /* Timer is to early, let's set it again using the normal routines */ - D1(printk(".\n")); - } - - if ((t = fast_timer_list) != NULL) - { - /* Start next timer.. */ - long us = 0; - struct fasttime_t tv; - - do_gettimeofday_fast(&tv); - - /* time_after_eq takes care of wrapping */ - if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff)) - us = ((t->tv_expires.tv_jiff - tv.tv_jiff) * - 1000000 / HZ + t->tv_expires.tv_usec - - tv.tv_usec); - - if (us > 0) - { - if (!fast_timer_running) - { -#ifdef FAST_TIMER_LOG - timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; -#endif - start_timer1(us); - } - break; - } - else - { - /* Timer already expired, let's handle it better late than never. - * The normal loop handles it - */ - D1(printk("e! %d\n", us)); - } - } - } - - local_irq_restore(flags); - - if (!t) - { - D1(printk("t1 stop!\n")); - } - - return IRQ_HANDLED; -} - -static void wake_up_func(unsigned long data) -{ - wait_queue_head_t *sleep_wait_p = (wait_queue_head_t *)data; - wake_up(sleep_wait_p); -} - - -/* Useful API */ - -void schedule_usleep(unsigned long us) -{ - struct fast_timer t; - wait_queue_head_t sleep_wait; - init_waitqueue_head(&sleep_wait); - - D1(printk("schedule_usleep(%d)\n", us)); - start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us, - "usleep"); - /* Uninterruptible sleep on the fast timer. (The condition is somewhat - * redundant since the timer is what wakes us up.) */ - wait_event(sleep_wait, !fast_timer_pending(&t)); - - D1(printk("done schedule_usleep(%d)\n", us)); -} - -#ifdef CONFIG_PROC_FS -/* This value is very much based on testing */ -#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300) - -static int proc_fasttimer_show(struct seq_file *m, void *v) -{ - unsigned long flags; - int i = 0; - int num_to_show; - struct fasttime_t tv; - struct fast_timer *t, *nextt; - - do_gettimeofday_fast(&tv); - - seq_printf(m, "Fast timers added: %i\n", fast_timers_added); - seq_printf(m, "Fast timers started: %i\n", fast_timers_started); - seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints); - seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired); - seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted); - seq_printf(m, "Fast timer running: %s\n", - fast_timer_running ? "yes" : "no"); - seq_printf(m, "Current time: %lu.%06lu\n", - (unsigned long)tv.tv_jiff, - (unsigned long)tv.tv_usec); -#ifdef FAST_TIMER_SANITY_CHECKS - seq_printf(m, "Sanity failed: %i\n", sanity_failed); -#endif - seq_putc(m, '\n'); - -#ifdef DEBUG_LOG_INCLUDED - { - int end_i = debug_log_cnt; - i = 0; - - if (debug_log_cnt_wrapped) - i = debug_log_cnt; - - while (i != end_i || debug_log_cnt_wrapped) { - seq_printf(m, debug_log_string[i], debug_log_value[i]); - if (seq_has_overflowed(m)) - return 0; - i = (i+1) % DEBUG_LOG_MAX; - } - } - seq_putc(m, '\n'); -#endif - - num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started: - NUM_TIMER_STATS); - seq_printf(m, "Timers started: %i\n", fast_timers_started); - for (i = 0; i < num_to_show; i++) { - int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS; - -#if 1 //ndef FAST_TIMER_LOG - seq_printf(m, "div: %i freq: %i delay: %i\n", - timer_div_settings[cur], - timer_freq_settings[cur], - timer_delay_settings[cur]); -#endif -#ifdef FAST_TIMER_LOG - t = &timer_started_log[cur]; - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; -#endif - } - seq_putc(m, '\n'); - -#ifdef FAST_TIMER_LOG - num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added: - NUM_TIMER_STATS); - seq_printf(m, "Timers added: %i\n", fast_timers_added); - for (i = 0; i < num_to_show; i++) { - t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS]; - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; - } - seq_putc(m, '\n'); - - num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired: - NUM_TIMER_STATS); - seq_printf(m, "Timers expired: %i\n", fast_timers_expired); - for (i = 0; i < num_to_show; i++) { - t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS]; - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; - } - seq_putc(m, '\n'); -#endif - - seq_puts(m, "Active timers:\n"); - local_irq_save(flags); - t = fast_timer_list; - while (t) { - nextt = t->next; - local_irq_restore(flags); - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; - local_irq_save(flags); - if (t->next != nextt) - printk(KERN_WARNING "timer removed!\n"); - t = nextt; - } - local_irq_restore(flags); - - return 0; -} - -static int proc_fasttimer_open(struct inode *inode, struct file *file) -{ - return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE); -} - -static const struct file_operations proc_fasttimer_fops = { - .open = proc_fasttimer_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif /* PROC_FS */ - -#ifdef FAST_TIMER_TEST -static volatile unsigned long i = 0; -static volatile int num_test_timeout = 0; -static struct fast_timer tr[10]; -static int exp_num[10]; - -static struct fasttime_t tv_exp[100]; - -static void test_timeout(unsigned long data) -{ - do_gettimeofday_fast(&tv_exp[data]); - exp_num[data] = num_test_timeout; - - num_test_timeout++; -} - -static void test_timeout1(unsigned long data) -{ - do_gettimeofday_fast(&tv_exp[data]); - exp_num[data] = num_test_timeout; - if (data < 7) - { - start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1"); - i++; - } - num_test_timeout++; -} - -DP( -static char buf0[2000]; -static char buf1[2000]; -static char buf2[2000]; -static char buf3[2000]; -static char buf4[2000]; -); - -static char buf5[6000]; -static int j_u[1000]; - -static void fast_timer_test(void) -{ - int prev_num; - int j; - - struct fasttime_t tv, tv0, tv1, tv2; - - printk("fast_timer_test() start\n"); - do_gettimeofday_fast(&tv); - - for (j = 0; j < 1000; j++) - { - j_u[j] = GET_JIFFIES_USEC(); - } - for (j = 0; j < 100; j++) - { - do_gettimeofday_fast(&tv_exp[j]); - } - printk(KERN_DEBUG "fast_timer_test() %is %06i\n", - tv.tv_jiff, tv.tv_usec); - - for (j = 0; j < 1000; j++) - { - printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]); - j += 4; - } - for (j = 0; j < 100; j++) - { - printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n", - tv_exp[j].tv_jiff, tv_exp[j].tv_usec, - tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec, - tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec, - tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec, - tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec); - j += 4; - } - do_gettimeofday_fast(&tv0); - start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0"); - DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1"); - DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2"); - DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3"); - DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx"); - DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); - i++; - do_gettimeofday_fast(&tv1); - - proc_fasttimer_read(buf5, NULL, 0, 0, 0); - - prev_num = num_test_timeout; - while (num_test_timeout < i) - { - if (num_test_timeout != prev_num) - { - prev_num = num_test_timeout; - } - } - do_gettimeofday_fast(&tv2); - printk(KERN_DEBUG "Timers started %is %06i\n", - tv0.tv_jiff, tv0.tv_usec); - printk(KERN_DEBUG "Timers started at %is %06i\n", - tv1.tv_jiff, tv1.tv_usec); - printk(KERN_DEBUG "Timers done %is %06i\n", - tv2.tv_jiff, tv2.tv_usec); - DP(printk("buf0:\n"); - printk(buf0); - printk("buf1:\n"); - printk(buf1); - printk("buf2:\n"); - printk(buf2); - printk("buf3:\n"); - printk(buf3); - printk("buf4:\n"); - printk(buf4); - ); - printk("buf5:\n"); - printk(buf5); - - printk("timers set:\n"); - for(j = 0; jname, - t->tv_set.tv_jiff, - t->tv_set.tv_usec, - t->tv_expires.tv_jiff, - t->tv_expires.tv_usec, - t->data, - t->function - ); - - printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n", - t->delay_us, - tv_exp[j].tv_jiff, - tv_exp[j].tv_usec, - exp_num[j], - (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) * - 1000000 + tv_exp[j].tv_usec - - t->tv_expires.tv_usec); - } - proc_fasttimer_read(buf5, NULL, 0, 0, 0); - printk("buf5 after all done:\n"); - printk(buf5); - printk("fast_timer_test() done\n"); -} -#endif - - -int fast_timer_init(void) -{ - /* For some reason, request_irq() hangs when called froom time_init() */ - if (!fast_timer_is_init) - { -#if 0 && defined(FAST_TIMER_TEST) - int i; -#endif - - printk(KERN_INFO "fast_timer_init()\n"); - -#if 0 && defined(FAST_TIMER_TEST) - for (i = 0; i <= TIMER0_DIV; i++) - { - /* We must be careful not to get overflow... */ - printk("%3i %6u\n", i, timer0_value_us[i]); - } -#endif -#ifdef CONFIG_PROC_FS - proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops); -#endif /* PROC_FS */ - if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0, - "fast timer int", NULL)) - { - printk("err: timer1 irq\n"); - } - fast_timer_is_init = 1; -#ifdef FAST_TIMER_TEST - printk("do test\n"); - fast_timer_test(); -#endif - } - return 0; -} -__initcall(fast_timer_init); diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S deleted file mode 100644 index b260a8833903..000000000000 --- a/arch/cris/arch-v10/kernel/head.S +++ /dev/null @@ -1,620 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Head of the kernel - alter with care - * - * Copyright (C) 2000, 2001, 2010 Axis Communications AB - * - */ - -#include - -#define ASSEMBLER_MACROS_ONLY -/* The IO_* macros use the ## token concatenation operator, so - -traditional must not be used when assembling this file. */ -#include - -#define CRAMFS_MAGIC 0x28cd3d45 -#define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 - -#define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\ - IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk) - - ;; exported symbols - - .globl etrax_irv - .globl romfs_start - .globl romfs_length - .globl romfs_in_flash - .globl swapper_pg_dir - - __HEAD - - ;; This is the entry point of the kernel. We are in supervisor mode. - ;; 0x00000000 if Flash, 0x40004000 if DRAM - ;; since etrax actually starts at address 2 when booting from flash, we - ;; put a nop (2 bytes) here first so we dont accidentally skip the di - ;; - ;; NOTICE! The registers r8 and r9 are used as parameters carrying - ;; information from the decompressor (if the kernel was compressed). - ;; They should not be used in the code below until read. - - nop - di - - ;; First setup the kseg_c mapping from where the kernel is linked - ;; to 0x40000000 (where the actual DRAM resides) otherwise - ;; we cannot do very much! See arch/cris/README.mm - ;; - ;; Notice that since we're potentially running at 0x00 or 0x40 right now, - ;; we will get a fault as soon as we enable the MMU if we dont - ;; temporarily map those segments linearily. - ;; - ;; Due to a bug in Etrax-100 LX version 1 we need to map the memory - ;; slightly different. The bug is that you can't remap bit 31 of - ;; an address. Though we can check the version register for - ;; whether the bug is present, some constants would then have to - ;; be variables, so we don't. The drawback is that you can "only" map - ;; 1G per process with CONFIG_CRIS_LOW_MAP. - -#ifdef CONFIG_CRIS_LOW_MAP - ; kseg mappings, temporary map of 0xc0->0x40 - move.d IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \ - | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb) \ - | IO_FIELD (R_MMU_KBASE_HI, base_9, 9) \ - | IO_FIELD (R_MMU_KBASE_HI, base_8, 8), $r0 - move.d $r0, [R_MMU_KBASE_HI] - - ; temporary map of 0x40->0x40 and 0x60->0x40 - move.d IO_FIELD (R_MMU_KBASE_LO, base_6, 4) \ - | IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0 - move.d $r0, [R_MMU_KBASE_LO] - - ; mmu enable, segs e,c,b,a,6,5,4,0 segment mapped - move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \ - | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \ - | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \ - | IO_STATE (R_MMU_CONFIG, we_excp, enable) \ - | IO_STATE (R_MMU_CONFIG, seg_f, page) \ - | IO_STATE (R_MMU_CONFIG, seg_e, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_d, page) \ - | IO_STATE (R_MMU_CONFIG, seg_c, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_b, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_a, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_9, page) \ - | IO_STATE (R_MMU_CONFIG, seg_8, page) \ - | IO_STATE (R_MMU_CONFIG, seg_7, page) \ - | IO_STATE (R_MMU_CONFIG, seg_6, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_5, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_4, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_3, page) \ - | IO_STATE (R_MMU_CONFIG, seg_2, page) \ - | IO_STATE (R_MMU_CONFIG, seg_1, page) \ - | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0 - move.d $r0, [R_MMU_CONFIG] -#else - ; kseg mappings - move.d IO_FIELD (R_MMU_KBASE_HI, base_e, 8) \ - | IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \ - | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb), $r0 - move.d $r0, [R_MMU_KBASE_HI] - - ; temporary map of 0x40->0x40 and 0x00->0x00 - move.d IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0 - move.d $r0, [R_MMU_KBASE_LO] - - ; mmu enable, segs f,e,c,b,4,0 segment mapped - move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \ - | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \ - | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \ - | IO_STATE (R_MMU_CONFIG, we_excp, enable) \ - | IO_STATE (R_MMU_CONFIG, seg_f, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_e, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_d, page) \ - | IO_STATE (R_MMU_CONFIG, seg_c, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_b, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_a, page) \ - | IO_STATE (R_MMU_CONFIG, seg_9, page) \ - | IO_STATE (R_MMU_CONFIG, seg_8, page) \ - | IO_STATE (R_MMU_CONFIG, seg_7, page) \ - | IO_STATE (R_MMU_CONFIG, seg_6, page) \ - | IO_STATE (R_MMU_CONFIG, seg_5, page) \ - | IO_STATE (R_MMU_CONFIG, seg_4, seg) \ - | IO_STATE (R_MMU_CONFIG, seg_3, page) \ - | IO_STATE (R_MMU_CONFIG, seg_2, page) \ - | IO_STATE (R_MMU_CONFIG, seg_1, page) \ - | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0 - move.d $r0, [R_MMU_CONFIG] -#endif - - ;; Now we need to sort out the segments and their locations in RAM or - ;; Flash. The image in the Flash (or in DRAM) consists of 3 pieces: - ;; 1) kernel text, 2) kernel data, 3) ROM filesystem image - ;; But the linker has linked the kernel to expect this layout in - ;; DRAM memory: - ;; 1) kernel text, 2) kernel data, 3) kernel BSS - ;; (the location of the ROM filesystem is determined by the krom driver) - ;; If we boot this from Flash, we want to keep the ROM filesystem in - ;; the flash, we want to copy the text and need to copy the data to DRAM. - ;; But if we boot from DRAM, we need to move the ROMFS image - ;; from its position after kernel data, to after kernel BSS, BEFORE the - ;; kernel starts using the BSS area (since its "overlayed" with the ROMFS) - ;; - ;; In both cases, we start in un-cached mode, and need to jump into a - ;; cached PC after we're done fiddling around with the segments. - ;; - ;; arch/etrax100/etrax100.ld sets some symbols that define the start - ;; and end of each segment. - - ;; Check if we start from DRAM or FLASH by testing PC - - move.d $pc,$r0 - and.d 0x7fffffff,$r0 ; get rid of the non-cache bit - cmp.d 0x10000,$r0 ; arbitrary... just something above this code - blo _inflash0 - nop - - jump _inram ; enter cached ram - - ;; Jumpgate for branches. -_inflash0: - jump _inflash - - ;; Put this in a suitable section where we can reclaim storage - ;; after init. - __INIT -_inflash: -#ifdef CONFIG_ETRAX_ETHERNET - ;; Start MII clock to make sure it is running when tranceiver is reset - move.d START_ETHERNET_CLOCK, $r0 - move.d $r0, [R_NETWORK_GEN_CONFIG] -#endif - - ;; Set up waitstates etc according to kernel configuration. - move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 - move.d $r0, [R_WAITSTATES] - - move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 - move.d $r0, [R_BUS_CONFIG] - - ;; We need to initialze DRAM registers before we start using the DRAM - - cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? - beq _dram_init_finished - nop - -#include "../lib/dram_init.S" - -_dram_init_finished: - ;; Copy text+data to DRAM - ;; This is fragile - the calculation of r4 as the image size depends - ;; on that the labels below actually are the first and last positions - ;; in the linker-script. - ;; - ;; Then the locating of the cramfs image depends on the aforementioned - ;; image being located in the flash at 0. This is most often not true, - ;; thus the following does not work (normally there is a rescue-block - ;; between the physical start of the flash and the flash-image start, - ;; and when run with compression, the kernel is actually unpacked to - ;; DRAM and we never get here in the first place :)) - - moveq 0, $r0 ; source - move.d text_start, $r1 ; destination - move.d __vmlinux_end, $r2 ; end destination - move.d $r2, $r4 - sub.d $r1, $r4 ; r4=__vmlinux_end in flash, used below -1: move.w [$r0+], $r3 - move.w $r3, [$r1+] - cmp.d $r2, $r1 - blo 1b - nop - - ;; We keep the cramfs in the flash. - ;; There might be none, but that does not matter because - ;; we don't do anything than read some bytes here. - - moveq 0, $r0 - move.d $r0, [romfs_length] ; default if there is no cramfs - - move.d [$r4], $r0 ; cramfs_super.magic - cmp.d CRAMFS_MAGIC, $r0 - bne 1f - nop - move.d [$r4 + 4], $r0 ; cramfs_super.size - move.d $r0, [romfs_length] -#ifdef CONFIG_CRIS_LOW_MAP - add.d 0x50000000, $r4 ; add flash start in virtual memory (cached) -#else - add.d 0xf0000000, $r4 ; add flash start in virtual memory (cached) -#endif - move.d $r4, [romfs_start] -1: - moveq 1, $r0 - move.d $r0, [romfs_in_flash] - - jump _start_it ; enter code, cached this time - -_inram: - ;; Move the ROM fs to after BSS end. This assumes that the cramfs - ;; second longword contains the length of the cramfs - - moveq 0, $r0 - move.d $r0, [romfs_length] ; default if there is no cramfs - - ;; The kernel could have been unpacked to DRAM by the loader, but - ;; the cramfs image could still be in the Flash directly after the - ;; compressed kernel image. The loader passes the address of the - ;; byte succeeding the last compressed byte in the flash in the - ;; register r9 when starting the kernel. Check if r9 points to a - ;; decent cramfs image! - ;; (Notice that if this is not booted from the loader, r9 will be - ;; garbage but we do sanity checks on it, the chance that it points - ;; to a cramfs magic is small.. ) - - cmp.d 0x0ffffff8, $r9 - bhs _no_romfs_in_flash ; r9 points outside the flash area - nop - move.d [$r9], $r0 ; cramfs_super.magic - cmp.d CRAMFS_MAGIC, $r0 - bne _no_romfs_in_flash - nop - move.d [$r9+4], $r0 ; cramfs_super.length - move.d $r0, [romfs_length] -#ifdef CONFIG_CRIS_LOW_MAP - add.d 0x50000000, $r9 ; add flash start in virtual memory (cached) -#else - add.d 0xf0000000, $r9 ; add flash start in virtual memory (cached) -#endif - move.d $r9, [romfs_start] - - moveq 1, $r0 - move.d $r0, [romfs_in_flash] - - jump _start_it ; enter code, cached this time - -_no_romfs_in_flash: - - ;; Check if there is a cramfs (magic value). - ;; Notice that we check for cramfs magic value - which is - ;; the "rom fs" we'll possibly use in 2.4 if not JFFS (which does - ;; not need this mechanism anyway) - - move.d __init_end, $r0; the image will be after the end of init - move.d [$r0], $r1 ; cramfs assumes same endian on host/target - cmp.d CRAMFS_MAGIC, $r1; magic value in cramfs superblock - bne 2f - nop - - ;; Ok. What is its size ? - - move.d [$r0 + 4], $r2 ; cramfs_super.size (again, no need to swapwb) - - ;; We want to copy it to the end of the BSS - - move.d _end, $r1 - - ;; Remember values so cramfs and setup can find this info - - move.d $r1, [romfs_start] ; new romfs location - move.d $r2, [romfs_length] - - ;; We need to copy it backwards, since they can be overlapping - - add.d $r2, $r0 - add.d $r2, $r1 - - ;; Go ahead. Make my loop. - - lsrq 1, $r2 ; size is in bytes, we copy words - -1: move.w [$r0=$r0-2],$r3 - move.w $r3,[$r1=$r1-2] - subq 1, $r2 - bne 1b - nop - -2: - ;; Dont worry that the BSS is tainted. It will be cleared later. - - moveq 0, $r0 - move.d $r0, [romfs_in_flash] - - jump _start_it ; better skip the additional cramfs check below - -_start_it: - - ;; Check if kernel command line is supplied - cmp.d COMMAND_LINE_MAGIC, $r10 - bne no_command_line - nop - - move.d 256, $r13 - move.d cris_command_line, $r10 - or.d 0x80000000, $r11 ; Make it virtual -1: - move.b [$r11+], $r12 - move.b $r12, [$r10+] - subq 1, $r13 - bne 1b - nop - -no_command_line: - - ;; the kernel stack is overlayed with the task structure for each - ;; task. thus the initial kernel stack is in the same page as the - ;; init_task (but starts in the top of the page, size 8192) - move.d init_thread_union + 8192, $sp - move.d ibr_start,$r0 ; this symbol is set by the linker script - move $r0,$ibr - move.d $r0,[etrax_irv] ; set the interrupt base register and pointer - - ;; Clear BSS region, from _bss_start to _end - - move.d __bss_start, $r0 - move.d _end, $r1 -1: clear.d [$r0+] - cmp.d $r1, $r0 - blo 1b - nop - - ;; Etrax product HW genconfig setup - - moveq 0,$r0 - - ;; Select or disable serial port 2 -#ifdef CONFIG_ETRAX_SERIAL_PORT2 - or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0 -#else - or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0 -#endif - - ;; Init interfaces (disable them). - or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \ - | IO_STATE (R_GEN_CONFIG, ata, disable) \ - | IO_STATE (R_GEN_CONFIG, par0, disable) \ - | IO_STATE (R_GEN_CONFIG, mio, disable) \ - | IO_STATE (R_GEN_CONFIG, scsi1, disable) \ - | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \ - | IO_STATE (R_GEN_CONFIG, par1, disable) \ - | IO_STATE (R_GEN_CONFIG, ser3, disable) \ - | IO_STATE (R_GEN_CONFIG, mio_w, disable) \ - | IO_STATE (R_GEN_CONFIG, usb1, disable) \ - | IO_STATE (R_GEN_CONFIG, usb2, disable) \ - | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0 - - ;; Init DMA channel muxing (set to unused clients). - or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \ - | IO_STATE (R_GEN_CONFIG, dma3, ata) \ - | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \ - | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \ - | IO_STATE (R_GEN_CONFIG, dma6, unused) \ - | IO_STATE (R_GEN_CONFIG, dma7, unused) \ - | IO_STATE (R_GEN_CONFIG, dma8, usb) \ - | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0 - - - move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG - - move.d $r0,[R_GEN_CONFIG] - -#if 0 - moveq 4,$r0 - move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out) - move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in) -1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish - and.b 7,$r0 - cmp.b 4,$r0 - beq 1b - nop -1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish - and.b 7,$r0 - cmp.b 4,$r0 - beq 1b - nop -#endif - - moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0 - move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out) - move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in) -1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish - andq IO_MASK (R_DMA_CH8_CMD, cmd),$r0 - cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0 - beq 1b - nop -1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish - andq IO_MASK (R_DMA_CH9_CMD, cmd),$r0 - cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0 - beq 1b - nop - - ;; setup port PA and PB default initial directions and data - ;; including their shadow registers - - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0 - move.b $r0,[port_pa_dir_shadow] - move.b $r0,[R_PORT_PA_DIR] - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0 - move.b $r0,[port_pa_data_shadow] - move.b $r0,[R_PORT_PA_DATA] - - move.b CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG,$r0 - move.b $r0,[port_pb_config_shadow] - move.b $r0,[R_PORT_PB_CONFIG] - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0 - move.b $r0,[port_pb_dir_shadow] - move.b $r0,[R_PORT_PB_DIR] - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0 - move.b $r0,[port_pb_data_shadow] - move.b $r0,[R_PORT_PB_DATA] - - moveq 0, $r0 - move.d $r0,[port_pb_i2c_shadow] - move.d $r0, [R_PORT_PB_I2C] - - moveq 0,$r0 - move.d $r0,[port_g_data_shadow] - move.d $r0,[R_PORT_G_DATA] - - ;; setup the serial port 0 at 115200 baud for debug purposes - - moveq IO_STATE (R_SERIAL0_XOFF, tx_stop, enable) \ - | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable) \ - | IO_FIELD (R_SERIAL0_XOFF, xoff_char, 0),$r0 - move.d $r0,[R_SERIAL0_XOFF] - - ; 115.2kbaud for both transmit and receive - move.b IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz) \ - | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0 - move.b $r0,[R_SERIAL0_BAUD] - - ; Set up and enable the serial0 receiver. - move.b IO_STATE (R_SERIAL0_REC_CTRL, dma_err, stop) \ - | IO_STATE (R_SERIAL0_REC_CTRL, rec_enable, enable) \ - | IO_STATE (R_SERIAL0_REC_CTRL, rts_, active) \ - | IO_STATE (R_SERIAL0_REC_CTRL, sampling, middle) \ - | IO_STATE (R_SERIAL0_REC_CTRL, rec_stick_par, normal) \ - | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even) \ - | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable) \ - | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0 - move.b $r0,[R_SERIAL0_REC_CTRL] - - ; Set up and enable the serial0 transmitter. - move.b IO_FIELD (R_SERIAL0_TR_CTRL, txd, 0) \ - | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable) \ - | IO_STATE (R_SERIAL0_TR_CTRL, auto_cts, disabled) \ - | IO_STATE (R_SERIAL0_TR_CTRL, stop_bits, one_bit) \ - | IO_STATE (R_SERIAL0_TR_CTRL, tr_stick_par, normal) \ - | IO_STATE (R_SERIAL0_TR_CTRL, tr_par, even) \ - | IO_STATE (R_SERIAL0_TR_CTRL, tr_par_en, disable) \ - | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0 - move.b $r0,[R_SERIAL0_TR_CTRL] - - ;; setup the serial port 1 at 115200 baud for debug purposes - - moveq IO_STATE (R_SERIAL1_XOFF, tx_stop, enable) \ - | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable) \ - | IO_FIELD (R_SERIAL1_XOFF, xoff_char, 0),$r0 - move.d $r0,[R_SERIAL1_XOFF] - - ; 115.2kbaud for both transmit and receive - move.b IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz) \ - | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0 - move.b $r0,[R_SERIAL1_BAUD] - - ; Set up and enable the serial1 receiver. - move.b IO_STATE (R_SERIAL1_REC_CTRL, dma_err, stop) \ - | IO_STATE (R_SERIAL1_REC_CTRL, rec_enable, enable) \ - | IO_STATE (R_SERIAL1_REC_CTRL, rts_, active) \ - | IO_STATE (R_SERIAL1_REC_CTRL, sampling, middle) \ - | IO_STATE (R_SERIAL1_REC_CTRL, rec_stick_par, normal) \ - | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even) \ - | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable) \ - | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0 - move.b $r0,[R_SERIAL1_REC_CTRL] - - ; Set up and enable the serial1 transmitter. - move.b IO_FIELD (R_SERIAL1_TR_CTRL, txd, 0) \ - | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable) \ - | IO_STATE (R_SERIAL1_TR_CTRL, auto_cts, disabled) \ - | IO_STATE (R_SERIAL1_TR_CTRL, stop_bits, one_bit) \ - | IO_STATE (R_SERIAL1_TR_CTRL, tr_stick_par, normal) \ - | IO_STATE (R_SERIAL1_TR_CTRL, tr_par, even) \ - | IO_STATE (R_SERIAL1_TR_CTRL, tr_par_en, disable) \ - | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0 - move.b $r0,[R_SERIAL1_TR_CTRL] - -#ifdef CONFIG_ETRAX_SERIAL_PORT2 - ;; setup the serial port 2 at 115200 baud for debug purposes - - moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \ - | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \ - | IO_FIELD (R_SERIAL2_XOFF, xoff_char, 0),$r0 - move.d $r0,[R_SERIAL2_XOFF] - - ; 115.2kbaud for both transmit and receive - move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \ - | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0 - move.b $r0,[R_SERIAL2_BAUD] - - ; Set up and enable the serial2 receiver. - move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \ - | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \ - | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \ - | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \ - | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \ - | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \ - | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \ - | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0 - move.b $r0,[R_SERIAL2_REC_CTRL] - - ; Set up and enable the serial2 transmitter. - move.b IO_FIELD (R_SERIAL2_TR_CTRL, txd, 0) \ - | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \ - | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \ - | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \ - | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \ - | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \ - | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \ - | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0 - move.b $r0,[R_SERIAL2_TR_CTRL] -#endif - -#ifdef CONFIG_ETRAX_SERIAL_PORT3 - ;; setup the serial port 3 at 115200 baud for debug purposes - - moveq IO_STATE (R_SERIAL3_XOFF, tx_stop, enable) \ - | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable) \ - | IO_FIELD (R_SERIAL3_XOFF, xoff_char, 0),$r0 - move.d $r0,[R_SERIAL3_XOFF] - - ; 115.2kbaud for both transmit and receive - move.b IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz) \ - | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0 - move.b $r0,[R_SERIAL3_BAUD] - - ; Set up and enable the serial3 receiver. - move.b IO_STATE (R_SERIAL3_REC_CTRL, dma_err, stop) \ - | IO_STATE (R_SERIAL3_REC_CTRL, rec_enable, enable) \ - | IO_STATE (R_SERIAL3_REC_CTRL, rts_, active) \ - | IO_STATE (R_SERIAL3_REC_CTRL, sampling, middle) \ - | IO_STATE (R_SERIAL3_REC_CTRL, rec_stick_par, normal) \ - | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even) \ - | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable) \ - | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0 - move.b $r0,[R_SERIAL3_REC_CTRL] - - ; Set up and enable the serial3 transmitter. - move.b IO_FIELD (R_SERIAL3_TR_CTRL, txd, 0) \ - | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable) \ - | IO_STATE (R_SERIAL3_TR_CTRL, auto_cts, disabled) \ - | IO_STATE (R_SERIAL3_TR_CTRL, stop_bits, one_bit) \ - | IO_STATE (R_SERIAL3_TR_CTRL, tr_stick_par, normal) \ - | IO_STATE (R_SERIAL3_TR_CTRL, tr_par, even) \ - | IO_STATE (R_SERIAL3_TR_CTRL, tr_par_en, disable) \ - | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0 - move.b $r0,[R_SERIAL3_TR_CTRL] -#endif - - jump start_kernel ; jump into the C-function start_kernel in init/main.c - - .data -etrax_irv: - .dword 0 -romfs_start: - .dword 0 -romfs_length: - .dword 0 -romfs_in_flash: - .dword 0 - - ;; put some special pages at the beginning of the kernel aligned - ;; to page boundaries - the kernel cannot start until after this - -#ifdef CONFIG_CRIS_LOW_MAP -swapper_pg_dir = 0x60002000 -#else -swapper_pg_dir = 0xc0002000 -#endif - - .section ".init.data", "aw" -#include "../lib/hw_settings.S" diff --git a/arch/cris/arch-v10/kernel/io_interface_mux.c b/arch/cris/arch-v10/kernel/io_interface_mux.c deleted file mode 100644 index 13a887ce115a..000000000000 --- a/arch/cris/arch-v10/kernel/io_interface_mux.c +++ /dev/null @@ -1,1183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* IO interface mux allocator for ETRAX100LX. - * Copyright 2004-2007, Axis Communications AB - */ - - -/* C.f. ETRAX100LX Designer's Reference chapter 19.9 */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - - -#define DBG(s) - -/* Macro to access ETRAX 100 registers */ -#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \ - IO_STATE_(reg##_, field##_, _##val) - -enum io_if_group { - group_a = (1<<0), - group_b = (1<<1), - group_c = (1<<2), - group_d = (1<<3), - group_e = (1<<4), - group_f = (1<<5) -}; - -struct watcher -{ - void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available); - struct watcher *next; -}; - - -struct if_group -{ - enum io_if_group group; - /* name - the name of the group 'A' to 'F' */ - char *name; - /* used - a bit mask of all pins in the group in the order listed - * in the tables in 19.9.1 to 19.9.6. Note that no - * distinction is made between in, out and in/out pins. */ - unsigned int used; -}; - - -struct interface -{ - enum cris_io_interface ioif; - /* name - the name of the interface */ - char *name; - /* groups - OR'ed together io_if_group flags describing what pin groups - * the interface uses pins in. */ - unsigned char groups; - /* used - set when the interface is allocated. */ - unsigned char used; - char *owner; - /* group_a through group_f - bit masks describing what pins in the - * pin groups the interface uses. */ - unsigned int group_a; - unsigned int group_b; - unsigned int group_c; - unsigned int group_d; - unsigned int group_e; - unsigned int group_f; - - /* gpio_g_in, gpio_g_out, gpio_b - bit masks telling what pins in the - * GPIO ports the interface uses. This could be reconstucted using - * the group_X masks and a table of what pins the GPIO ports use, - * but that would be messy. */ - unsigned int gpio_g_in; - unsigned int gpio_g_out; - unsigned char gpio_b; -}; - -static struct if_group if_groups[6] = { - { - .group = group_a, - .name = "A", - .used = 0, - }, - { - .group = group_b, - .name = "B", - .used = 0, - }, - { - .group = group_c, - .name = "C", - .used = 0, - }, - { - .group = group_d, - .name = "D", - .used = 0, - }, - { - .group = group_e, - .name = "E", - .used = 0, - }, - { - .group = group_f, - .name = "F", - .used = 0, - } -}; - -/* The order in the array must match the order of enum - * cris_io_interface in io_interface_mux.h */ -static struct interface interfaces[] = { - /* Begin Non-multiplexed interfaces */ - { - .ioif = if_eth, - .name = "ethernet", - .groups = 0, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0, - .gpio_g_out = 0, - .gpio_b = 0 - }, - { - .ioif = if_serial_0, - .name = "serial_0", - .groups = 0, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0, - .gpio_g_out = 0, - .gpio_b = 0 - }, - /* End Non-multiplexed interfaces */ - { - .ioif = if_serial_1, - .name = "serial_1", - .groups = group_e, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0x0f, - .group_f = 0, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x00 - }, - { - .ioif = if_serial_2, - .name = "serial_2", - .groups = group_b, - - .group_a = 0, - .group_b = 0x0f, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x000000c0, - .gpio_g_out = 0x000000c0, - .gpio_b = 0x00 - }, - { - .ioif = if_serial_3, - .name = "serial_3", - .groups = group_c, - - .group_a = 0, - .group_b = 0, - .group_c = 0x0f, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0xc0000000, - .gpio_g_out = 0xc0000000, - .gpio_b = 0x00 - }, - { - .ioif = if_sync_serial_1, - .name = "sync_serial_1", - .groups = group_e | group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0x0f, - .group_f = 0x10, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x10 - }, - { - .ioif = if_sync_serial_3, - .name = "sync_serial_3", - .groups = group_c | group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0x0f, - .group_d = 0, - .group_e = 0, - .group_f = 0x80, - - .gpio_g_in = 0xc0000000, - .gpio_g_out = 0xc0000000, - .gpio_b = 0x80 - }, - { - .ioif = if_shared_ram, - .name = "shared_ram", - .groups = group_a, - - .group_a = 0x7f8ff, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x0000ff3e, - .gpio_g_out = 0x0000ff38, - .gpio_b = 0x00 - }, - { - .ioif = if_shared_ram_w, - .name = "shared_ram_w", - .groups = group_a | group_d, - - .group_a = 0x7f8ff, - .group_b = 0, - .group_c = 0, - .group_d = 0xff, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x00ffff3e, - .gpio_g_out = 0x00ffff38, - .gpio_b = 0x00 - }, - { - .ioif = if_par_0, - .name = "par_0", - .groups = group_a, - - .group_a = 0x7fbff, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x0000ff3e, - .gpio_g_out = 0x0000ff3e, - .gpio_b = 0x00 - }, - { - .ioif = if_par_1, - .name = "par_1", - .groups = group_d, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0x7feff, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x3eff0000, - .gpio_g_out = 0x3eff0000, - .gpio_b = 0x00 - }, - { - .ioif = if_par_w, - .name = "par_w", - .groups = group_a | group_d, - - .group_a = 0x7fbff, - .group_b = 0, - .group_c = 0, - .group_d = 0xff, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x00ffff3e, - .gpio_g_out = 0x00ffff3e, - .gpio_b = 0x00 - }, - { - .ioif = if_scsi8_0, - .name = "scsi8_0", - .groups = group_a | group_b | group_f, - - .group_a = 0x7ffff, - .group_b = 0x0f, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0x10, - - .gpio_g_in = 0x0000ffff, - .gpio_g_out = 0x0000ffff, - .gpio_b = 0x10 - }, - { - .ioif = if_scsi8_1, - .name = "scsi8_1", - .groups = group_c | group_d | group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0x0f, - .group_d = 0x7ffff, - .group_e = 0, - .group_f = 0x80, - - .gpio_g_in = 0xffff0000, - .gpio_g_out = 0xffff0000, - .gpio_b = 0x80 - }, - { - .ioif = if_scsi_w, - .name = "scsi_w", - .groups = group_a | group_b | group_d | group_f, - - .group_a = 0x7ffff, - .group_b = 0x0f, - .group_c = 0, - .group_d = 0x601ff, - .group_e = 0, - .group_f = 0x90, - - .gpio_g_in = 0x01ffffff, - .gpio_g_out = 0x07ffffff, - .gpio_b = 0x80 - }, - { - .ioif = if_ata, - .name = "ata", - .groups = group_a | group_b | group_c | group_d, - - .group_a = 0x7ffff, - .group_b = 0x0f, - .group_c = 0x0f, - .group_d = 0x7cfff, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0xf9ffffff, - .gpio_g_out = 0xffffffff, - .gpio_b = 0x80 - }, - { - .ioif = if_csp, - .name = "csp", - .groups = group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0xfc, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0xfc - }, - { - .ioif = if_i2c, - .name = "i2c", - .groups = group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0x03, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x03 - }, - { - .ioif = if_usb_1, - .name = "usb_1", - .groups = group_e | group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0x0f, - .group_f = 0x2c, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x2c - }, - { - .ioif = if_usb_2, - .name = "usb_2", - .groups = group_d, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0x33e00, - .group_f = 0, - - .gpio_g_in = 0x3e000000, - .gpio_g_out = 0x0c000000, - .gpio_b = 0x00 - }, - /* GPIO pins */ - { - .ioif = if_gpio_grp_a, - .name = "gpio_a", - .groups = group_a, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x0000ff3f, - .gpio_g_out = 0x0000ff3f, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_b, - .name = "gpio_b", - .groups = group_b, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x000000c0, - .gpio_g_out = 0x000000c0, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_c, - .name = "gpio_c", - .groups = group_c, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0xc0000000, - .gpio_g_out = 0xc0000000, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_d, - .name = "gpio_d", - .groups = group_d, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x3fff0000, - .gpio_g_out = 0x3fff0000, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_e, - .name = "gpio_e", - .groups = group_e, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0x00 - }, - { - .ioif = if_gpio_grp_f, - .name = "gpio_f", - .groups = group_f, - - .group_a = 0, - .group_b = 0, - .group_c = 0, - .group_d = 0, - .group_e = 0, - .group_f = 0, - - .gpio_g_in = 0x00000000, - .gpio_g_out = 0x00000000, - .gpio_b = 0xff - } - /* Array end */ -}; - -static struct watcher *watchers = NULL; - -/* The pins that are free to use in the GPIO ports. */ -static unsigned int gpio_in_pins = 0xffffffff; -static unsigned int gpio_out_pins = 0xffffffff; -static unsigned char gpio_pb_pins = 0xff; -static unsigned char gpio_pa_pins = 0xff; - -/* Identifiers for the owners of the GPIO pins. */ -static enum cris_io_interface gpio_pa_owners[8]; -static enum cris_io_interface gpio_pb_owners[8]; -static enum cris_io_interface gpio_pg_owners[32]; - -static int cris_io_interface_init(void); - -static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group) -{ - return (groups & ~group->group); -} - - -static struct if_group *get_group(const unsigned char groups) -{ - int i; - for (i = 0; i < ARRAY_SIZE(if_groups); i++) { - if (groups & if_groups[i].group) { - return &if_groups[i]; - } - } - return NULL; -} - - -static void notify_watchers(void) -{ - struct watcher *w = watchers; - - DBG(printk("io_interface_mux: notifying watchers\n")); - - while (NULL != w) { - w->notify((const unsigned int)gpio_in_pins, - (const unsigned int)gpio_out_pins, - (const unsigned char)gpio_pa_pins, - (const unsigned char)gpio_pb_pins); - w = w->next; - } -} - - -int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id) -{ - int set_gen_config = 0; - int set_gen_config_ii = 0; - unsigned long int gens; - unsigned long int gens_ii; - struct if_group *grp; - unsigned char group_set; - unsigned long flags; - int res = 0; - - (void)cris_io_interface_init(); - - DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id)); - - if ((ioif >= if_max_interfaces) || (ioif < 0)) { - printk(KERN_CRIT "cris_request_io_interface: Bad interface " - "%u submitted for %s\n", - ioif, - device_id); - return -EINVAL; - } - - local_irq_save(flags); - - if (interfaces[ioif].used) { - printk(KERN_CRIT "cris_io_interface: Cannot allocate interface " - "%s for %s, in use by %s\n", - interfaces[ioif].name, - device_id, - interfaces[ioif].owner); - res = -EBUSY; - goto exit; - } - - /* Check that all required pins in the used groups are free - * before allocating. */ - group_set = interfaces[ioif].groups; - while (NULL != (grp = get_group(group_set))) { - unsigned int if_group_use = 0; - - switch (grp->group) { - case group_a: - if_group_use = interfaces[ioif].group_a; - break; - case group_b: - if_group_use = interfaces[ioif].group_b; - break; - case group_c: - if_group_use = interfaces[ioif].group_c; - break; - case group_d: - if_group_use = interfaces[ioif].group_d; - break; - case group_e: - if_group_use = interfaces[ioif].group_e; - break; - case group_f: - if_group_use = interfaces[ioif].group_f; - break; - default: - BUG_ON(1); - } - - if (if_group_use & grp->used) { - printk(KERN_INFO "cris_request_io_interface: group " - "%s needed by %s not available\n", - grp->name, interfaces[ioif].name); - res = -EBUSY; - goto exit; - } - - group_set = clear_group_from_set(group_set, grp); - } - - /* Are the required GPIO pins available too? */ - if (((interfaces[ioif].gpio_g_in & gpio_in_pins) != - interfaces[ioif].gpio_g_in) || - ((interfaces[ioif].gpio_g_out & gpio_out_pins) != - interfaces[ioif].gpio_g_out) || - ((interfaces[ioif].gpio_b & gpio_pb_pins) != - interfaces[ioif].gpio_b)) { - printk(KERN_CRIT "cris_request_io_interface: Could not get " - "required pins for interface %u\n", ioif); - res = -EBUSY; - goto exit; - } - - /* Check which registers need to be reconfigured. */ - gens = genconfig_shadow; - gens_ii = gen_config_ii_shadow; - - set_gen_config = 1; - switch (ioif) - { - /* Begin Non-multiplexed interfaces */ - case if_eth: - /* fall through */ - case if_serial_0: - set_gen_config = 0; - break; - /* End Non-multiplexed interfaces */ - case if_serial_1: - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async); - break; - case if_serial_2: - SETS(gens, R_GEN_CONFIG, ser2, select); - break; - case if_serial_3: - SETS(gens, R_GEN_CONFIG, ser3, select); - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async); - break; - case if_sync_serial_1: - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync); - break; - case if_sync_serial_3: - SETS(gens, R_GEN_CONFIG, ser3, select); - set_gen_config_ii = 1; - SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync); - break; - case if_shared_ram: - SETS(gens, R_GEN_CONFIG, mio, select); - break; - case if_shared_ram_w: - SETS(gens, R_GEN_CONFIG, mio_w, select); - break; - case if_par_0: - SETS(gens, R_GEN_CONFIG, par0, select); - break; - case if_par_1: - SETS(gens, R_GEN_CONFIG, par1, select); - break; - case if_par_w: - SETS(gens, R_GEN_CONFIG, par0, select); - SETS(gens, R_GEN_CONFIG, par_w, select); - break; - case if_scsi8_0: - SETS(gens, R_GEN_CONFIG, scsi0, select); - break; - case if_scsi8_1: - SETS(gens, R_GEN_CONFIG, scsi1, select); - break; - case if_scsi_w: - SETS(gens, R_GEN_CONFIG, scsi0, select); - SETS(gens, R_GEN_CONFIG, scsi0w, select); - break; - case if_ata: - SETS(gens, R_GEN_CONFIG, ata, select); - break; - case if_csp: - /* fall through */ - case if_i2c: - set_gen_config = 0; - break; - case if_usb_1: - SETS(gens, R_GEN_CONFIG, usb1, select); - break; - case if_usb_2: - SETS(gens, R_GEN_CONFIG, usb2, select); - break; - case if_gpio_grp_a: - /* GPIO groups are only accounted, don't do configuration changes. */ - /* fall through */ - case if_gpio_grp_b: - /* fall through */ - case if_gpio_grp_c: - /* fall through */ - case if_gpio_grp_d: - /* fall through */ - case if_gpio_grp_e: - /* fall through */ - case if_gpio_grp_f: - set_gen_config = 0; - break; - default: - printk(KERN_INFO "cris_request_io_interface: Bad interface " - "%u submitted for %s\n", - ioif, device_id); - res = -EBUSY; - goto exit; - } - - /* All needed I/O pins and pin groups are free, allocate. */ - group_set = interfaces[ioif].groups; - while (NULL != (grp = get_group(group_set))) { - unsigned int if_group_use = 0; - - switch (grp->group) { - case group_a: - if_group_use = interfaces[ioif].group_a; - break; - case group_b: - if_group_use = interfaces[ioif].group_b; - break; - case group_c: - if_group_use = interfaces[ioif].group_c; - break; - case group_d: - if_group_use = interfaces[ioif].group_d; - break; - case group_e: - if_group_use = interfaces[ioif].group_e; - break; - case group_f: - if_group_use = interfaces[ioif].group_f; - break; - default: - BUG_ON(1); - } - grp->used |= if_group_use; - - group_set = clear_group_from_set(group_set, grp); - } - - interfaces[ioif].used = 1; - interfaces[ioif].owner = (char*)device_id; - - if (set_gen_config) { - volatile int i; - genconfig_shadow = gens; - *R_GEN_CONFIG = genconfig_shadow; - /* Wait 12 cycles before doing any DMA command */ - for(i = 6; i > 0; i--) - nop(); - } - if (set_gen_config_ii) { - gen_config_ii_shadow = gens_ii; - *R_GEN_CONFIG_II = gen_config_ii_shadow; - } - - DBG(printk(KERN_DEBUG "GPIO pins: available before: " - "g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - DBG(printk(KERN_DEBUG - "grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - interfaces[ioif].gpio_g_in, - interfaces[ioif].gpio_g_out, - interfaces[ioif].gpio_b)); - - gpio_in_pins &= ~interfaces[ioif].gpio_g_in; - gpio_out_pins &= ~interfaces[ioif].gpio_g_out; - gpio_pb_pins &= ~interfaces[ioif].gpio_b; - - DBG(printk(KERN_DEBUG "GPIO pins: available after: " - "g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - -exit: - local_irq_restore(flags); - if (res == 0) - notify_watchers(); - return res; -} - - -void cris_free_io_interface(enum cris_io_interface ioif) -{ - struct if_group *grp; - unsigned char group_set; - unsigned long flags; - - (void)cris_io_interface_init(); - - if ((ioif >= if_max_interfaces) || (ioif < 0)) { - printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n", - ioif); - return; - } - local_irq_save(flags); - if (!interfaces[ioif].used) { - printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n", - ioif); - local_irq_restore(flags); - return; - } - group_set = interfaces[ioif].groups; - while (NULL != (grp = get_group(group_set))) { - unsigned int if_group_use = 0; - - switch (grp->group) { - case group_a: - if_group_use = interfaces[ioif].group_a; - break; - case group_b: - if_group_use = interfaces[ioif].group_b; - break; - case group_c: - if_group_use = interfaces[ioif].group_c; - break; - case group_d: - if_group_use = interfaces[ioif].group_d; - break; - case group_e: - if_group_use = interfaces[ioif].group_e; - break; - case group_f: - if_group_use = interfaces[ioif].group_f; - break; - default: - BUG_ON(1); - } - - if ((grp->used & if_group_use) != if_group_use) - BUG_ON(1); - grp->used = grp->used & ~if_group_use; - - group_set = clear_group_from_set(group_set, grp); - } - interfaces[ioif].used = 0; - interfaces[ioif].owner = NULL; - - DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - interfaces[ioif].gpio_g_in, - interfaces[ioif].gpio_g_out, - interfaces[ioif].gpio_b)); - - gpio_in_pins |= interfaces[ioif].gpio_g_in; - gpio_out_pins |= interfaces[ioif].gpio_g_out; - gpio_pb_pins |= interfaces[ioif].gpio_b; - - DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n", - gpio_in_pins, gpio_out_pins, gpio_pb_pins)); - - local_irq_restore(flags); - - notify_watchers(); -} - -/* Create a bitmask from bit 0 (inclusive) to bit stop_bit - (non-inclusive). stop_bit == 0 returns 0x0 */ -static inline unsigned int create_mask(const unsigned stop_bit) -{ - /* Avoid overflow */ - if (stop_bit >= 32) { - return 0xffffffff; - } - return (1<notify = notify; - w->next = watchers; - watchers = w; - - w->notify((const unsigned int)gpio_in_pins, - (const unsigned int)gpio_out_pins, - (const unsigned char)gpio_pa_pins, - (const unsigned char)gpio_pb_pins); - - return 0; -} - -void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)) -{ - struct watcher *w = watchers, *prev = NULL; - - (void)cris_io_interface_init(); - - while ((NULL != w) && (w->notify != notify)){ - prev = w; - w = w->next; - } - if (NULL != w) { - if (NULL != prev) { - prev->next = w->next; - } else { - watchers = w->next; - } - kfree(w); - return; - } - printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify); -} - - -static int cris_io_interface_init(void) -{ - static int first = 1; - int i; - - if (!first) { - return 0; - } - first = 0; - - for (i = 0; i<8; i++) { - gpio_pa_owners[i] = if_unclaimed; - gpio_pb_owners[i] = if_unclaimed; - gpio_pg_owners[i] = if_unclaimed; - } - for (; i<32; i++) { - gpio_pg_owners[i] = if_unclaimed; - } - return 0; -} - - -module_init(cris_io_interface_init); - - -EXPORT_SYMBOL(cris_request_io_interface); -EXPORT_SYMBOL(cris_free_io_interface); -EXPORT_SYMBOL(cris_io_interface_allocate_pins); -EXPORT_SYMBOL(cris_io_interface_free_pins); -EXPORT_SYMBOL(cris_io_interface_register_watcher); -EXPORT_SYMBOL(cris_io_interface_delete_watcher); diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c deleted file mode 100644 index df11e383acdd..000000000000 --- a/arch/cris/arch-v10/kernel/irq.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/irq.c - * - * Copyright (c) 2000-2002 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - * This file contains the interrupt vectors and some - * helper functions - * - */ - -#include -#include -#include -#include -#include -#include - -#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr)); -#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr)); - -extern void kgdb_init(void); -extern void breakpoint(void); - -/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is - * global just so that the kernel gdb can use it. - */ - -void -set_int_vector(int n, irqvectptr addr) -{ - etrax_irv->v[n + 0x20] = (irqvectptr)addr; -} - -/* the breakpoint vector is obviously not made just like the normal irq handlers - * but needs to contain _code_ to jump to addr. - * - * the BREAK n instruction jumps to IBR + n * 8 - */ - -void -set_break_vector(int n, irqvectptr addr) -{ - unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2]; - unsigned long *jaddr = (unsigned long *)(jinstr + 1); - - /* if you don't know what this does, do not touch it! */ - - *jinstr = 0x0d3f; - *jaddr = (unsigned long)addr; - - /* 00000026 3f0d82000000 jump 0x82 */ -} - -/* - * This builds up the IRQ handler stubs using some ugly macros in irq.h - * - * These macros create the low-level assembly IRQ routines that do all - * the operations that are needed. They are also written to be fast - and to - * disable interrupts as little as humanly possible. - * - */ - -/* IRQ0 and 1 are special traps */ -void hwbreakpoint(void); -void IRQ1_interrupt(void); -BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */ -BUILD_IRQ(3, 0x08) -BUILD_IRQ(4, 0x10) -BUILD_IRQ(5, 0x20) -BUILD_IRQ(6, 0x40) -BUILD_IRQ(7, 0x80) -BUILD_IRQ(8, 0x100) -BUILD_IRQ(9, 0x200) -BUILD_IRQ(10, 0x400) -BUILD_IRQ(11, 0x800) -BUILD_IRQ(12, 0x1000) -BUILD_IRQ(13, 0x2000) -void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */ -void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */ -BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */ -BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */ -BUILD_IRQ(18, 0x40000) -BUILD_IRQ(19, 0x80000) -BUILD_IRQ(20, 0x100000) -BUILD_IRQ(21, 0x200000) -BUILD_IRQ(22, 0x400000) -BUILD_IRQ(23, 0x800000) -BUILD_IRQ(24, 0x1000000) -BUILD_IRQ(25, 0x2000000) -/* IRQ 26-30 are reserved */ -BUILD_IRQ(31, 0x80000000) - -/* - * Pointers to the low-level handlers - */ - -static void (*interrupt[NR_IRQS])(void) = { - NULL, NULL, IRQ2_interrupt, IRQ3_interrupt, - IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt, - IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt, - IRQ12_interrupt, IRQ13_interrupt, NULL, NULL, - IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt, - IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt, - IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL, - IRQ31_interrupt -}; - -static void enable_crisv10_irq(struct irq_data *data) -{ - crisv10_unmask_irq(data->irq); -} - -static void disable_crisv10_irq(struct irq_data *data) -{ - crisv10_mask_irq(data->irq); -} - -static struct irq_chip crisv10_irq_type = { - .name = "CRISv10", - .irq_shutdown = disable_crisv10_irq, - .irq_enable = enable_crisv10_irq, - .irq_disable = disable_crisv10_irq, -}; - -void weird_irq(void); -void system_call(void); /* from entry.S */ -void do_sigtrap(void); /* from entry.S */ -void gdb_handle_breakpoint(void); /* from entry.S */ - -extern void do_IRQ(int irq, struct pt_regs * regs); - -/* Handle multiple IRQs */ -void do_multiple_IRQ(struct pt_regs* regs) -{ - int bit; - unsigned masked; - unsigned mask; - unsigned ethmask = 0; - - /* Get interrupts to mask and handle */ - mask = masked = *R_VECT_MASK_RD; - - /* Never mask timer IRQ */ - mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0)); - - /* - * If either ethernet interrupt (rx or tx) is active then block - * the other one too. Unblock afterwards also. - */ - if (mask & - (IO_STATE(R_VECT_MASK_RD, dma0, active) | - IO_STATE(R_VECT_MASK_RD, dma1, active))) { - ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) | - IO_MASK(R_VECT_MASK_RD, dma1)); - } - - /* Block them */ - *R_VECT_MASK_CLR = (mask | ethmask); - - /* An extra irq_enter here to prevent softIRQs to run after - * each do_IRQ. This will decrease the interrupt latency. - */ - irq_enter(); - - /* Handle all IRQs */ - for (bit = 2; bit < 32; bit++) { - if (masked & (1 << bit)) { - do_IRQ(bit, regs); - } - } - - /* This irq_exit() will trigger the soft IRQs. */ - irq_exit(); - - /* Unblock the IRQs again */ - *R_VECT_MASK_SET = (masked | ethmask); -} - -/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and - setting the irq vector table. -*/ - -void __init init_IRQ(void) -{ - int i; - - /* clear all interrupt masks */ - *R_IRQ_MASK0_CLR = 0xffffffff; - *R_IRQ_MASK1_CLR = 0xffffffff; - *R_IRQ_MASK2_CLR = 0xffffffff; - *R_VECT_MASK_CLR = 0xffffffff; - - for (i = 0; i < 256; i++) - etrax_irv->v[i] = weird_irq; - - /* Initialize IRQ handler descriptors. */ - for(i = 2; i < NR_IRQS; i++) { - irq_set_chip_and_handler(i, &crisv10_irq_type, - handle_simple_irq); - set_int_vector(i, interrupt[i]); - } - - /* the entries in the break vector contain actual code to be - executed by the associated break handler, rather than just a jump - address. therefore we need to setup a default breakpoint handler - for all breakpoints */ - for (i = 0; i < 16; i++) - set_break_vector(i, do_sigtrap); - - /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */ - set_int_vector(15, multiple_interrupt); - - /* 0 and 1 which are special breakpoint/NMI traps */ - set_int_vector(0, hwbreakpoint); - set_int_vector(1, IRQ1_interrupt); - - /* and irq 14 which is the mmu bus fault handler */ - set_int_vector(14, mmu_bus_fault); - - /* setup the system-call trap, which is reached by BREAK 13 */ - set_break_vector(13, system_call); - - /* setup a breakpoint handler for debugging used for both user and - kernel mode debugging (which is why it is not inside an ifdef - CONFIG_ETRAX_KGDB) */ - set_break_vector(8, gdb_handle_breakpoint); - -#ifdef CONFIG_ETRAX_KGDB - /* setup kgdb if its enabled, and break into the debugger */ - kgdb_init(); - breakpoint(); -#endif -} diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c deleted file mode 100644 index 79b13564d15c..000000000000 --- a/arch/cris/arch-v10/kernel/kgdb.c +++ /dev/null @@ -1,1128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/*!************************************************************************** -*! -*! FILE NAME : kgdb.c -*! -*! DESCRIPTION: Implementation of the gdb stub with respect to ETRAX 100. -*! It is a mix of arch/m68k/kernel/kgdb.c and cris_stub.c. -*! -*!--------------------------------------------------------------------------- -*! HISTORY -*! -*! DATE NAME CHANGES -*! ---- ---- ------- -*! Apr 26 1999 Hendrik Ruijter Initial version. -*! May 6 1999 Hendrik Ruijter Removed call to strlen in libc and removed -*! struct assignment as it generates calls to -*! memcpy in libc. -*! Jun 17 1999 Hendrik Ruijter Added gdb 4.18 support. 'X', 'qC' and 'qL'. -*! Jul 21 1999 Bjorn Wesen eLinux port -*! -*!--------------------------------------------------------------------------- -*! -*! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN -*! -*!**************************************************************************/ -/* @(#) cris_stub.c 1.3 06/17/99 */ - -/* - * kgdb usage notes: - * ----------------- - * - * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be - * built with different gcc flags: "-g" is added to get debug infos, and - * "-fomit-frame-pointer" is omitted to make debugging easier. Since the - * resulting kernel will be quite big (approx. > 7 MB), it will be stripped - * before compresion. Such a kernel will behave just as usually, except if - * given a "debug=" command line option. (Only serial devices are - * allowed for , i.e. no printers or the like; possible values are - * machine depedend and are the same as for the usual debug device, the one - * for logging kernel messages.) If that option is given and the device can be - * initialized, the kernel will connect to the remote gdb in trap_init(). The - * serial parameters are fixed to 8N1 and 115200 bps, for easyness of - * implementation. - * - * To start a debugging session, start that gdb with the debugging kernel - * image (the one with the symbols, vmlinux.debug) named on the command line. - * This file will be used by gdb to get symbol and debugging infos about the - * kernel. Next, select remote debug mode by - * target remote - * where is the name of the serial device over which the debugged - * machine is connected. Maybe you have to adjust the baud rate by - * set remotebaud - * or also other parameters with stty: - * shell stty ... #. - * - * where - * :: - * :: < two hex digits computed as modulo 256 sum of > - * - * When a packet is received, it is first acknowledged with either '+' or '-'. - * '+' indicates a successful transfer. '-' indicates a failed transfer. - * - * Example: - * - * Host: Reply: - * $m0,10#2a +$00010203040506070809101112131415#42 - * - */ - - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -static int kgdb_started = 0; - -/********************************* Register image ****************************/ -/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's - Reference", p. 1-1, with the additional register definitions of the - ETRAX 100LX in cris-opc.h. - There are 16 general 32-bit registers, R0-R15, where R14 is the stack - pointer, SP, and R15 is the program counter, PC. - There are 16 special registers, P0-P15, where three of the unimplemented - registers, P0, P4 and P8, are reserved as zero-registers. A read from - any of these registers returns zero and a write has no effect. */ - -typedef -struct register_image -{ - /* Offset */ - unsigned int r0; /* 0x00 */ - unsigned int r1; /* 0x04 */ - unsigned int r2; /* 0x08 */ - unsigned int r3; /* 0x0C */ - unsigned int r4; /* 0x10 */ - unsigned int r5; /* 0x14 */ - unsigned int r6; /* 0x18 */ - unsigned int r7; /* 0x1C */ - unsigned int r8; /* 0x20 Frame pointer */ - unsigned int r9; /* 0x24 */ - unsigned int r10; /* 0x28 */ - unsigned int r11; /* 0x2C */ - unsigned int r12; /* 0x30 */ - unsigned int r13; /* 0x34 */ - unsigned int sp; /* 0x38 Stack pointer */ - unsigned int pc; /* 0x3C Program counter */ - - unsigned char p0; /* 0x40 8-bit zero-register */ - unsigned char vr; /* 0x41 Version register */ - - unsigned short p4; /* 0x42 16-bit zero-register */ - unsigned short ccr; /* 0x44 Condition code register */ - - unsigned int mof; /* 0x46 Multiply overflow register */ - - unsigned int p8; /* 0x4A 32-bit zero-register */ - unsigned int ibr; /* 0x4E Interrupt base register */ - unsigned int irp; /* 0x52 Interrupt return pointer */ - unsigned int srp; /* 0x56 Subroutine return pointer */ - unsigned int bar; /* 0x5A Breakpoint address register */ - unsigned int dccr; /* 0x5E Double condition code register */ - unsigned int brp; /* 0x62 Breakpoint return pointer (pc in caller) */ - unsigned int usp; /* 0x66 User mode stack pointer */ -} registers; - -/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */ -int getDebugChar (void); - -/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */ -void putDebugChar (int val); - -void enableDebugIRQ (void); - -/******************** Prototypes for global functions. ***********************/ - -/* The string str is prepended with the GDB printout token and sent. */ -void putDebugString (const unsigned char *str, int length); /* used by etrax100ser.c */ - -/* The hook for both static (compiled) and dynamic breakpoints set by GDB. - ETRAX 100 specific. */ -void handle_breakpoint (void); /* used by irq.c */ - -/* The hook for an interrupt generated by GDB. ETRAX 100 specific. */ -void handle_interrupt (void); /* used by irq.c */ - -/* A static breakpoint to be used at startup. */ -void breakpoint (void); /* called by init/main.c */ - -/* From osys_int.c, executing_task contains the number of the current - executing task in osys. Does not know of object-oriented threads. */ -extern unsigned char executing_task; - -/* The number of characters used for a 64 bit thread identifier. */ -#define HEXCHARS_IN_THREAD_ID 16 - -/********************************** Packet I/O ******************************/ -/* BUFMAX defines the maximum number of characters in - inbound/outbound buffers */ -#define BUFMAX 512 - -/* Run-length encoding maximum length. Send 64 at most. */ -#define RUNLENMAX 64 - -/* The inbound/outbound buffers used in packet I/O */ -static char remcomInBuffer[BUFMAX]; -static char remcomOutBuffer[BUFMAX]; - -/* Error and warning messages. */ -enum error_type -{ - SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08 -}; -static char *error_message[] = -{ - "", - "E01 Set current or general thread - H[c,g] - internal error.", - "E02 Change register content - P - cannot change read-only register.", - "E03 Thread is not alive.", /* T, not used. */ - "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.", - "E05 Change register content - P - the register is not implemented..", - "E06 Change memory content - M - internal error.", - "E07 Change register content - P - the register is not stored on the stack", - "E08 Invalid parameter" -}; -/********************************* Register image ****************************/ -/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's - Reference", p. 1-1, with the additional register definitions of the - ETRAX 100LX in cris-opc.h. - There are 16 general 32-bit registers, R0-R15, where R14 is the stack - pointer, SP, and R15 is the program counter, PC. - There are 16 special registers, P0-P15, where three of the unimplemented - registers, P0, P4 and P8, are reserved as zero-registers. A read from - any of these registers returns zero and a write has no effect. */ -enum register_name -{ - R0, R1, R2, R3, - R4, R5, R6, R7, - R8, R9, R10, R11, - R12, R13, SP, PC, - P0, VR, P2, P3, - P4, CCR, P6, MOF, - P8, IBR, IRP, SRP, - BAR, DCCR, BRP, USP -}; - -/* The register sizes of the registers in register_name. An unimplemented register - is designated by size 0 in this array. */ -static int register_size[] = -{ - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 1, 1, 0, 0, - 2, 2, 0, 4, - 4, 4, 4, 4, - 4, 4, 4, 4 -}; - -/* Contains the register image of the executing thread in the assembler - part of the code in order to avoid horrible addressing modes. */ -registers cris_reg; - -/* FIXME: Should this be used? Delete otherwise. */ -/* Contains the assumed consistency state of the register image. Uses the - enum error_type for state information. */ -static int consistency_status = SUCCESS; - -/********************************** Handle exceptions ************************/ -/* The variable cris_reg contains the register image associated with the - current_thread_c variable. It is a complete register image created at - entry. The reg_g contains a register image of a task where the general - registers are taken from the stack and all special registers are taken - from the executing task. It is associated with current_thread_g and used - in order to provide access mainly for 'g', 'G' and 'P'. -*/ - -/********************************** Breakpoint *******************************/ -/* Use an internal stack in the breakpoint and interrupt response routines */ -#define INTERNAL_STACK_SIZE 1024 -char internal_stack[INTERNAL_STACK_SIZE]; - -/* Due to the breakpoint return pointer, a state variable is needed to keep - track of whether it is a static (compiled) or dynamic (gdb-invoked) - breakpoint to be handled. A static breakpoint uses the content of register - BRP as it is whereas a dynamic breakpoint requires subtraction with 2 - in order to execute the instruction. The first breakpoint is static. */ -static unsigned char __used is_dyn_brkp; - -/********************************* String library ****************************/ -/* Single-step over library functions creates trap loops. */ - -/* Copy char s2[] to s1[]. */ -static char* -gdb_cris_strcpy (char *s1, const char *s2) -{ - char *s = s1; - - for (s = s1; (*s++ = *s2++) != '\0'; ) - ; - return (s1); -} - -/* Find length of s[]. */ -static int -gdb_cris_strlen (const char *s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; sc++) - ; - return (sc - s); -} - -/* Find first occurrence of c in s[n]. */ -static void* -gdb_cris_memchr (const void *s, int c, int n) -{ - const unsigned char uc = c; - const unsigned char *su; - - for (su = s; 0 < n; ++su, --n) - if (*su == uc) - return ((void *)su); - return (NULL); -} -/******************************* Standard library ****************************/ -/* Single-step over library functions creates trap loops. */ -/* Convert string to long. */ -static int -gdb_cris_strtol (const char *s, char **endptr, int base) -{ - char *s1; - char *sd; - int x = 0; - - for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1) - x = x * base + (sd - hex_asc); - - if (endptr) - { - /* Unconverted suffix is stored in endptr unless endptr is NULL. */ - *endptr = s1; - } - - return x; -} - -/********************************** Packet I/O ******************************/ - -/* Convert the memory, pointed to by mem into hexadecimal representation. - Put the result in buf, and return a pointer to the last character - in buf (null). */ - -static char * -mem2hex(char *buf, unsigned char *mem, int count) -{ - int i; - int ch; - - if (mem == NULL) { - /* Bogus read from m0. FIXME: What constitutes a valid address? */ - for (i = 0; i < count; i++) { - *buf++ = '0'; - *buf++ = '0'; - } - } else { - /* Valid mem address. */ - for (i = 0; i < count; i++) { - ch = *mem++; - buf = hex_byte_pack(buf, ch); - } - } - - /* Terminate properly. */ - *buf = '\0'; - return (buf); -} - -/* Put the content of the array, in binary representation, pointed to by buf - into memory pointed to by mem, and return a pointer to the character after - the last byte written. - Gdb will escape $, #, and the escape char (0x7d). */ -static unsigned char* -bin2mem (unsigned char *mem, unsigned char *buf, int count) -{ - int i; - unsigned char *next; - for (i = 0; i < count; i++) { - /* Check for any escaped characters. Be paranoid and - only unescape chars that should be escaped. */ - if (*buf == 0x7d) { - next = buf + 1; - if (*next == 0x3 || *next == 0x4 || *next == 0x5D) /* #, $, ESC */ - { - buf++; - *buf += 0x20; - } - } - *mem++ = *buf++; - } - return (mem); -} - -/* Await the sequence $# and store in the array buffer - returned. */ -static void -getpacket (char *buffer) -{ - unsigned char checksum; - unsigned char xmitcsum; - int i; - int count; - char ch; - do { - while ((ch = getDebugChar ()) != '$') - /* Wait for the start character $ and ignore all other characters */; - checksum = 0; - xmitcsum = -1; - count = 0; - /* Read until a # or the end of the buffer is reached */ - while (count < BUFMAX - 1) { - ch = getDebugChar (); - if (ch == '#') - break; - checksum = checksum + ch; - buffer[count] = ch; - count = count + 1; - } - buffer[count] = '\0'; - - if (ch == '#') { - xmitcsum = hex_to_bin(getDebugChar()) << 4; - xmitcsum += hex_to_bin(getDebugChar()); - if (checksum != xmitcsum) { - /* Wrong checksum */ - putDebugChar ('-'); - } - else { - /* Correct checksum */ - putDebugChar ('+'); - /* If sequence characters are received, reply with them */ - if (buffer[2] == ':') { - putDebugChar (buffer[0]); - putDebugChar (buffer[1]); - /* Remove the sequence characters from the buffer */ - count = gdb_cris_strlen (buffer); - for (i = 3; i <= count; i++) - buffer[i - 3] = buffer[i]; - } - } - } - } while (checksum != xmitcsum); -} - -/* Send $# from the in the array buffer. */ - -static void -putpacket(char *buffer) -{ - int checksum; - int runlen; - int encode; - - do { - char *src = buffer; - putDebugChar ('$'); - checksum = 0; - while (*src) { - /* Do run length encoding */ - putDebugChar (*src); - checksum += *src; - runlen = 0; - while (runlen < RUNLENMAX && *src == src[runlen]) { - runlen++; - } - if (runlen > 3) { - /* Got a useful amount */ - putDebugChar ('*'); - checksum += '*'; - encode = runlen + ' ' - 4; - putDebugChar (encode); - checksum += encode; - src += runlen; - } - else { - src++; - } - } - putDebugChar('#'); - putDebugChar(hex_asc_hi(checksum)); - putDebugChar(hex_asc_lo(checksum)); - } while(kgdb_started && (getDebugChar() != '+')); -} - -/* The string str is prepended with the GDB printout token and sent. Required - in traditional implementations. */ -void -putDebugString (const unsigned char *str, int length) -{ - remcomOutBuffer[0] = 'O'; - mem2hex(&remcomOutBuffer[1], (unsigned char *)str, length); - putpacket(remcomOutBuffer); -} - -/********************************* Register image ****************************/ -/* Write a value to a specified register in the register image of the current - thread. Returns status code SUCCESS, E02, E05 or E08. */ -static int -write_register (int regno, char *val) -{ - int status = SUCCESS; - registers *current_reg = &cris_reg; - - if (regno >= R0 && regno <= PC) { - /* 32-bit register with simple offset. */ - if (hex2bin((unsigned char *)current_reg + regno * sizeof(unsigned int), - val, sizeof(unsigned int))) - status = E08; - } - else if (regno == P0 || regno == VR || regno == P4 || regno == P8) { - /* Do not support read-only registers. */ - status = E02; - } - else if (regno == CCR) { - /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented, - and P7 (MOF) is 32 bits in ETRAX 100LX. */ - if (hex2bin((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short), - val, sizeof(unsigned short))) - status = E08; - } - else if (regno >= MOF && regno <= USP) { - /* 32 bit register with complex offset. (P8 has been taken care of.) */ - if (hex2bin((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int), - val, sizeof(unsigned int))) - status = E08; - } - else { - /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */ - status = E05; - } - return status; -} - -/* Read a value from a specified register in the register image. Returns the - value in the register or -1 for non-implemented registers. - Should check consistency_status after a call which may be E05 after changes - in the implementation. */ -static int -read_register (char regno, unsigned int *valptr) -{ - registers *current_reg = &cris_reg; - - if (regno >= R0 && regno <= PC) { - /* 32-bit register with simple offset. */ - *valptr = *(unsigned int *)((char *)current_reg + regno * sizeof(unsigned int)); - return SUCCESS; - } - else if (regno == P0 || regno == VR) { - /* 8 bit register with complex offset. */ - *valptr = (unsigned int)(*(unsigned char *) - ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char))); - return SUCCESS; - } - else if (regno == P4 || regno == CCR) { - /* 16 bit register with complex offset. */ - *valptr = (unsigned int)(*(unsigned short *) - ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short))); - return SUCCESS; - } - else if (regno >= MOF && regno <= USP) { - /* 32 bit register with complex offset. */ - *valptr = *(unsigned int *)((char *)&(current_reg->p8) - + (regno-P8) * sizeof(unsigned int)); - return SUCCESS; - } - else { - /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */ - consistency_status = E05; - return E05; - } -} - -/********************************** Handle exceptions ************************/ -/* Build and send a response packet in order to inform the host the - stub is stopped. TAAn...:r...;n...:r...;n...:r...; - AA = signal number - n... = register number (hex) - r... = register contents - n... = `thread' - r... = thread process ID. This is a hex integer. - n... = other string not starting with valid hex digit. - gdb should ignore this n,r pair and go on to the next. - This way we can extend the protocol. */ -static void -stub_is_stopped(int sigval) -{ - char *ptr = remcomOutBuffer; - int regno; - - unsigned int reg_cont; - int status; - - /* Send trap type (converted to signal) */ - - *ptr++ = 'T'; - ptr = hex_byte_pack(ptr, sigval); - - /* Send register contents. We probably only need to send the - * PC, frame pointer and stack pointer here. Other registers will be - * explicitly asked for. But for now, send all. - */ - - for (regno = R0; regno <= USP; regno++) { - /* Store n...:r...; for the registers in the buffer. */ - - status = read_register (regno, ®_cont); - - if (status == SUCCESS) { - ptr = hex_byte_pack(ptr, regno); - *ptr++ = ':'; - - ptr = mem2hex(ptr, (unsigned char *)®_cont, - register_size[regno]); - *ptr++ = ';'; - } - - } - - /* null-terminate and send it off */ - - *ptr = 0; - - putpacket (remcomOutBuffer); -} - -/* Performs a complete re-start from scratch. */ -static void -kill_restart (void) -{ - machine_restart(""); -} - -/* All expected commands are sent from remote.c. Send a response according - to the description in remote.c. */ -void -handle_exception (int sigval) -{ - /* Send response. */ - - stub_is_stopped (sigval); - - for (;;) { - remcomOutBuffer[0] = '\0'; - getpacket (remcomInBuffer); - switch (remcomInBuffer[0]) { - case 'g': - /* Read registers: g - Success: Each byte of register data is described by two hex digits. - Registers are in the internal order for GDB, and the bytes - in a register are in the same order the machine uses. - Failure: void. */ - - mem2hex(remcomOutBuffer, (char *)&cris_reg, sizeof(registers)); - break; - - case 'G': - /* Write registers. GXX..XX - Each byte of register data is described by two hex digits. - Success: OK - Failure: E08. */ - if (hex2bin((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers))) - gdb_cris_strcpy (remcomOutBuffer, error_message[E08]); - else - gdb_cris_strcpy (remcomOutBuffer, "OK"); - break; - - case 'P': - /* Write register. Pn...=r... - Write register n..., hex value without 0x, with value r..., - which contains a hex value without 0x and two hex digits - for each byte in the register (target byte order). P1f=11223344 means - set register 31 to 44332211. - Success: OK - Failure: E02, E05, E08 */ - { - char *suffix; - int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16); - int status; - status = write_register (regno, suffix+1); - - switch (status) { - case E02: - /* Do not support read-only registers. */ - gdb_cris_strcpy (remcomOutBuffer, error_message[E02]); - break; - case E05: - /* Do not support non-existing registers. */ - gdb_cris_strcpy (remcomOutBuffer, error_message[E05]); - break; - case E07: - /* Do not support non-existing registers on the stack. */ - gdb_cris_strcpy (remcomOutBuffer, error_message[E07]); - break; - case E08: - /* Invalid parameter. */ - gdb_cris_strcpy (remcomOutBuffer, error_message[E08]); - break; - default: - /* Valid register number. */ - gdb_cris_strcpy (remcomOutBuffer, "OK"); - break; - } - } - break; - - case 'm': - /* Read from memory. mAA..AA,LLLL - AA..AA is the address and LLLL is the length. - Success: XX..XX is the memory content. Can be fewer bytes than - requested if only part of the data may be read. m6000120a,6c means - retrieve 108 byte from base address 6000120a. - Failure: void. */ - { - char *suffix; - unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1], - &suffix, 16); int length = gdb_cris_strtol(suffix+1, 0, 16); - - mem2hex(remcomOutBuffer, addr, length); - } - break; - - case 'X': - /* Write to memory. XAA..AA,LLLL:XX..XX - AA..AA is the start address, LLLL is the number of bytes, and - XX..XX is the binary data. - Success: OK - Failure: void. */ - case 'M': - /* Write to memory. MAA..AA,LLLL:XX..XX - AA..AA is the start address, LLLL is the number of bytes, and - XX..XX is the hexadecimal data. - Success: OK - Failure: E08. */ - { - char *lenptr; - char *dataptr; - unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1], - &lenptr, 16); - int length = gdb_cris_strtol(lenptr+1, &dataptr, 16); - if (*lenptr == ',' && *dataptr == ':') { - if (remcomInBuffer[0] == 'M') { - if (hex2bin(addr, dataptr + 1, length)) - gdb_cris_strcpy (remcomOutBuffer, error_message[E08]); - else - gdb_cris_strcpy (remcomOutBuffer, "OK"); - } else /* X */ { - bin2mem(addr, dataptr + 1, length); - gdb_cris_strcpy (remcomOutBuffer, "OK"); - } - } else { - gdb_cris_strcpy (remcomOutBuffer, error_message[E06]); - } - } - break; - - case 'c': - /* Continue execution. cAA..AA - AA..AA is the address where execution is resumed. If AA..AA is - omitted, resume at the present address. - Success: return to the executing thread. - Failure: will never know. */ - if (remcomInBuffer[1] != '\0') { - cris_reg.pc = gdb_cris_strtol (&remcomInBuffer[1], 0, 16); - } - enableDebugIRQ(); - return; - - case 's': - /* Step. sAA..AA - AA..AA is the address where execution is resumed. If AA..AA is - omitted, resume at the present address. Success: return to the - executing thread. Failure: will never know. - - Should never be invoked. The single-step is implemented on - the host side. If ever invoked, it is an internal error E04. */ - gdb_cris_strcpy (remcomOutBuffer, error_message[E04]); - putpacket (remcomOutBuffer); - return; - - case '?': - /* The last signal which caused a stop. ? - Success: SAA, where AA is the signal number. - Failure: void. */ - remcomOutBuffer[0] = 'S'; - remcomOutBuffer[1] = hex_asc_hi(sigval); - remcomOutBuffer[2] = hex_asc_lo(sigval); - remcomOutBuffer[3] = 0; - break; - - case 'D': - /* Detach from host. D - Success: OK, and return to the executing thread. - Failure: will never know */ - putpacket ("OK"); - return; - - case 'k': - case 'r': - /* kill request or reset request. - Success: restart of target. - Failure: will never know. */ - kill_restart (); - break; - - case 'C': - case 'S': - case '!': - case 'R': - case 'd': - /* Continue with signal sig. Csig;AA..AA - Step with signal sig. Ssig;AA..AA - Use the extended remote protocol. ! - Restart the target system. R0 - Toggle debug flag. d - Search backwards. tAA:PP,MM - Not supported: E04 */ - gdb_cris_strcpy (remcomOutBuffer, error_message[E04]); - break; - - default: - /* The stub should ignore other request and send an empty - response ($#). This way we can extend the protocol and GDB - can tell whether the stub it is talking to uses the old or the new. */ - remcomOutBuffer[0] = 0; - break; - } - putpacket(remcomOutBuffer); - } -} - -/********************************** Breakpoint *******************************/ -/* The hook for both a static (compiled) and a dynamic breakpoint set by GDB. - An internal stack is used by the stub. The register image of the caller is - stored in the structure register_image. - Interactive communication with the host is handled by handle_exception and - finally the register image is restored. */ - -void kgdb_handle_breakpoint(void); - -asm ("\n" -" .global kgdb_handle_breakpoint\n" -"kgdb_handle_breakpoint:\n" -";;\n" -";; Response to the break-instruction\n" -";;\n" -";; Create a register image of the caller\n" -";;\n" -" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR before disable interrupts\n" -" di ; Disable interrupts\n" -" move.d $r0,[cris_reg] ; Save R0\n" -" move.d $r1,[cris_reg+0x04] ; Save R1\n" -" move.d $r2,[cris_reg+0x08] ; Save R2\n" -" move.d $r3,[cris_reg+0x0C] ; Save R3\n" -" move.d $r4,[cris_reg+0x10] ; Save R4\n" -" move.d $r5,[cris_reg+0x14] ; Save R5\n" -" move.d $r6,[cris_reg+0x18] ; Save R6\n" -" move.d $r7,[cris_reg+0x1C] ; Save R7\n" -" move.d $r8,[cris_reg+0x20] ; Save R8\n" -" move.d $r9,[cris_reg+0x24] ; Save R9\n" -" move.d $r10,[cris_reg+0x28] ; Save R10\n" -" move.d $r11,[cris_reg+0x2C] ; Save R11\n" -" move.d $r12,[cris_reg+0x30] ; Save R12\n" -" move.d $r13,[cris_reg+0x34] ; Save R13\n" -" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n" -";; Due to the old assembler-versions BRP might not be recognized\n" -" .word 0xE670 ; move brp,$r0\n" -" subq 2,$r0 ; Set to address of previous instruction.\n" -" move.d $r0,[cris_reg+0x3c] ; Save the address in PC (R15)\n" -" clear.b [cris_reg+0x40] ; Clear P0\n" -" move $vr,[cris_reg+0x41] ; Save special register P1\n" -" clear.w [cris_reg+0x42] ; Clear P4\n" -" move $ccr,[cris_reg+0x44] ; Save special register CCR\n" -" move $mof,[cris_reg+0x46] ; P7\n" -" clear.d [cris_reg+0x4A] ; Clear P8\n" -" move $ibr,[cris_reg+0x4E] ; P9,\n" -" move $irp,[cris_reg+0x52] ; P10,\n" -" move $srp,[cris_reg+0x56] ; P11,\n" -" move $bar,[cris_reg+0x5A] ; P12,\n" -" ; P13, register DCCR already saved\n" -";; Due to the old assembler-versions BRP might not be recognized\n" -" .word 0xE670 ; move brp,r0\n" -";; Static (compiled) breakpoints must return to the next instruction in order\n" -";; to avoid infinite loops. Dynamic (gdb-invoked) must restore the instruction\n" -";; in order to execute it when execution is continued.\n" -" test.b [is_dyn_brkp] ; Is this a dynamic breakpoint?\n" -" beq is_static ; No, a static breakpoint\n" -" nop\n" -" subq 2,$r0 ; rerun the instruction the break replaced\n" -"is_static:\n" -" moveq 1,$r1\n" -" move.b $r1,[is_dyn_brkp] ; Set the state variable to dynamic breakpoint\n" -" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n" -" move $usp,[cris_reg+0x66] ; USP\n" -";;\n" -";; Handle the communication\n" -";;\n" -" move.d internal_stack+1020,$sp ; Use the internal stack which grows upward\n" -" moveq 5,$r10 ; SIGTRAP\n" -" jsr handle_exception ; Interactive routine\n" -";;\n" -";; Return to the caller\n" -";;\n" -" move.d [cris_reg],$r0 ; Restore R0\n" -" move.d [cris_reg+0x04],$r1 ; Restore R1\n" -" move.d [cris_reg+0x08],$r2 ; Restore R2\n" -" move.d [cris_reg+0x0C],$r3 ; Restore R3\n" -" move.d [cris_reg+0x10],$r4 ; Restore R4\n" -" move.d [cris_reg+0x14],$r5 ; Restore R5\n" -" move.d [cris_reg+0x18],$r6 ; Restore R6\n" -" move.d [cris_reg+0x1C],$r7 ; Restore R7\n" -" move.d [cris_reg+0x20],$r8 ; Restore R8\n" -" move.d [cris_reg+0x24],$r9 ; Restore R9\n" -" move.d [cris_reg+0x28],$r10 ; Restore R10\n" -" move.d [cris_reg+0x2C],$r11 ; Restore R11\n" -" move.d [cris_reg+0x30],$r12 ; Restore R12\n" -" move.d [cris_reg+0x34],$r13 ; Restore R13\n" -";;\n" -";; FIXME: Which registers should be restored?\n" -";;\n" -" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n" -" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n" -" move [cris_reg+0x5E],$dccr ; Restore DCCR\n" -" move [cris_reg+0x66],$usp ; Restore USP\n" -" jump [cris_reg+0x62] ; A jump to the content in register BRP works.\n" -" nop ;\n" -"\n"); - -/* The hook for an interrupt generated by GDB. An internal stack is used - by the stub. The register image of the caller is stored in the structure - register_image. Interactive communication with the host is handled by - handle_exception and finally the register image is restored. Due to the - old assembler which does not recognise the break instruction and the - breakpoint return pointer hex-code is used. */ - -void kgdb_handle_serial(void); - -asm ("\n" -" .global kgdb_handle_serial\n" -"kgdb_handle_serial:\n" -";;\n" -";; Response to a serial interrupt\n" -";;\n" -"\n" -" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR\n" -" di ; Disable interrupts\n" -" move.d $r0,[cris_reg] ; Save R0\n" -" move.d $r1,[cris_reg+0x04] ; Save R1\n" -" move.d $r2,[cris_reg+0x08] ; Save R2\n" -" move.d $r3,[cris_reg+0x0C] ; Save R3\n" -" move.d $r4,[cris_reg+0x10] ; Save R4\n" -" move.d $r5,[cris_reg+0x14] ; Save R5\n" -" move.d $r6,[cris_reg+0x18] ; Save R6\n" -" move.d $r7,[cris_reg+0x1C] ; Save R7\n" -" move.d $r8,[cris_reg+0x20] ; Save R8\n" -" move.d $r9,[cris_reg+0x24] ; Save R9\n" -" move.d $r10,[cris_reg+0x28] ; Save R10\n" -" move.d $r11,[cris_reg+0x2C] ; Save R11\n" -" move.d $r12,[cris_reg+0x30] ; Save R12\n" -" move.d $r13,[cris_reg+0x34] ; Save R13\n" -" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n" -" move $irp,[cris_reg+0x3c] ; Save the address in PC (R15)\n" -" clear.b [cris_reg+0x40] ; Clear P0\n" -" move $vr,[cris_reg+0x41] ; Save special register P1,\n" -" clear.w [cris_reg+0x42] ; Clear P4\n" -" move $ccr,[cris_reg+0x44] ; Save special register CCR\n" -" move $mof,[cris_reg+0x46] ; P7\n" -" clear.d [cris_reg+0x4A] ; Clear P8\n" -" move $ibr,[cris_reg+0x4E] ; P9,\n" -" move $irp,[cris_reg+0x52] ; P10,\n" -" move $srp,[cris_reg+0x56] ; P11,\n" -" move $bar,[cris_reg+0x5A] ; P12,\n" -" ; P13, register DCCR already saved\n" -";; Due to the old assembler-versions BRP might not be recognized\n" -" .word 0xE670 ; move brp,r0\n" -" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n" -" move $usp,[cris_reg+0x66] ; USP\n" -"\n" -";; get the serial character (from debugport.c) and check if it is a ctrl-c\n" -"\n" -" jsr getDebugChar\n" -" cmp.b 3, $r10\n" -" bne goback\n" -" nop\n" -"\n" -" move.d [cris_reg+0x5E], $r10 ; Get DCCR\n" -" btstq 8, $r10 ; Test the U-flag.\n" -" bmi goback\n" -" nop\n" -"\n" -";;\n" -";; Handle the communication\n" -";;\n" -" move.d internal_stack+1020,$sp ; Use the internal stack\n" -" moveq 2,$r10 ; SIGINT\n" -" jsr handle_exception ; Interactive routine\n" -"\n" -"goback:\n" -";;\n" -";; Return to the caller\n" -";;\n" -" move.d [cris_reg],$r0 ; Restore R0\n" -" move.d [cris_reg+0x04],$r1 ; Restore R1\n" -" move.d [cris_reg+0x08],$r2 ; Restore R2\n" -" move.d [cris_reg+0x0C],$r3 ; Restore R3\n" -" move.d [cris_reg+0x10],$r4 ; Restore R4\n" -" move.d [cris_reg+0x14],$r5 ; Restore R5\n" -" move.d [cris_reg+0x18],$r6 ; Restore R6\n" -" move.d [cris_reg+0x1C],$r7 ; Restore R7\n" -" move.d [cris_reg+0x20],$r8 ; Restore R8\n" -" move.d [cris_reg+0x24],$r9 ; Restore R9\n" -" move.d [cris_reg+0x28],$r10 ; Restore R10\n" -" move.d [cris_reg+0x2C],$r11 ; Restore R11\n" -" move.d [cris_reg+0x30],$r12 ; Restore R12\n" -" move.d [cris_reg+0x34],$r13 ; Restore R13\n" -";;\n" -";; FIXME: Which registers should be restored?\n" -";;\n" -" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n" -" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n" -" move [cris_reg+0x5E],$dccr ; Restore DCCR\n" -" move [cris_reg+0x66],$usp ; Restore USP\n" -" reti ; Return from the interrupt routine\n" -" nop\n" -"\n"); - -/* Use this static breakpoint in the start-up only. */ - -void -breakpoint(void) -{ - kgdb_started = 1; - is_dyn_brkp = 0; /* This is a static, not a dynamic breakpoint. */ - __asm__ volatile ("break 8"); /* Jump to handle_breakpoint. */ -} - -/* initialize kgdb. doesn't break into the debugger, but sets up irq and ports */ - -void -kgdb_init(void) -{ - /* could initialize debug port as well but it's done in head.S already... */ - - /* breakpoint handler is now set in irq.c */ - set_int_vector(8, kgdb_handle_serial); - - enableDebugIRQ(); -} - -/****************************** End of file **********************************/ diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c deleted file mode 100644 index 16848b2c61c8..000000000000 --- a/arch/cris/arch-v10/kernel/process.c +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/process.c - * - * Copyright (C) 1995 Linus Torvalds - * Copyright (C) 2000-2002 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * Mikael Starvik (starvik@axis.com) - * - * This file handles the architecture-dependent parts of process handling.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_ETRAX_GPIO -void etrax_gpio_wake_up_check(void); /* drivers/gpio.c */ -#endif - -/* - * We use this if we don't have any better - * idle routine.. - */ -void default_idle(void) -{ -#ifdef CONFIG_ETRAX_GPIO - etrax_gpio_wake_up_check(); -#endif - local_irq_enable(); -} - -/* if the watchdog is enabled, we can simply disable interrupts and go - * into an eternal loop, and the watchdog will reset the CPU after 0.1s - * if on the other hand the watchdog wasn't enabled, we just enable it and wait - */ - -void hard_reset_now (void) -{ - /* - * Don't declare this variable elsewhere. We don't want any other - * code to know about it than the watchdog handler in entry.S and - * this code, implementing hard reset through the watchdog. - */ -#if defined(CONFIG_ETRAX_WATCHDOG) - extern int cause_of_death; -#endif - - printk("*** HARD RESET ***\n"); - local_irq_disable(); - -#if defined(CONFIG_ETRAX_WATCHDOG) - cause_of_death = 0xbedead; -#else - /* Since we dont plan to keep on resetting the watchdog, - the key can be arbitrary hence three */ - *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, 3) | - IO_STATE(R_WATCHDOG, enable, start); -#endif - - while(1) /* waiting for RETRIBUTION! */ ; -} - -/* setup the child's kernel stack with a pt_regs and switch_stack on it. - * it will be un-nested during _resume and _ret_from_sys_call when the - * new thread is scheduled. - * - * also setup the thread switching structure which is used to keep - * thread-specific data during _resumes. - * - */ -asmlinkage void ret_from_fork(void); -asmlinkage void ret_from_kernel_thread(void); - -int copy_thread(unsigned long clone_flags, unsigned long usp, - unsigned long arg, struct task_struct *p) -{ - struct pt_regs *childregs = task_pt_regs(p); - struct switch_stack *swstack = ((struct switch_stack *)childregs) - 1; - - /* put the pt_regs structure at the end of the new kernel stack page and fix it up - * remember that the task_struct doubles as the kernel stack for the task - */ - - if (unlikely(p->flags & PF_KTHREAD)) { - memset(swstack, 0, - sizeof(struct switch_stack) + sizeof(struct pt_regs)); - swstack->r1 = usp; - swstack->r2 = arg; - childregs->dccr = 1 << I_DCCR_BITNR; - swstack->return_ip = (unsigned long) ret_from_kernel_thread; - p->thread.ksp = (unsigned long) swstack; - p->thread.usp = 0; - return 0; - } - *childregs = *current_pt_regs(); /* struct copy of pt_regs */ - - childregs->r10 = 0; /* child returns 0 after a fork/clone */ - - /* put the switch stack right below the pt_regs */ - - swstack->r9 = 0; /* parameter to ret_from_sys_call, 0 == dont restart the syscall */ - - /* we want to return into ret_from_sys_call after the _resume */ - - swstack->return_ip = (unsigned long) ret_from_fork; /* Will call ret_from_sys_call */ - - /* fix the user-mode stackpointer */ - - p->thread.usp = usp ?: rdusp(); - - /* and the kernel-mode one */ - - p->thread.ksp = (unsigned long) swstack; - -#ifdef DEBUG - printk("copy_thread: new regs at 0x%p, as shown below:\n", childregs); - show_registers(childregs); -#endif - - return 0; -} - -unsigned long get_wchan(struct task_struct *p) -{ -#if 0 - /* YURGH. TODO. */ - - unsigned long ebp, esp, eip; - unsigned long stack_page; - int count = 0; - if (!p || p == current || p->state == TASK_RUNNING) - return 0; - stack_page = (unsigned long)p; - esp = p->thread.esp; - if (!stack_page || esp < stack_page || esp > 8188+stack_page) - return 0; - /* include/asm-i386/system.h:switch_to() pushes ebp last. */ - ebp = *(unsigned long *) esp; - do { - if (ebp < stack_page || ebp > 8184+stack_page) - return 0; - eip = *(unsigned long *) (ebp+4); - if (!in_sched_functions(eip)) - return eip; - ebp = *(unsigned long *) ebp; - } while (count++ < 16); -#endif - return 0; -} -#undef last_sched -#undef first_sched - -void show_regs(struct pt_regs * regs) -{ - unsigned long usp = rdusp(); - - show_regs_print_info(KERN_DEFAULT); - - printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n", - regs->irp, regs->srp, regs->dccr, usp, regs->mof ); - printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", - regs->r0, regs->r1, regs->r2, regs->r3); - printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", - regs->r4, regs->r5, regs->r6, regs->r7); - printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", - regs->r8, regs->r9, regs->r10, regs->r11); - printk("r12: %08lx r13: %08lx oR10: %08lx\n", - regs->r12, regs->r13, regs->orig_r10); -} - diff --git a/arch/cris/arch-v10/kernel/ptrace.c b/arch/cris/arch-v10/kernel/ptrace.c deleted file mode 100644 index b89f57ae096e..000000000000 --- a/arch/cris/arch-v10/kernel/ptrace.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2000-2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* - * Determines which bits in DCCR the user has access to. - * 1 = access, 0 = no access. - */ -#define DCCR_MASK 0x0000001f /* XNZVC */ - -/* - * Get contents of register REGNO in task TASK. - */ -inline long get_reg(struct task_struct *task, unsigned int regno) -{ - /* USP is a special case, it's not in the pt_regs struct but - * in the tasks thread struct - */ - - if (regno == PT_USP) - return task->thread.usp; - else if (regno < PT_MAX) - return ((unsigned long *)task_pt_regs(task))[regno]; - else - return 0; -} - -/* - * Write contents of register REGNO in task TASK. - */ -inline int put_reg(struct task_struct *task, unsigned int regno, - unsigned long data) -{ - if (regno == PT_USP) - task->thread.usp = data; - else if (regno < PT_MAX) - ((unsigned long *)task_pt_regs(task))[regno] = data; - else - return -1; - return 0; -} - -/* - * Called by kernel/ptrace.c when detaching. - * - * Make sure the single step bit is not set. - */ -void -ptrace_disable(struct task_struct *child) -{ - /* Todo - pending singlesteps? */ - clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); -} - -/* - * Note that this implementation of ptrace behaves differently from vanilla - * ptrace. Contrary to what the man page says, in the PTRACE_PEEKTEXT, - * PTRACE_PEEKDATA, and PTRACE_PEEKUSER requests the data variable is not - * ignored. Instead, the data variable is expected to point at a location - * (in user space) where the result of the ptrace call is written (instead of - * being returned). - */ -long arch_ptrace(struct task_struct *child, long request, - unsigned long addr, unsigned long data) -{ - int ret; - unsigned int regno = addr >> 2; - unsigned long __user *datap = (unsigned long __user *)data; - - switch (request) { - /* Read word at location address. */ - case PTRACE_PEEKTEXT: - case PTRACE_PEEKDATA: - ret = generic_ptrace_peekdata(child, addr, data); - break; - - /* Read the word at location address in the USER area. */ - case PTRACE_PEEKUSR: { - unsigned long tmp; - - ret = -EIO; - if ((addr & 3) || regno > PT_MAX) - break; - - tmp = get_reg(child, regno); - ret = put_user(tmp, datap); - break; - } - - /* Write the word at location address. */ - case PTRACE_POKETEXT: - case PTRACE_POKEDATA: - ret = generic_ptrace_pokedata(child, addr, data); - break; - - /* Write the word at location address in the USER area. */ - case PTRACE_POKEUSR: - ret = -EIO; - if ((addr & 3) || regno > PT_MAX) - break; - - if (regno == PT_DCCR) { - /* don't allow the tracing process to change stuff like - * interrupt enable, kernel/user bit, dma enables etc. - */ - data &= DCCR_MASK; - data |= get_reg(child, PT_DCCR) & ~DCCR_MASK; - } - if (put_reg(child, regno, data)) - break; - ret = 0; - break; - - /* Get all GP registers from the child. */ - case PTRACE_GETREGS: { - int i; - unsigned long tmp; - - ret = 0; - for (i = 0; i <= PT_MAX; i++) { - tmp = get_reg(child, i); - - if (put_user(tmp, datap)) { - ret = -EFAULT; - break; - } - - datap++; - } - - break; - } - - /* Set all GP registers in the child. */ - case PTRACE_SETREGS: { - int i; - unsigned long tmp; - - ret = 0; - for (i = 0; i <= PT_MAX; i++) { - if (get_user(tmp, datap)) { - ret = -EFAULT; - break; - } - - if (i == PT_DCCR) { - tmp &= DCCR_MASK; - tmp |= get_reg(child, PT_DCCR) & ~DCCR_MASK; - } - - put_reg(child, i, tmp); - datap++; - } - - break; - } - - default: - ret = ptrace_request(child, request, addr, data); - break; - } - - return ret; -} - -void do_syscall_trace(void) -{ - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - return; - - if (!(current->ptrace & PT_PTRACED)) - return; - - /* the 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) - ? 0x80 : 0)); - - /* - * This isn't the same as continuing with a signal, but it will do for - * normal use. - */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } -} diff --git a/arch/cris/arch-v10/kernel/setup.c b/arch/cris/arch-v10/kernel/setup.c deleted file mode 100644 index 8e4fc248f96f..000000000000 --- a/arch/cris/arch-v10/kernel/setup.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * - * linux/arch/cris/arch-v10/kernel/setup.c - * - * Copyright (C) 1995 Linus Torvalds - * Copyright (c) 2001-2002 Axis Communications AB - */ - -/* - * This file handles the architecture-dependent parts of initialization - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_PROC_FS -#define HAS_FPU 0x0001 -#define HAS_MMU 0x0002 -#define HAS_ETHERNET100 0x0004 -#define HAS_TOKENRING 0x0008 -#define HAS_SCSI 0x0010 -#define HAS_ATA 0x0020 -#define HAS_USB 0x0040 -#define HAS_IRQ_BUG 0x0080 -#define HAS_MMU_BUG 0x0100 - -static struct cpu_info { - char *model; - unsigned short cache; - unsigned short flags; -} cpu_info[] = { - /* The first four models will never ever run this code and are - only here for display. */ - { "ETRAX 1", 0, 0 }, - { "ETRAX 2", 0, 0 }, - { "ETRAX 3", 0, HAS_TOKENRING }, - { "ETRAX 4", 0, HAS_TOKENRING | HAS_SCSI }, - { "Unknown", 0, 0 }, - { "Unknown", 0, 0 }, - { "Unknown", 0, 0 }, - { "Simulator", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA }, - { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG }, - { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA }, - { "ETRAX 100LX", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU | HAS_MMU_BUG }, - { "ETRAX 100LX v2", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU }, - { "Unknown", 0, 0 } /* This entry MUST be the last */ -}; - -int show_cpuinfo(struct seq_file *m, void *v) -{ - unsigned long revision; - struct cpu_info *info; - - /* read the version register in the CPU and print some stuff */ - - revision = rdvr(); - - if (revision >= ARRAY_SIZE(cpu_info)) - info = &cpu_info[ARRAY_SIZE(cpu_info) - 1]; - else - info = &cpu_info[revision]; - - seq_printf(m, - "processor\t: 0\n" - "cpu\t\t: CRIS\n" - "cpu revision\t: %lu\n" - "cpu model\t: %s\n" - "cache size\t: %d kB\n" - "fpu\t\t: %s\n" - "mmu\t\t: %s\n" - "mmu DMA bug\t: %s\n" - "ethernet\t: %s Mbps\n" - "token ring\t: %s\n" - "scsi\t\t: %s\n" - "ata\t\t: %s\n" - "usb\t\t: %s\n" - "bogomips\t: %lu.%02lu\n", - - revision, - info->model, - info->cache, - info->flags & HAS_FPU ? "yes" : "no", - info->flags & HAS_MMU ? "yes" : "no", - info->flags & HAS_MMU_BUG ? "yes" : "no", - info->flags & HAS_ETHERNET100 ? "10/100" : "10", - info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no", - info->flags & HAS_SCSI ? "yes" : "no", - info->flags & HAS_ATA ? "yes" : "no", - info->flags & HAS_USB ? "yes" : "no", - (loops_per_jiffy * HZ + 500) / 500000, - ((loops_per_jiffy * HZ + 500) / 5000) % 100); - - return 0; -} - -#endif /* CONFIG_PROC_FS */ - -void -show_etrax_copyright(void) -{ - printk(KERN_INFO - "Linux/CRIS port on ETRAX 100LX (c) 2001 Axis Communications AB\n"); -} diff --git a/arch/cris/arch-v10/kernel/shadows.c b/arch/cris/arch-v10/kernel/shadows.c deleted file mode 100644 index 2e9565e868f2..000000000000 --- a/arch/cris/arch-v10/kernel/shadows.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Various shadow registers. Defines for these are in include/asm-etrax100/io.h - */ - -/* Shadows for internal Etrax-registers */ - -unsigned long genconfig_shadow; -unsigned long gen_config_ii_shadow; -unsigned long port_g_data_shadow; -unsigned char port_pa_dir_shadow; -unsigned char port_pa_data_shadow; -unsigned char port_pb_i2c_shadow; -unsigned char port_pb_config_shadow; -unsigned char port_pb_dir_shadow; -unsigned char port_pb_data_shadow; -unsigned long r_timer_ctrl_shadow; - -/* Shadows for external I/O port registers. - * These are only usable if there actually IS a latch connected - * to the corresponding external chip-select pin. - * - * A common usage is that CSP0 controls LEDs and CSP4 video chips. - */ - -unsigned long port_cse1_shadow; -unsigned long port_csp0_shadow; -unsigned long port_csp4_shadow; - -/* Corresponding addresses for the ports. - * These are initialized in arch/cris/mm/init.c using ioremap. - */ - -volatile unsigned long *port_cse1_addr; -volatile unsigned long *port_csp0_addr; -volatile unsigned long *port_csp4_addr; - diff --git a/arch/cris/arch-v10/kernel/signal.c b/arch/cris/arch-v10/kernel/signal.c deleted file mode 100644 index 2beffc37faf8..000000000000 --- a/arch/cris/arch-v10/kernel/signal.c +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/signal.c - * - * Based on arch/i386/kernel/signal.c by - * Copyright (C) 1991, 1992 Linus Torvalds - * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson * - * - * Ideas also taken from arch/arm. - * - * Copyright (C) 2000-2007 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DEBUG_SIG 0 - -/* a syscall in Linux/CRIS is a break 13 instruction which is 2 bytes */ -/* manipulate regs so that upon return, it will be re-executed */ - -/* We rely on that pc points to the instruction after "break 13", so the - * library must never do strange things like putting it in a delay slot. - */ -#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->irp -= 2; - -void do_signal(int canrestart, struct pt_regs *regs); - -/* - * Do a signal return; undo the signal stack. - */ - -struct sigframe { - struct sigcontext sc; - unsigned long extramask[_NSIG_WORDS-1]; - unsigned char retcode[8]; /* trampoline code */ -}; - -struct rt_sigframe { - struct siginfo *pinfo; - void *puc; - struct siginfo info; - struct ucontext uc; - unsigned char retcode[8]; /* trampoline code */ -}; - - -static int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) -{ - unsigned int err = 0; - unsigned long old_usp; - - /* Always make any pending restarted system calls return -EINTR */ - current->restart_block.fn = do_no_restart_syscall; - - /* restore the regs from &sc->regs (same as sc, since regs is first) - * (sc is already checked for VERIFY_READ since the sigframe was - * checked in sys_sigreturn previously) - */ - - if (__copy_from_user(regs, sc, sizeof(struct pt_regs))) - goto badframe; - - /* make sure the U-flag is set so user-mode cannot fool us */ - - regs->dccr |= 1 << 8; - - /* restore the old USP as it was before we stacked the sc etc. - * (we cannot just pop the sigcontext since we aligned the sp and - * stuff after pushing it) - */ - - err |= __get_user(old_usp, &sc->usp); - - wrusp(old_usp); - - /* TODO: the other ports use regs->orig_XX to disable syscall checks - * after this completes, but we don't use that mechanism. maybe we can - * use it now ? - */ - - return err; - -badframe: - return 1; -} - -asmlinkage int sys_sigreturn(void) -{ - struct pt_regs *regs = current_pt_regs(); - struct sigframe __user *frame = (struct sigframe *)rdusp(); - sigset_t set; - - /* - * Since we stacked the signal on a dword boundary, - * then frame should be dword aligned here. If it's - * not, then the user is trying to mess with us. - */ - if (((long)frame) & 3) - goto badframe; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__get_user(set.sig[0], &frame->sc.oldmask) - || (_NSIG_WORDS > 1 - && __copy_from_user(&set.sig[1], frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(regs, &frame->sc)) - goto badframe; - - /* TODO: SIGTRAP when single-stepping as in arm ? */ - - return regs->r10; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -asmlinkage int sys_rt_sigreturn(void) -{ - struct pt_regs *regs = current_pt_regs(); - struct rt_sigframe __user *frame = (struct rt_sigframe *)rdusp(); - sigset_t set; - - /* - * Since we stacked the signal on a dword boundary, - * then frame should be dword aligned here. If it's - * not, then the user is trying to mess with us. - */ - if (((long)frame) & 3) - goto badframe; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(regs, &frame->uc.uc_mcontext)) - goto badframe; - - if (restore_altstack(&frame->uc.uc_stack)) - goto badframe; - - return regs->r10; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* - * Set up a signal frame. - */ - -static int setup_sigcontext(struct sigcontext __user *sc, - struct pt_regs *regs, unsigned long mask) -{ - int err = 0; - unsigned long usp = rdusp(); - - /* copy the regs. they are first in sc so we can use sc directly */ - - err |= __copy_to_user(sc, regs, sizeof(struct pt_regs)); - - /* Set the frametype to CRIS_FRAME_NORMAL for the execution of - the signal handler. The frametype will be restored to its previous - value in restore_sigcontext. */ - regs->frametype = CRIS_FRAME_NORMAL; - - /* then some other stuff */ - - err |= __put_user(mask, &sc->oldmask); - - err |= __put_user(usp, &sc->usp); - - return err; -} - -/* Figure out where we want to put the new signal frame - * - usually on the stack. */ - -static inline void __user * -get_sigframe(struct ksignal *ksig, size_t frame_size) -{ - unsigned long sp = sigsp(rdusp(), ksig); - - /* make sure the frame is dword-aligned */ - - sp &= ~3; - - return (void __user*)(sp - frame_size); -} - -/* grab and setup a signal frame. - * - * basically we stack a lot of state info, and arrange for the - * user-mode program to return to the kernel using either a - * trampoline which performs the syscall sigreturn, or a provided - * user-mode trampoline. - */ - -static int setup_frame(struct ksignal *ksig, sigset_t *set, - struct pt_regs *regs) -{ - struct sigframe __user *frame; - unsigned long return_ip; - int err = 0; - - frame = get_sigframe(ksig, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - err |= setup_sigcontext(&frame->sc, regs, set->sig[0]); - if (err) - return -EFAULT; - - if (_NSIG_WORDS > 1) { - err |= __copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - } - if (err) - return -EFAULT; - - /* Set up to return from userspace. If provided, use a stub - already in userspace. */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { - return_ip = (unsigned long)ksig->ka.sa.sa_restorer; - } else { - /* trampoline - the desired return ip is the retcode itself */ - return_ip = (unsigned long)&frame->retcode; - /* This is movu.w __NR_sigreturn, r9; break 13; */ - err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); - err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2)); - err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); - } - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - - regs->irp = (unsigned long) ksig->ka.sa.sa_handler; /* what we enter NOW */ - regs->srp = return_ip; /* what we enter LATER */ - regs->r10 = ksig->sig; /* first argument is signo */ - - /* actually move the usp to reflect the stacked frame */ - - wrusp((unsigned long)frame); - - return 0; -} - -static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, - struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - unsigned long return_ip; - int err = 0; - - frame = get_sigframe(ksig, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, &ksig->info); - if (err) - return -EFAULT; - - /* Clear all the bits of the ucontext we don't use. */ - err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext)); - - err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); - - err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - - err |= __save_altstack(&frame->uc.uc_stack, rdusp()); - - if (err) - return -EFAULT; - - /* Set up to return from userspace. If provided, use a stub - already in userspace. */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { - return_ip = (unsigned long)ksig->ka.sa.sa_restorer; - } else { - /* trampoline - the desired return ip is the retcode itself */ - return_ip = (unsigned long)&frame->retcode; - /* This is movu.w __NR_rt_sigreturn, r9; break 13; */ - err |= __put_user(0x9c5f, (short __user *)(frame->retcode+0)); - err |= __put_user(__NR_rt_sigreturn, - (short __user *)(frame->retcode+2)); - err |= __put_user(0xe93d, (short __user *)(frame->retcode+4)); - } - - if (err) - return -EFAULT; - - /* Set up registers for signal handler */ - - /* What we enter NOW */ - regs->irp = (unsigned long) ksig->ka.sa.sa_handler; - /* What we enter LATER */ - regs->srp = return_ip; - /* First argument is signo */ - regs->r10 = ksig->sig; - /* Second argument is (siginfo_t *) */ - regs->r11 = (unsigned long)&frame->info; - /* Third argument is unused */ - regs->r12 = 0; - - /* Actually move the usp to reflect the stacked frame */ - wrusp((unsigned long)frame); - - return 0; -} - -/* - * OK, we're invoking a handler - */ - -static inline void handle_signal(int canrestart, struct ksignal *ksig, - struct pt_regs *regs) -{ - sigset_t *oldset = sigmask_to_save(); - int ret; - - /* Are we from a system call? */ - if (canrestart) { - /* If so, check system call restarting.. */ - switch (regs->r10) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - /* ERESTARTNOHAND means that the syscall should - * only be restarted if there was no handler for - * the signal, and since we only get here if there - * is a handler, we don't restart */ - regs->r10 = -EINTR; - break; - case -ERESTARTSYS: - /* ERESTARTSYS means to restart the syscall if - * there is no handler or the handler was - * registered with SA_RESTART */ - if (!(ksig->ka.sa.sa_flags & SA_RESTART)) { - regs->r10 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - /* ERESTARTNOINTR means that the syscall should - * be called again after the signal handler returns. */ - RESTART_CRIS_SYS(regs); - } - } - - /* Set up the stack frame */ - if (ksig->ka.sa.sa_flags & SA_SIGINFO) - ret = setup_rt_frame(ksig, oldset, regs); - else - ret = setup_frame(ksig, oldset, regs); - - signal_setup_done(ret, ksig, 0); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - * - * Also note that the regs structure given here as an argument, is the latest - * pushed pt_regs. It may or may not be the same as the first pushed registers - * when the initial usermode->kernelmode transition took place. Therefore - * we can use user_mode(regs) to see if we came directly from kernel or user - * mode below. - */ - -void do_signal(int canrestart, struct pt_regs *regs) -{ - struct ksignal ksig; - - /* - * We want the common case to go fast, which - * is why we may in certain cases get here from - * kernel mode. Just return without doing anything - * if so. - */ - if (!user_mode(regs)) - return; - - if (get_signal(&ksig)) { - /* Whee! Actually deliver the signal. */ - handle_signal(canrestart, &ksig, regs); - return; - } - - /* Did we come from a system call? */ - if (canrestart) { - /* Restart the system call - no handlers present */ - if (regs->r10 == -ERESTARTNOHAND || - regs->r10 == -ERESTARTSYS || - regs->r10 == -ERESTARTNOINTR) { - RESTART_CRIS_SYS(regs); - } - if (regs->r10 == -ERESTART_RESTARTBLOCK) { - regs->r9 = __NR_restart_syscall; - regs->irp -= 2; - } - } - - /* if there's no signal to deliver, we just put the saved sigmask - * back */ - restore_saved_sigmask(); -} diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c deleted file mode 100644 index 3d78373db254..000000000000 --- a/arch/cris/arch-v10/kernel/time.c +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/arch-v10/kernel/time.c - * - * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * Copyright (C) 1999-2002 Axis Communications AB - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* define this if you need to use print_timestamp */ -/* it will make jiffies at 96 hz instead of 100 hz though */ -#undef USE_CASCADE_TIMERS - -unsigned long get_ns_in_jiffie(void) -{ - unsigned char timer_count, t1; - unsigned short presc_count; - unsigned long ns; - unsigned long flags; - - local_irq_save(flags); - timer_count = *R_TIMER0_DATA; - presc_count = *R_TIM_PRESC_STATUS; - /* presc_count might be wrapped */ - t1 = *R_TIMER0_DATA; - - if (timer_count != t1){ - /* it wrapped, read prescaler again... */ - presc_count = *R_TIM_PRESC_STATUS; - timer_count = t1; - } - local_irq_restore(flags); - if (presc_count >= PRESCALE_VALUE/2 ){ - presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2; - } else { - presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2; - } - - ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + - ( (presc_count) * (1000000000/PRESCALE_FREQ)); - return ns; -} - -static u32 cris_v10_gettimeoffset(void) -{ - u32 count; - - /* The timer interrupt comes from Etrax timer 0. In order to get - * better precision, we check the current value. It might have - * underflowed already though. - */ - count = *R_TIMER0_DATA; - - /* Convert timer value to nsec */ - return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV; -} - -/* Excerpt from the Etrax100 HSDD about the built-in watchdog: - * - * 3.10.4 Watchdog timer - - * When the watchdog timer is started, it generates an NMI if the watchdog - * isn't restarted or stopped within 0.1 s. If it still isn't restarted or - * stopped after an additional 3.3 ms, the watchdog resets the chip. - * The watchdog timer is stopped after reset. The watchdog timer is controlled - * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit - * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is - * described in the table below: - * - * Watchdog Value written: - * state: To enable: To key: Operation: - * -------- ---------- ------- ---------- - * stopped 0 X No effect. - * stopped 1 key_val Start watchdog with key = key_val. - * started 0 ~key Stop watchdog - * started 1 ~key Restart watchdog with key = ~key. - * started X new_key_val Change key to new_key_val. - * - * Note: '~' is the bitwise NOT operator. - * - */ - -/* right now, starting the watchdog is the same as resetting it */ -#define start_watchdog reset_watchdog - -#ifdef CONFIG_ETRAX_WATCHDOG -static int watchdog_key = 0; /* arbitrary number */ -#endif - -/* number of pages to consider "out of memory". it is normal that the memory - * is used though, so put this really low. - */ - -#define WATCHDOG_MIN_FREE_PAGES 8 - -void reset_watchdog(void) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - /* only keep watchdog happy as long as we have memory left! */ - if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { - /* reset the watchdog with the inverse of the old key */ - watchdog_key ^= 0x7; /* invert key, which is 3 bits */ - *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | - IO_STATE(R_WATCHDOG, enable, start); - } -#endif -} - -/* stop the watchdog - we still need the correct key */ - -void stop_watchdog(void) -{ -#ifdef CONFIG_ETRAX_WATCHDOG - watchdog_key ^= 0x7; /* invert key, which is 3 bits */ - *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | - IO_STATE(R_WATCHDOG, enable, stop); -#endif -} - - -extern void cris_do_profile(struct pt_regs *regs); - -/* - * timer_interrupt() needs to keep up the real-time clock, - * as well as call the "xtime_update()" routine every clocktick - */ -static inline irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - /* acknowledge the timer irq */ - -#ifdef USE_CASCADE_TIMERS - *R_TIMER_CTRL = - IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | - IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | - IO_STATE( R_TIMER_CTRL, i1, clr) | - IO_STATE( R_TIMER_CTRL, tm1, run) | - IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | - IO_STATE( R_TIMER_CTRL, i0, clr) | - IO_STATE( R_TIMER_CTRL, tm0, run) | - IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); -#else - *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr); -#endif - - /* reset watchdog otherwise it resets us! */ - reset_watchdog(); - - /* Update statistics. */ - update_process_times(user_mode(regs)); - - /* call the real timer interrupt handler */ - xtime_update(1); - - cris_do_profile(regs); /* Save profiling information */ - return IRQ_HANDLED; -} - -/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */ - -static struct irqaction irq2 = { - .handler = timer_interrupt, - .flags = IRQF_SHARED, - .name = "timer", -}; - -void __init time_init(void) -{ - arch_gettimeoffset = cris_v10_gettimeoffset; - - /* probe for the RTC and read it if it exists - * Before the RTC can be probed the loops_per_usec variable needs - * to be initialized to make usleep work. A better value for - * loops_per_usec is calculated by the kernel later once the - * clock has started. - */ - loops_per_usec = 50; - - /* Setup the etrax timers - * Base frequency is 25000 hz, divider 250 -> 100 HZ - * In normal mode, we use timer0, so timer1 is free. In cascade - * mode (which we sometimes use for debugging) both timers are used. - * Remember that linux/timex.h contains #defines that rely on the - * timer settings below (hz and divide factor) !!! - */ - -#ifdef USE_CASCADE_TIMERS - *R_TIMER_CTRL = - IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | - IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | - IO_STATE( R_TIMER_CTRL, i1, nop) | - IO_STATE( R_TIMER_CTRL, tm1, stop_ld) | - IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | - IO_STATE( R_TIMER_CTRL, i0, nop) | - IO_STATE( R_TIMER_CTRL, tm0, stop_ld) | - IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); - - *R_TIMER_CTRL = r_timer_ctrl_shadow = - IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | - IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | - IO_STATE( R_TIMER_CTRL, i1, nop) | - IO_STATE( R_TIMER_CTRL, tm1, run) | - IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | - IO_STATE( R_TIMER_CTRL, i0, nop) | - IO_STATE( R_TIMER_CTRL, tm0, run) | - IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); -#else - *R_TIMER_CTRL = - IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | - IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | - IO_STATE(R_TIMER_CTRL, i1, nop) | - IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | - IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | - IO_STATE(R_TIMER_CTRL, i0, nop) | - IO_STATE(R_TIMER_CTRL, tm0, stop_ld) | - IO_STATE(R_TIMER_CTRL, clksel0, flexible); - - *R_TIMER_CTRL = r_timer_ctrl_shadow = - IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | - IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | - IO_STATE(R_TIMER_CTRL, i1, nop) | - IO_STATE(R_TIMER_CTRL, tm1, run) | - IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | - IO_STATE(R_TIMER_CTRL, i0, nop) | - IO_STATE(R_TIMER_CTRL, tm0, run) | - IO_STATE(R_TIMER_CTRL, clksel0, flexible); - - *R_TIMER_PRESCALE = PRESCALE_VALUE; -#endif - - /* unmask the timer irq */ - *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set); - - /* now actually register the irq handler that calls timer_interrupt() */ - setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */ - - /* enable watchdog if we should use one */ -#if defined(CONFIG_ETRAX_WATCHDOG) - printk("Enabling watchdog...\n"); - start_watchdog(); - - /* If we use the hardware watchdog, we want to trap it as an NMI - and dump registers before it resets us. For this to happen, we - must set the "m" NMI enable flag (which once set, is unset only - when an NMI is taken). - - The same goes for the external NMI, but that doesn't have any - driver or infrastructure support yet. */ - asm ("setf m"); - - *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set); - *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set); -#endif -} diff --git a/arch/cris/arch-v10/kernel/traps.c b/arch/cris/arch-v10/kernel/traps.c deleted file mode 100644 index 876d45b957f4..000000000000 --- a/arch/cris/arch-v10/kernel/traps.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Helper functions for trap handlers - * - * Copyright (C) 2000-2007, Axis Communications AB. - * - * Authors: Bjorn Wesen - * Hans-Peter Nilsson - * - */ - -#include -#include -#include - -#include -#include - -void -show_registers(struct pt_regs *regs) -{ - /* - * It's possible to use either the USP register or current->thread.usp. - * USP might not correspond to the current process for all cases this - * function is called, and current->thread.usp isn't up to date for the - * current process. Experience shows that using USP is the way to go. - */ - unsigned long usp = rdusp(); - - printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n", - regs->irp, regs->srp, regs->dccr, usp, regs->mof); - - printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", - regs->r0, regs->r1, regs->r2, regs->r3); - - printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", - regs->r4, regs->r5, regs->r6, regs->r7); - - printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", - regs->r8, regs->r9, regs->r10, regs->r11); - - printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n", - regs->r12, regs->r13, regs->orig_r10, (long unsigned)regs); - - printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE); - - printk("Process %s (pid: %d, stackpage=%08lx)\n", - current->comm, current->pid, (unsigned long)current); - - /* - * When in-kernel, we also print out the stack and code at the - * time of the fault.. - */ - if (!user_mode(regs)) { - int i; - - show_stack(NULL, (unsigned long *)usp); - - /* - * If the previous stack-dump wasn't a kernel one, dump the - * kernel stack now. - */ - if (usp != 0) - show_stack(NULL, NULL); - - printk("\nCode: "); - - if (regs->irp < PAGE_OFFSET) - goto bad_value; - - /* - * Quite often the value at regs->irp doesn't point to the - * interesting instruction, which often is the previous - * instruction. So dump at an offset large enough that the - * instruction decoding should be in sync at the interesting - * point, but small enough to fit on a row. The regs->irp - * location is pointed out in a ksymoops-friendly way by - * wrapping the byte for that address in parenthesises. - */ - for (i = -12; i < 12; i++) { - unsigned char c; - - if (__get_user(c, &((unsigned char *)regs->irp)[i])) { -bad_value: - printk(" Bad IP value."); - break; - } - - if (i == 0) - printk("(%02x) ", c); - else - printk("%02x ", c); - } - printk("\n"); - } -} - -void -arch_enable_nmi(void) -{ - asm volatile ("setf m"); -} - -extern void (*nmi_handler)(struct pt_regs *); -void handle_nmi(struct pt_regs *regs) -{ - if (nmi_handler) - nmi_handler(regs); - - /* Wait until nmi is no longer active. (We enable NMI immediately after - returning from this function, and we don't want it happening while - exiting from the NMI interrupt handler.) */ - while (*R_IRQ_MASK0_RD & IO_STATE(R_IRQ_MASK0_RD, nmi_pin, active)) - ; -} - -#ifdef CONFIG_DEBUG_BUGVERBOSE -void -handle_BUG(struct pt_regs *regs) -{ - struct bug_frame f; - unsigned char c; - unsigned long irp = regs->irp; - - if (__copy_from_user(&f, (const void __user *)(irp - 8), sizeof f)) - return; - if (f.prefix != BUG_PREFIX || f.magic != BUG_MAGIC) - return; - if (__get_user(c, f.filename)) - f.filename = ""; - - printk("kernel BUG at %s:%d!\n", f.filename, f.line); -} -#endif diff --git a/arch/cris/arch-v10/lib/Makefile b/arch/cris/arch-v10/lib/Makefile deleted file mode 100644 index 725153edb764..000000000000 --- a/arch/cris/arch-v10/lib/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for Etrax-specific library files.. -# - -lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o - diff --git a/arch/cris/arch-v10/lib/checksum.S b/arch/cris/arch-v10/lib/checksum.S deleted file mode 100644 index a3b96391706f..000000000000 --- a/arch/cris/arch-v10/lib/checksum.S +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * A fast checksum routine using movem - * Copyright (c) 1998-2001 Axis Communications AB - * - * csum_partial(const unsigned char * buff, int len, unsigned int sum) - */ - - .globl csum_partial -csum_partial: - - ;; r10 - src - ;; r11 - length - ;; r12 - checksum - - ;; check for breakeven length between movem and normal word looping versions - ;; we also do _NOT_ want to compute a checksum over more than the - ;; actual length when length < 40 - - cmpu.w 80,$r11 - blo _word_loop - nop - - ;; need to save the registers we use below in the movem loop - ;; this overhead is why we have a check above for breakeven length - ;; only r0 - r8 have to be saved, the other ones are clobber-able - ;; according to the ABI - - subq 9*4,$sp - movem $r8,[$sp] - - ;; do a movem checksum - - subq 10*4,$r11 ; update length for the first loop - -_mloop: movem [$r10+],$r9 ; read 10 longwords - - ;; perform dword checksumming on the 10 longwords - - add.d $r0,$r12 - ax - add.d $r1,$r12 - ax - add.d $r2,$r12 - ax - add.d $r3,$r12 - ax - add.d $r4,$r12 - ax - add.d $r5,$r12 - ax - add.d $r6,$r12 - ax - add.d $r7,$r12 - ax - add.d $r8,$r12 - ax - add.d $r9,$r12 - - ;; fold the carry into the checksum, to avoid having to loop the carry - ;; back into the top - - ax - addq 0,$r12 - - subq 10*4,$r11 - bge _mloop - nop - - addq 10*4,$r11 ; compensate for last loop underflowing length - - movem [$sp+],$r8 ; restore regs - -_word_loop: - ;; only fold if there is anything to fold. - - cmpq 0,$r12 - beq _no_fold - - ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below. - ;; r9 and r13 can be used as temporaries. - - moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9 - lsrq 16,$r9 - - move.d $r12,$r13 - lsrq 16,$r13 ; r13 = checksum >> 16 - and.d $r9,$r12 ; checksum = checksum & 0xffff - add.d $r13,$r12 ; checksum += r13 - -_no_fold: - cmpq 2,$r11 - blt _no_words - nop - - ;; checksum the rest of the words - - subq 2,$r11 - -_wloop: subq 2,$r11 - bge _wloop - addu.w [$r10+],$r12 - - addq 2,$r11 - -_no_words: - ;; see if we have one odd byte more - cmpq 1,$r11 - beq _do_byte - nop - ret - move.d $r12, $r10 - -_do_byte: - ;; copy and checksum the last byte - addu.b [$r10],$r12 - ret - move.d $r12, $r10 - diff --git a/arch/cris/arch-v10/lib/checksumcopy.S b/arch/cris/arch-v10/lib/checksumcopy.S deleted file mode 100644 index b21449cb1ad3..000000000000 --- a/arch/cris/arch-v10/lib/checksumcopy.S +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * A fast checksum+copy routine using movem - * Copyright (c) 1998, 2001 Axis Communications AB - * - * Authors: Bjorn Wesen - * - * csum_partial_copy_nocheck(const char *src, char *dst, - * int len, unsigned int sum) - */ - - .globl csum_partial_copy_nocheck -csum_partial_copy_nocheck: - - ;; r10 - src - ;; r11 - dst - ;; r12 - length - ;; r13 - checksum - - ;; check for breakeven length between movem and normal word looping versions - ;; we also do _NOT_ want to compute a checksum over more than the - ;; actual length when length < 40 - - cmpu.w 80, $r12 - blo _word_loop - nop - - ;; need to save the registers we use below in the movem loop - ;; this overhead is why we have a check above for breakeven length - ;; only r0 - r8 have to be saved, the other ones are clobber-able - ;; according to the ABI - - subq 9*4, $sp - movem $r8, [$sp] - - ;; do a movem copy and checksum - - subq 10*4, $r12 ; update length for the first loop - -_mloop: movem [$r10+],$r9 ; read 10 longwords -1: ;; A failing userspace access will have this as PC. - movem $r9,[$r11+] ; write 10 longwords - - ;; perform dword checksumming on the 10 longwords - - add.d $r0,$r13 - ax - add.d $r1,$r13 - ax - add.d $r2,$r13 - ax - add.d $r3,$r13 - ax - add.d $r4,$r13 - ax - add.d $r5,$r13 - ax - add.d $r6,$r13 - ax - add.d $r7,$r13 - ax - add.d $r8,$r13 - ax - add.d $r9,$r13 - - ;; fold the carry into the checksum, to avoid having to loop the carry - ;; back into the top - - ax - addq 0,$r13 - - subq 10*4,$r12 - bge _mloop - nop - - addq 10*4,$r12 ; compensate for last loop underflowing length - - movem [$sp+],$r8 ; restore regs - -_word_loop: - ;; only fold if there is anything to fold. - - cmpq 0,$r13 - beq _no_fold - - ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below - ;; r9 can be used as temporary. - - move.d $r13,$r9 - lsrq 16,$r9 ; r0 = checksum >> 16 - and.d 0xffff,$r13 ; checksum = checksum & 0xffff - add.d $r9,$r13 ; checksum += r0 - -_no_fold: - cmpq 2,$r12 - blt _no_words - nop - - ;; copy and checksum the rest of the words - - subq 2,$r12 - -_wloop: move.w [$r10+],$r9 -2: ;; A failing userspace access will have this as PC. - addu.w $r9,$r13 - subq 2,$r12 - bge _wloop - move.w $r9,[$r11+] - - addq 2,$r12 - -_no_words: - ;; see if we have one odd byte more - cmpq 1,$r12 - beq _do_byte - nop - ret - move.d $r13, $r10 - -_do_byte: - ;; copy and checksum the last byte - move.b [$r10],$r9 -3: ;; A failing userspace access will have this as PC. - addu.b $r9,$r13 - move.b $r9,[$r11] - ret - move.d $r13, $r10 diff --git a/arch/cris/arch-v10/lib/csumcpfruser.S b/arch/cris/arch-v10/lib/csumcpfruser.S deleted file mode 100644 index beb8992ed478..000000000000 --- a/arch/cris/arch-v10/lib/csumcpfruser.S +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into - * csum_partial_copy_from_user by adding exception records. - * - * Copyright (C) 2001 Axis Communications AB. - * - * Author: Hans-Peter Nilsson. - */ - -#include - -/* Same function body, but a different name. If we just added exception - records to _csum_partial_copy_nocheck and made it generic, we wouldn't - know a user fault from a kernel fault and we would have overhead in - each kernel caller for the error-pointer argument. - - unsigned int csum_partial_copy_from_user - (const char *src, char *dst, int len, unsigned int sum, int *errptr); - - Note that the errptr argument is only set if we encounter an error. - It is conveniently located on the stack, so the normal function body - does not have to handle it. */ - -#define csum_partial_copy_nocheck csum_partial_copy_from_user - -/* There are local labels numbered 1, 2 and 3 present to mark the - different from-user accesses. */ -#include "checksumcopy.S" - - .section .fixup,"ax" - -;; Here from the movem loop; restore stack. -4: - movem [$sp+],$r8 -;; r12 is already decremented. Add back chunk_size-2. - addq 40-2,$r12 - -;; Here from the word loop; r12 is off by 2; add it back. -5: - addq 2,$r12 - -;; Here from a failing single byte. -6: - -;; Signal in *errptr that we had a failing access. - moveq -EFAULT,$r9 - move.d $r9,[[$sp]] - -;; Clear the rest of the destination area using memset. Preserve the -;; checksum for the readable bytes. - push $srp - push $r13 - move.d $r11,$r10 - clear.d $r11 - jsr memset - pop $r10 - jump [$sp+] - - .previous - .section __ex_table,"a" - .dword 1b,4b - .dword 2b,5b - .dword 3b,6b - .previous diff --git a/arch/cris/arch-v10/lib/dram_init.S b/arch/cris/arch-v10/lib/dram_init.S deleted file mode 100644 index fd7437577938..000000000000 --- a/arch/cris/arch-v10/lib/dram_init.S +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * DRAM/SDRAM initialization - alter with care - * This file is intended to be included from other assembler files - * - * Note: This file may not modify r9 because r9 is used to carry - * information from the decompressor to the kernel - * - * Copyright (C) 2000-2012 Axis Communications AB - * - */ - -/* Just to be certain the config file is included, we include it here - * explicitly instead of depending on it being included in the file that - * uses this code. - */ - - - ;; WARNING! The registers r8 and r9 are used as parameters carrying - ;; information from the decompressor (if the kernel was compressed). - ;; They should not be used in the code below. - - move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0 - move.d $r0, [R_WAITSTATES] - - move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0 - move.d $r0, [R_BUS_CONFIG] - -#ifndef CONFIG_ETRAX_SDRAM - move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0 - move.d $r0, [R_DRAM_CONFIG] - - move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0 - move.d $r0, [R_DRAM_TIMING] -#else - ;; Samsung SDRAMs seem to require to be initialized twice to work properly. - moveq 2, $r6 -_sdram_init: - - ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization - - ; Bank configuration - move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0 - move.d $r0, [R_SDRAM_CONFIG] - - ; Calculate value of mrs_data - ; CAS latency = 2 && bus_width = 32 => 0x40 - ; CAS latency = 3 && bus_width = 32 => 0x60 - ; CAS latency = 2 && bus_width = 16 => 0x20 - ; CAS latency = 3 && bus_width = 16 => 0x30 - - ; Check if value is already supplied in kernel config - move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2 - and.d 0x00ff0000, $r2 - bne _set_timing - lsrq 16, $r2 - - move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2 - move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 - move.d $r1, $r3 - and.d 0x03, $r1 ; Get CAS latency - and.d 0x1000, $r3 ; 50 or 100 MHz? - beq _speed_50 - nop -_speed_100: - cmp.d 0x00, $r1 ; CAS latency = 2? - beq _bw_check - nop - or.d 0x20, $r2 ; CAS latency = 3 - ba _bw_check - nop -_speed_50: - cmp.d 0x01, $r1 ; CAS latency = 2? - beq _bw_check - nop - or.d 0x20, $r2 ; CAS latency = 3 -_bw_check: - move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1 - and.d 0x800000, $r1 ; DRAM width is bit 23 - bne _set_timing - nop - lsrq 1, $r2 ; 16 bits. Shift down value. - - ; Set timing parameters. Starts master clock -_set_timing: - move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1 - and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0 - or.d 0x80000000, $r1 ; Make sure sdram enable bit is set - move.d $r1, $r5 - or.d 0x0000c000, $r1 ; ref = disable - lslq 16, $r2 ; mrs data starts at bit 16 - or.d $r2, $r1 - move.d $r1, [R_SDRAM_TIMING] - - ; Wait 200us - move.d 10000, $r2 -1: bne 1b - subq 1, $r2 - - ; Issue initialization command sequence - move.d _sdram_commands_start, $r2 - and.d 0x000fffff, $r2 ; Make sure commands are read from flash - move.d _sdram_commands_end, $r3 - and.d 0x000fffff, $r3 -1: clear.d $r4 - move.b [$r2+], $r4 - lslq 9, $r4 ; Command starts at bit 9 - or.d $r1, $r4 - move.d $r4, [R_SDRAM_TIMING] - nop ; Wait five nop cycles between each command - nop - nop - nop - nop - cmp.d $r2, $r3 - bne 1b - nop - move.d $r5, [R_SDRAM_TIMING] - subq 1, $r6 - bne _sdram_init - nop - ba _sdram_commands_end - nop - -_sdram_commands_start: - .byte 3 ; Precharge - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 2 ; refresh - .byte 0 ; nop - .byte 1 ; mrs - .byte 0 ; nop -_sdram_commands_end: -#endif diff --git a/arch/cris/arch-v10/lib/hw_settings.S b/arch/cris/arch-v10/lib/hw_settings.S deleted file mode 100644 index 0d449852517e..000000000000 --- a/arch/cris/arch-v10/lib/hw_settings.S +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This table is used by some tools to extract hardware parameters. - * The table should be included in the kernel and the decompressor. - * Don't forget to update the tools if you change this table. - * - * Copyright (C) 2001 Axis Communications AB - * - * Authors: Mikael Starvik (starvik@axis.com) - */ - -#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \ - (CONFIG_ETRAX_DEF_R_PORT_PA_DATA)) -#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \ - (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \ - (CONFIG_ETRAX_DEF_R_PORT_PB_DATA)) - - .ascii "HW_PARAM_MAGIC" ; Magic number - .dword 0xc0004000 ; Kernel start address - - ; Debug port -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - .dword 0 -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) - .dword 1 -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) - .dword 2 -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) - .dword 3 -#else - .dword 4 ; No debug -#endif - - ; SDRAM or EDO DRAM? -#ifdef CONFIG_ETRAX_SDRAM - .dword 1 -#else - .dword 0 -#endif - - ; Register values - .dword R_WAITSTATES - .dword CONFIG_ETRAX_DEF_R_WAITSTATES - .dword R_BUS_CONFIG - .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG -#ifdef CONFIG_ETRAX_SDRAM - .dword R_SDRAM_CONFIG - .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG - .dword R_SDRAM_TIMING - .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING -#else - .dword R_DRAM_CONFIG - .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG - .dword R_DRAM_TIMING - .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING -#endif - .dword R_PORT_PA_SET - .dword PA_SET_VALUE - .dword R_PORT_PB_SET - .dword PB_SET_VALUE - .dword 0 ; No more register values diff --git a/arch/cris/arch-v10/lib/memset.c b/arch/cris/arch-v10/lib/memset.c deleted file mode 100644 index c94ea9b3ec29..000000000000 --- a/arch/cris/arch-v10/lib/memset.c +++ /dev/null @@ -1,259 +0,0 @@ -/* A memset for CRIS. - Copyright (C) 1999-2005 Axis Communications. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - 2. Neither the name of Axis Communications nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS - ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS - COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* FIXME: This file should really only be used for reference, as the - result is somewhat depending on gcc generating what we expect rather - than what we describe. An assembly file should be used instead. */ - -/* Note the multiple occurrence of the expression "12*4", including the - asm. It is hard to get it into the asm in a good way. Thus better to - expose the problem everywhere: no macro. */ - -/* Assuming one cycle per dword written or read (ok, not really true; the - world is not ideal), and one cycle per instruction, then 43+3*(n/48-1) - <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full - 48-byte block to set. */ - -#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48) - -/* No name ambiguities in this file. */ -__asm__ (".syntax no_register_prefix"); - -void *memset(void *pdst, int c, unsigned int plen) -{ - /* Now we want the parameters in special registers. Make sure the - compiler does something usable with this. */ - - register char *return_dst __asm__ ("r10") = pdst; - register int n __asm__ ("r12") = plen; - register int lc __asm__ ("r11") = c; - - /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get - penalized here compared to the generic implementation. */ - - /* This is fragile performancewise at best. Check with newer GCC - releases, if they compile cascaded "x |= x << 8" to sane code. */ - __asm__("movu.b %0,r13 \n\ - lslq 8,r13 \n\ - move.b %0,r13 \n\ - move.d r13,%0 \n\ - lslq 16,r13 \n\ - or.d r13,%0" - : "=r" (lc) /* Inputs. */ - : "0" (lc) /* Outputs. */ - : "r13"); /* Trash. */ - - { - register char *dst __asm__ ("r13") = pdst; - - if (((unsigned long) pdst & 3) != 0 - /* Oops! n = 0 must be a valid call, regardless of alignment. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - *dst = (char) lc; - n--; - dst++; - } - - if ((unsigned long) dst & 2) - { - *(short *) dst = lc; - n -= 2; - dst += 2; - } - } - - /* Decide which setting method to use. */ - if (n >= MEMSET_BY_BLOCK_THRESHOLD) - { - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-block sizes - suboptimal. */ - __asm__ volatile - ("\ - ;; GCC does promise correct register allocations, but let's \n\ - ;; make sure it keeps its promises. \n\ - .ifnc %0-%1-%4,$r13-$r12-$r11 \n\ - .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ - .endif \n\ - \n\ - ;; Save the registers we'll clobber in the movem process \n\ - ;; on the stack. Don't mention them to gcc, it will only be \n\ - ;; upset. \n\ - subq 11*4,sp \n\ - movem r10,[sp] \n\ - \n\ - move.d r11,r0 \n\ - move.d r11,r1 \n\ - move.d r11,r2 \n\ - move.d r11,r3 \n\ - move.d r11,r4 \n\ - move.d r11,r5 \n\ - move.d r11,r6 \n\ - move.d r11,r7 \n\ - move.d r11,r8 \n\ - move.d r11,r9 \n\ - move.d r11,r10 \n\ - \n\ - ;; Now we've got this: \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 12*4,r12 \n\ -0: \n\ -" -#ifdef __arch_common_v10_v32 - /* Cater to branch offset difference between v32 and v10. We - assume the branch below has an 8-bit offset. */ -" setf\n" -#endif -" subq 12*4,r12 \n\ - bge 0b \n\ - movem r11,[r13+] \n\ - \n\ - ;; Compensate for last loop underflowing n. \n\ - addq 12*4,r12 \n\ - \n\ - ;; Restore registers from stack. \n\ - movem [sp+],r10" - - /* Outputs. */ - : "=r" (dst), "=r" (n) - - /* Inputs. */ - : "0" (dst), "1" (n), "r" (lc)); - } - - /* An ad-hoc unroll, used for 4*12-1..16 bytes. */ - while (n >= 16) - { - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - n -= 16; - } - - switch (n) - { - case 0: - break; - - case 1: - *dst = (char) lc; - break; - - case 2: - *(short *) dst = (short) lc; - break; - - case 3: - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - - case 4: - *(long *) dst = lc; - break; - - case 5: - *(long *) dst = lc; dst += 4; - *dst = (char) lc; - break; - - case 6: - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; - break; - - case 7: - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - - case 8: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; - break; - - case 9: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *dst = (char) lc; - break; - - case 10: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; - break; - - case 11: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - - case 12: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; - break; - - case 13: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *dst = (char) lc; - break; - - case 14: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; - break; - - case 15: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - } - } - - return return_dst; -} diff --git a/arch/cris/arch-v10/lib/string.c b/arch/cris/arch-v10/lib/string.c deleted file mode 100644 index c7bd6ebdc93c..000000000000 --- a/arch/cris/arch-v10/lib/string.c +++ /dev/null @@ -1,236 +0,0 @@ -/* A memcpy for CRIS. - Copyright (C) 1994-2005 Axis Communications. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - 2. Neither the name of Axis Communications nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS - ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS - COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* FIXME: This file should really only be used for reference, as the - result is somewhat depending on gcc generating what we expect rather - than what we describe. An assembly file should be used instead. */ - -#include - -/* Break even between movem and move16 is really at 38.7 * 2, but - modulo 44, so up to the next multiple of 44, we use ordinary code. */ -#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2) - -/* No name ambiguities in this file. */ -__asm__ (".syntax no_register_prefix"); - -void * -memcpy(void *pdst, const void *psrc, size_t pn) -{ - /* Now we want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - If gcc was allright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register void *return_dst __asm__ ("r10") = pdst; - register unsigned char *dst __asm__ ("r13") = pdst; - register unsigned const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - - /* When src is aligned but not dst, this makes a few extra needless - cycles. I believe it would take as many to check that the - re-alignment was unnecessary. */ - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes; so we - don't have to check further for overflows. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - n--; - *dst = *src; - src++; - dst++; - } - - if ((unsigned long) dst & 2) - { - n -= 2; - *(short *) dst = *(short *) src; - src += 2; - dst += 2; - } - } - - /* Decide which copying method to use. */ - if (n >= MEMCPY_BY_BLOCK_THRESHOLD) - { - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile - ("\ - ;; GCC does promise correct register allocations, but let's \n\ - ;; make sure it keeps its promises. \n\ - .ifnc %0-%1-%2,$r13-$r11-$r12 \n\ - .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,sp \n\ - movem r10,[sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop. \n\ - subq 44,r12 \n\ -0: \n\ -" -#ifdef __arch_common_v10_v32 - /* Cater to branch offset difference between v32 and v10. We - assume the branch below has an 8-bit offset. */ -" setf\n" -#endif -" movem [r11+],r10 \n\ - subq 44,r12 \n\ - bge 0b \n\ - movem r10,[r13+] \n\ - \n\ - ;; Compensate for last loop underflowing n. \n\ - addq 44,r12 \n\ - \n\ - ;; Restore registers from stack. \n\ - movem [sp+],r10" - - /* Outputs. */ - : "=r" (dst), "=r" (src), "=r" (n) - - /* Inputs. */ - : "0" (dst), "1" (src), "2" (n)); - } - - while (n >= 16) - { - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - - n -= 16; - } - - switch (n) - { - case 0: - break; - - case 1: - *dst = *src; - break; - - case 2: - *(short *) dst = *(short *) src; - break; - - case 3: - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - - case 4: - *(long *) dst = *(long *) src; - break; - - case 5: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *dst = *src; - break; - - case 6: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; - break; - - case 7: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - - case 8: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; - break; - - case 9: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *dst = *src; - break; - - case 10: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; - break; - - case 11: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - - case 12: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; - break; - - case 13: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *dst = *src; - break; - - case 14: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; - break; - - case 15: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - } - - return return_dst; -} diff --git a/arch/cris/arch-v10/lib/usercopy.c b/arch/cris/arch-v10/lib/usercopy.c deleted file mode 100644 index 3f1e2f4680f7..000000000000 --- a/arch/cris/arch-v10/lib/usercopy.c +++ /dev/null @@ -1,511 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * User address space access functions. - * The non-inlined parts of asm-cris/uaccess.h are here. - * - * Copyright (C) 2000, Axis Communications AB. - * - * Written by Hans-Peter Nilsson. - * Pieces used from memcpy, originally by Kenny Ranerup long time ago. - */ - -#include - -/* Asm:s have been tweaked (within the domain of correctness) to give - satisfactory results for "gcc version 2.96 20000427 (experimental)". - - Check regularly... - - Note that the PC saved at a bus-fault is the address *after* the - faulting instruction, which means the branch-target for instructions in - delay-slots for taken branches. Note also that the postincrement in - the instruction is performed regardless of bus-fault; the register is - seen updated in fault handlers. - - Oh, and on the code formatting issue, to whomever feels like "fixing - it" to Conformity: I'm too "lazy", but why don't you go ahead and "fix" - string.c too. I just don't think too many people will hack this file - for the code format to be an issue. */ - - -/* Copy to userspace. This is based on the memcpy used for - kernel-to-kernel copying; see "string.c". */ - -unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was alright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - - /* When src is aligned but not dst, this makes a few extra needless - cycles. I believe it would take as many to check that the - re-alignment was unnecessary. */ - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes; so we - don't have to check further for overflows. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - __asm_copy_to_user_1 (dst, src, retn); - n--; - } - - if ((unsigned long) dst & 2) - { - __asm_copy_to_user_2 (dst, src, retn); - n -= 2; - } - } - - /* Decide which copying method to use. */ - if (n >= 44*2) /* Break even between movem and - move16 is at 38.7*2, but modulo 44. */ - { - /* For large copies we use 'movem'. */ - - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. - - This method is not foolproof; it assumes that the "asm reg" - declarations at the beginning of the function really are used - here (beware: they may be moved to temporary registers). - This way, we do not have to save/move the registers around into - temporaries; we can safely use them straight away. - - If you want to check that the allocation was right; then - check the equalities in the first comment. It should say - "r13=r13, r11=r11, r12=r12". */ - __asm__ volatile ("\ - .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ - \n\ -; Since the noted PC of a faulting instruction in a delay-slot of a taken \n\ -; branch, is that of the branch target, we actually point at the from-movem \n\ -; for this case. There is no ambiguity here; if there was a fault in that \n\ -; instruction (meaning a kernel oops), the faulted PC would be the address \n\ -; after *that* movem. \n\ - \n\ -0: \n\ - movem [$r11+],$r10 \n\ - subq 44,$r12 \n\ - bge 0b \n\ - movem $r10,[$r13+] \n\ -1: \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -2: \n\ - .section .fixup,\"ax\" \n\ - \n\ -; To provide a correct count in r10 of bytes that failed to be copied, \n\ -; we jump back into the loop if the loop-branch was taken. There is no \n\ -; performance penalty for sany use; the program will segfault soon enough.\n\ - \n\ -3: \n\ - move.d [$sp],$r10 \n\ - addq 44,$r10 \n\ - move.d $r10,[$sp] \n\ - jump 0b \n\ -4: \n\ - movem [$sp+],$r10 \n\ - addq 44,$r10 \n\ - addq 44,$r12 \n\ - jump 2b \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 0b,3b \n\ - .dword 1b,4b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); - - } - - /* Either we directly start copying, using dword copying in a loop, or - we copy as much as possible with 'movem' and then the last block (<44 - bytes) is copied here. This will work since 'movem' will have - updated SRC, DST and N. */ - - while (n >= 16) - { - __asm_copy_to_user_16 (dst, src, retn); - n -= 16; - } - - /* Having a separate by-four loops cuts down on cache footprint. - FIXME: Test with and without; increasing switch to be 0..15. */ - while (n >= 4) - { - __asm_copy_to_user_4 (dst, src, retn); - n -= 4; - } - - switch (n) - { - case 0: - break; - case 1: - __asm_copy_to_user_1 (dst, src, retn); - break; - case 2: - __asm_copy_to_user_2 (dst, src, retn); - break; - case 3: - __asm_copy_to_user_3 (dst, src, retn); - break; - } - - return retn; -} -EXPORT_SYMBOL(__copy_user); - -/* Copy from user to kernel. The return-value is the number of bytes that were - inaccessible. */ - -unsigned long __copy_user_in(void *pdst, const void __user *psrc, - unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was alright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - /* The best reason to align src is that we then know that a read-fault - was for aligned bytes; there's no 1..3 remaining good bytes to - pickle. */ - if (((unsigned long) src & 3) != 0) - { - if (((unsigned long) src & 1) && n != 0) - { - __asm_copy_from_user_1 (dst, src, retn); - n--; - if (retn) - goto exception; - } - - if (((unsigned long) src & 2) && n >= 2) - { - __asm_copy_from_user_2 (dst, src, retn); - n -= 2; - if (retn) - goto exception; - } - } - - /* Decide which copying method to use. */ - if (n >= 44*2) /* Break even between movem and - move16 is at 38.7*2, but modulo 44. - FIXME: We use move4 now. */ - { - /* For large copies we use 'movem' */ - - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. - - This method is not foolproof; it assumes that the "asm reg" - declarations at the beginning of the function really are used - here (beware: they may be moved to temporary registers). - This way, we do not have to save/move the registers around into - temporaries; we can safely use them straight away. - - If you want to check that the allocation was right; then - check the equalities in the first comment. It should say - "r13=r13, r11=r11, r12=r12" */ - __asm__ volatile ("\n\ - .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ -0: \n\ - movem [$r11+],$r10 \n\ -1: \n\ - subq 44,$r12 \n\ - bge 0b \n\ - movem $r10,[$r13+] \n\ - \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -4: \n\ - .section .fixup,\"ax\" \n\ - \n\ -;; Do not jump back into the loop if we fail. For some uses, we get a \n\ -;; page fault somewhere on the line. Without checking for page limits, \n\ -;; we don't know where, but we need to copy accurately and keep an \n\ -;; accurate count; not just clear the whole line. To do that, we fall \n\ -;; down in the code below, proceeding with smaller amounts. It should \n\ -;; be kept in mind that we have to cater to code like what at one time \n\ -;; was in fs/super.c: \n\ -;; i = size - copy_from_user((void *)page, data, size); \n\ -;; which would cause repeated faults while clearing the remainder of \n\ -;; the SIZE bytes at PAGE after the first fault. \n\ -;; A caveat here is that we must not fall through from a failing page \n\ -;; to a valid page. \n\ - \n\ -3: \n\ - movem [$sp+],$r10 \n\ - addq 44,$r12 ;; Get back count before faulting point. \n\ - subq 44,$r11 ;; Get back pointer to faulting movem-line. \n\ - jump 4b ;; Fall through, pretending the fault didn't happen.\n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 1b,3b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); - - } - - /* Either we directly start copying here, using dword copying in a loop, - or we copy as much as possible with 'movem' and then the last block - (<44 bytes) is copied here. This will work since 'movem' will have - updated src, dst and n. (Except with failing src.) - - Since we want to keep src accurate, we can't use - __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and - retn, but not src (by design; it's value is ignored elsewhere). */ - - while (n >= 4) - { - __asm_copy_from_user_4 (dst, src, retn); - n -= 4; - - if (retn) - goto exception; - } - - /* If we get here, there were no memory read faults. */ - switch (n) - { - /* These copies are at least "naturally aligned" (so we don't have - to check each byte), due to the src alignment code before the - movem loop. The *_3 case *will* get the correct count for retn. */ - case 0: - /* This case deliberately left in (if you have doubts check the - generated assembly code). */ - break; - case 1: - __asm_copy_from_user_1 (dst, src, retn); - break; - case 2: - __asm_copy_from_user_2 (dst, src, retn); - break; - case 3: - __asm_copy_from_user_3 (dst, src, retn); - break; - } - - /* If we get here, retn correctly reflects the number of failing - bytes. */ - return retn; - -exception: - return retn + n; -} -EXPORT_SYMBOL(__copy_user_in); - -/* Zero userspace. */ -unsigned long __do_clear_user(void __user *pto, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was alright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pto; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - __asm_clear_1 (dst, retn); - n--; - } - - if ((unsigned long) dst & 2) - { - __asm_clear_2 (dst, retn); - n -= 2; - } - } - - /* Decide which copying method to use. - FIXME: This number is from the "ordinary" kernel memset. */ - if (n >= (1*48)) - { - /* For large clears we use 'movem' */ - - /* It is not optimal to tell the compiler about clobbering any - call-saved registers; that will move the saving/restoring of - those registers to the function prologue/epilogue, and make - non-movem sizes suboptimal. - - This method is not foolproof; it assumes that the "asm reg" - declarations at the beginning of the function really are used - here (beware: they may be moved to temporary registers). - This way, we do not have to save/move the registers around into - temporaries; we can safely use them straight away. - - If you want to check that the allocation was right; then - check the equalities in the first comment. It should say - something like "r13=r13, r11=r11, r12=r12". */ - __asm__ volatile ("\n\ - .ifnc %0%1%2,$r13$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll clobber in the movem process \n\ - ;; on the stack. Don't mention them to gcc, it will only be \n\ - ;; upset. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - clear.d $r0 \n\ - clear.d $r1 \n\ - clear.d $r2 \n\ - clear.d $r3 \n\ - clear.d $r4 \n\ - clear.d $r5 \n\ - clear.d $r6 \n\ - clear.d $r7 \n\ - clear.d $r8 \n\ - clear.d $r9 \n\ - clear.d $r10 \n\ - clear.d $r11 \n\ - \n\ - ;; Now we've got this: \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 12*4,$r12 \n\ -0: \n\ - subq 12*4,$r12 \n\ - bge 0b \n\ - movem $r11,[$r13+] \n\ -1: \n\ - addq 12*4,$r12 ;; compensate for last loop underflowing n\n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -2: \n\ - .section .fixup,\"ax\" \n\ -3: \n\ - move.d [$sp],$r10 \n\ - addq 12*4,$r10 \n\ - move.d $r10,[$sp] \n\ - clear.d $r10 \n\ - jump 0b \n\ - \n\ -4: \n\ - movem [$sp+],$r10 \n\ - addq 12*4,$r10 \n\ - addq 12*4,$r12 \n\ - jump 2b \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 0b,3b \n\ - .dword 1b,4b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (n), "2" (retn) - /* Clobber */ : "r11"); - } - - while (n >= 16) - { - __asm_clear_16 (dst, retn); - n -= 16; - } - - /* Having a separate by-four loops cuts down on cache footprint. - FIXME: Test with and without; increasing switch to be 0..15. */ - while (n >= 4) - { - __asm_clear_4 (dst, retn); - n -= 4; - } - - switch (n) - { - case 0: - break; - case 1: - __asm_clear_1 (dst, retn); - break; - case 2: - __asm_clear_2 (dst, retn); - break; - case 3: - __asm_clear_3 (dst, retn); - break; - } - - return retn; -} -EXPORT_SYMBOL(__do_clear_user); diff --git a/arch/cris/arch-v10/mm/Makefile b/arch/cris/arch-v10/mm/Makefile deleted file mode 100644 index 588b4baee85e..000000000000 --- a/arch/cris/arch-v10/mm/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the linux cris-specific parts of the memory manager. -# - -obj-y := fault.o init.o tlb.o - diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c deleted file mode 100644 index e6c225169642..000000000000 --- a/arch/cris/arch-v10/mm/fault.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/mm/fault.c - * - * Low level bus fault handler - * - * - * Copyright (C) 2000-2007 Axis Communications AB - * - * Authors: Bjorn Wesen - * - */ - -#include -#include -#include -#include -#include - -/* debug of low-level TLB reload */ -#undef DEBUG - -#ifdef DEBUG -#define D(x) x -#else -#define D(x) -#endif - -extern const struct exception_table_entry - *search_exception_tables(unsigned long addr); - -asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs, - int protection, int writeaccess); - -/* fast TLB-fill fault handler - * this is called from entry.S with interrupts disabled - */ - -void -handle_mmu_bus_fault(struct pt_regs *regs) -{ - int cause; - int select; -#ifdef DEBUG - int index; - int page_id; - int acc, inv; -#endif - pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id()); - pmd_t *pmd; - pte_t pte; - int miss, we, writeac; - unsigned long address; - unsigned long flags; - - cause = *R_MMU_CAUSE; - - address = cause & PAGE_MASK; /* get faulting address */ - select = *R_TLB_SELECT; - -#ifdef DEBUG - page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause); - acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause); - inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause); - index = IO_EXTRACT(R_TLB_SELECT, index, select); -#endif - miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause); - we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause); - writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause); - - D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n", - regs->irp, address, miss, inv, we, acc, index, page_id)); - - /* leave it to the MM system fault handler */ - if (miss) - do_page_fault(address, regs, 0, writeac); - else - do_page_fault(address, regs, 1, we); - - /* Reload TLB with new entry to avoid an extra miss exception. - * do_page_fault may have flushed the TLB so we have to restore - * the MMU registers. - */ - local_irq_save(flags); - pmd = (pmd_t *)(pgd + pgd_index(address)); - if (pmd_none(*pmd)) - goto exit; - pte = *pte_offset_kernel(pmd, address); - if (!pte_present(pte)) - goto exit; - *R_TLB_SELECT = select; - *R_TLB_HI = cause; - *R_TLB_LO = pte_val(pte); -exit: - local_irq_restore(flags); -} diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c deleted file mode 100644 index 4da99a0e3b57..000000000000 --- a/arch/cris/arch-v10/mm/init.c +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/arch-v10/mm/init.c - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void tlb_init(void); - -/* - * The kernel is already mapped with a kernel segment at kseg_c so - * we don't need to map it with a page table. However head.S also - * temporarily mapped it at kseg_4 so we should set up the ksegs again, - * clear the TLB and do some other paging setup stuff. - */ - -void __init -paging_init(void) -{ - int i; - unsigned long zones_size[MAX_NR_ZONES]; - - printk("Setting up paging and the MMU.\n"); - - /* clear out the init_mm.pgd that will contain the kernel's mappings */ - - for(i = 0; i < PTRS_PER_PGD; i++) - swapper_pg_dir[i] = __pgd(0); - - /* make sure the current pgd table points to something sane - * (even if it is most probably not used until the next - * switch_mm) - */ - - per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; - - /* initialise the TLB (tlb.c) */ - - tlb_init(); - - /* see README.mm for details on the KSEG setup */ - -#ifdef CONFIG_CRIS_LOW_MAP - /* Etrax-100 LX version 1 has a bug so that we cannot map anything - * across the 0x80000000 boundary, so we need to shrink the user-virtual - * area to 0x50000000 instead of 0xb0000000 and map things slightly - * different. The unused areas are marked as paged so that we can catch - * freak kernel accesses there. - * - * The ARTPEC chip is mapped at 0xa so we pass that segment straight - * through. We cannot vremap it because the vmalloc area is below 0x8 - * and Juliette needs an uncached area above 0x8. - * - * Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards. - * We map them straight over in LOW_MAP, but use vremap in LX version 2. - */ - -#define CACHED_BOOTROM (KSEG_F | 0x08000000UL) - - *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */ - IO_STATE(R_MMU_KSEG, seg_e, page ) | - IO_STATE(R_MMU_KSEG, seg_d, page ) | - IO_STATE(R_MMU_KSEG, seg_c, page ) | - IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ - IO_STATE(R_MMU_KSEG, seg_a, page ) | - IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */ - IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */ - IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */ - IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */ - IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */ - IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */ - IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */ - IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */ - IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */ - IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */ - - *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) | - IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) | - IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) | - IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) ); - - *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) | - IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) ); -#else - /* This code is for the corrected Etrax-100 LX version 2... */ - -#define CACHED_BOOTROM (KSEG_A | 0x08000000UL) - - *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */ - IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */ - IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */ - IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */ - IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ - IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */ - IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */ - IO_STATE(R_MMU_KSEG, seg_8, page ) | - IO_STATE(R_MMU_KSEG, seg_7, page ) | - IO_STATE(R_MMU_KSEG, seg_6, page ) | - IO_STATE(R_MMU_KSEG, seg_5, page ) | - IO_STATE(R_MMU_KSEG, seg_4, page ) | - IO_STATE(R_MMU_KSEG, seg_3, page ) | - IO_STATE(R_MMU_KSEG, seg_2, page ) | - IO_STATE(R_MMU_KSEG, seg_1, page ) | - IO_STATE(R_MMU_KSEG, seg_0, page ) ); - - *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) | - IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) | - IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) | - IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) | - IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) | - IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) ); - - *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) | - IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) ); -#endif - - *R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) ); - - /* The MMU has been enabled ever since head.S but just to make - * it totally obvious we do it here as well. - */ - - *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) | - IO_STATE(R_MMU_CTRL, acc_excp, enable ) | - IO_STATE(R_MMU_CTRL, we_excp, enable ) ); - - *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable); - - /* - * initialize the bad page table and bad page to point - * to a couple of allocated pages - */ - - empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); - memset((void *)empty_zero_page, 0, PAGE_SIZE); - - /* All pages are DMA'able in Etrax, so put all in the DMA'able zone */ - - zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT; - - for (i = 1; i < MAX_NR_ZONES; i++) - zones_size[i] = 0; - - /* Use free_area_init_node instead of free_area_init, because the former - * is designed for systems where the DRAM starts at an address substantially - * higher than 0, like us (we start at PAGE_OFFSET). This saves space in the - * mem_map page array. - */ - - free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); -} - -/* Initialize remaps of some I/O-ports. It is important that this - * is called before any driver is initialized. - */ - -static int -__init init_ioremap(void) -{ - - /* Give the external I/O-port addresses their values */ - -#ifdef CONFIG_CRIS_LOW_MAP - /* Simply a linear map (see the KSEG map above in paging_init) */ - port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START | - MEM_NON_CACHEABLE); - port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START | - MEM_NON_CACHEABLE); - port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START | - MEM_NON_CACHEABLE); -#else - /* Note that nothing blows up just because we do this remapping - * it's ok even if the ports are not used or connected - * to anything (or connected to a non-I/O thing) */ - port_cse1_addr = (volatile unsigned long *) - ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16); - port_csp0_addr = (volatile unsigned long *) - ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16); - port_csp4_addr = (volatile unsigned long *) - ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16); -#endif - return 0; -} - -__initcall(init_ioremap); - -/* Helper function for the two below */ - -static inline void -flush_etrax_cacherange(void *startadr, int length) -{ - /* CACHED_BOOTROM is mapped to the boot-rom area (cached) which - * we can use to get fast dummy-reads of cachelines - */ - - volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) | - CACHED_BOOTROM); - - length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */ - - while(length > 0) { - *flushadr; /* dummy read to flush */ - flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */ - length -= 32; - } -} - -/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers - * will occasionally corrupt certain CPU writes if the DMA buffers - * happen to be hot in the cache. - * - * As a workaround, we have to flush the relevant parts of the cache - * before (re) inserting any receiving descriptor into the DMA HW. - */ - -void -prepare_rx_descriptor(struct etrax_dma_descr *desc) -{ - flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536); -} - -/* Do the same thing but flush the entire cache */ - -void -flush_etrax_cache(void) -{ - flush_etrax_cacherange(0, 8192); -} diff --git a/arch/cris/arch-v10/mm/tlb.c b/arch/cris/arch-v10/mm/tlb.c deleted file mode 100644 index 7f1f752f2445..000000000000 --- a/arch/cris/arch-v10/mm/tlb.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/arch-v10/mm/tlb.c - * - * Low level TLB handling - * - * - * Copyright (C) 2000-2007 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - */ - -#include - -#include -#include -#include - -#define D(x) - -/* The TLB can host up to 64 different mm contexts at the same time. - * The running context is R_MMU_CONTEXT, and each TLB entry contains a - * page_id that has to match to give a hit. In page_id_map, we keep track - * of which mm's we have assigned which page_id's, so that we know when - * to invalidate TLB entries. - * - * The last page_id is never running - it is used as an invalid page_id - * so we can make TLB entries that will never match. - * - * Notice that we need to make the flushes atomic, otherwise an interrupt - * handler that uses vmalloced memory might cause a TLB load in the middle - * of a flush causing. - */ - -/* invalidate all TLB entries */ - -void -flush_tlb_all(void) -{ - int i; - unsigned long flags; - - /* the vpn of i & 0xf is so we dont write similar TLB entries - * in the same 4-way entry group. details... - */ - - local_irq_save(flags); - for(i = 0; i < NUM_TLB_ENTRIES; i++) { - *R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) ); - *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | - IO_FIELD(R_TLB_HI, vpn, i & 0xf ) ); - - *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | - IO_STATE(R_TLB_LO, valid, no ) | - IO_STATE(R_TLB_LO, kernel,no ) | - IO_STATE(R_TLB_LO, we, no ) | - IO_FIELD(R_TLB_LO, pfn, 0 ) ); - } - local_irq_restore(flags); - D(printk("tlb: flushed all\n")); -} - -/* invalidate the selected mm context only */ - -void -flush_tlb_mm(struct mm_struct *mm) -{ - int i; - int page_id = mm->context.page_id; - unsigned long flags; - - D(printk("tlb: flush mm context %d (%p)\n", page_id, mm)); - - if(page_id == NO_CONTEXT) - return; - - /* mark the TLB entries that match the page_id as invalid. - * here we could also check the _PAGE_GLOBAL bit and NOT flush - * global pages. is it worth the extra I/O ? - */ - - local_irq_save(flags); - for(i = 0; i < NUM_TLB_ENTRIES; i++) { - *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i); - if (IO_EXTRACT(R_TLB_HI, page_id, *R_TLB_HI) == page_id) { - *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | - IO_FIELD(R_TLB_HI, vpn, i & 0xf ) ); - - *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | - IO_STATE(R_TLB_LO, valid, no ) | - IO_STATE(R_TLB_LO, kernel,no ) | - IO_STATE(R_TLB_LO, we, no ) | - IO_FIELD(R_TLB_LO, pfn, 0 ) ); - } - } - local_irq_restore(flags); -} - -/* invalidate a single page */ - -void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) -{ - struct mm_struct *mm = vma->vm_mm; - int page_id = mm->context.page_id; - int i; - unsigned long flags; - - D(printk("tlb: flush page %p in context %d (%p)\n", addr, page_id, mm)); - - if(page_id == NO_CONTEXT) - return; - - addr &= PAGE_MASK; /* perhaps not necessary */ - - /* invalidate those TLB entries that match both the mm context - * and the virtual address requested - */ - - local_irq_save(flags); - for(i = 0; i < NUM_TLB_ENTRIES; i++) { - unsigned long tlb_hi; - *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i); - tlb_hi = *R_TLB_HI; - if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id && - (tlb_hi & PAGE_MASK) == addr) { - *R_TLB_HI = IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) | - addr; /* same addr as before works. */ - - *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | - IO_STATE(R_TLB_LO, valid, no ) | - IO_STATE(R_TLB_LO, kernel,no ) | - IO_STATE(R_TLB_LO, we, no ) | - IO_FIELD(R_TLB_LO, pfn, 0 ) ); - } - } - local_irq_restore(flags); -} - -/* - * Initialize the context related info for a new mm_struct - * instance. - */ - -int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - mm->context.page_id = NO_CONTEXT; - return 0; -} - -/* called in schedule() just before actually doing the switch_to */ - -void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - if (prev != next) { - /* make sure we have a context */ - get_mmu_context(next); - - /* remember the pgd for the fault handlers - * this is similar to the pgd register in some other CPU's. - * we need our own copy of it because current and active_mm - * might be invalid at points where we still need to derefer - * the pgd. - */ - - per_cpu(current_pgd, smp_processor_id()) = next->pgd; - - /* switch context in the MMU */ - - D(printk(KERN_DEBUG "switching mmu_context to %d (%p)\n", - next->context, next)); - - *R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT, - page_id, next->context.page_id); - } -} - diff --git a/arch/cris/arch-v10/output_arch.ld b/arch/cris/arch-v10/output_arch.ld deleted file mode 100644 index 2f3288006991..000000000000 --- a/arch/cris/arch-v10/output_arch.ld +++ /dev/null @@ -1,2 +0,0 @@ -/* At the time of this writing, there's no equivalent ld option. */ -OUTPUT_ARCH (cris) diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig deleted file mode 100644 index 958dabfca7eb..000000000000 --- a/arch/cris/arch-v32/Kconfig +++ /dev/null @@ -1,211 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ETRAX_ARCH_V32 - -source arch/cris/arch-v32/mach-fs/Kconfig -source arch/cris/arch-v32/mach-a3/Kconfig - -source drivers/cpufreq/Kconfig - -config ETRAX_DRAM_VIRTUAL_BASE - hex - depends on ETRAX_ARCH_V32 - default "c0000000" - -choice - prompt "Kernel GDB port" - depends on ETRAX_KGDB - default ETRAX_KGDB_PORT0 - help - Choose a serial port for kernel debugging. NOTE: This port should - not be enabled under Drivers for built-in interfaces (as it has its - own initialization code) and should not be the same as the debug port. - -config ETRAX_KGDB_PORT4 - bool "Serial-4" - depends on ETRAX_SERIAL_PORTS = 5 - help - Use serial port 4 for kernel debugging. - -endchoice - -config ETRAX_MEM_GRP1_CONFIG - hex "MEM_GRP1_CONFIG" - depends on ETRAX_ARCH_V32 - default "4044a" - help - Waitstates for flash. The default value is suitable for the - standard flashes used in axis products (120 ns). - -config ETRAX_MEM_GRP2_CONFIG - hex "MEM_GRP2_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for SRAM. 0 is a good choice for most Axis products. - -config ETRAX_MEM_GRP3_CONFIG - hex "MEM_GRP3_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for CSP0-3. 0 is a good choice for most Axis products. - It may need to be changed if external devices such as extra - register-mapped LEDs are used. - -config ETRAX_MEM_GRP4_CONFIG - hex "MEM_GRP4_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for CSP4-6. 0 is a good choice for most Axis products. - -config ETRAX_SDRAM_GRP0_CONFIG - hex "SDRAM_GRP0_CONFIG" - depends on ETRAX_ARCH_V32 - default "336" - help - SDRAM configuration for group 0. The value depends on the - hardware configuration. The default value is suitable - for 32 MB organized as two 16 bits chips (e.g. Axis - part number 18550) connected as one 32 bit device (i.e. in - the same group). - -config ETRAX_SDRAM_GRP1_CONFIG - hex "SDRAM_GRP1_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - SDRAM configuration for group 1. The default value is 0 - because group 1 is not used in the default configuration, - described in the help for SDRAM_GRP0_CONFIG. - -config ETRAX_SDRAM_TIMING - hex "SDRAM_TIMING" - depends on ETRAX_ARCH_V32 - default "104a" - help - SDRAM timing parameters. The default value is ok for - most hardwares but large SDRAMs may require a faster - refresh (a.k.a 8K refresh). The default value implies - 100MHz clock and SDR mode. - -config ETRAX_SDRAM_COMMAND - hex "SDRAM_COMMAND" - depends on ETRAX_ARCH_V32 - default "0" - help - SDRAM command. Should be 0 unless you really know what - you are doing (may be != 0 for unusual address line - mappings such as in a MCM).. - -config ETRAX_DEF_GIO_PA_OE - hex "GIO_PA_OE" - depends on ETRAX_ARCH_V32 - default "1c" - help - Configures the direction of general port A bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PA_OUT - hex "GIO_PA_OUT" - depends on ETRAX_ARCH_V32 - default "00" - help - Configures the initial data for the general port A bits. Most - products should use 00 here. - -config ETRAX_DEF_GIO_PB_OE - hex "GIO_PB_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port B bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PB_OUT - hex "GIO_PB_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port B bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PC_OE - hex "GIO_PC_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port C bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PC_OUT - hex "GIO_PC_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port C bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PD_OE - hex "GIO_PD_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port D bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PD_OUT - hex "GIO_PD_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port D bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PE_OE - hex "GIO_PE_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port E bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PE_OUT - hex "GIO_PE_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port E bits. Most - products should use 00000 here. - -endif diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig deleted file mode 100644 index 4d2d744bced2..000000000000 --- a/arch/cris/arch-v32/drivers/Kconfig +++ /dev/null @@ -1,263 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ETRAX_ARCH_V32 - -config ETRAX_ETHERNET - bool "Ethernet support" - depends on ETRAX_ARCH_V32 && NETDEVICES - select MII - help - This option enables the ETRAX FS built-in 10/100Mbit Ethernet - controller. - -config ETRAX_NO_PHY - bool "PHY not present" - depends on ETRAX_ETHERNET - help - This option disables all MDIO communication with an ethernet - transceiver connected to the MII interface. This option shall - typically be enabled if the MII interface is connected to a - switch. This option should normally be disabled. If enabled, - speed and duplex will be locked to 100 Mbit and full duplex. - -config ETRAXFS_SERIAL - bool "Serial-port support" - depends on ETRAX_ARCH_V32 - select SERIAL_CORE - select SERIAL_CORE_CONSOLE - help - Enables the ETRAX FS serial driver for ser0 (ttyS0) - You probably want this enabled. - -config ETRAX_RS485 - bool "RS-485 support" - depends on ETRAXFS_SERIAL - help - Enables support for RS-485 serial communication. - -config ETRAX_RS485_DISABLE_RECEIVER - bool "Disable serial receiver" - depends on ETRAX_RS485 - help - It is necessary to disable the serial receiver to avoid serial - loopback. Not all products are able to do this in software only. - -config ETRAX_SERIAL_PORT0 - bool "Serial port 0 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser0 (ttyS0) - Normally you want this on. You can control what DMA channels to use - if you do not need DMA to something else. - ser0 can use dma4 or dma6 for output and dma5 or dma7 for input. - -config ETRAX_SERIAL_PORT1 - bool "Serial port 1 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser1 (ttyS1). - -config ETRAX_SERIAL_PORT2 - bool "Serial port 2 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser2 (ttyS2). - -config ETRAX_SERIAL_PORT3 - bool "Serial port 3 enabled" - depends on ETRAXFS_SERIAL - help - Enables the ETRAX FS serial driver for ser3 (ttyS3). - -config ETRAX_SYNCHRONOUS_SERIAL - bool "Synchronous serial-port support" - depends on ETRAX_ARCH_V32 - help - Enables the ETRAX FS synchronous serial driver. - -config ETRAX_SYNCHRONOUS_SERIAL_PORT0 - bool "Synchronous serial port 0 enabled" - depends on ETRAX_SYNCHRONOUS_SERIAL - help - Enabled synchronous serial port 0. - -config ETRAX_SYNCHRONOUS_SERIAL0_DMA - bool "Enable DMA on synchronous serial port 0." - depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0 - help - A synchronous serial port can run in manual or DMA mode. - Selecting this option will make it run in DMA mode. - -config ETRAX_SYNCHRONOUS_SERIAL_PORT1 - bool "Synchronous serial port 1 enabled" - depends on ETRAX_SYNCHRONOUS_SERIAL && ETRAXFS - help - Enabled synchronous serial port 1. - -config ETRAX_SYNCHRONOUS_SERIAL1_DMA - bool "Enable DMA on synchronous serial port 1." - depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1 - help - A synchronous serial port can run in manual or DMA mode. - Selecting this option will make it run in DMA mode. - -config ETRAX_AXISFLASHMAP - bool "Axis flash-map support" - depends on ETRAX_ARCH_V32 - select MTD - select MTD_CFI - select MTD_CFI_AMDSTD - select MTD_JEDECPROBE - select MTD_BLOCK - select MTD_COMPLEX_MAPPINGS - select MTD_MTDRAM - help - This option enables MTD mapping of flash devices. Needed to use - flash memories. If unsure, say Y. - -config ETRAX_AXISFLASHMAP_MTD0WHOLE - bool "MTD0 is whole boot flash device" - depends on ETRAX_AXISFLASHMAP - help - When this option is not set, mtd0 refers to the first partition - on the boot flash device. When set, mtd0 refers to the whole - device, with mtd1 referring to the first partition etc. - -config ETRAX_PTABLE_SECTOR - int "Byte-offset of partition table sector" - depends on ETRAX_AXISFLASHMAP - default "65536" - help - Byte-offset of the partition table in the first flash chip. - The default value is 64kB and should not be changed unless - you know exactly what you are doing. The only valid reason - for changing this is when the flash block size is bigger - than 64kB (e.g. when using two parallel 16 bit flashes). - -config ETRAX_NANDFLASH - bool "NAND flash support" - depends on ETRAX_ARCH_V32 - select MTD_NAND - help - This option enables MTD mapping of NAND flash devices. Needed to use - NAND flash memories. If unsure, say Y. - -config ETRAX_NANDBOOT - bool "Boot from NAND flash" - depends on ETRAX_NANDFLASH - help - This options enables booting from NAND flash devices. - Say Y if your boot code, kernel and root file system is in - NAND flash. Say N if they are in NOR flash. - -config ETRAX_CARDBUS - bool "Cardbus support" - depends on ETRAX_ARCH_V32 - help - Enabled the ETRAX Cardbus driver. - -config PCI - bool - depends on ETRAX_CARDBUS - default y - select HAVE_GENERIC_DMA_COHERENT - -config ETRAX_IOP_FW_LOAD - tristate "IO-processor hotplug firmware loading support" - depends on ETRAX_ARCH_V32 - select FW_LOADER - help - Enables IO-processor hotplug firmware loading support. - -config ETRAX_STREAMCOPROC - tristate "Stream co-processor driver enabled" - depends on ETRAX_ARCH_V32 - help - This option enables a driver for the stream co-processor - for cryptographic operations. - -config ETRAX_MMC_IOP - tristate "MMC/SD host driver using IO-processor" - depends on ETRAX_ARCH_V32 && MMC - help - This option enables the SD/MMC host controller interface. - The host controller is implemented using the built in - IO-Processor. Only the SPU is used in this implementation. - -config ETRAX_SPI_MMC -# Make this one of several "choices" (possible simultaneously but -# suggested uniquely) when an IOP driver emerges for "real" MMC/SD -# protocol support. - tristate - depends on !ETRAX_MMC_IOP - default MMC - select SPI - select MMC_SPI - -# While the board info is MMC_SPI only, the drivers are written to be -# independent of MMC_SPI, so we'll keep SPI non-dependent on the -# MMC_SPI config choices (well, except for a single depends-on-line -# for the board-info file until a separate non-MMC SPI board file -# emerges). -# FIXME: When that happens, we'll need to be able to ask for and -# configure non-MMC SPI ports together with MMC_SPI ports (if multiple -# SPI ports are enabled). - -config SPI_ETRAX_SSER - tristate - depends on SPI_MASTER && ETRAX_ARCH_V32 - select SPI_BITBANG - help - This enables using an synchronous serial (sser) port as a - SPI master controller on Axis ETRAX FS and later. The - driver can be configured to use any sser port. - -config SPI_ETRAX_GPIO - tristate - depends on SPI_MASTER && ETRAX_ARCH_V32 - select SPI_BITBANG - help - This enables using GPIO pins port as a SPI master controller - on Axis ETRAX FS and later. The driver can be configured to - use any GPIO pins. - -config ETRAX_SPI_SSER0 - tristate "SPI using synchronous serial port 0 (sser0)" - depends on ETRAX_SPI_MMC - default m if MMC_SPI=m - default y if MMC_SPI=y - default y if MMC_SPI=n - select SPI_ETRAX_SSER - help - Say Y for an MMC/SD socket connected to synchronous serial port 0, - or for devices using the SPI protocol on that port. Say m if you - want to build it as a module, which will be named spi_crisv32_sser. - (You need to select MMC separately.) - -config ETRAX_SPI_SSER1 - tristate "SPI using synchronous serial port 1 (sser1)" - depends on ETRAX_SPI_MMC - default m if MMC_SPI=m && ETRAX_SPI_SSER0=n - default y if MMC_SPI=y && ETRAX_SPI_SSER0=n - default y if MMC_SPI=n && ETRAX_SPI_SSER0=n - select SPI_ETRAX_SSER - help - Say Y for an MMC/SD socket connected to synchronous serial port 1, - or for devices using the SPI protocol on that port. Say m if you - want to build it as a module, which will be named spi_crisv32_sser. - (You need to select MMC separately.) - -config ETRAX_SPI_GPIO - tristate "Bitbanged SPI using gpio pins" - depends on ETRAX_SPI_MMC - select SPI_ETRAX_GPIO - default m if MMC_SPI=m && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n - default y if MMC_SPI=y && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n - default y if MMC_SPI=n && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n - help - Say Y for an MMC/SD socket connected to general I/O pins (but not - a complete synchronous serial ports), or for devices using the SPI - protocol on general I/O pins. Slow and slows down the system. - Say m to build it as a module, which will be called spi_crisv32_gpio. - (You need to select MMC separately.) - -endif diff --git a/arch/cris/arch-v32/drivers/Makefile b/arch/cris/arch-v32/drivers/Makefile deleted file mode 100644 index 57c9568707b0..000000000000 --- a/arch/cris/arch-v32/drivers/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for Etrax-specific drivers -# - -obj-$(CONFIG_ETRAX_STREAMCOPROC) += cryptocop.o -obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o -obj-$(CONFIG_ETRAXFS) += mach-fs/ -obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/ -obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o -obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o -obj-$(CONFIG_PCI) += pci/ diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c deleted file mode 100644 index 87656c41fec7..000000000000 --- a/arch/cris/arch-v32/drivers/axisflashmap.c +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Physical mapping layer for MTD using the Axis partitiontable format - * - * Copyright (c) 2001-2007 Axis Communications AB - * - * This file is under the GPL. - * - * First partition is always sector 0 regardless of if we find a partitiontable - * or not. In the start of the next sector, there can be a partitiontable that - * tells us what other partitions to define. If there isn't, we use a default - * partition split defined below. - * - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) - -#define FLASH_UNCACHED_ADDR KSEG_E -#define FLASH_CACHED_ADDR KSEG_F - -#define PAGESIZE (512) - -#if CONFIG_ETRAX_FLASH_BUSWIDTH==1 -#define flash_data __u8 -#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2 -#define flash_data __u16 -#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4 -#define flash_data __u32 -#endif - -/* From head.S */ -extern unsigned long romfs_in_flash; /* 1 when romfs_start, _length in flash */ -extern unsigned long romfs_start, romfs_length; -extern unsigned long nand_boot; /* 1 when booted from nand flash */ - -struct partition_name { - char name[6]; -}; - -/* The master mtd for the entire flash. */ -struct mtd_info* axisflash_mtd = NULL; - -/* Map driver functions. */ - -static map_word flash_read(struct map_info *map, unsigned long ofs) -{ - map_word tmp; - tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs); - return tmp; -} - -static void flash_copy_from(struct map_info *map, void *to, - unsigned long from, ssize_t len) -{ - memcpy(to, (void *)(map->map_priv_1 + from), len); -} - -static void flash_write(struct map_info *map, map_word d, unsigned long adr) -{ - *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0]; -} - -/* - * The map for chip select e0. - * - * We run into tricky coherence situations if we mix cached with uncached - * accesses to we only use the uncached version here. - * - * The size field is the total size where the flash chips may be mapped on the - * chip select. MTD probes should find all devices there and it does not matter - * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD - * probes will ignore them. - * - * The start address in map_priv_1 is in virtual memory so we cannot use - * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start - * address of cse0. - */ -static struct map_info map_cse0 = { - .name = "cse0", - .size = MEM_CSE0_SIZE, - .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, - .read = flash_read, - .copy_from = flash_copy_from, - .write = flash_write, - .map_priv_1 = FLASH_UNCACHED_ADDR -}; - -/* - * The map for chip select e1. - * - * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong - * address, but there isn't. - */ -static struct map_info map_cse1 = { - .name = "cse1", - .size = MEM_CSE1_SIZE, - .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH, - .read = flash_read, - .copy_from = flash_copy_from, - .write = flash_write, - .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE -}; - -#define MAX_PARTITIONS 7 -#ifdef CONFIG_ETRAX_NANDBOOT -#define NUM_DEFAULT_PARTITIONS 4 -#define DEFAULT_ROOTFS_PARTITION_NO 2 -#define DEFAULT_MEDIA_SIZE 0x2000000 /* 32 megs */ -#else -#define NUM_DEFAULT_PARTITIONS 3 -#define DEFAULT_ROOTFS_PARTITION_NO (-1) -#define DEFAULT_MEDIA_SIZE 0x800000 /* 8 megs */ -#endif - -#if (MAX_PARTITIONS < NUM_DEFAULT_PARTITIONS) -#error MAX_PARTITIONS must be >= than NUM_DEFAULT_PARTITIONS -#endif - -/* Initialize the ones normally used. */ -static struct mtd_partition axis_partitions[MAX_PARTITIONS] = { - { - .name = "part0", - .size = CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0 - }, - { - .name = "part1", - .size = 0, - .offset = 0 - }, - { - .name = "part2", - .size = 0, - .offset = 0 - }, - { - .name = "part3", - .size = 0, - .offset = 0 - }, - { - .name = "part4", - .size = 0, - .offset = 0 - }, - { - .name = "part5", - .size = 0, - .offset = 0 - }, - { - .name = "part6", - .size = 0, - .offset = 0 - }, -}; - - -/* If no partition-table was found, we use this default-set. - * Default flash size is 8MB (NOR). CONFIG_ETRAX_PTABLE_SECTOR is most - * likely the size of one flash block and "filesystem"-partition needs - * to be >=5 blocks to be able to use JFFS. - */ -static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { - { - .name = "boot firmware", - .size = CONFIG_ETRAX_PTABLE_SECTOR, - .offset = 0 - }, - { - .name = "kernel", - .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR, - .offset = CONFIG_ETRAX_PTABLE_SECTOR - }, -#define FILESYSTEM_SECTOR (11 * CONFIG_ETRAX_PTABLE_SECTOR) -#ifdef CONFIG_ETRAX_NANDBOOT - { - .name = "rootfs", - .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR, - .offset = FILESYSTEM_SECTOR - }, -#undef FILESYSTEM_SECTOR -#define FILESYSTEM_SECTOR (21 * CONFIG_ETRAX_PTABLE_SECTOR) -#endif - { - .name = "rwfs", - .size = DEFAULT_MEDIA_SIZE - FILESYSTEM_SECTOR, - .offset = FILESYSTEM_SECTOR - } -}; - -#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE -/* Main flash device */ -static struct mtd_partition main_partition = { - .name = "main", - .size = 0, - .offset = 0 -}; -#endif - -/* Auxiliary partition if we find another flash */ -static struct mtd_partition aux_partition = { - .name = "aux", - .size = 0, - .offset = 0 -}; - -/* - * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash - * chips in that order (because the amd_flash-driver is faster). - */ -static struct mtd_info *probe_cs(struct map_info *map_cs) -{ - struct mtd_info *mtd_cs = NULL; - - printk(KERN_INFO - "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n", - map_cs->name, map_cs->size, map_cs->map_priv_1); - -#ifdef CONFIG_MTD_CFI - mtd_cs = do_map_probe("cfi_probe", map_cs); -#endif -#ifdef CONFIG_MTD_JEDECPROBE - if (!mtd_cs) - mtd_cs = do_map_probe("jedec_probe", map_cs); -#endif - - return mtd_cs; -} - -/* - * Probe each chip select individually for flash chips. If there are chips on - * both cse0 and cse1, the mtd_info structs will be concatenated to one struct - * so that MTD partitions can cross chip boundaries. - * - * The only known restriction to how you can mount your chips is that each - * chip select must hold similar flash chips. But you need external hardware - * to do that anyway and you can put totally different chips on cse0 and cse1 - * so it isn't really much of a restriction. - */ -extern struct mtd_info* __init crisv32_nand_flash_probe (void); -static struct mtd_info *flash_probe(void) -{ - struct mtd_info *mtd_cse0; - struct mtd_info *mtd_cse1; - struct mtd_info *mtd_total; - struct mtd_info *mtds[2]; - int count = 0; - - if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL) - mtds[count++] = mtd_cse0; - if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL) - mtds[count++] = mtd_cse1; - - if (!mtd_cse0 && !mtd_cse1) { - /* No chip found. */ - return NULL; - } - - if (count > 1) { - /* Since the concatenation layer adds a small overhead we - * could try to figure out if the chips in cse0 and cse1 are - * identical and reprobe the whole cse0+cse1 window. But since - * flash chips are slow, the overhead is relatively small. - * So we use the MTD concatenation layer instead of further - * complicating the probing procedure. - */ - mtd_total = mtd_concat_create(mtds, count, "cse0+cse1"); - if (!mtd_total) { - printk(KERN_ERR "%s and %s: Concatenation failed!\n", - map_cse0.name, map_cse1.name); - - /* The best we can do now is to only use what we found - * at cse0. */ - mtd_total = mtd_cse0; - map_destroy(mtd_cse1); - } - } else - mtd_total = mtd_cse0 ? mtd_cse0 : mtd_cse1; - - return mtd_total; -} - -/* - * Probe the flash chip(s) and, if it succeeds, read the partition-table - * and register the partitions with MTD. - */ -static int __init init_axis_flash(void) -{ - struct mtd_info *main_mtd; - struct mtd_info *aux_mtd = NULL; - int err = 0; - int pidx = 0; - struct partitiontable_head *ptable_head = NULL; - struct partitiontable_entry *ptable; - int ptable_ok = 0; - static char page[PAGESIZE]; - size_t len; - int ram_rootfs_partition = -1; /* -1 => no RAM rootfs partition */ - int part; - struct mtd_partition *partition; - - /* We need a root fs. If it resides in RAM, we need to use an - * MTDRAM device, so it must be enabled in the kernel config, - * but its size must be configured as 0 so as not to conflict - * with our usage. - */ -#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) - if (!romfs_in_flash && !nand_boot) { - printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " - "device; configure CONFIG_MTD_MTDRAM with size = 0!\n"); - panic("This kernel cannot boot from RAM!\n"); - } -#endif - - main_mtd = flash_probe(); - if (main_mtd) - printk(KERN_INFO "%s: 0x%08llx bytes of NOR flash memory.\n", - main_mtd->name, main_mtd->size); - -#ifdef CONFIG_ETRAX_NANDFLASH - aux_mtd = crisv32_nand_flash_probe(); - if (aux_mtd) - printk(KERN_INFO "%s: 0x%08x bytes of NAND flash memory.\n", - aux_mtd->name, aux_mtd->size); - -#ifdef CONFIG_ETRAX_NANDBOOT - { - struct mtd_info *tmp_mtd; - - printk(KERN_INFO "axisflashmap: Set to boot from NAND flash, " - "making NAND flash primary device.\n"); - tmp_mtd = main_mtd; - main_mtd = aux_mtd; - aux_mtd = tmp_mtd; - } -#endif /* CONFIG_ETRAX_NANDBOOT */ -#endif /* CONFIG_ETRAX_NANDFLASH */ - - if (!main_mtd && !aux_mtd) { - /* There's no reason to use this module if no flash chip can - * be identified. Make sure that's understood. - */ - printk(KERN_INFO "axisflashmap: Found no flash chip.\n"); - } - -#if 0 /* Dump flash memory so we can see what is going on */ - if (main_mtd) { - int sectoraddr; - for (sectoraddr = 0; sectoraddr < 2*65536+4096; - sectoraddr += PAGESIZE) { - main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len, - page); - printk(KERN_INFO - "Sector at %d (length %d):\n", - sectoraddr, len); - print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, page, PAGESIZE, false); - } - } -#endif - - if (main_mtd) { - loff_t ptable_sector = CONFIG_ETRAX_PTABLE_SECTOR; - main_mtd->owner = THIS_MODULE; - axisflash_mtd = main_mtd; - - - /* First partition (rescue) is always set to the default. */ - pidx++; -#ifdef CONFIG_ETRAX_NANDBOOT - /* We know where the partition table should be located, - * it will be in first good block after that. - */ - int blockstat; - do { - blockstat = mtd_block_isbad(main_mtd, ptable_sector); - if (blockstat < 0) - ptable_sector = 0; /* read error */ - else if (blockstat) - ptable_sector += main_mtd->erasesize; - } while (blockstat && ptable_sector); -#endif - if (ptable_sector) { - mtd_read(main_mtd, ptable_sector, PAGESIZE, &len, - page); - ptable_head = &((struct partitiontable *) page)->head; - } - -#if 0 /* Dump partition table so we can see what is going on */ - printk(KERN_INFO - "axisflashmap: flash read %d bytes at 0x%08x, data: %8ph\n", - len, CONFIG_ETRAX_PTABLE_SECTOR, page); - printk(KERN_INFO - "axisflashmap: partition table offset %d, data: %8ph\n", - PARTITION_TABLE_OFFSET, page + PARTITION_TABLE_OFFSET); -#endif - } - - if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC) - && (ptable_head->size < - (MAX_PARTITIONS * sizeof(struct partitiontable_entry) + - PARTITIONTABLE_END_MARKER_SIZE)) - && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) + - ptable_head->size - - PARTITIONTABLE_END_MARKER_SIZE) - == PARTITIONTABLE_END_MARKER)) { - /* Looks like a start, sane length and end of a - * partition table, lets check csum etc. - */ - struct partitiontable_entry *max_addr = - (struct partitiontable_entry *) - ((unsigned long)ptable_head + sizeof(*ptable_head) + - ptable_head->size); - unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR; - unsigned char *p; - unsigned long csum = 0; - - ptable = (struct partitiontable_entry *) - ((unsigned long)ptable_head + sizeof(*ptable_head)); - - /* Lets be PARANOID, and check the checksum. */ - p = (unsigned char*) ptable; - - while (p <= (unsigned char*)max_addr) { - csum += *p++; - csum += *p++; - csum += *p++; - csum += *p++; - } - ptable_ok = (csum == ptable_head->checksum); - - /* Read the entries and use/show the info. */ - printk(KERN_INFO "axisflashmap: " - "Found a%s partition table at 0x%p-0x%p.\n", - (ptable_ok ? " valid" : "n invalid"), ptable_head, - max_addr); - - /* We have found a working bootblock. Now read the - * partition table. Scan the table. It ends with 0xffffffff. - */ - while (ptable_ok - && ptable->offset != PARTITIONTABLE_END_MARKER - && ptable < max_addr - && pidx < MAX_PARTITIONS - 1) { - - axis_partitions[pidx].offset = offset + ptable->offset; -#ifdef CONFIG_ETRAX_NANDFLASH - if (main_mtd->type == MTD_NANDFLASH) { - axis_partitions[pidx].size = - (((ptable+1)->offset == - PARTITIONTABLE_END_MARKER) ? - main_mtd->size : - ((ptable+1)->offset + offset)) - - (ptable->offset + offset); - - } else -#endif /* CONFIG_ETRAX_NANDFLASH */ - axis_partitions[pidx].size = ptable->size; -#ifdef CONFIG_ETRAX_NANDBOOT - /* Save partition number of jffs2 ro partition. - * Needed if RAM booting or root file system in RAM. - */ - if (!nand_boot && - ram_rootfs_partition < 0 && /* not already set */ - ptable->type == PARTITION_TYPE_JFFS2 && - (ptable->flags & PARTITION_FLAGS_READONLY_MASK) == - PARTITION_FLAGS_READONLY) - ram_rootfs_partition = pidx; -#endif /* CONFIG_ETRAX_NANDBOOT */ - pidx++; - ptable++; - } - } - - /* Decide whether to use default partition table. */ - /* Only use default table if we actually have a device (main_mtd) */ - - partition = &axis_partitions[0]; - if (main_mtd && !ptable_ok) { - memcpy(axis_partitions, axis_default_partitions, - sizeof(axis_default_partitions)); - pidx = NUM_DEFAULT_PARTITIONS; - ram_rootfs_partition = DEFAULT_ROOTFS_PARTITION_NO; - } - - /* Add artificial partitions for rootfs if necessary */ - if (romfs_in_flash) { - /* rootfs is in directly accessible flash memory = NOR flash. - Add an overlapping device for the rootfs partition. */ - printk(KERN_INFO "axisflashmap: Adding partition for " - "overlapping root file system image\n"); - axis_partitions[pidx].size = romfs_length; - axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; - axis_partitions[pidx].name = "romfs"; - axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; - ram_rootfs_partition = -1; - pidx++; - } else if (romfs_length && !nand_boot) { - /* romfs exists in memory, but not in flash, so must be in RAM. - * Configure an MTDRAM partition. */ - if (ram_rootfs_partition < 0) { - /* None set yet, put it at the end */ - ram_rootfs_partition = pidx; - pidx++; - } - printk(KERN_INFO "axisflashmap: Adding partition for " - "root file system image in RAM\n"); - axis_partitions[ram_rootfs_partition].size = romfs_length; - axis_partitions[ram_rootfs_partition].offset = romfs_start; - axis_partitions[ram_rootfs_partition].name = "romfs"; - axis_partitions[ram_rootfs_partition].mask_flags |= - MTD_WRITEABLE; - } - -#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE - if (main_mtd) { - main_partition.size = main_mtd->size; - err = mtd_device_register(main_mtd, &main_partition, 1); - if (err) - panic("axisflashmap: Could not initialize " - "partition for whole main mtd device!\n"); - } -#endif - - /* Now, register all partitions with mtd. - * We do this one at a time so we can slip in an MTDRAM device - * in the proper place if required. */ - - for (part = 0; part < pidx; part++) { - if (part == ram_rootfs_partition) { - /* add MTDRAM partition here */ - struct mtd_info *mtd_ram; - - mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); - if (!mtd_ram) - panic("axisflashmap: Couldn't allocate memory " - "for mtd_info!\n"); - printk(KERN_INFO "axisflashmap: Adding RAM partition " - "for rootfs image.\n"); - err = mtdram_init_device(mtd_ram, - (void *)(u_int32_t)partition[part].offset, - partition[part].size, - partition[part].name); - if (err) - panic("axisflashmap: Could not initialize " - "MTD RAM device!\n"); - /* JFFS2 likes to have an erasesize. Keep potential - * JFFS2 rootfs happy by providing one. Since image - * was most likely created for main mtd, use that - * erasesize, if available. Otherwise, make a guess. */ - mtd_ram->erasesize = (main_mtd ? main_mtd->erasesize : - CONFIG_ETRAX_PTABLE_SECTOR); - } else { - err = mtd_device_register(main_mtd, &partition[part], - 1); - if (err) - panic("axisflashmap: Could not add mtd " - "partition %d\n", part); - } - } - - if (aux_mtd) { - aux_partition.size = aux_mtd->size; - err = mtd_device_register(aux_mtd, &aux_partition, 1); - if (err) - panic("axisflashmap: Could not initialize " - "aux mtd device!\n"); - - } - - return err; -} - -/* This adds the above to the kernels init-call chain. */ -module_init(init_axis_flash); - -EXPORT_SYMBOL(axisflash_mtd); diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c deleted file mode 100644 index a3c353472a8c..000000000000 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ /dev/null @@ -1,3522 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Stream co-processor driver for the ETRAX FS - * - * Copyright (C) 2003-2007 Axis Communications AB - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_ETRAXFS -#define IN_DMA 9 -#define OUT_DMA 8 -#define IN_DMA_INST regi_dma9 -#define OUT_DMA_INST regi_dma8 -#define DMA_IRQ DMA9_INTR_VECT -#else -#define IN_DMA 3 -#define OUT_DMA 2 -#define IN_DMA_INST regi_dma3 -#define OUT_DMA_INST regi_dma2 -#define DMA_IRQ DMA3_INTR_VECT -#endif - -#define DESCR_ALLOC_PAD (31) - -struct cryptocop_dma_desc { - char *free_buf; /* If non-null will be kfreed in free_cdesc() */ - dma_descr_data *dma_descr; - - unsigned char dma_descr_buf[sizeof(dma_descr_data) + DESCR_ALLOC_PAD]; - - unsigned int from_pool:1; /* If 1 'allocated' from the descriptor pool. */ - struct cryptocop_dma_desc *next; -}; - - -struct cryptocop_int_operation{ - void *alloc_ptr; - cryptocop_session_id sid; - - dma_descr_context ctx_out; - dma_descr_context ctx_in; - - /* DMA descriptors allocated by driver. */ - struct cryptocop_dma_desc *cdesc_out; - struct cryptocop_dma_desc *cdesc_in; - - /* Strcop config to use. */ - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; - - /* DMA descrs provided by consumer. */ - dma_descr_data *ddesc_out; - dma_descr_data *ddesc_in; -}; - - -struct cryptocop_tfrm_ctx { - cryptocop_tfrm_id tid; - unsigned int blocklength; - - unsigned int start_ix; - - struct cryptocop_tfrm_cfg *tcfg; - struct cryptocop_transform_ctx *tctx; - - unsigned char previous_src; - unsigned char current_src; - - /* Values to use in metadata out. */ - unsigned char hash_conf; - unsigned char hash_mode; - unsigned char ciph_conf; - unsigned char cbcmode; - unsigned char decrypt; - - unsigned int requires_padding:1; - unsigned int strict_block_length:1; - unsigned int active:1; - unsigned int done:1; - size_t consumed; - size_t produced; - - /* Pad (input) descriptors to put in the DMA out list when the transform - * output is put on the DMA in list. */ - struct cryptocop_dma_desc *pad_descs; - - struct cryptocop_tfrm_ctx *prev_src; - struct cryptocop_tfrm_ctx *curr_src; - - /* Mapping to HW. */ - unsigned char unit_no; -}; - - -struct cryptocop_private{ - cryptocop_session_id sid; - struct cryptocop_private *next; -}; - -/* Session list. */ - -struct cryptocop_transform_ctx{ - struct cryptocop_transform_init init; - unsigned char dec_key[CRYPTOCOP_MAX_KEY_LENGTH]; - unsigned int dec_key_set:1; - - struct cryptocop_transform_ctx *next; -}; - - -struct cryptocop_session{ - cryptocop_session_id sid; - - struct cryptocop_transform_ctx *tfrm_ctx; - - struct cryptocop_session *next; -}; - -/* Priority levels for jobs sent to the cryptocop. Checksum operations from - kernel have highest priority since TCPIP stack processing must not - be a bottleneck. */ -typedef enum { - cryptocop_prio_kernel_csum = 0, - cryptocop_prio_kernel = 1, - cryptocop_prio_user = 2, - cryptocop_prio_no_prios = 3 -} cryptocop_queue_priority; - -struct cryptocop_prio_queue{ - struct list_head jobs; - cryptocop_queue_priority prio; -}; - -struct cryptocop_prio_job{ - struct list_head node; - cryptocop_queue_priority prio; - - struct cryptocop_operation *oper; - struct cryptocop_int_operation *iop; -}; - -struct ioctl_job_cb_ctx { - unsigned int processed:1; -}; - - -static struct cryptocop_session *cryptocop_sessions = NULL; -spinlock_t cryptocop_sessions_lock; - -/* Next Session ID to assign. */ -static cryptocop_session_id next_sid = 1; - -/* Pad for checksum. */ -static const char csum_zero_pad[1] = {0x00}; - -/* Trash buffer for mem2mem operations. */ -#define MEM2MEM_DISCARD_BUF_LENGTH (512) -static unsigned char mem2mem_discard_buf[MEM2MEM_DISCARD_BUF_LENGTH]; - -/* Descriptor pool. */ -/* FIXME Tweak this value. */ -#define CRYPTOCOP_DESCRIPTOR_POOL_SIZE (100) -static struct cryptocop_dma_desc descr_pool[CRYPTOCOP_DESCRIPTOR_POOL_SIZE]; -static struct cryptocop_dma_desc *descr_pool_free_list; -static int descr_pool_no_free; -static spinlock_t descr_pool_lock; - -/* Lock to stop cryptocop to start processing of a new operation. The holder - of this lock MUST call cryptocop_start_job() after it is unlocked. */ -spinlock_t cryptocop_process_lock; - -static struct cryptocop_prio_queue cryptocop_job_queues[cryptocop_prio_no_prios]; -static spinlock_t cryptocop_job_queue_lock; -static struct cryptocop_prio_job *cryptocop_running_job = NULL; -static spinlock_t running_job_lock; - -/* The interrupt handler appends completed jobs to this list. The scehduled - * tasklet removes them upon sending the response to the crypto consumer. */ -static struct list_head cryptocop_completed_jobs; -static spinlock_t cryptocop_completed_jobs_lock; - -DECLARE_WAIT_QUEUE_HEAD(cryptocop_ioc_process_wq); - - -/** Local functions. **/ - -static int cryptocop_open(struct inode *, struct file *); - -static int cryptocop_release(struct inode *, struct file *); - -static long cryptocop_ioctl(struct file *file, - unsigned int cmd, unsigned long arg); - -static void cryptocop_start_job(void); - -static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation); -static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation); - -static int cryptocop_job_queue_init(void); -static void cryptocop_job_queue_close(void); - -static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length); - -static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length); - -static int transform_ok(struct cryptocop_transform_init *tinit); - -static struct cryptocop_session *get_session(cryptocop_session_id sid); - -static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid); - -static void delete_internal_operation(struct cryptocop_int_operation *iop); - -static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength); - -static int init_stream_coprocessor(void); - -static void __exit exit_stream_coprocessor(void); - -/*#define LDEBUG*/ -#ifdef LDEBUG -#define DEBUG(s) s -#define DEBUG_API(s) s -static void print_cryptocop_operation(struct cryptocop_operation *cop); -static void print_dma_descriptors(struct cryptocop_int_operation *iop); -static void print_strcop_crypto_op(struct strcop_crypto_op *cop); -static void print_lock_status(void); -static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op); -#define assert(s) do{if (!(s)) panic(#s);} while(0); -#else -#define DEBUG(s) -#define DEBUG_API(s) -#define assert(s) -#endif - - -/* Transform constants. */ -#define DES_BLOCK_LENGTH (8) -#define AES_BLOCK_LENGTH (16) -#define MD5_BLOCK_LENGTH (64) -#define SHA1_BLOCK_LENGTH (64) -#define CSUM_BLOCK_LENGTH (2) -#define MD5_STATE_LENGTH (16) -#define SHA1_STATE_LENGTH (20) - -/* The device number. */ -#define CRYPTOCOP_MAJOR (254) -#define CRYPTOCOP_MINOR (0) - - - -const struct file_operations cryptocop_fops = { - .owner = THIS_MODULE, - .open = cryptocop_open, - .release = cryptocop_release, - .unlocked_ioctl = cryptocop_ioctl, - .llseek = noop_llseek, -}; - - -static void free_cdesc(struct cryptocop_dma_desc *cdesc) -{ - DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool)); - kfree(cdesc->free_buf); - - if (cdesc->from_pool) { - unsigned long int flags; - spin_lock_irqsave(&descr_pool_lock, flags); - cdesc->next = descr_pool_free_list; - descr_pool_free_list = cdesc; - ++descr_pool_no_free; - spin_unlock_irqrestore(&descr_pool_lock, flags); - } else { - kfree(cdesc); - } -} - - -static struct cryptocop_dma_desc *alloc_cdesc(int alloc_flag) -{ - int use_pool = (alloc_flag & GFP_ATOMIC) ? 1 : 0; - struct cryptocop_dma_desc *cdesc; - - if (use_pool) { - unsigned long int flags; - spin_lock_irqsave(&descr_pool_lock, flags); - if (!descr_pool_free_list) { - spin_unlock_irqrestore(&descr_pool_lock, flags); - DEBUG_API(printk("alloc_cdesc: pool is empty\n")); - return NULL; - } - cdesc = descr_pool_free_list; - descr_pool_free_list = descr_pool_free_list->next; - --descr_pool_no_free; - spin_unlock_irqrestore(&descr_pool_lock, flags); - cdesc->from_pool = 1; - } else { - cdesc = kmalloc(sizeof(struct cryptocop_dma_desc), alloc_flag); - if (!cdesc) { - DEBUG_API(printk("alloc_cdesc: kmalloc\n")); - return NULL; - } - cdesc->from_pool = 0; - } - cdesc->dma_descr = (dma_descr_data*)(((unsigned long int)cdesc + offsetof(struct cryptocop_dma_desc, dma_descr_buf) + DESCR_ALLOC_PAD) & ~0x0000001F); - - cdesc->next = NULL; - - cdesc->free_buf = NULL; - cdesc->dma_descr->out_eop = 0; - cdesc->dma_descr->in_eop = 0; - cdesc->dma_descr->intr = 0; - cdesc->dma_descr->eol = 0; - cdesc->dma_descr->wait = 0; - cdesc->dma_descr->buf = NULL; - cdesc->dma_descr->after = NULL; - - DEBUG_API(printk("alloc_cdesc: return 0x%p, cdesc->dma_descr=0x%p, from_pool=%d\n", cdesc, cdesc->dma_descr, cdesc->from_pool)); - return cdesc; -} - - -static void setup_descr_chain(struct cryptocop_dma_desc *cd) -{ - DEBUG(printk("setup_descr_chain: entering\n")); - while (cd) { - if (cd->next) { - cd->dma_descr->next = (dma_descr_data*)virt_to_phys(cd->next->dma_descr); - } else { - cd->dma_descr->next = NULL; - } - cd = cd->next; - } - DEBUG(printk("setup_descr_chain: exit\n")); -} - - -/* Create a pad descriptor for the transform. - * Return -1 for error, 0 if pad created. */ -static int create_pad_descriptor(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **pad_desc, int alloc_flag) -{ - struct cryptocop_dma_desc *cdesc = NULL; - int error = 0; - struct strcop_meta_out mo = { - .ciphsel = src_none, - .hashsel = src_none, - .csumsel = src_none - }; - char *pad; - size_t plen; - - DEBUG(printk("create_pad_descriptor: start.\n")); - /* Setup pad descriptor. */ - - DEBUG(printk("create_pad_descriptor: setting up padding.\n")); - cdesc = alloc_cdesc(alloc_flag); - if (!cdesc){ - DEBUG_API(printk("create_pad_descriptor: alloc pad desc\n")); - goto error_cleanup; - } - switch (tc->unit_no) { - case src_md5: - error = create_md5_pad(alloc_flag, tc->consumed, &pad, &plen); - if (error){ - DEBUG_API(printk("create_pad_descriptor: create_md5_pad_failed\n")); - goto error_cleanup; - } - cdesc->free_buf = pad; - mo.hashsel = src_dma; - mo.hashconf = tc->hash_conf; - mo.hashmode = tc->hash_mode; - break; - case src_sha1: - error = create_sha1_pad(alloc_flag, tc->consumed, &pad, &plen); - if (error){ - DEBUG_API(printk("create_pad_descriptor: create_sha1_pad_failed\n")); - goto error_cleanup; - } - cdesc->free_buf = pad; - mo.hashsel = src_dma; - mo.hashconf = tc->hash_conf; - mo.hashmode = tc->hash_mode; - break; - case src_csum: - if (tc->consumed % tc->blocklength){ - pad = (char*)csum_zero_pad; - plen = 1; - } else { - pad = (char*)cdesc; /* Use any pointer. */ - plen = 0; - } - mo.csumsel = src_dma; - break; - } - cdesc->dma_descr->wait = 1; - cdesc->dma_descr->out_eop = 1; /* Since this is a pad output is pushed. EOP is ok here since the padded unit is the only one active. */ - cdesc->dma_descr->buf = (char*)virt_to_phys((char*)pad); - cdesc->dma_descr->after = cdesc->dma_descr->buf + plen; - - cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); - *pad_desc = cdesc; - - return 0; - - error_cleanup: - if (cdesc) free_cdesc(cdesc); - return -1; -} - - -static int setup_key_dl_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **kd, int alloc_flag) -{ - struct cryptocop_dma_desc *key_desc = alloc_cdesc(alloc_flag); - struct strcop_meta_out mo = {0}; - - DEBUG(printk("setup_key_dl_desc\n")); - - if (!key_desc) { - DEBUG_API(printk("setup_key_dl_desc: failed descriptor allocation.\n")); - return -ENOMEM; - } - - /* Download key. */ - if ((tc->tctx->init.alg == cryptocop_alg_aes) && (tc->tcfg->flags & CRYPTOCOP_DECRYPT)) { - /* Precook the AES decrypt key. */ - if (!tc->tctx->dec_key_set){ - get_aes_decrypt_key(tc->tctx->dec_key, tc->tctx->init.key, tc->tctx->init.keylen); - tc->tctx->dec_key_set = 1; - } - key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->dec_key); - key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8; - } else { - key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->init.key); - key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8; - } - /* Setup metadata. */ - mo.dlkey = 1; - switch (tc->tctx->init.keylen) { - case 64: - mo.decrypt = 0; - mo.hashmode = 0; - break; - case 128: - mo.decrypt = 0; - mo.hashmode = 1; - break; - case 192: - mo.decrypt = 1; - mo.hashmode = 0; - break; - case 256: - mo.decrypt = 1; - mo.hashmode = 1; - break; - default: - break; - } - mo.ciphsel = mo.hashsel = mo.csumsel = src_none; - key_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); - - key_desc->dma_descr->out_eop = 1; - key_desc->dma_descr->wait = 1; - key_desc->dma_descr->intr = 0; - - *kd = key_desc; - return 0; -} - -static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) -{ - struct cryptocop_dma_desc *iv_desc = alloc_cdesc(alloc_flag); - struct strcop_meta_out mo = {0}; - - DEBUG(printk("setup_cipher_iv_desc\n")); - - if (!iv_desc) { - DEBUG_API(printk("setup_cipher_iv_desc: failed CBC IV descriptor allocation.\n")); - return -ENOMEM; - } - /* Download IV. */ - iv_desc->dma_descr->buf = (char*)virt_to_phys(tc->tcfg->iv); - iv_desc->dma_descr->after = iv_desc->dma_descr->buf + tc->blocklength; - - /* Setup metadata. */ - mo.hashsel = mo.csumsel = src_none; - mo.ciphsel = src_dma; - mo.ciphconf = tc->ciph_conf; - mo.cbcmode = tc->cbcmode; - - iv_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo); - - iv_desc->dma_descr->out_eop = 0; - iv_desc->dma_descr->wait = 1; - iv_desc->dma_descr->intr = 0; - - *id = iv_desc; - return 0; -} - -/* Map the output length of the transform to operation output starting on the inject index. */ -static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag) -{ - int err = 0; - struct cryptocop_dma_desc head = {0}; - struct cryptocop_dma_desc *outdesc = &head; - size_t iov_offset = 0; - size_t out_ix = 0; - int outiov_ix = 0; - struct strcop_meta_in mi = {0}; - - size_t out_length = tc->produced; - int rem_length; - int dlength; - - assert(out_length != 0); - if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operation->tfrm_op.outlen == 0))) { - DEBUG_API(printk("create_input_descriptors: operation outdata too small\n")); - return -EINVAL; - } - /* Traverse the out iovec until the result inject index is reached. */ - while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_ix].iov_len) <= tc->tcfg->inject_ix)){ - out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len; - outiov_ix++; - } - if (outiov_ix >= operation->tfrm_op.outcount){ - DEBUG_API(printk("create_input_descriptors: operation outdata too small\n")); - return -EINVAL; - } - iov_offset = tc->tcfg->inject_ix - out_ix; - mi.dmasel = tc->unit_no; - - /* Setup the output descriptors. */ - while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) { - outdesc->next = alloc_cdesc(alloc_flag); - if (!outdesc->next) { - DEBUG_API(printk("create_input_descriptors: alloc_cdesc\n")); - err = -ENOMEM; - goto error_cleanup; - } - outdesc = outdesc->next; - rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset; - dlength = (out_length < rem_length) ? out_length : rem_length; - - DEBUG(printk("create_input_descriptors:\n" - "outiov_ix=%d, rem_length=%d, dlength=%d\n" - "iov_offset=%d, outdata[outiov_ix].iov_len=%d\n" - "outcount=%d, outiov_ix=%d\n", - outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operation->tfrm_op.outcount, outiov_ix)); - - outdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.outdata[outiov_ix].iov_base + iov_offset); - outdesc->dma_descr->after = outdesc->dma_descr->buf + dlength; - outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - - out_length -= dlength; - iov_offset += dlength; - if (iov_offset >= operation->tfrm_op.outdata[outiov_ix].iov_len) { - iov_offset = 0; - ++outiov_ix; - } - } - if (out_length > 0){ - DEBUG_API(printk("create_input_descriptors: not enough room for output, %d remained\n", out_length)); - err = -EINVAL; - goto error_cleanup; - } - /* Set sync in last descriptor. */ - mi.sync = 1; - outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - - *id = head.next; - return 0; - - error_cleanup: - while (head.next) { - outdesc = head.next->next; - free_cdesc(head.next); - head.next = outdesc; - } - return err; -} - - -static int create_output_descriptors(struct cryptocop_operation *operation, int *iniov_ix, int *iniov_offset, size_t desc_len, struct cryptocop_dma_desc **current_out_cdesc, struct strcop_meta_out *meta_out, int alloc_flag) -{ - while (desc_len != 0) { - struct cryptocop_dma_desc *cdesc; - int rem_length = operation->tfrm_op.indata[*iniov_ix].iov_len - *iniov_offset; - int dlength = (desc_len < rem_length) ? desc_len : rem_length; - - cdesc = alloc_cdesc(alloc_flag); - if (!cdesc) { - DEBUG_API(printk("create_output_descriptors: alloc_cdesc\n")); - return -ENOMEM; - } - (*current_out_cdesc)->next = cdesc; - (*current_out_cdesc) = cdesc; - - cdesc->free_buf = NULL; - - cdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.indata[*iniov_ix].iov_base + *iniov_offset); - cdesc->dma_descr->after = cdesc->dma_descr->buf + dlength; - - assert(desc_len >= dlength); - desc_len -= dlength; - *iniov_offset += dlength; - if (*iniov_offset >= operation->tfrm_op.indata[*iniov_ix].iov_len) { - *iniov_offset = 0; - ++(*iniov_ix); - if (*iniov_ix > operation->tfrm_op.incount) { - DEBUG_API(printk("create_output_descriptors: not enough indata in operation.")); - return -EINVAL; - } - } - cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, (*meta_out)); - } /* while (desc_len != 0) */ - /* Last DMA descriptor gets a 'wait' bit to signal expected change in metadata. */ - (*current_out_cdesc)->dma_descr->wait = 1; /* This will set extraneous WAIT in some situations, e.g. when padding hashes and checksums. */ - - return 0; -} - - -static int append_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_dma_desc **current_in_cdesc, struct cryptocop_dma_desc **current_out_cdesc, struct cryptocop_tfrm_ctx *tc, int alloc_flag) -{ - DEBUG(printk("append_input_descriptors, tc=0x%p, unit_no=%d\n", tc, tc->unit_no)); - if (tc->tcfg) { - int failed = 0; - struct cryptocop_dma_desc *idescs = NULL; - DEBUG(printk("append_input_descriptors: pushing output, consumed %d produced %d bytes.\n", tc->consumed, tc->produced)); - if (tc->pad_descs) { - DEBUG(printk("append_input_descriptors: append pad descriptors to DMA out list.\n")); - while (tc->pad_descs) { - DEBUG(printk("append descriptor 0x%p\n", tc->pad_descs)); - (*current_out_cdesc)->next = tc->pad_descs; - tc->pad_descs = tc->pad_descs->next; - (*current_out_cdesc) = (*current_out_cdesc)->next; - } - } - - /* Setup and append output descriptors to DMA in list. */ - if (tc->unit_no == src_dma){ - /* mem2mem. Setup DMA in descriptors to discard all input prior to the requested mem2mem data. */ - struct strcop_meta_in mi = {.sync = 0, .dmasel = src_dma}; - unsigned int start_ix = tc->start_ix; - while (start_ix){ - unsigned int desclen = start_ix < MEM2MEM_DISCARD_BUF_LENGTH ? start_ix : MEM2MEM_DISCARD_BUF_LENGTH; - (*current_in_cdesc)->next = alloc_cdesc(alloc_flag); - if (!(*current_in_cdesc)->next){ - DEBUG_API(printk("append_input_descriptors: alloc_cdesc mem2mem discard failed\n")); - return -ENOMEM; - } - (*current_in_cdesc) = (*current_in_cdesc)->next; - (*current_in_cdesc)->dma_descr->buf = (char*)virt_to_phys(mem2mem_discard_buf); - (*current_in_cdesc)->dma_descr->after = (*current_in_cdesc)->dma_descr->buf + desclen; - (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - start_ix -= desclen; - } - mi.sync = 1; - (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi); - } - - failed = create_input_descriptors(operation, tc, &idescs, alloc_flag); - if (failed){ - DEBUG_API(printk("append_input_descriptors: output descriptor setup failed\n")); - return failed; - } - DEBUG(printk("append_input_descriptors: append output descriptors to DMA in list.\n")); - while (idescs) { - DEBUG(printk("append descriptor 0x%p\n", idescs)); - (*current_in_cdesc)->next = idescs; - idescs = idescs->next; - (*current_in_cdesc) = (*current_in_cdesc)->next; - } - } - return 0; -} - - - -static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struct cryptocop_int_operation **int_op, int alloc_flag) -{ - struct cryptocop_session *sess; - struct cryptocop_transform_ctx *tctx; - - struct cryptocop_tfrm_ctx digest_ctx = { - .previous_src = src_none, - .current_src = src_none, - .start_ix = 0, - .requires_padding = 1, - .strict_block_length = 0, - .hash_conf = 0, - .hash_mode = 0, - .ciph_conf = 0, - .cbcmode = 0, - .decrypt = 0, - .consumed = 0, - .produced = 0, - .pad_descs = NULL, - .active = 0, - .done = 0, - .prev_src = NULL, - .curr_src = NULL, - .tcfg = NULL}; - struct cryptocop_tfrm_ctx cipher_ctx = { - .previous_src = src_none, - .current_src = src_none, - .start_ix = 0, - .requires_padding = 0, - .strict_block_length = 1, - .hash_conf = 0, - .hash_mode = 0, - .ciph_conf = 0, - .cbcmode = 0, - .decrypt = 0, - .consumed = 0, - .produced = 0, - .pad_descs = NULL, - .active = 0, - .done = 0, - .prev_src = NULL, - .curr_src = NULL, - .tcfg = NULL}; - struct cryptocop_tfrm_ctx csum_ctx = { - .previous_src = src_none, - .current_src = src_none, - .start_ix = 0, - .blocklength = 2, - .requires_padding = 1, - .strict_block_length = 0, - .hash_conf = 0, - .hash_mode = 0, - .ciph_conf = 0, - .cbcmode = 0, - .decrypt = 0, - .consumed = 0, - .produced = 0, - .pad_descs = NULL, - .active = 0, - .done = 0, - .tcfg = NULL, - .prev_src = NULL, - .curr_src = NULL, - .unit_no = src_csum}; - struct cryptocop_tfrm_cfg *tcfg = operation->tfrm_op.tfrm_cfg; - - unsigned int indata_ix = 0; - - /* iovec accounting. */ - int iniov_ix = 0; - int iniov_offset = 0; - - /* Operation descriptor cfg traversal pointer. */ - struct cryptocop_desc *odsc; - - int failed = 0; - /* List heads for allocated descriptors. */ - struct cryptocop_dma_desc out_cdesc_head = {0}; - struct cryptocop_dma_desc in_cdesc_head = {0}; - - struct cryptocop_dma_desc *current_out_cdesc = &out_cdesc_head; - struct cryptocop_dma_desc *current_in_cdesc = &in_cdesc_head; - - struct cryptocop_tfrm_ctx *output_tc = NULL; - void *iop_alloc_ptr; - - assert(operation != NULL); - assert(int_op != NULL); - - DEBUG(printk("cryptocop_setup_dma_list: start\n")); - DEBUG(print_cryptocop_operation(operation)); - - sess = get_session(operation->sid); - if (!sess) { - DEBUG_API(printk("cryptocop_setup_dma_list: no session found for operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag); - if (!iop_alloc_ptr) { - DEBUG_API(printk("cryptocop_setup_dma_list: kmalloc cryptocop_int_operation\n")); - failed = -ENOMEM; - goto error_cleanup; - } - (*int_op) = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out)); - DEBUG(memset((*int_op), 0xff, sizeof(struct cryptocop_int_operation))); - (*int_op)->alloc_ptr = iop_alloc_ptr; - DEBUG(printk("cryptocop_setup_dma_list: *int_op=0x%p, alloc_ptr=0x%p\n", *int_op, (*int_op)->alloc_ptr)); - - (*int_op)->sid = operation->sid; - (*int_op)->cdesc_out = NULL; - (*int_op)->cdesc_in = NULL; - (*int_op)->tdes_mode = cryptocop_3des_ede; - (*int_op)->csum_mode = cryptocop_csum_le; - (*int_op)->ddesc_out = NULL; - (*int_op)->ddesc_in = NULL; - - /* Scan operation->tfrm_op.tfrm_cfg for bad configuration and set up the local contexts. */ - if (!tcfg) { - DEBUG_API(printk("cryptocop_setup_dma_list: no configured transforms in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - while (tcfg) { - tctx = get_transform_ctx(sess, tcfg->tid); - if (!tctx) { - DEBUG_API(printk("cryptocop_setup_dma_list: no transform id %d in session.\n", tcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - if (tcfg->inject_ix > operation->tfrm_op.outlen){ - DEBUG_API(printk("cryptocop_setup_dma_list: transform id %d inject_ix (%d) > operation->tfrm_op.outlen(%d)", tcfg->tid, tcfg->inject_ix, operation->tfrm_op.outlen)); - failed = -EINVAL; - goto error_cleanup; - } - switch (tctx->init.alg){ - case cryptocop_alg_mem2mem: - if (cipher_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - /* mem2mem is handled as a NULL cipher. */ - cipher_ctx.cbcmode = 0; - cipher_ctx.decrypt = 0; - cipher_ctx.blocklength = 1; - cipher_ctx.ciph_conf = 0; - cipher_ctx.unit_no = src_dma; - cipher_ctx.tcfg = tcfg; - cipher_ctx.tctx = tctx; - break; - case cryptocop_alg_des: - case cryptocop_alg_3des: - case cryptocop_alg_aes: - /* cipher */ - if (cipher_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - cipher_ctx.tcfg = tcfg; - cipher_ctx.tctx = tctx; - if (cipher_ctx.tcfg->flags & CRYPTOCOP_DECRYPT){ - cipher_ctx.decrypt = 1; - } - switch (tctx->init.cipher_mode) { - case cryptocop_cipher_mode_ecb: - cipher_ctx.cbcmode = 0; - break; - case cryptocop_cipher_mode_cbc: - cipher_ctx.cbcmode = 1; - break; - default: - DEBUG_API(printk("cryptocop_setup_dma_list: cipher_ctx, bad cipher mode==%d\n", tctx->init.cipher_mode)); - failed = -EINVAL; - goto error_cleanup; - } - DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx, set CBC mode==%d\n", cipher_ctx.cbcmode)); - switch (tctx->init.alg){ - case cryptocop_alg_des: - cipher_ctx.ciph_conf = 0; - cipher_ctx.unit_no = src_des; - cipher_ctx.blocklength = DES_BLOCK_LENGTH; - break; - case cryptocop_alg_3des: - cipher_ctx.ciph_conf = 1; - cipher_ctx.unit_no = src_des; - cipher_ctx.blocklength = DES_BLOCK_LENGTH; - break; - case cryptocop_alg_aes: - cipher_ctx.ciph_conf = 2; - cipher_ctx.unit_no = src_aes; - cipher_ctx.blocklength = AES_BLOCK_LENGTH; - break; - default: - panic("cryptocop_setup_dma_list: impossible algorithm %d\n", tctx->init.alg); - } - (*int_op)->tdes_mode = tctx->init.tdes_mode; - break; - case cryptocop_alg_md5: - case cryptocop_alg_sha1: - /* digest */ - if (digest_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple digests in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - digest_ctx.tcfg = tcfg; - digest_ctx.tctx = tctx; - digest_ctx.hash_mode = 0; /* Don't use explicit IV in this API. */ - switch (tctx->init.alg){ - case cryptocop_alg_md5: - digest_ctx.blocklength = MD5_BLOCK_LENGTH; - digest_ctx.unit_no = src_md5; - digest_ctx.hash_conf = 1; /* 1 => MD-5 */ - break; - case cryptocop_alg_sha1: - digest_ctx.blocklength = SHA1_BLOCK_LENGTH; - digest_ctx.unit_no = src_sha1; - digest_ctx.hash_conf = 0; /* 0 => SHA-1 */ - break; - default: - panic("cryptocop_setup_dma_list: impossible digest algorithm\n"); - } - break; - case cryptocop_alg_csum: - /* digest */ - if (csum_ctx.tcfg != NULL){ - DEBUG_API(printk("cryptocop_setup_dma_list: multiple checksums in operation.\n")); - failed = -EINVAL; - goto error_cleanup; - } - (*int_op)->csum_mode = tctx->init.csum_mode; - csum_ctx.tcfg = tcfg; - csum_ctx.tctx = tctx; - break; - default: - /* no algorithm. */ - DEBUG_API(printk("cryptocop_setup_dma_list: invalid algorithm %d specified in tfrm %d.\n", tctx->init.alg, tcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - tcfg = tcfg->next; - } - /* Download key if a cipher is used. */ - if (cipher_ctx.tcfg && (cipher_ctx.tctx->init.alg != cryptocop_alg_mem2mem)){ - struct cryptocop_dma_desc *key_desc = NULL; - - failed = setup_key_dl_desc(&cipher_ctx, &key_desc, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: setup key dl\n")); - goto error_cleanup; - } - current_out_cdesc->next = key_desc; - current_out_cdesc = key_desc; - indata_ix += (unsigned int)(key_desc->dma_descr->after - key_desc->dma_descr->buf); - - /* Download explicit IV if a cipher is used and CBC mode and explicit IV selected. */ - if ((cipher_ctx.tctx->init.cipher_mode == cryptocop_cipher_mode_cbc) && (cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV)) { - struct cryptocop_dma_desc *iv_desc = NULL; - - DEBUG(printk("cryptocop_setup_dma_list: setup cipher CBC IV descriptor.\n")); - - failed = setup_cipher_iv_desc(&cipher_ctx, &iv_desc, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: CBC IV descriptor.\n")); - goto error_cleanup; - } - current_out_cdesc->next = iv_desc; - current_out_cdesc = iv_desc; - indata_ix += (unsigned int)(iv_desc->dma_descr->after - iv_desc->dma_descr->buf); - } - } - - /* Process descriptors. */ - odsc = operation->tfrm_op.desc; - while (odsc) { - struct cryptocop_desc_cfg *dcfg = odsc->cfg; - struct strcop_meta_out meta_out = {0}; - size_t desc_len = odsc->length; - int active_count, eop_needed_count; - - output_tc = NULL; - - DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor\n")); - - while (dcfg) { - struct cryptocop_tfrm_ctx *tc = NULL; - - DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor configuration.\n")); - /* Get the local context for the transform and mark it as the output unit if it produces output. */ - if (digest_ctx.tcfg && (digest_ctx.tcfg->tid == dcfg->tid)){ - tc = &digest_ctx; - } else if (cipher_ctx.tcfg && (cipher_ctx.tcfg->tid == dcfg->tid)){ - tc = &cipher_ctx; - } else if (csum_ctx.tcfg && (csum_ctx.tcfg->tid == dcfg->tid)){ - tc = &csum_ctx; - } - if (!tc) { - DEBUG_API(printk("cryptocop_setup_dma_list: invalid transform %d specified in descriptor.\n", dcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - if (tc->done) { - DEBUG_API(printk("cryptocop_setup_dma_list: completed transform %d reused.\n", dcfg->tid)); - failed = -EINVAL; - goto error_cleanup; - } - if (!tc->active) { - tc->start_ix = indata_ix; - tc->active = 1; - } - - tc->previous_src = tc->current_src; - tc->prev_src = tc->curr_src; - /* Map source unit id to DMA source config. */ - switch (dcfg->src){ - case cryptocop_source_dma: - tc->current_src = src_dma; - break; - case cryptocop_source_des: - tc->current_src = src_des; - break; - case cryptocop_source_3des: - tc->current_src = src_des; - break; - case cryptocop_source_aes: - tc->current_src = src_aes; - break; - case cryptocop_source_md5: - case cryptocop_source_sha1: - case cryptocop_source_csum: - case cryptocop_source_none: - default: - /* We do not allow using accumulating style units (SHA-1, MD5, checksum) as sources to other units. - */ - DEBUG_API(printk("cryptocop_setup_dma_list: bad unit source configured %d.\n", dcfg->src)); - failed = -EINVAL; - goto error_cleanup; - } - if (tc->current_src != src_dma) { - /* Find the unit we are sourcing from. */ - if (digest_ctx.unit_no == tc->current_src){ - tc->curr_src = &digest_ctx; - } else if (cipher_ctx.unit_no == tc->current_src){ - tc->curr_src = &cipher_ctx; - } else if (csum_ctx.unit_no == tc->current_src){ - tc->curr_src = &csum_ctx; - } - if ((tc->curr_src == tc) && (tc->unit_no != src_dma)){ - DEBUG_API(printk("cryptocop_setup_dma_list: unit %d configured to source from itself.\n", tc->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - } else { - tc->curr_src = NULL; - } - - /* Detect source switch. */ - DEBUG(printk("cryptocop_setup_dma_list: tc->active=%d tc->unit_no=%d tc->current_src=%d tc->previous_src=%d, tc->curr_src=0x%p, tc->prev_srv=0x%p\n", tc->active, tc->unit_no, tc->current_src, tc->previous_src, tc->curr_src, tc->prev_src)); - if (tc->active && (tc->current_src != tc->previous_src)) { - /* Only allow source switch when both the old source unit and the new one have - * no pending data to process (i.e. the consumed length must be a multiple of the - * transform blocklength). */ - /* Note: if the src == NULL we are actually sourcing from DMA out. */ - if (((tc->prev_src != NULL) && (tc->prev_src->consumed % tc->prev_src->blocklength)) || - ((tc->curr_src != NULL) && (tc->curr_src->consumed % tc->curr_src->blocklength))) - { - DEBUG_API(printk("cryptocop_setup_dma_list: can only disconnect from or connect to a unit on a multiple of the blocklength, old: cons=%d, prod=%d, block=%d, new: cons=%d prod=%d, block=%d.\n", tc->prev_src ? tc->prev_src->consumed : INT_MIN, tc->prev_src ? tc->prev_src->produced : INT_MIN, tc->prev_src ? tc->prev_src->blocklength : INT_MIN, tc->curr_src ? tc->curr_src->consumed : INT_MIN, tc->curr_src ? tc->curr_src->produced : INT_MIN, tc->curr_src ? tc->curr_src->blocklength : INT_MIN)); - failed = -EINVAL; - goto error_cleanup; - } - } - /* Detect unit deactivation. */ - if (dcfg->last) { - /* Length check of this is handled below. */ - tc->done = 1; - } - dcfg = dcfg->next; - } /* while (dcfg) */ - DEBUG(printk("cryptocop_setup_dma_list: parsing operation descriptor configuration complete.\n")); - - if (cipher_ctx.active && (cipher_ctx.curr_src != NULL) && !cipher_ctx.curr_src->active){ - DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", cipher_ctx.curr_src->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - if (digest_ctx.active && (digest_ctx.curr_src != NULL) && !digest_ctx.curr_src->active){ - DEBUG_API(printk("cryptocop_setup_dma_list: digest source from inactive unit %d\n", digest_ctx.curr_src->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - if (csum_ctx.active && (csum_ctx.curr_src != NULL) && !csum_ctx.curr_src->active){ - DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", csum_ctx.curr_src->unit_no)); - failed = -EINVAL; - goto error_cleanup; - } - - /* Update consumed and produced lengths. - - The consumed length accounting here is actually cheating. If a unit source from DMA (or any - other unit that process data in blocks of one octet) it is correct, but if it source from a - block processing unit, i.e. a cipher, it will be temporarily incorrect at some times. However - since it is only allowed--by the HW--to change source to or from a block processing unit at times where that - unit has processed an exact multiple of its block length the end result will be correct. - Beware that if the source change restriction change this code will need to be (much) reworked. - */ - DEBUG(printk("cryptocop_setup_dma_list: desc->length=%d, desc_len=%d.\n", odsc->length, desc_len)); - - if (csum_ctx.active) { - csum_ctx.consumed += desc_len; - if (csum_ctx.done) { - csum_ctx.produced = 2; - } - DEBUG(printk("cryptocop_setup_dma_list: csum_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", csum_ctx.consumed, csum_ctx.produced, csum_ctx.blocklength)); - } - if (digest_ctx.active) { - digest_ctx.consumed += desc_len; - if (digest_ctx.done) { - if (digest_ctx.unit_no == src_md5) { - digest_ctx.produced = MD5_STATE_LENGTH; - } else { - digest_ctx.produced = SHA1_STATE_LENGTH; - } - } - DEBUG(printk("cryptocop_setup_dma_list: digest_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", digest_ctx.consumed, digest_ctx.produced, digest_ctx.blocklength)); - } - if (cipher_ctx.active) { - /* Ciphers are allowed only to source from DMA out. That is filtered above. */ - assert(cipher_ctx.current_src == src_dma); - cipher_ctx.consumed += desc_len; - cipher_ctx.produced = cipher_ctx.blocklength * (cipher_ctx.consumed / cipher_ctx.blocklength); - if (cipher_ctx.cbcmode && !(cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV) && cipher_ctx.produced){ - cipher_ctx.produced -= cipher_ctx.blocklength; /* Compensate for CBC iv. */ - } - DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", cipher_ctx.consumed, cipher_ctx.produced, cipher_ctx.blocklength)); - } - - /* Setup the DMA out descriptors. */ - /* Configure the metadata. */ - active_count = 0; - eop_needed_count = 0; - if (cipher_ctx.active) { - ++active_count; - if (cipher_ctx.unit_no == src_dma){ - /* mem2mem */ - meta_out.ciphsel = src_none; - } else { - meta_out.ciphsel = cipher_ctx.current_src; - } - meta_out.ciphconf = cipher_ctx.ciph_conf; - meta_out.cbcmode = cipher_ctx.cbcmode; - meta_out.decrypt = cipher_ctx.decrypt; - DEBUG(printk("set ciphsel=%d ciphconf=%d cbcmode=%d decrypt=%d\n", meta_out.ciphsel, meta_out.ciphconf, meta_out.cbcmode, meta_out.decrypt)); - if (cipher_ctx.done) ++eop_needed_count; - } else { - meta_out.ciphsel = src_none; - } - - if (digest_ctx.active) { - ++active_count; - meta_out.hashsel = digest_ctx.current_src; - meta_out.hashconf = digest_ctx.hash_conf; - meta_out.hashmode = 0; /* Explicit mode is not used here. */ - DEBUG(printk("set hashsel=%d hashconf=%d hashmode=%d\n", meta_out.hashsel, meta_out.hashconf, meta_out.hashmode)); - if (digest_ctx.done) { - assert(digest_ctx.pad_descs == NULL); - failed = create_pad_descriptor(&digest_ctx, &digest_ctx.pad_descs, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: failed digest pad creation.\n")); - goto error_cleanup; - } - } - } else { - meta_out.hashsel = src_none; - } - - if (csum_ctx.active) { - ++active_count; - meta_out.csumsel = csum_ctx.current_src; - if (csum_ctx.done) { - assert(csum_ctx.pad_descs == NULL); - failed = create_pad_descriptor(&csum_ctx, &csum_ctx.pad_descs, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: failed csum pad creation.\n")); - goto error_cleanup; - } - } - } else { - meta_out.csumsel = src_none; - } - DEBUG(printk("cryptocop_setup_dma_list: %d eop needed, %d active units\n", eop_needed_count, active_count)); - /* Setup DMA out descriptors for the indata. */ - failed = create_output_descriptors(operation, &iniov_ix, &iniov_offset, desc_len, ¤t_out_cdesc, &meta_out, alloc_flag); - if (failed) { - DEBUG_API(printk("cryptocop_setup_dma_list: create_output_descriptors %d\n", failed)); - goto error_cleanup; - } - /* Setup out EOP. If there are active units that are not done here they cannot get an EOP - * so we ust setup a zero length descriptor to DMA to signal EOP only to done units. - * If there is a pad descriptor EOP for the padded unit will be EOPed by it. - */ - assert(active_count >= eop_needed_count); - assert((eop_needed_count == 0) || (eop_needed_count == 1)); - if (eop_needed_count) { - /* This means that the bulk operation (cipher/m2m) is terminated. */ - if (active_count > 1) { - /* Use zero length EOP descriptor. */ - struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag); - struct strcop_meta_out ed_mo = {0}; - if (!ed) { - DEBUG_API(printk("cryptocop_setup_dma_list: alloc EOP descriptor for cipher\n")); - failed = -ENOMEM; - goto error_cleanup; - } - - assert(cipher_ctx.active && cipher_ctx.done); - - if (cipher_ctx.unit_no == src_dma){ - /* mem2mem */ - ed_mo.ciphsel = src_none; - } else { - ed_mo.ciphsel = cipher_ctx.current_src; - } - ed_mo.ciphconf = cipher_ctx.ciph_conf; - ed_mo.cbcmode = cipher_ctx.cbcmode; - ed_mo.decrypt = cipher_ctx.decrypt; - - ed->free_buf = NULL; - ed->dma_descr->wait = 1; - ed->dma_descr->out_eop = 1; - - ed->dma_descr->buf = (char*)virt_to_phys(&ed); /* Use any valid physical address for zero length descriptor. */ - ed->dma_descr->after = ed->dma_descr->buf; - ed->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, ed_mo); - current_out_cdesc->next = ed; - current_out_cdesc = ed; - } else { - /* Set EOP in the current out descriptor since the only active module is - * the one needing the EOP. */ - - current_out_cdesc->dma_descr->out_eop = 1; - } - } - - if (cipher_ctx.done && cipher_ctx.active) cipher_ctx.active = 0; - if (digest_ctx.done && digest_ctx.active) digest_ctx.active = 0; - if (csum_ctx.done && csum_ctx.active) csum_ctx.active = 0; - indata_ix += odsc->length; - odsc = odsc->next; - } /* while (odsc) */ /* Process descriptors. */ - DEBUG(printk("cryptocop_setup_dma_list: done parsing operation descriptors\n")); - if (cipher_ctx.tcfg && (cipher_ctx.active || !cipher_ctx.done)){ - DEBUG_API(printk("cryptocop_setup_dma_list: cipher operation not terminated.\n")); - failed = -EINVAL; - goto error_cleanup; - } - if (digest_ctx.tcfg && (digest_ctx.active || !digest_ctx.done)){ - DEBUG_API(printk("cryptocop_setup_dma_list: digest operation not terminated.\n")); - failed = -EINVAL; - goto error_cleanup; - } - if (csum_ctx.tcfg && (csum_ctx.active || !csum_ctx.done)){ - DEBUG_API(printk("cryptocop_setup_dma_list: csum operation not terminated.\n")); - failed = -EINVAL; - goto error_cleanup; - } - - failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &cipher_ctx, alloc_flag); - if (failed){ - DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); - goto error_cleanup; - } - failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &digest_ctx, alloc_flag); - if (failed){ - DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); - goto error_cleanup; - } - failed = append_input_descriptors(operation, ¤t_in_cdesc, ¤t_out_cdesc, &csum_ctx, alloc_flag); - if (failed){ - DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed)); - goto error_cleanup; - } - - DEBUG(printk("cryptocop_setup_dma_list: int_op=0x%p, *int_op=0x%p\n", int_op, *int_op)); - (*int_op)->cdesc_out = out_cdesc_head.next; - (*int_op)->cdesc_in = in_cdesc_head.next; - DEBUG(printk("cryptocop_setup_dma_list: out_cdesc_head=0x%p in_cdesc_head=0x%p\n", (*int_op)->cdesc_out, (*int_op)->cdesc_in)); - - setup_descr_chain(out_cdesc_head.next); - setup_descr_chain(in_cdesc_head.next); - - /* Last but not least: mark the last DMA in descriptor for a INTR and EOL and the the - * last DMA out descriptor for EOL. - */ - current_in_cdesc->dma_descr->intr = 1; - current_in_cdesc->dma_descr->eol = 1; - current_out_cdesc->dma_descr->eol = 1; - - /* Setup DMA contexts. */ - (*int_op)->ctx_out.next = NULL; - (*int_op)->ctx_out.eol = 1; - (*int_op)->ctx_out.intr = 0; - (*int_op)->ctx_out.store_mode = 0; - (*int_op)->ctx_out.en = 0; - (*int_op)->ctx_out.dis = 0; - (*int_op)->ctx_out.md0 = 0; - (*int_op)->ctx_out.md1 = 0; - (*int_op)->ctx_out.md2 = 0; - (*int_op)->ctx_out.md3 = 0; - (*int_op)->ctx_out.md4 = 0; - (*int_op)->ctx_out.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_out->dma_descr); - (*int_op)->ctx_out.saved_data_buf = (*int_op)->cdesc_out->dma_descr->buf; /* Already physical address. */ - - (*int_op)->ctx_in.next = NULL; - (*int_op)->ctx_in.eol = 1; - (*int_op)->ctx_in.intr = 0; - (*int_op)->ctx_in.store_mode = 0; - (*int_op)->ctx_in.en = 0; - (*int_op)->ctx_in.dis = 0; - (*int_op)->ctx_in.md0 = 0; - (*int_op)->ctx_in.md1 = 0; - (*int_op)->ctx_in.md2 = 0; - (*int_op)->ctx_in.md3 = 0; - (*int_op)->ctx_in.md4 = 0; - - (*int_op)->ctx_in.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_in->dma_descr); - (*int_op)->ctx_in.saved_data_buf = (*int_op)->cdesc_in->dma_descr->buf; /* Already physical address. */ - - DEBUG(printk("cryptocop_setup_dma_list: done\n")); - return 0; - -error_cleanup: - { - /* Free all allocated resources. */ - struct cryptocop_dma_desc *tmp_cdesc; - while (digest_ctx.pad_descs){ - tmp_cdesc = digest_ctx.pad_descs->next; - free_cdesc(digest_ctx.pad_descs); - digest_ctx.pad_descs = tmp_cdesc; - } - while (csum_ctx.pad_descs){ - tmp_cdesc = csum_ctx.pad_descs->next; - free_cdesc(csum_ctx.pad_descs); - csum_ctx.pad_descs = tmp_cdesc; - } - assert(cipher_ctx.pad_descs == NULL); /* The ciphers are never padded. */ - - if (*int_op != NULL) delete_internal_operation(*int_op); - } - DEBUG_API(printk("cryptocop_setup_dma_list: done with error %d\n", failed)); - return failed; -} - - -static void delete_internal_operation(struct cryptocop_int_operation *iop) -{ - void *ptr = iop->alloc_ptr; - struct cryptocop_dma_desc *cd = iop->cdesc_out; - struct cryptocop_dma_desc *next; - - DEBUG(printk("delete_internal_operation: iop=0x%p, alloc_ptr=0x%p\n", iop, ptr)); - - while (cd) { - next = cd->next; - free_cdesc(cd); - cd = next; - } - cd = iop->cdesc_in; - while (cd) { - next = cd->next; - free_cdesc(cd); - cd = next; - } - kfree(ptr); -} - -#define MD5_MIN_PAD_LENGTH (9) -#define MD5_PAD_LENGTH_FIELD_LENGTH (8) - -static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length) -{ - size_t padlen = MD5_BLOCK_LENGTH - (hashed_length % MD5_BLOCK_LENGTH); - unsigned char *p; - int i; - unsigned long long int bit_length = hashed_length << 3; - - if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH; - - p = kzalloc(padlen, alloc_flag); - if (!p) return -ENOMEM; - - *p = 0x80; - - DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); - - i = padlen - MD5_PAD_LENGTH_FIELD_LENGTH; - while (bit_length != 0){ - p[i++] = bit_length % 0x100; - bit_length >>= 8; - } - - *pad = (char*)p; - *pad_length = padlen; - - return 0; -} - -#define SHA1_MIN_PAD_LENGTH (9) -#define SHA1_PAD_LENGTH_FIELD_LENGTH (8) - -static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length) -{ - size_t padlen = SHA1_BLOCK_LENGTH - (hashed_length % SHA1_BLOCK_LENGTH); - unsigned char *p; - int i; - unsigned long long int bit_length = hashed_length << 3; - - if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH; - - p = kzalloc(padlen, alloc_flag); - if (!p) return -ENOMEM; - - *p = 0x80; - - DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length)); - - i = padlen - 1; - while (bit_length != 0){ - p[i--] = bit_length % 0x100; - bit_length >>= 8; - } - - *pad = (char*)p; - *pad_length = padlen; - - return 0; -} - - -static int transform_ok(struct cryptocop_transform_init *tinit) -{ - switch (tinit->alg){ - case cryptocop_alg_csum: - switch (tinit->csum_mode){ - case cryptocop_csum_le: - case cryptocop_csum_be: - break; - default: - DEBUG_API(printk("transform_ok: Bad mode set for csum transform\n")); - return -EINVAL; - } - case cryptocop_alg_mem2mem: - case cryptocop_alg_md5: - case cryptocop_alg_sha1: - if (tinit->keylen != 0) { - DEBUG_API(printk("transform_ok: non-zero keylength, %d, for a digest/csum algorithm\n", tinit->keylen)); - return -EINVAL; /* This check is a bit strict. */ - } - break; - case cryptocop_alg_des: - if (tinit->keylen != 64) { - DEBUG_API(printk("transform_ok: keylen %d invalid for DES\n", tinit->keylen)); - return -EINVAL; - } - break; - case cryptocop_alg_3des: - if (tinit->keylen != 192) { - DEBUG_API(printk("transform_ok: keylen %d invalid for 3DES\n", tinit->keylen)); - return -EINVAL; - } - break; - case cryptocop_alg_aes: - if (tinit->keylen != 128 && tinit->keylen != 192 && tinit->keylen != 256) { - DEBUG_API(printk("transform_ok: keylen %d invalid for AES\n", tinit->keylen)); - return -EINVAL; - } - break; - case cryptocop_no_alg: - default: - DEBUG_API(printk("transform_ok: no such algorithm %d\n", tinit->alg)); - return -EINVAL; - } - - switch (tinit->alg){ - case cryptocop_alg_des: - case cryptocop_alg_3des: - case cryptocop_alg_aes: - if (tinit->cipher_mode != cryptocop_cipher_mode_ecb && tinit->cipher_mode != cryptocop_cipher_mode_cbc) return -EINVAL; - default: - break; - } - return 0; -} - - -int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag) -{ - struct cryptocop_session *sess; - struct cryptocop_transform_init *tfrm_in = tinit; - struct cryptocop_transform_init *tmp_in; - int no_tfrms = 0; - int i; - unsigned long int flags; - - init_stream_coprocessor(); /* For safety if we are called early */ - - while (tfrm_in){ - int err; - ++no_tfrms; - if ((err = transform_ok(tfrm_in))) { - DEBUG_API(printk("cryptocop_new_session, bad transform\n")); - return err; - } - tfrm_in = tfrm_in->next; - } - if (0 == no_tfrms) { - DEBUG_API(printk("cryptocop_new_session, no transforms specified\n")); - return -EINVAL; - } - - sess = kmalloc(sizeof(struct cryptocop_session), alloc_flag); - if (!sess){ - DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_session\n")); - return -ENOMEM; - } - - sess->tfrm_ctx = kmalloc(no_tfrms * sizeof(struct cryptocop_transform_ctx), alloc_flag); - if (!sess->tfrm_ctx) { - DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_transform_ctx\n")); - kfree(sess); - return -ENOMEM; - } - - tfrm_in = tinit; - for (i = 0; i < no_tfrms; i++){ - tmp_in = tfrm_in->next; - while (tmp_in){ - if (tmp_in->tid == tfrm_in->tid) { - DEBUG_API(printk("cryptocop_new_session, duplicate transform ids\n")); - kfree(sess->tfrm_ctx); - kfree(sess); - return -EINVAL; - } - tmp_in = tmp_in->next; - } - memcpy(&sess->tfrm_ctx[i].init, tfrm_in, sizeof(struct cryptocop_transform_init)); - sess->tfrm_ctx[i].dec_key_set = 0; - sess->tfrm_ctx[i].next = &sess->tfrm_ctx[i] + 1; - - tfrm_in = tfrm_in->next; - } - sess->tfrm_ctx[i-1].next = NULL; - - spin_lock_irqsave(&cryptocop_sessions_lock, flags); - sess->sid = next_sid; - next_sid++; - /* TODO If we are really paranoid we should do duplicate check to handle sid wraparound. - * OTOH 2^64 is a really large number of session. */ - if (next_sid == 0) next_sid = 1; - - /* Prepend to session list. */ - sess->next = cryptocop_sessions; - cryptocop_sessions = sess; - spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); - *sid = sess->sid; - return 0; -} - - -int cryptocop_free_session(cryptocop_session_id sid) -{ - struct cryptocop_transform_ctx *tc; - struct cryptocop_session *sess = NULL; - struct cryptocop_session *psess = NULL; - unsigned long int flags; - int i; - LIST_HEAD(remove_list); - struct list_head *node, *tmp; - struct cryptocop_prio_job *pj; - - DEBUG(printk("cryptocop_free_session: sid=%lld\n", sid)); - - spin_lock_irqsave(&cryptocop_sessions_lock, flags); - sess = cryptocop_sessions; - while (sess && sess->sid != sid){ - psess = sess; - sess = sess->next; - } - if (sess){ - if (psess){ - psess->next = sess->next; - } else { - cryptocop_sessions = sess->next; - } - } - spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); - - if (!sess) return -EINVAL; - - /* Remove queued jobs. */ - spin_lock_irqsave(&cryptocop_job_queue_lock, flags); - - for (i = 0; i < cryptocop_prio_no_prios; i++){ - if (!list_empty(&(cryptocop_job_queues[i].jobs))){ - list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) { - pj = list_entry(node, struct cryptocop_prio_job, node); - if (pj->oper->sid == sid) { - list_move_tail(node, &remove_list); - } - } - } - } - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - - list_for_each_safe(node, tmp, &remove_list) { - list_del(node); - pj = list_entry(node, struct cryptocop_prio_job, node); - pj->oper->operation_status = -EAGAIN; /* EAGAIN is not ideal for job/session terminated but it's the best choice I know of. */ - DEBUG(printk("cryptocop_free_session: pj=0x%p, pj->oper=0x%p, pj->iop=0x%p\n", pj, pj->oper, pj->iop)); - pj->oper->cb(pj->oper, pj->oper->cb_data); - delete_internal_operation(pj->iop); - kfree(pj); - } - - tc = sess->tfrm_ctx; - /* Erase keying data. */ - while (tc){ - DEBUG(printk("cryptocop_free_session: memset keys, tfrm id=%d\n", tc->init.tid)); - memset(tc->init.key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH); - memset(tc->dec_key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH); - tc = tc->next; - } - kfree(sess->tfrm_ctx); - kfree(sess); - - return 0; -} - -static struct cryptocop_session *get_session(cryptocop_session_id sid) -{ - struct cryptocop_session *sess; - unsigned long int flags; - - spin_lock_irqsave(&cryptocop_sessions_lock, flags); - sess = cryptocop_sessions; - while (sess && (sess->sid != sid)){ - sess = sess->next; - } - spin_unlock_irqrestore(&cryptocop_sessions_lock, flags); - - return sess; -} - -static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid) -{ - struct cryptocop_transform_ctx *tc = sess->tfrm_ctx; - - DEBUG(printk("get_transform_ctx, sess=0x%p, tid=%d\n", sess, tid)); - assert(sess != NULL); - while (tc && tc->init.tid != tid){ - DEBUG(printk("tc=0x%p, tc->next=0x%p\n", tc, tc->next)); - tc = tc->next; - } - DEBUG(printk("get_transform_ctx, returning tc=0x%p\n", tc)); - return tc; -} - - - -/* The AES s-transform matrix (s-box). */ -static const u8 aes_sbox[256] = { - 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, - 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, - 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, - 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, - 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, - 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, - 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, - 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, - 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, - 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, - 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, - 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, - 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, - 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, - 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, - 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22 -}; - -/* AES has a 32 bit word round constants for each round in the - * key schedule. round_constant[i] is really Rcon[i+1] in FIPS187. - */ -static u32 round_constant[11] = { - 0x01000000, 0x02000000, 0x04000000, 0x08000000, - 0x10000000, 0x20000000, 0x40000000, 0x80000000, - 0x1B000000, 0x36000000, 0x6C000000 -}; - -/* Apply the s-box to each of the four occtets in w. */ -static u32 aes_ks_subword(const u32 w) -{ - u8 bytes[4]; - - *(u32*)(&bytes[0]) = w; - bytes[0] = aes_sbox[bytes[0]]; - bytes[1] = aes_sbox[bytes[1]]; - bytes[2] = aes_sbox[bytes[2]]; - bytes[3] = aes_sbox[bytes[3]]; - return *(u32*)(&bytes[0]); -} - -/* The encrypt (forward) Rijndael key schedule algorithm pseudo code: - * (Note that AES words are 32 bit long) - * - * KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk){ - * word temp - * i = 0 - * while (i < Nk) { - * w[i] = word(key[4*i, 4*i + 1, 4*i + 2, 4*i + 3]) - * i = i + 1 - * } - * i = Nk - * - * while (i < (Nb * (Nr + 1))) { - * temp = w[i - 1] - * if ((i mod Nk) == 0) { - * temp = SubWord(RotWord(temp)) xor Rcon[i/Nk] - * } - * else if ((Nk > 6) && ((i mod Nk) == 4)) { - * temp = SubWord(temp) - * } - * w[i] = w[i - Nk] xor temp - * } - * RotWord(t) does a 8 bit cyclic shift left on a 32 bit word. - * SubWord(t) applies the AES s-box individually to each octet - * in a 32 bit word. - * - * For AES Nk can have the values 4, 6, and 8 (corresponding to - * values for Nr of 10, 12, and 14). Nb is always 4. - * - * To construct w[i], w[i - 1] and w[i - Nk] must be - * available. Consequently we must keep a state of the last Nk words - * to be able to create the last round keys. - */ -static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength) -{ - u32 temp; - u32 w_ring[8]; /* nk is max 8, use elements 0..(nk - 1) as a ringbuffer */ - u8 w_last_ix; - int i; - u8 nr, nk; - - switch (keylength){ - case 128: - nk = 4; - nr = 10; - break; - case 192: - nk = 6; - nr = 12; - break; - case 256: - nk = 8; - nr = 14; - break; - default: - panic("stream co-processor: bad aes key length in get_aes_decrypt_key\n"); - }; - - /* Need to do host byte order correction here since key is byte oriented and the - * kx algorithm is word (u32) oriented. */ - for (i = 0; i < nk; i+=1) { - w_ring[i] = be32_to_cpu(*(u32*)&key[4*i]); - } - - i = (int)nk; - w_last_ix = i - 1; - while (i < (4 * (nr + 2))) { - temp = w_ring[w_last_ix]; - if (!(i % nk)) { - /* RotWord(temp) */ - temp = (temp << 8) | (temp >> 24); - temp = aes_ks_subword(temp); - temp ^= round_constant[i/nk - 1]; - } else if ((nk > 6) && ((i % nk) == 4)) { - temp = aes_ks_subword(temp); - } - w_last_ix = (w_last_ix + 1) % nk; /* This is the same as (i-Nk) mod Nk */ - temp ^= w_ring[w_last_ix]; - w_ring[w_last_ix] = temp; - - /* We need the round keys for round Nr+1 and Nr+2 (round key - * Nr+2 is the round key beyond the last one used when - * encrypting). Rounds are numbered starting from 0, Nr=10 - * implies 11 rounds are used in encryption/decryption. - */ - if (i >= (4 * nr)) { - /* Need to do host byte order correction here, the key - * is byte oriented. */ - *(u32*)dec_key = cpu_to_be32(temp); - dec_key += 4; - } - ++i; - } -} - - -/**** Job/operation management. ****/ - -int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation) -{ - return cryptocop_job_queue_insert(cryptocop_prio_kernel_csum, operation); -} - -int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation) -{ - return cryptocop_job_queue_insert(cryptocop_prio_kernel, operation); -} - -int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation) -{ - return cryptocop_job_queue_insert(cryptocop_prio_user, operation); -} - -static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation) -{ - int ret; - struct cryptocop_prio_job *pj = NULL; - unsigned long int flags; - - DEBUG(printk("cryptocop_job_queue_insert(%d, 0x%p)\n", prio, operation)); - - if (!operation || !operation->cb){ - DEBUG_API(printk("cryptocop_job_queue_insert oper=0x%p, NULL operation or callback\n", operation)); - return -EINVAL; - } - - if ((ret = cryptocop_job_setup(&pj, operation)) != 0){ - DEBUG_API(printk("cryptocop_job_queue_insert: job setup failed\n")); - return ret; - } - assert(pj != NULL); - - spin_lock_irqsave(&cryptocop_job_queue_lock, flags); - list_add_tail(&pj->node, &cryptocop_job_queues[prio].jobs); - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - - /* Make sure a job is running */ - cryptocop_start_job(); - return 0; -} - -static void cryptocop_do_tasklet(unsigned long unused); -DECLARE_TASKLET (cryptocop_tasklet, cryptocop_do_tasklet, 0); - -static void cryptocop_do_tasklet(unsigned long unused) -{ - struct list_head *node; - struct cryptocop_prio_job *pj = NULL; - unsigned long flags; - - DEBUG(printk("cryptocop_do_tasklet: entering\n")); - - do { - spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags); - if (!list_empty(&cryptocop_completed_jobs)){ - node = cryptocop_completed_jobs.next; - list_del(node); - pj = list_entry(node, struct cryptocop_prio_job, node); - } else { - pj = NULL; - } - spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags); - if (pj) { - assert(pj->oper != NULL); - - /* Notify consumer of operation completeness. */ - DEBUG(printk("cryptocop_do_tasklet: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - - pj->oper->operation_status = 0; /* Job is completed. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - delete_internal_operation(pj->iop); - kfree(pj); - } - } while (pj != NULL); - - DEBUG(printk("cryptocop_do_tasklet: exiting\n")); -} - -static irqreturn_t -dma_done_interrupt(int irq, void *dev_id) -{ - struct cryptocop_prio_job *done_job; - reg_dma_rw_ack_intr ack_intr = { - .data = 1, - }; - - REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); - - DEBUG(printk("cryptocop DMA done\n")); - - spin_lock(&running_job_lock); - if (cryptocop_running_job == NULL){ - printk("stream co-processor got interrupt when not busy\n"); - spin_unlock(&running_job_lock); - return IRQ_HANDLED; - } - done_job = cryptocop_running_job; - cryptocop_running_job = NULL; - spin_unlock(&running_job_lock); - - /* Start processing a job. */ - if (!spin_trylock(&cryptocop_process_lock)){ - DEBUG(printk("cryptocop irq handler, not starting a job\n")); - } else { - cryptocop_start_job(); - spin_unlock(&cryptocop_process_lock); - } - - done_job->oper->operation_status = 0; /* Job is completed. */ - if (done_job->oper->fast_callback){ - /* This operation wants callback from interrupt. */ - done_job->oper->cb(done_job->oper, done_job->oper->cb_data); - delete_internal_operation(done_job->iop); - kfree(done_job); - } else { - spin_lock(&cryptocop_completed_jobs_lock); - list_add_tail(&(done_job->node), &cryptocop_completed_jobs); - spin_unlock(&cryptocop_completed_jobs_lock); - tasklet_schedule(&cryptocop_tasklet); - } - - DEBUG(printk("cryptocop leave irq handler\n")); - return IRQ_HANDLED; -} - - -/* Setup interrupts and DMA channels. */ -static int init_cryptocop(void) -{ - unsigned long flags; - reg_dma_rw_cfg dma_cfg = {.en = 1}; - reg_dma_rw_intr_mask intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */ - reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 }; - reg_strcop_rw_cfg strcop_cfg = { - .ipend = regk_strcop_little, - .td1 = regk_strcop_e, - .td2 = regk_strcop_d, - .td3 = regk_strcop_e, - .ignore_sync = 0, - .en = 1 - }; - - if (request_irq(DMA_IRQ, dma_done_interrupt, 0, - "stream co-processor DMA", NULL)) - panic("request_irq stream co-processor irq dma9"); - - (void)crisv32_request_dma(OUT_DMA, "strcop", DMA_PANIC_ON_ERROR, - 0, dma_strp); - (void)crisv32_request_dma(IN_DMA, "strcop", DMA_PANIC_ON_ERROR, - 0, dma_strp); - - local_irq_save(flags); - - /* Reset and enable the cryptocop. */ - strcop_cfg.en = 0; - REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); - strcop_cfg.en = 1; - REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); - - /* Enable DMAs. */ - REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ - REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ - - /* Set up wordsize = 4 for DMAs. */ - DMA_WR_CMD(OUT_DMA_INST, regk_dma_set_w_size4); - DMA_WR_CMD(IN_DMA_INST, regk_dma_set_w_size4); - - /* Enable interrupts. */ - REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); - - /* Clear intr ack. */ - REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); - - local_irq_restore(flags); - - return 0; -} - -/* Free used cryptocop hw resources (interrupt and DMA channels). */ -static void release_cryptocop(void) -{ - unsigned long flags; - reg_dma_rw_cfg dma_cfg = {.en = 0}; - reg_dma_rw_intr_mask intr_mask_in = {0}; - reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 }; - - local_irq_save(flags); - - /* Clear intr ack. */ - REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); - - /* Disable DMAs. */ - REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ - REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ - - /* Disable interrupts. */ - REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); - - local_irq_restore(flags); - - free_irq(DMA_IRQ, NULL); - - (void)crisv32_free_dma(OUT_DMA); - (void)crisv32_free_dma(IN_DMA); -} - - -/* Init job queue. */ -static int cryptocop_job_queue_init(void) -{ - int i; - - INIT_LIST_HEAD(&cryptocop_completed_jobs); - - for (i = 0; i < cryptocop_prio_no_prios; i++){ - cryptocop_job_queues[i].prio = (cryptocop_queue_priority)i; - INIT_LIST_HEAD(&cryptocop_job_queues[i].jobs); - } - return 0; -} - - -static void cryptocop_job_queue_close(void) -{ - struct list_head *node, *tmp; - struct cryptocop_prio_job *pj = NULL; - unsigned long int process_flags, flags; - int i; - - /* FIXME: This is as yet untested code. */ - - /* Stop strcop from getting an operation to process while we are closing the - module. */ - spin_lock_irqsave(&cryptocop_process_lock, process_flags); - - /* Empty the job queue. */ - for (i = 0; i < cryptocop_prio_no_prios; i++){ - if (!list_empty(&(cryptocop_job_queues[i].jobs))){ - list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) { - pj = list_entry(node, struct cryptocop_prio_job, node); - list_del(node); - - /* Call callback to notify consumer of job removal. */ - DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - - delete_internal_operation(pj->iop); - kfree(pj); - } - } - } - spin_unlock_irqrestore(&cryptocop_process_lock, process_flags); - - /* Remove the running job, if any. */ - spin_lock_irqsave(&running_job_lock, flags); - if (cryptocop_running_job){ - reg_strcop_rw_cfg rw_cfg; - reg_dma_rw_cfg dma_out_cfg, dma_in_cfg; - - /* Stop DMA. */ - dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg); - dma_out_cfg.en = regk_dma_no; - REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_out_cfg); - - dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg); - dma_in_cfg.en = regk_dma_no; - REG_WR(dma, IN_DMA_INST, rw_cfg, dma_in_cfg); - - /* Disable the cryptocop. */ - rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg); - rw_cfg.en = 0; - REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); - - pj = cryptocop_running_job; - cryptocop_running_job = NULL; - - /* Call callback to notify consumer of job removal. */ - DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - - delete_internal_operation(pj->iop); - kfree(pj); - } - spin_unlock_irqrestore(&running_job_lock, flags); - - /* Remove completed jobs, if any. */ - spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags); - - list_for_each_safe(node, tmp, &cryptocop_completed_jobs) { - pj = list_entry(node, struct cryptocop_prio_job, node); - list_del(node); - /* Call callback to notify consumer of job removal. */ - DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data)); - pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */ - pj->oper->cb(pj->oper, pj->oper->cb_data); - - delete_internal_operation(pj->iop); - kfree(pj); - } - spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags); -} - - -static void cryptocop_start_job(void) -{ - int i; - struct cryptocop_prio_job *pj; - unsigned long int flags; - unsigned long int running_job_flags; - reg_strcop_rw_cfg rw_cfg = {.en = 1, .ignore_sync = 0}; - - DEBUG(printk("cryptocop_start_job: entering\n")); - - spin_lock_irqsave(&running_job_lock, running_job_flags); - if (cryptocop_running_job != NULL){ - /* Already running. */ - DEBUG(printk("cryptocop_start_job: already running, exit\n")); - spin_unlock_irqrestore(&running_job_lock, running_job_flags); - return; - } - spin_lock_irqsave(&cryptocop_job_queue_lock, flags); - - /* Check the queues in priority order. */ - for (i = cryptocop_prio_kernel_csum; (i < cryptocop_prio_no_prios) && list_empty(&cryptocop_job_queues[i].jobs); i++); - if (i == cryptocop_prio_no_prios) { - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - spin_unlock_irqrestore(&running_job_lock, running_job_flags); - DEBUG(printk("cryptocop_start_job: no jobs to run\n")); - return; /* No jobs to run */ - } - DEBUG(printk("starting job for prio %d\n", i)); - - /* TODO: Do not starve lower priority jobs. Let in a lower - * prio job for every N-th processed higher prio job or some - * other scheduling policy. This could reasonably be - * tweakable since the optimal balance would depend on the - * type of load on the system. */ - - /* Pull the DMA lists from the job and start the DMA client. */ - pj = list_entry(cryptocop_job_queues[i].jobs.next, struct cryptocop_prio_job, node); - list_del(&pj->node); - spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags); - cryptocop_running_job = pj; - - /* Set config register (3DES and CSUM modes). */ - switch (pj->iop->tdes_mode){ - case cryptocop_3des_eee: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_eed: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_d; - break; - case cryptocop_3des_ede: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_edd: - rw_cfg.td1 = regk_strcop_e; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_d; - break; - case cryptocop_3des_dee: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_ded: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_e; - rw_cfg.td3 = regk_strcop_d; - break; - case cryptocop_3des_dde: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_e; - break; - case cryptocop_3des_ddd: - rw_cfg.td1 = regk_strcop_d; - rw_cfg.td2 = regk_strcop_d; - rw_cfg.td3 = regk_strcop_d; - break; - default: - DEBUG(printk("cryptocop_setup_dma_list: bad 3DES mode\n")); - } - switch (pj->iop->csum_mode){ - case cryptocop_csum_le: - rw_cfg.ipend = regk_strcop_little; - break; - case cryptocop_csum_be: - rw_cfg.ipend = regk_strcop_big; - break; - default: - DEBUG(printk("cryptocop_setup_dma_list: bad checksum mode\n")); - } - REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); - - DEBUG(printk("cryptocop_start_job: starting DMA, new cryptocop_running_job=0x%p\n" - "ctx_in: 0x%p, phys: 0x%p\n" - "ctx_out: 0x%p, phys: 0x%p\n", - pj, - &pj->iop->ctx_in, (char*)virt_to_phys(&pj->iop->ctx_in), - &pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out))); - - /* Start input DMA. */ - flush_dma_context(&pj->iop->ctx_in); - DMA_START_CONTEXT(IN_DMA_INST, virt_to_phys(&pj->iop->ctx_in)); - - /* Start output DMA. */ - DMA_START_CONTEXT(OUT_DMA_INST, virt_to_phys(&pj->iop->ctx_out)); - - spin_unlock_irqrestore(&running_job_lock, running_job_flags); - DEBUG(printk("cryptocop_start_job: exiting\n")); -} - - -static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation) -{ - int err; - int alloc_flag = operation->in_interrupt ? GFP_ATOMIC : GFP_KERNEL; - void *iop_alloc_ptr = NULL; - - *pj = kmalloc(sizeof (struct cryptocop_prio_job), alloc_flag); - if (!*pj) return -ENOMEM; - - DEBUG(printk("cryptocop_job_setup: operation=0x%p\n", operation)); - - (*pj)->oper = operation; - DEBUG(printk("cryptocop_job_setup, cb=0x%p cb_data=0x%p\n", (*pj)->oper->cb, (*pj)->oper->cb_data)); - - if (operation->use_dmalists) { - DEBUG(print_user_dma_lists(&operation->list_op)); - if (!operation->list_op.inlist || !operation->list_op.outlist || !operation->list_op.out_data_buf || !operation->list_op.in_data_buf){ - DEBUG_API(printk("cryptocop_job_setup: bad indata (use_dmalists)\n")); - kfree(*pj); - return -EINVAL; - } - iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag); - if (!iop_alloc_ptr) { - DEBUG_API(printk("cryptocop_job_setup: kmalloc cryptocop_int_operation\n")); - kfree(*pj); - return -ENOMEM; - } - (*pj)->iop = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out)); - DEBUG(memset((*pj)->iop, 0xff, sizeof(struct cryptocop_int_operation))); - (*pj)->iop->alloc_ptr = iop_alloc_ptr; - (*pj)->iop->sid = operation->sid; - (*pj)->iop->cdesc_out = NULL; - (*pj)->iop->cdesc_in = NULL; - (*pj)->iop->tdes_mode = operation->list_op.tdes_mode; - (*pj)->iop->csum_mode = operation->list_op.csum_mode; - (*pj)->iop->ddesc_out = operation->list_op.outlist; - (*pj)->iop->ddesc_in = operation->list_op.inlist; - - /* Setup DMA contexts. */ - (*pj)->iop->ctx_out.next = NULL; - (*pj)->iop->ctx_out.eol = 1; - (*pj)->iop->ctx_out.saved_data = operation->list_op.outlist; - (*pj)->iop->ctx_out.saved_data_buf = operation->list_op.out_data_buf; - - (*pj)->iop->ctx_in.next = NULL; - (*pj)->iop->ctx_in.eol = 1; - (*pj)->iop->ctx_in.saved_data = operation->list_op.inlist; - (*pj)->iop->ctx_in.saved_data_buf = operation->list_op.in_data_buf; - } else { - if ((err = cryptocop_setup_dma_list(operation, &(*pj)->iop, alloc_flag))) { - DEBUG_API(printk("cryptocop_job_setup: cryptocop_setup_dma_list failed %d\n", err)); - kfree(*pj); - return err; - } - } - DEBUG(print_dma_descriptors((*pj)->iop)); - - DEBUG(printk("cryptocop_job_setup, DMA list setup successful\n")); - - return 0; -} - -static int cryptocop_open(struct inode *inode, struct file *filp) -{ - int p = iminor(inode); - - if (p != CRYPTOCOP_MINOR) return -EINVAL; - - filp->private_data = NULL; - return 0; -} - - -static int cryptocop_release(struct inode *inode, struct file *filp) -{ - struct cryptocop_private *dev = filp->private_data; - struct cryptocop_private *dev_next; - - while (dev){ - dev_next = dev->next; - if (dev->sid != CRYPTOCOP_SESSION_ID_NONE) { - (void)cryptocop_free_session(dev->sid); - } - kfree(dev); - dev = dev_next; - } - - return 0; -} - - -static int cryptocop_ioctl_close_session(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) -{ - struct cryptocop_private *dev = filp->private_data; - struct cryptocop_private *prev_dev = NULL; - struct strcop_session_op *sess_op = (struct strcop_session_op *)arg; - struct strcop_session_op sop; - int err; - - DEBUG(printk("cryptocop_ioctl_close_session\n")); - - if (!access_ok(VERIFY_READ, sess_op, sizeof(struct strcop_session_op))) - return -EFAULT; - err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op)); - if (err) return -EFAULT; - - while (dev && (dev->sid != sop.ses_id)) { - prev_dev = dev; - dev = dev->next; - } - if (dev){ - if (prev_dev){ - prev_dev->next = dev->next; - } else { - filp->private_data = dev->next; - } - err = cryptocop_free_session(dev->sid); - if (err) return -EFAULT; - } else { - DEBUG_API(printk("cryptocop_ioctl_close_session: session %lld not found\n", sop.ses_id)); - return -EINVAL; - } - return 0; -} - - -static void ioctl_process_job_callback(struct cryptocop_operation *op, void*cb_data) -{ - struct ioctl_job_cb_ctx *jc = (struct ioctl_job_cb_ctx *)cb_data; - - DEBUG(printk("ioctl_process_job_callback: op=0x%p, cb_data=0x%p\n", op, cb_data)); - - jc->processed = 1; - wake_up(&cryptocop_ioc_process_wq); -} - - -#define CRYPTOCOP_IOCTL_CIPHER_TID (1) -#define CRYPTOCOP_IOCTL_DIGEST_TID (2) -#define CRYPTOCOP_IOCTL_CSUM_TID (3) - -static size_t first_cfg_change_ix(struct strcop_crypto_op *crp_op) -{ - size_t ch_ix = 0; - - if (crp_op->do_cipher) ch_ix = crp_op->cipher_start; - if (crp_op->do_digest && (crp_op->digest_start < ch_ix)) ch_ix = crp_op->digest_start; - if (crp_op->do_csum && (crp_op->csum_start < ch_ix)) ch_ix = crp_op->csum_start; - - DEBUG(printk("first_cfg_change_ix: ix=%d\n", ch_ix)); - return ch_ix; -} - - -static size_t next_cfg_change_ix(struct strcop_crypto_op *crp_op, size_t ix) -{ - size_t ch_ix = INT_MAX; - size_t tmp_ix = 0; - - if (crp_op->do_cipher && ((crp_op->cipher_start + crp_op->cipher_len) > ix)){ - if (crp_op->cipher_start > ix) { - ch_ix = crp_op->cipher_start; - } else { - ch_ix = crp_op->cipher_start + crp_op->cipher_len; - } - } - if (crp_op->do_digest && ((crp_op->digest_start + crp_op->digest_len) > ix)){ - if (crp_op->digest_start > ix) { - tmp_ix = crp_op->digest_start; - } else { - tmp_ix = crp_op->digest_start + crp_op->digest_len; - } - if (tmp_ix < ch_ix) ch_ix = tmp_ix; - } - if (crp_op->do_csum && ((crp_op->csum_start + crp_op->csum_len) > ix)){ - if (crp_op->csum_start > ix) { - tmp_ix = crp_op->csum_start; - } else { - tmp_ix = crp_op->csum_start + crp_op->csum_len; - } - if (tmp_ix < ch_ix) ch_ix = tmp_ix; - } - if (ch_ix == INT_MAX) ch_ix = ix; - DEBUG(printk("next_cfg_change_ix prev ix=%d, next ix=%d\n", ix, ch_ix)); - return ch_ix; -} - - -/* Map map_length bytes from the pages starting on *pageix and *pageoffset to iovecs starting on *iovix. - * Return -1 for ok, 0 for fail. */ -static int map_pages_to_iovec(struct iovec *iov, int iovlen, int *iovix, struct page **pages, int nopages, int *pageix, int *pageoffset, int map_length ) -{ - int tmplen; - - assert(iov != NULL); - assert(iovix != NULL); - assert(pages != NULL); - assert(pageix != NULL); - assert(pageoffset != NULL); - - DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset)); - - while (map_length > 0){ - DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset)); - if (*iovix >= iovlen){ - DEBUG_API(printk("map_page_to_iovec: *iovix=%d >= iovlen=%d\n", *iovix, iovlen)); - return 0; - } - if (*pageix >= nopages){ - DEBUG_API(printk("map_page_to_iovec: *pageix=%d >= nopages=%d\n", *pageix, nopages)); - return 0; - } - iov[*iovix].iov_base = (unsigned char*)page_address(pages[*pageix]) + *pageoffset; - tmplen = PAGE_SIZE - *pageoffset; - if (tmplen < map_length){ - (*pageoffset) = 0; - (*pageix)++; - } else { - tmplen = map_length; - (*pageoffset) += map_length; - } - DEBUG(printk("mapping %d bytes from page %d (or %d) to iovec %d\n", tmplen, *pageix, *pageix-1, *iovix)); - iov[*iovix].iov_len = tmplen; - map_length -= tmplen; - (*iovix)++; - } - DEBUG(printk("map_page_to_iovec, exit, *iovix=%d\n", *iovix)); - return -1; -} - - - -static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - int i; - struct cryptocop_private *dev = filp->private_data; - struct strcop_crypto_op *crp_oper = (struct strcop_crypto_op *)arg; - struct strcop_crypto_op oper = {0}; - int err = 0; - struct cryptocop_operation *cop = NULL; - - struct ioctl_job_cb_ctx *jc = NULL; - - struct page **inpages = NULL; - struct page **outpages = NULL; - int noinpages = 0; - int nooutpages = 0; - - struct cryptocop_desc descs[5]; /* Max 5 descriptors are needed, there are three transforms that - * can get connected/disconnected on different places in the indata. */ - struct cryptocop_desc_cfg dcfgs[5*3]; - int desc_ix = 0; - int dcfg_ix = 0; - struct cryptocop_tfrm_cfg ciph_tcfg = {0}; - struct cryptocop_tfrm_cfg digest_tcfg = {0}; - struct cryptocop_tfrm_cfg csum_tcfg = {0}; - - unsigned char *digest_result = NULL; - int digest_length = 0; - int cblocklen = 0; - unsigned char csum_result[CSUM_BLOCK_LENGTH]; - struct cryptocop_session *sess; - - int iovlen = 0; - int iovix = 0; - int pageix = 0; - int pageoffset = 0; - - size_t prev_ix = 0; - size_t next_ix; - - int cipher_active, digest_active, csum_active; - int end_digest, end_csum; - int digest_done = 0; - int cipher_done = 0; - int csum_done = 0; - - DEBUG(printk("cryptocop_ioctl_process\n")); - - if (!access_ok(VERIFY_WRITE, crp_oper, sizeof(struct strcop_crypto_op))){ - DEBUG_API(printk("cryptocop_ioctl_process: !access_ok crp_oper!\n")); - return -EFAULT; - } - if (copy_from_user(&oper, crp_oper, sizeof(struct strcop_crypto_op))) { - DEBUG_API(printk("cryptocop_ioctl_process: copy_from_user\n")); - return -EFAULT; - } - DEBUG(print_strcop_crypto_op(&oper)); - - while (dev && dev->sid != oper.ses_id) dev = dev->next; - if (!dev){ - DEBUG_API(printk("cryptocop_ioctl_process: session %lld not found\n", oper.ses_id)); - return -EINVAL; - } - - /* Check buffers. */ - if (((oper.indata + oper.inlen) < oper.indata) || ((oper.cipher_outdata + oper.cipher_outlen) < oper.cipher_outdata)){ - DEBUG_API(printk("cryptocop_ioctl_process: user buffers wrapped around, bad user!\n")); - return -EINVAL; - } - - if (!access_ok(VERIFY_WRITE, oper.cipher_outdata, oper.cipher_outlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: !access_ok out data!\n")); - return -EFAULT; - } - if (!access_ok(VERIFY_READ, oper.indata, oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: !access_ok in data!\n")); - return -EFAULT; - } - - cop = kmalloc(sizeof(struct cryptocop_operation), GFP_KERNEL); - if (!cop) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n")); - return -ENOMEM; - } - jc = kmalloc(sizeof(struct ioctl_job_cb_ctx), GFP_KERNEL); - if (!jc) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n")); - err = -ENOMEM; - goto error_cleanup; - } - jc->processed = 0; - - cop->cb_data = jc; - cop->cb = ioctl_process_job_callback; - cop->operation_status = 0; - cop->use_dmalists = 0; - cop->in_interrupt = 0; - cop->fast_callback = 0; - cop->tfrm_op.tfrm_cfg = NULL; - cop->tfrm_op.desc = NULL; - cop->tfrm_op.indata = NULL; - cop->tfrm_op.incount = 0; - cop->tfrm_op.inlen = 0; - cop->tfrm_op.outdata = NULL; - cop->tfrm_op.outcount = 0; - cop->tfrm_op.outlen = 0; - - sess = get_session(oper.ses_id); - if (!sess){ - DEBUG_API(printk("cryptocop_ioctl_process: bad session id.\n")); - kfree(cop); - kfree(jc); - return -EINVAL; - } - - if (oper.do_cipher) { - unsigned int cipher_outlen = 0; - struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_CIPHER_TID); - if (!tc) { - DEBUG_API(printk("cryptocop_ioctl_process: no cipher transform in session.\n")); - err = -EINVAL; - goto error_cleanup; - } - ciph_tcfg.tid = CRYPTOCOP_IOCTL_CIPHER_TID; - ciph_tcfg.inject_ix = 0; - ciph_tcfg.flags = 0; - if ((oper.cipher_start < 0) || (oper.cipher_len <= 0) || (oper.cipher_start > oper.inlen) || ((oper.cipher_start + oper.cipher_len) > oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: bad cipher length\n")); - kfree(cop); - kfree(jc); - return -EINVAL; - } - cblocklen = tc->init.alg == cryptocop_alg_aes ? AES_BLOCK_LENGTH : DES_BLOCK_LENGTH; - if (oper.cipher_len % cblocklen) { - kfree(cop); - kfree(jc); - DEBUG_API(printk("cryptocop_ioctl_process: cipher inlength not multiple of block length.\n")); - return -EINVAL; - } - cipher_outlen = oper.cipher_len; - if (tc->init.cipher_mode == cryptocop_cipher_mode_cbc){ - if (oper.cipher_explicit) { - ciph_tcfg.flags |= CRYPTOCOP_EXPLICIT_IV; - memcpy(ciph_tcfg.iv, oper.cipher_iv, cblocklen); - } else { - cipher_outlen = oper.cipher_len - cblocklen; - } - } else { - if (oper.cipher_explicit){ - kfree(cop); - kfree(jc); - DEBUG_API(printk("cryptocop_ioctl_process: explicit_iv when not CBC mode\n")); - return -EINVAL; - } - } - if (oper.cipher_outlen != cipher_outlen) { - kfree(cop); - kfree(jc); - DEBUG_API(printk("cryptocop_ioctl_process: cipher_outlen incorrect, should be %d not %d.\n", cipher_outlen, oper.cipher_outlen)); - return -EINVAL; - } - - if (oper.decrypt){ - ciph_tcfg.flags |= CRYPTOCOP_DECRYPT; - } else { - ciph_tcfg.flags |= CRYPTOCOP_ENCRYPT; - } - ciph_tcfg.next = cop->tfrm_op.tfrm_cfg; - cop->tfrm_op.tfrm_cfg = &ciph_tcfg; - } - if (oper.do_digest){ - struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_DIGEST_TID); - if (!tc) { - DEBUG_API(printk("cryptocop_ioctl_process: no digest transform in session.\n")); - err = -EINVAL; - goto error_cleanup; - } - digest_length = tc->init.alg == cryptocop_alg_md5 ? 16 : 20; - digest_result = kmalloc(digest_length, GFP_KERNEL); - if (!digest_result) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc digest_result\n")); - err = -EINVAL; - goto error_cleanup; - } - DEBUG(memset(digest_result, 0xff, digest_length)); - - digest_tcfg.tid = CRYPTOCOP_IOCTL_DIGEST_TID; - digest_tcfg.inject_ix = 0; - ciph_tcfg.inject_ix += digest_length; - if ((oper.digest_start < 0) || (oper.digest_len <= 0) || (oper.digest_start > oper.inlen) || ((oper.digest_start + oper.digest_len) > oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: bad digest length\n")); - err = -EINVAL; - goto error_cleanup; - } - - digest_tcfg.next = cop->tfrm_op.tfrm_cfg; - cop->tfrm_op.tfrm_cfg = &digest_tcfg; - } - if (oper.do_csum){ - csum_tcfg.tid = CRYPTOCOP_IOCTL_CSUM_TID; - csum_tcfg.inject_ix = digest_length; - ciph_tcfg.inject_ix += 2; - - if ((oper.csum_start < 0) || (oper.csum_len <= 0) || (oper.csum_start > oper.inlen) || ((oper.csum_start + oper.csum_len) > oper.inlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: bad csum length\n")); - kfree(cop); - kfree(jc); - return -EINVAL; - } - - csum_tcfg.next = cop->tfrm_op.tfrm_cfg; - cop->tfrm_op.tfrm_cfg = &csum_tcfg; - } - - prev_ix = first_cfg_change_ix(&oper); - if (prev_ix > oper.inlen) { - DEBUG_API(printk("cryptocop_ioctl_process: length mismatch\n")); - nooutpages = noinpages = 0; - err = -EINVAL; - goto error_cleanup; - } - DEBUG(printk("cryptocop_ioctl_process: inlen=%d, cipher_outlen=%d\n", oper.inlen, oper.cipher_outlen)); - - /* Map user pages for in and out data of the operation. */ - noinpages = (((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK) + oper.inlen - 1 - prev_ix + ~PAGE_MASK) >> PAGE_SHIFT; - DEBUG(printk("cryptocop_ioctl_process: noinpages=%d\n", noinpages)); - inpages = kmalloc(noinpages * sizeof(struct page*), GFP_KERNEL); - if (!inpages){ - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc inpages\n")); - nooutpages = noinpages = 0; - err = -ENOMEM; - goto error_cleanup; - } - if (oper.do_cipher){ - nooutpages = (((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) + oper.cipher_outlen - 1 + ~PAGE_MASK) >> PAGE_SHIFT; - DEBUG(printk("cryptocop_ioctl_process: nooutpages=%d\n", nooutpages)); - outpages = kmalloc(nooutpages * sizeof(struct page*), GFP_KERNEL); - if (!outpages){ - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc outpages\n")); - nooutpages = noinpages = 0; - err = -ENOMEM; - goto error_cleanup; - } - } - - err = get_user_pages_fast((unsigned long)(oper.indata + prev_ix), - noinpages, - false, /* read access only for in data */ - inpages); - - if (err < 0) { - nooutpages = noinpages = 0; - DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages indata\n")); - goto error_cleanup; - } - noinpages = err; - if (oper.do_cipher) { - err = get_user_pages_fast((unsigned long)oper.cipher_outdata, - nooutpages, - true, /* write access for out data */ - outpages); - if (err < 0) { - nooutpages = 0; - DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages outdata\n")); - goto error_cleanup; - } - nooutpages = err; - } - - /* Add 6 to nooutpages to make room for possibly inserted buffers for storing digest and - * csum output and splits when units are (dis-)connected. */ - cop->tfrm_op.indata = kmalloc((noinpages) * sizeof(struct iovec), GFP_KERNEL); - cop->tfrm_op.outdata = kmalloc((6 + nooutpages) * sizeof(struct iovec), GFP_KERNEL); - if (!cop->tfrm_op.indata || !cop->tfrm_op.outdata) { - DEBUG_API(printk("cryptocop_ioctl_process: kmalloc iovecs\n")); - err = -ENOMEM; - goto error_cleanup; - } - - cop->tfrm_op.inlen = oper.inlen - prev_ix; - cop->tfrm_op.outlen = 0; - if (oper.do_cipher) cop->tfrm_op.outlen += oper.cipher_outlen; - if (oper.do_digest) cop->tfrm_op.outlen += digest_length; - if (oper.do_csum) cop->tfrm_op.outlen += 2; - - /* Setup the in iovecs. */ - cop->tfrm_op.incount = noinpages; - if (noinpages > 1){ - size_t tmplen = cop->tfrm_op.inlen; - - cop->tfrm_op.indata[0].iov_len = PAGE_SIZE - ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); - cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); - tmplen -= cop->tfrm_op.indata[0].iov_len; - for (i = 1; itfrm_op.indata[i].iov_len = tmplen < PAGE_SIZE ? tmplen : PAGE_SIZE; - cop->tfrm_op.indata[i].iov_base = (unsigned char*)page_address(inpages[i]); - tmplen -= PAGE_SIZE; - } - } else { - cop->tfrm_op.indata[0].iov_len = oper.inlen - prev_ix; - cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK); - } - - iovlen = nooutpages + 6; - pageoffset = oper.do_cipher ? ((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) : 0; - - next_ix = next_cfg_change_ix(&oper, prev_ix); - if (prev_ix == next_ix){ - DEBUG_API(printk("cryptocop_ioctl_process: length configuration broken.\n")); - err = -EINVAL; /* This should be impossible barring bugs. */ - goto error_cleanup; - } - while (prev_ix != next_ix){ - end_digest = end_csum = cipher_active = digest_active = csum_active = 0; - descs[desc_ix].cfg = NULL; - descs[desc_ix].length = next_ix - prev_ix; - - if (oper.do_cipher && (oper.cipher_start < next_ix) && (prev_ix < (oper.cipher_start + oper.cipher_len))) { - dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CIPHER_TID; - dcfgs[dcfg_ix].src = cryptocop_source_dma; - cipher_active = 1; - - if (next_ix == (oper.cipher_start + oper.cipher_len)){ - cipher_done = 1; - dcfgs[dcfg_ix].last = 1; - } else { - dcfgs[dcfg_ix].last = 0; - } - dcfgs[dcfg_ix].next = descs[desc_ix].cfg; - descs[desc_ix].cfg = &dcfgs[dcfg_ix]; - ++dcfg_ix; - } - if (oper.do_digest && (oper.digest_start < next_ix) && (prev_ix < (oper.digest_start + oper.digest_len))) { - digest_active = 1; - dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_DIGEST_TID; - dcfgs[dcfg_ix].src = cryptocop_source_dma; - if (next_ix == (oper.digest_start + oper.digest_len)){ - assert(!digest_done); - digest_done = 1; - dcfgs[dcfg_ix].last = 1; - } else { - dcfgs[dcfg_ix].last = 0; - } - dcfgs[dcfg_ix].next = descs[desc_ix].cfg; - descs[desc_ix].cfg = &dcfgs[dcfg_ix]; - ++dcfg_ix; - } - if (oper.do_csum && (oper.csum_start < next_ix) && (prev_ix < (oper.csum_start + oper.csum_len))){ - csum_active = 1; - dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CSUM_TID; - dcfgs[dcfg_ix].src = cryptocop_source_dma; - if (next_ix == (oper.csum_start + oper.csum_len)){ - csum_done = 1; - dcfgs[dcfg_ix].last = 1; - } else { - dcfgs[dcfg_ix].last = 0; - } - dcfgs[dcfg_ix].next = descs[desc_ix].cfg; - descs[desc_ix].cfg = &dcfgs[dcfg_ix]; - ++dcfg_ix; - } - if (!descs[desc_ix].cfg){ - DEBUG_API(printk("cryptocop_ioctl_process: data segment %d (%d to %d) had no active transforms\n", desc_ix, prev_ix, next_ix)); - err = -EINVAL; - goto error_cleanup; - } - descs[desc_ix].next = &(descs[desc_ix]) + 1; - ++desc_ix; - prev_ix = next_ix; - next_ix = next_cfg_change_ix(&oper, prev_ix); - } - if (desc_ix > 0){ - descs[desc_ix-1].next = NULL; - } else { - descs[0].next = NULL; - } - if (oper.do_digest) { - DEBUG(printk("cryptocop_ioctl_process: mapping %d byte digest output to iovec %d\n", digest_length, iovix)); - /* Add outdata iovec, length == */ - cop->tfrm_op.outdata[iovix].iov_base = digest_result; - cop->tfrm_op.outdata[iovix].iov_len = digest_length; - ++iovix; - } - if (oper.do_csum) { - /* Add outdata iovec, length == 2, the length of csum. */ - DEBUG(printk("cryptocop_ioctl_process: mapping 2 byte csum output to iovec %d\n", iovix)); - /* Add outdata iovec, length == */ - cop->tfrm_op.outdata[iovix].iov_base = csum_result; - cop->tfrm_op.outdata[iovix].iov_len = 2; - ++iovix; - } - if (oper.do_cipher) { - if (!map_pages_to_iovec(cop->tfrm_op.outdata, iovlen, &iovix, outpages, nooutpages, &pageix, &pageoffset, oper.cipher_outlen)){ - DEBUG_API(printk("cryptocop_ioctl_process: failed to map pages to iovec.\n")); - err = -ENOSYS; /* This should be impossible barring bugs. */ - goto error_cleanup; - } - } - DEBUG(printk("cryptocop_ioctl_process: setting cop->tfrm_op.outcount %d\n", iovix)); - cop->tfrm_op.outcount = iovix; - assert(iovix <= (nooutpages + 6)); - - cop->sid = oper.ses_id; - cop->tfrm_op.desc = &descs[0]; - - DEBUG(printk("cryptocop_ioctl_process: inserting job, cb_data=0x%p\n", cop->cb_data)); - - if ((err = cryptocop_job_queue_insert_user_job(cop)) != 0) { - DEBUG_API(printk("cryptocop_ioctl_process: insert job %d\n", err)); - err = -EINVAL; - goto error_cleanup; - } - - DEBUG(printk("cryptocop_ioctl_process: begin wait for result\n")); - - wait_event(cryptocop_ioc_process_wq, (jc->processed != 0)); - DEBUG(printk("cryptocop_ioctl_process: end wait for result\n")); - if (!jc->processed){ - printk(KERN_WARNING "cryptocop_ioctl_process: job not processed at completion\n"); - err = -EIO; - goto error_cleanup; - } - - /* Job process done. Cipher output should already be correct in job so no post processing of outdata. */ - DEBUG(printk("cryptocop_ioctl_process: operation_status = %d\n", cop->operation_status)); - if (cop->operation_status == 0){ - if (oper.do_digest){ - DEBUG(printk("cryptocop_ioctl_process: copy %d bytes digest to user\n", digest_length)); - err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, digest), digest_result, digest_length); - if (0 != err){ - DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, digest length %d, err %d\n", digest_length, err)); - err = -EFAULT; - goto error_cleanup; - } - } - if (oper.do_csum){ - DEBUG(printk("cryptocop_ioctl_process: copy 2 bytes checksum to user\n")); - err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, csum), csum_result, 2); - if (0 != err){ - DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, csum, err %d\n", err)); - err = -EFAULT; - goto error_cleanup; - } - } - err = 0; - } else { - DEBUG(printk("cryptocop_ioctl_process: returning err = operation_status = %d\n", cop->operation_status)); - err = cop->operation_status; - } - - error_cleanup: - /* Release page caches. */ - for (i = 0; i < noinpages; i++){ - put_page(inpages[i]); - } - for (i = 0; i < nooutpages; i++){ - int spdl_err; - /* Mark output pages dirty. */ - spdl_err = set_page_dirty_lock(outpages[i]); - DEBUG(if (spdl_err < 0)printk("cryptocop_ioctl_process: set_page_dirty_lock returned %d\n", spdl_err)); - } - for (i = 0; i < nooutpages; i++){ - put_page(outpages[i]); - } - - kfree(digest_result); - kfree(inpages); - kfree(outpages); - if (cop){ - kfree(cop->tfrm_op.indata); - kfree(cop->tfrm_op.outdata); - kfree(cop); - } - kfree(jc); - - DEBUG(print_lock_status()); - - return err; -} - - -static int cryptocop_ioctl_create_session(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) -{ - cryptocop_session_id sid; - int err; - struct cryptocop_private *dev; - struct strcop_session_op *sess_op = (struct strcop_session_op *)arg; - struct strcop_session_op sop; - struct cryptocop_transform_init *tis = NULL; - struct cryptocop_transform_init ti_cipher = {0}; - struct cryptocop_transform_init ti_digest = {0}; - struct cryptocop_transform_init ti_csum = {0}; - - if (!access_ok(VERIFY_WRITE, sess_op, sizeof(struct strcop_session_op))) - return -EFAULT; - err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op)); - if (err) return -EFAULT; - if (sop.cipher != cryptocop_cipher_none) { - if (!access_ok(VERIFY_READ, sop.key, sop.keylen)) return -EFAULT; - } - DEBUG(printk("cryptocop_ioctl_create_session, sess_op:\n")); - - DEBUG(printk("\tcipher:%d\n" - "\tcipher_mode:%d\n" - "\tdigest:%d\n" - "\tcsum:%d\n", - (int)sop.cipher, - (int)sop.cmode, - (int)sop.digest, - (int)sop.csum)); - - if (sop.cipher != cryptocop_cipher_none){ - /* Init the cipher. */ - switch (sop.cipher){ - case cryptocop_cipher_des: - ti_cipher.alg = cryptocop_alg_des; - break; - case cryptocop_cipher_3des: - ti_cipher.alg = cryptocop_alg_3des; - break; - case cryptocop_cipher_aes: - ti_cipher.alg = cryptocop_alg_aes; - break; - default: - DEBUG_API(printk("create session, bad cipher algorithm %d\n", sop.cipher)); - return -EINVAL; - }; - DEBUG(printk("setting cipher transform %d\n", ti_cipher.alg)); - copy_from_user(ti_cipher.key, sop.key, sop.keylen/8); - ti_cipher.keylen = sop.keylen; - switch (sop.cmode){ - case cryptocop_cipher_mode_cbc: - case cryptocop_cipher_mode_ecb: - ti_cipher.cipher_mode = sop.cmode; - break; - default: - DEBUG_API(printk("create session, bad cipher mode %d\n", sop.cmode)); - return -EINVAL; - } - DEBUG(printk("cryptocop_ioctl_create_session: setting CBC mode %d\n", ti_cipher.cipher_mode)); - switch (sop.des3_mode){ - case cryptocop_3des_eee: - case cryptocop_3des_eed: - case cryptocop_3des_ede: - case cryptocop_3des_edd: - case cryptocop_3des_dee: - case cryptocop_3des_ded: - case cryptocop_3des_dde: - case cryptocop_3des_ddd: - ti_cipher.tdes_mode = sop.des3_mode; - break; - default: - DEBUG_API(printk("create session, bad 3DES mode %d\n", sop.des3_mode)); - return -EINVAL; - } - ti_cipher.tid = CRYPTOCOP_IOCTL_CIPHER_TID; - ti_cipher.next = tis; - tis = &ti_cipher; - } /* if (sop.cipher != cryptocop_cipher_none) */ - if (sop.digest != cryptocop_digest_none){ - DEBUG(printk("setting digest transform\n")); - switch (sop.digest){ - case cryptocop_digest_md5: - ti_digest.alg = cryptocop_alg_md5; - break; - case cryptocop_digest_sha1: - ti_digest.alg = cryptocop_alg_sha1; - break; - default: - DEBUG_API(printk("create session, bad digest algorithm %d\n", sop.digest)); - return -EINVAL; - } - ti_digest.tid = CRYPTOCOP_IOCTL_DIGEST_TID; - ti_digest.next = tis; - tis = &ti_digest; - } /* if (sop.digest != cryptocop_digest_none) */ - if (sop.csum != cryptocop_csum_none){ - DEBUG(printk("setting csum transform\n")); - switch (sop.csum){ - case cryptocop_csum_le: - case cryptocop_csum_be: - ti_csum.csum_mode = sop.csum; - break; - default: - DEBUG_API(printk("create session, bad checksum algorithm %d\n", sop.csum)); - return -EINVAL; - } - ti_csum.alg = cryptocop_alg_csum; - ti_csum.tid = CRYPTOCOP_IOCTL_CSUM_TID; - ti_csum.next = tis; - tis = &ti_csum; - } /* (sop.csum != cryptocop_csum_none) */ - dev = kmalloc(sizeof(struct cryptocop_private), GFP_KERNEL); - if (!dev){ - DEBUG_API(printk("create session, alloc dev\n")); - return -ENOMEM; - } - - err = cryptocop_new_session(&sid, tis, GFP_KERNEL); - DEBUG({ if (err) printk("create session, cryptocop_new_session %d\n", err);}); - - if (err) { - kfree(dev); - return err; - } - sess_op->ses_id = sid; - dev->sid = sid; - dev->next = filp->private_data; - filp->private_data = dev; - - return 0; -} - -static long cryptocop_ioctl_unlocked(struct inode *inode, - struct file *filp, unsigned int cmd, unsigned long arg) -{ - int err = 0; - if (_IOC_TYPE(cmd) != ETRAXCRYPTOCOP_IOCTYPE) { - DEBUG_API(printk("cryptocop_ioctl: wrong type\n")); - return -ENOTTY; - } - if (_IOC_NR(cmd) > CRYPTOCOP_IO_MAXNR){ - return -ENOTTY; - } - /* Access check of the argument. Some commands, e.g. create session and process op, - needs additional checks. Those are handled in the command handling functions. */ - if (_IOC_DIR(cmd) & _IOC_READ) - err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); - else if (_IOC_DIR(cmd) & _IOC_WRITE) - err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); - if (err) return -EFAULT; - - switch (cmd) { - case CRYPTOCOP_IO_CREATE_SESSION: - return cryptocop_ioctl_create_session(inode, filp, cmd, arg); - case CRYPTOCOP_IO_CLOSE_SESSION: - return cryptocop_ioctl_close_session(inode, filp, cmd, arg); - case CRYPTOCOP_IO_PROCESS_OP: - return cryptocop_ioctl_process(inode, filp, cmd, arg); - default: - DEBUG_API(printk("cryptocop_ioctl: unknown command\n")); - return -ENOTTY; - } - return 0; -} - -static long -cryptocop_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) -{ - long ret; - - mutex_lock(&cryptocop_mutex); - ret = cryptocop_ioctl_unlocked(file_inode(filp), filp, cmd, arg); - mutex_unlock(&cryptocop_mutex); - - return ret; -} - - -#ifdef LDEBUG -static void print_dma_descriptors(struct cryptocop_int_operation *iop) -{ - struct cryptocop_dma_desc *cdesc_out = iop->cdesc_out; - struct cryptocop_dma_desc *cdesc_in = iop->cdesc_in; - int i; - - printk("print_dma_descriptors start\n"); - - printk("iop:\n"); - printk("\tsid: 0x%llx\n", iop->sid); - - printk("\tcdesc_out: 0x%p\n", iop->cdesc_out); - printk("\tcdesc_in: 0x%p\n", iop->cdesc_in); - printk("\tddesc_out: 0x%p\n", iop->ddesc_out); - printk("\tddesc_in: 0x%p\n", iop->ddesc_in); - - printk("\niop->ctx_out: 0x%p phys: 0x%p\n", &iop->ctx_out, (char*)virt_to_phys(&iop->ctx_out)); - printk("\tnext: 0x%p\n" - "\tsaved_data: 0x%p\n" - "\tsaved_data_buf: 0x%p\n", - iop->ctx_out.next, - iop->ctx_out.saved_data, - iop->ctx_out.saved_data_buf); - - printk("\niop->ctx_in: 0x%p phys: 0x%p\n", &iop->ctx_in, (char*)virt_to_phys(&iop->ctx_in)); - printk("\tnext: 0x%p\n" - "\tsaved_data: 0x%p\n" - "\tsaved_data_buf: 0x%p\n", - iop->ctx_in.next, - iop->ctx_in.saved_data, - iop->ctx_in.saved_data_buf); - - i = 0; - while (cdesc_out) { - dma_descr_data *td; - printk("cdesc_out %d, desc=0x%p\n", i, cdesc_out->dma_descr); - printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_out->dma_descr)); - td = cdesc_out->dma_descr; - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - td->buf, - td->after, - td->md, - td->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - td->wait, - td->eol, - td->out_eop, - td->in_eop, - td->intr); - cdesc_out = cdesc_out->next; - i++; - } - i = 0; - while (cdesc_in) { - dma_descr_data *td; - printk("cdesc_in %d, desc=0x%p\n", i, cdesc_in->dma_descr); - printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_in->dma_descr)); - td = cdesc_in->dma_descr; - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - td->buf, - td->after, - td->md, - td->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - td->wait, - td->eol, - td->out_eop, - td->in_eop, - td->intr); - cdesc_in = cdesc_in->next; - i++; - } - - printk("print_dma_descriptors end\n"); -} - - -static void print_strcop_crypto_op(struct strcop_crypto_op *cop) -{ - printk("print_strcop_crypto_op, 0x%p\n", cop); - - /* Indata. */ - printk("indata=0x%p\n" - "inlen=%d\n" - "do_cipher=%d\n" - "decrypt=%d\n" - "cipher_explicit=%d\n" - "cipher_start=%d\n" - "cipher_len=%d\n" - "outdata=0x%p\n" - "outlen=%d\n", - cop->indata, - cop->inlen, - cop->do_cipher, - cop->decrypt, - cop->cipher_explicit, - cop->cipher_start, - cop->cipher_len, - cop->cipher_outdata, - cop->cipher_outlen); - - printk("do_digest=%d\n" - "digest_start=%d\n" - "digest_len=%d\n", - cop->do_digest, - cop->digest_start, - cop->digest_len); - - printk("do_csum=%d\n" - "csum_start=%d\n" - "csum_len=%d\n", - cop->do_csum, - cop->csum_start, - cop->csum_len); -} - -static void print_cryptocop_operation(struct cryptocop_operation *cop) -{ - struct cryptocop_desc *d; - struct cryptocop_tfrm_cfg *tc; - struct cryptocop_desc_cfg *dc; - int i; - - printk("print_cryptocop_operation, cop=0x%p\n\n", cop); - printk("sid: %lld\n", cop->sid); - printk("operation_status=%d\n" - "use_dmalists=%d\n" - "in_interrupt=%d\n" - "fast_callback=%d\n", - cop->operation_status, - cop->use_dmalists, - cop->in_interrupt, - cop->fast_callback); - - if (cop->use_dmalists){ - print_user_dma_lists(&cop->list_op); - } else { - printk("cop->tfrm_op\n" - "tfrm_cfg=0x%p\n" - "desc=0x%p\n" - "indata=0x%p\n" - "incount=%d\n" - "inlen=%d\n" - "outdata=0x%p\n" - "outcount=%d\n" - "outlen=%d\n\n", - cop->tfrm_op.tfrm_cfg, - cop->tfrm_op.desc, - cop->tfrm_op.indata, - cop->tfrm_op.incount, - cop->tfrm_op.inlen, - cop->tfrm_op.outdata, - cop->tfrm_op.outcount, - cop->tfrm_op.outlen); - - tc = cop->tfrm_op.tfrm_cfg; - while (tc){ - printk("tfrm_cfg, 0x%p\n" - "tid=%d\n" - "flags=%d\n" - "inject_ix=%d\n" - "next=0x%p\n", - tc, - tc->tid, - tc->flags, - tc->inject_ix, - tc->next); - tc = tc->next; - } - d = cop->tfrm_op.desc; - while (d){ - printk("\n======================desc, 0x%p\n" - "length=%d\n" - "cfg=0x%p\n" - "next=0x%p\n", - d, - d->length, - d->cfg, - d->next); - dc = d->cfg; - while (dc){ - printk("=========desc_cfg, 0x%p\n" - "tid=%d\n" - "src=%d\n" - "last=%d\n" - "next=0x%p\n", - dc, - dc->tid, - dc->src, - dc->last, - dc->next); - dc = dc->next; - } - d = d->next; - } - printk("\n====iniov\n"); - for (i = 0; i < cop->tfrm_op.incount; i++){ - printk("indata[%d]\n" - "base=0x%p\n" - "len=%d\n", - i, - cop->tfrm_op.indata[i].iov_base, - cop->tfrm_op.indata[i].iov_len); - } - printk("\n====outiov\n"); - for (i = 0; i < cop->tfrm_op.outcount; i++){ - printk("outdata[%d]\n" - "base=0x%p\n" - "len=%d\n", - i, - cop->tfrm_op.outdata[i].iov_base, - cop->tfrm_op.outdata[i].iov_len); - } - } - printk("------------end print_cryptocop_operation\n"); -} - - -static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op) -{ - dma_descr_data *dd; - int i; - - printk("print_user_dma_lists, dma_op=0x%p\n", dma_op); - - printk("out_data_buf = 0x%p, phys_to_virt(out_data_buf) = 0x%p\n", dma_op->out_data_buf, phys_to_virt((unsigned long int)dma_op->out_data_buf)); - printk("in_data_buf = 0x%p, phys_to_virt(in_data_buf) = 0x%p\n", dma_op->in_data_buf, phys_to_virt((unsigned long int)dma_op->in_data_buf)); - - printk("##############outlist\n"); - dd = phys_to_virt((unsigned long int)dma_op->outlist); - i = 0; - while (dd != NULL) { - printk("#%d phys_to_virt(desc) 0x%p\n", i, dd); - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - dd->buf, - dd->after, - dd->md, - dd->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - dd->wait, - dd->eol, - dd->out_eop, - dd->in_eop, - dd->intr); - if (dd->eol) - dd = NULL; - else - dd = phys_to_virt((unsigned long int)dd->next); - ++i; - } - - printk("##############inlist\n"); - dd = phys_to_virt((unsigned long int)dma_op->inlist); - i = 0; - while (dd != NULL) { - printk("#%d phys_to_virt(desc) 0x%p\n", i, dd); - printk("\n\tbuf: 0x%p\n" - "\tafter: 0x%p\n" - "\tmd: 0x%04x\n" - "\tnext: 0x%p\n", - dd->buf, - dd->after, - dd->md, - dd->next); - printk("flags:\n" - "\twait:\t%d\n" - "\teol:\t%d\n" - "\touteop:\t%d\n" - "\tineop:\t%d\n" - "\tintr:\t%d\n", - dd->wait, - dd->eol, - dd->out_eop, - dd->in_eop, - dd->intr); - if (dd->eol) - dd = NULL; - else - dd = phys_to_virt((unsigned long int)dd->next); - ++i; - } -} - - -static void print_lock_status(void) -{ - printk("**********************print_lock_status\n"); - printk("cryptocop_completed_jobs_lock %d\n", spin_is_locked(&cryptocop_completed_jobs_lock)); - printk("cryptocop_job_queue_lock %d\n", spin_is_locked(&cryptocop_job_queue_lock)); - printk("descr_pool_lock %d\n", spin_is_locked(&descr_pool_lock)); - printk("cryptocop_sessions_lock %d\n", spin_is_locked(cryptocop_sessions_lock)); - printk("running_job_lock %d\n", spin_is_locked(running_job_lock)); - printk("cryptocop_process_lock %d\n", spin_is_locked(cryptocop_process_lock)); -} -#endif /* LDEBUG */ - - -static const char cryptocop_name[] = "ETRAX FS stream co-processor"; - -static int init_stream_coprocessor(void) -{ - int err; - int i; - static int initialized = 0; - - if (initialized) - return 0; - - initialized = 1; - - printk("ETRAX FS stream co-processor driver v0.01, (c) 2003 Axis Communications AB\n"); - - err = register_chrdev(CRYPTOCOP_MAJOR, cryptocop_name, &cryptocop_fops); - if (err < 0) { - printk(KERN_ERR "stream co-processor: could not get major number.\n"); - return err; - } - - err = init_cryptocop(); - if (err) { - (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name); - return err; - } - err = cryptocop_job_queue_init(); - if (err) { - release_cryptocop(); - (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name); - return err; - } - /* Init the descriptor pool. */ - for (i = 0; i < CRYPTOCOP_DESCRIPTOR_POOL_SIZE - 1; i++) { - descr_pool[i].from_pool = 1; - descr_pool[i].next = &descr_pool[i + 1]; - } - descr_pool[i].from_pool = 1; - descr_pool[i].next = NULL; - descr_pool_free_list = &descr_pool[0]; - descr_pool_no_free = CRYPTOCOP_DESCRIPTOR_POOL_SIZE; - - spin_lock_init(&cryptocop_completed_jobs_lock); - spin_lock_init(&cryptocop_job_queue_lock); - spin_lock_init(&descr_pool_lock); - spin_lock_init(&cryptocop_sessions_lock); - spin_lock_init(&running_job_lock); - spin_lock_init(&cryptocop_process_lock); - - cryptocop_sessions = NULL; - next_sid = 1; - - cryptocop_running_job = NULL; - - printk("stream co-processor: init done.\n"); - return 0; -} - -static void __exit exit_stream_coprocessor(void) -{ - release_cryptocop(); - cryptocop_job_queue_close(); -} - -module_init(init_stream_coprocessor); -module_exit(exit_stream_coprocessor); - diff --git a/arch/cris/arch-v32/drivers/iop_fw_load.c b/arch/cris/arch-v32/drivers/iop_fw_load.c deleted file mode 100644 index 2f8ea0f7a63c..000000000000 --- a/arch/cris/arch-v32/drivers/iop_fw_load.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Firmware loader for ETRAX FS IO-Processor - * - * Copyright (C) 2004 Axis Communications AB - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define IOP_TIMEOUT 100 - -#error "This driver is broken with regard to its driver core usage." -#error "Please contact for details on how to fix it properly." - -static struct device iop_spu_device[2] = { - { .init_name = "iop-spu0", }, - { .init_name = "iop-spu1", }, -}; - -static struct device iop_mpu_device = { - .init_name = "iop-mpu", -}; - -static int wait_mpu_idle(void) -{ - reg_iop_mpu_r_stat mpu_stat; - unsigned int timeout = IOP_TIMEOUT; - - do { - mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat); - } while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0); - if (timeout == 0) { - printk(KERN_ERR "Timeout waiting for MPU to be idle\n"); - return -EBUSY; - } - return 0; -} - -int iop_fw_load_spu(const unsigned char *fw_name, unsigned int spu_inst) -{ - reg_iop_sw_cpu_rw_mc_ctrl mc_ctrl = { - .wr_spu0_mem = regk_iop_sw_cpu_no, - .wr_spu1_mem = regk_iop_sw_cpu_no, - .size = 4, - .cmd = regk_iop_sw_cpu_reg_copy, - .keep_owner = regk_iop_sw_cpu_yes - }; - reg_iop_spu_rw_ctrl spu_ctrl = { - .en = regk_iop_spu_no, - .fsm = regk_iop_spu_no, - }; - reg_iop_sw_cpu_r_mc_stat mc_stat; - const struct firmware *fw_entry; - u32 *data; - unsigned int timeout; - int retval, i; - - if (spu_inst > 1) - return -ENODEV; - - /* get firmware */ - retval = request_firmware(&fw_entry, - fw_name, - &iop_spu_device[spu_inst]); - if (retval != 0) - { - printk(KERN_ERR - "iop_load_spu: Failed to load firmware \"%s\"\n", - fw_name); - return retval; - } - data = (u32 *) fw_entry->data; - - /* acquire ownership of memory controller */ - switch (spu_inst) { - case 0: - mc_ctrl.wr_spu0_mem = regk_iop_sw_cpu_yes; - REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); - break; - case 1: - mc_ctrl.wr_spu1_mem = regk_iop_sw_cpu_yes; - REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); - break; - } - timeout = IOP_TIMEOUT; - do { - REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); - mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat); - } while (mc_stat.owned_by_cpu == regk_iop_sw_cpu_no && --timeout > 0); - if (timeout == 0) { - printk(KERN_ERR "Timeout waiting to acquire MC\n"); - retval = -EBUSY; - goto out; - } - - /* write to SPU memory */ - for (i = 0; i < (fw_entry->size/4); i++) { - switch (spu_inst) { - case 0: - REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4)); - break; - case 1: - REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4)); - break; - } - REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data); - data++; - } - - /* release ownership of memory controller */ - (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data); - - out: - release_firmware(fw_entry); - return retval; -} - -int iop_fw_load_mpu(unsigned char *fw_name) -{ - const unsigned int start_addr = 0; - reg_iop_mpu_rw_ctrl mpu_ctrl; - const struct firmware *fw_entry; - u32 *data; - int retval, i; - - /* get firmware */ - retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device); - if (retval != 0) - { - printk(KERN_ERR - "iop_load_spu: Failed to load firmware \"%s\"\n", - fw_name); - return retval; - } - data = (u32 *) fw_entry->data; - - /* disable MPU */ - mpu_ctrl.en = regk_iop_mpu_no; - REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); - /* put start address in R0 */ - REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, 0, start_addr); - /* write to memory by executing 'SWX i, 4, R0' for each word */ - if ((retval = wait_mpu_idle()) != 0) - goto out; - REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); - for (i = 0; i < (fw_entry->size / 4); i++) { - REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data); - if ((retval = wait_mpu_idle()) != 0) - goto out; - data++; - } - - out: - release_firmware(fw_entry); - return retval; -} - -int iop_start_mpu(unsigned int start_addr) -{ - reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes }; - int retval; - - /* disable MPU */ - if ((retval = wait_mpu_idle()) != 0) - goto out; - REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); - if ((retval = wait_mpu_idle()) != 0) - goto out; - /* set PC and wait for it to bite */ - if ((retval = wait_mpu_idle()) != 0) - goto out; - REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr)); - if ((retval = wait_mpu_idle()) != 0) - goto out; - /* make sure the MPU starts executing with interrupts disabled */ - REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); - if ((retval = wait_mpu_idle()) != 0) - goto out; - /* enable MPU */ - REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); - out: - return retval; -} - -static int __init iop_fw_load_init(void) -{ -#if 0 - /* - * static struct devices can not be added directly to sysfs by ignoring - * the driver model infrastructure. To fix this properly, please use - * the platform_bus to register these devices to be able to properly - * use the firmware infrastructure. - */ - device_initialize(&iop_spu_device[0]); - kobject_set_name(&iop_spu_device[0].kobj, "iop-spu0"); - kobject_add(&iop_spu_device[0].kobj); - device_initialize(&iop_spu_device[1]); - kobject_set_name(&iop_spu_device[1].kobj, "iop-spu1"); - kobject_add(&iop_spu_device[1].kobj); - device_initialize(&iop_mpu_device); - kobject_set_name(&iop_mpu_device.kobj, "iop-mpu"); - kobject_add(&iop_mpu_device.kobj); -#endif - return 0; -} - -static void __exit iop_fw_load_exit(void) -{ -} - -module_init(iop_fw_load_init); -module_exit(iop_fw_load_exit); - -MODULE_DESCRIPTION("ETRAX FS IO-Processor Firmware Loader"); -MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(iop_fw_load_spu); -EXPORT_SYMBOL(iop_fw_load_mpu); -EXPORT_SYMBOL(iop_start_mpu); diff --git a/arch/cris/arch-v32/drivers/mach-a3/Makefile b/arch/cris/arch-v32/drivers/mach-a3/Makefile deleted file mode 100644 index 59028d0b981c..000000000000 --- a/arch/cris/arch-v32/drivers/mach-a3/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for Etrax-specific drivers -# - -obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c deleted file mode 100644 index 925a98eb6d68..000000000000 --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * arch/cris/arch-v32/drivers/nandflash.c - * - * Copyright (c) 2007 - * - * Derived from drivers/mtd/nand/spia.c - * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MANUAL_ALE_CLE_CONTROL 1 - -#define regf_ALE a0 -#define regf_CLE a1 -#define regf_NCE ce0_n - -#define CLE_BIT 10 -#define ALE_BIT 11 -#define CE_BIT 12 - -struct mtd_info_wrapper { - struct nand_chip chip; -}; - -/* Bitmask for control pins */ -#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) - -static struct mtd_info *crisv32_mtd; -/* - * hardware specific access to control-lines - */ -static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - unsigned long flags; - reg_pio_rw_dout dout; - struct nand_chip *this = mtd_to_nand(mtd); - - local_irq_save(flags); - - /* control bits change */ - if (ctrl & NAND_CTRL_CHANGE) { - dout = REG_RD(pio, regi_pio, rw_dout); - dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1; - -#if !MANUAL_ALE_CLE_CONTROL - if (ctrl & NAND_ALE) { - /* A0 = ALE high */ - this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio, - regi_pio, rw_io_access1); - } else if (ctrl & NAND_CLE) { - /* A1 = CLE high */ - this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio, - regi_pio, rw_io_access2); - } else { - /* A1 = CLE and A0 = ALE low */ - this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio, - regi_pio, rw_io_access0); - } -#else - - dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0; - dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0; -#endif - REG_WR(pio, regi_pio, rw_dout, dout); - } - - /* command to chip */ - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); - - local_irq_restore(flags); -} - -/* -* read device ready pin -*/ -static int crisv32_device_ready(struct mtd_info *mtd) -{ - reg_pio_r_din din = REG_RD(pio, regi_pio, r_din); - return din.rdy; -} - -/* - * Main initialization routine - */ -struct mtd_info *__init crisv32_nand_flash_probe(void) -{ - void __iomem *read_cs; - void __iomem *write_cs; - - struct mtd_info_wrapper *wrapper; - struct nand_chip *this; - int err = 0; - - reg_pio_rw_man_ctrl man_ctrl = { - .regf_NCE = regk_pio_yes, -#if MANUAL_ALE_CLE_CONTROL - .regf_ALE = regk_pio_yes, - .regf_CLE = regk_pio_yes -#endif - }; - reg_pio_rw_oe oe = { - .regf_NCE = regk_pio_yes, -#if MANUAL_ALE_CLE_CONTROL - .regf_ALE = regk_pio_yes, - .regf_CLE = regk_pio_yes -#endif - }; - reg_pio_rw_dout dout = { .regf_NCE = 1 }; - - /* Allocate pio pins to pio */ - crisv32_pinmux_alloc_fixed(pinmux_pio); - /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */ - REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl); - REG_WR(pio, regi_pio, rw_dout, dout); - REG_WR(pio, regi_pio, rw_oe, oe); - - /* Allocate memory for MTD device structure and private data */ - wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL); - if (!wrapper) { - printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " - "device structure.\n"); - err = -ENOMEM; - return NULL; - } - - read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio, - rw_io_access0); - - /* Get pointer to private data */ - this = &wrapper->chip; - crisv32_mtd = nand_to_mtd(this); - - /* Set address of NAND IO lines */ - this->IO_ADDR_R = read_cs; - this->IO_ADDR_W = write_cs; - this->cmd_ctrl = crisv32_hwcontrol; - this->dev_ready = crisv32_device_ready; - /* 20 us command delay time */ - this->chip_delay = 20; - this->ecc.mode = NAND_ECC_SOFT; - this->ecc.algo = NAND_ECC_HAMMING; - - /* Enable the following for a flash based bad block table */ - /* this->bbt_options = NAND_BBT_USE_FLASH; */ - - /* Scan to find existence of the device */ - if (nand_scan(crisv32_mtd, 1)) { - err = -ENXIO; - goto out_mtd; - } - - return crisv32_mtd; - -out_mtd: - kfree(wrapper); - return NULL; -} - diff --git a/arch/cris/arch-v32/drivers/mach-fs/Makefile b/arch/cris/arch-v32/drivers/mach-fs/Makefile deleted file mode 100644 index 59028d0b981c..000000000000 --- a/arch/cris/arch-v32/drivers/mach-fs/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for Etrax-specific drivers -# - -obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c deleted file mode 100644 index 53b56a429dde..000000000000 --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * arch/cris/arch-v32/drivers/nandflash.c - * - * Copyright (c) 2004 - * - * Derived from drivers/mtd/nand/spia.c - * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CE_BIT 4 -#define CLE_BIT 5 -#define ALE_BIT 6 -#define BY_BIT 7 - -struct mtd_info_wrapper { - struct nand_chip chip; -}; - -/* Bitmask for control pins */ -#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT)) - -/* Bitmask for mtd nand control bits */ -#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE) - - -static struct mtd_info *crisv32_mtd; -/* - * hardware specific access to control-lines - */ -static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - unsigned long flags; - reg_gio_rw_pa_dout dout; - struct nand_chip *this = mtd_to_nand(mtd); - - local_irq_save(flags); - - /* control bits change */ - if (ctrl & NAND_CTRL_CHANGE) { - dout = REG_RD(gio, regi_gio, rw_pa_dout); - dout.data &= ~PIN_BITMASK; - -#if (CE_BIT == 4 && NAND_NCE == 1 && \ - CLE_BIT == 5 && NAND_CLE == 2 && \ - ALE_BIT == 6 && NAND_ALE == 4) - /* Pins in same order as control bits, but shifted. - * Optimize for this case; works for 2.6.18 */ - dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT; -#else - /* the slow way */ - if (!(ctrl & NAND_NCE)) - dout.data |= (1 << CE_BIT); - if (ctrl & NAND_CLE) - dout.data |= (1 << CLE_BIT); - if (ctrl & NAND_ALE) - dout.data |= (1 << ALE_BIT); -#endif - REG_WR(gio, regi_gio, rw_pa_dout, dout); - } - - /* command to chip */ - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); - - local_irq_restore(flags); -} - -/* -* read device ready pin -*/ -static int crisv32_device_ready(struct mtd_info *mtd) -{ - reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); - return ((din.data & (1 << BY_BIT)) >> BY_BIT); -} - -/* - * Main initialization routine - */ -struct mtd_info *__init crisv32_nand_flash_probe(void) -{ - void __iomem *read_cs; - void __iomem *write_cs; - - reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, - rw_grp3_cfg); - reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); - struct mtd_info_wrapper *wrapper; - struct nand_chip *this; - int err = 0; - - /* Allocate memory for MTD device structure and private data */ - wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL); - if (!wrapper) { - printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD " - "device structure.\n"); - err = -ENOMEM; - return NULL; - } - - read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192); - write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192); - - if (!read_cs || !write_cs) { - printk(KERN_ERR "CRISv32 NAND ioremap failed\n"); - err = -EIO; - goto out_mtd; - } - - /* Get pointer to private data */ - this = &wrapper->chip; - crisv32_mtd = nand_to_mtd(this); - - pa_oe.oe |= 1 << CE_BIT; - pa_oe.oe |= 1 << ALE_BIT; - pa_oe.oe |= 1 << CLE_BIT; - pa_oe.oe &= ~(1 << BY_BIT); - REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); - - bif_cfg.gated_csp0 = regk_bif_core_rd; - bif_cfg.gated_csp1 = regk_bif_core_wr; - REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); - - /* Set address of NAND IO lines */ - this->IO_ADDR_R = read_cs; - this->IO_ADDR_W = write_cs; - this->cmd_ctrl = crisv32_hwcontrol; - this->dev_ready = crisv32_device_ready; - /* 20 us command delay time */ - this->chip_delay = 20; - this->ecc.mode = NAND_ECC_SOFT; - this->ecc.algo = NAND_ECC_HAMMING; - - /* Enable the following for a flash based bad block table */ - /* this->bbt_options = NAND_BBT_USE_FLASH; */ - - /* Scan to find existence of the device */ - if (nand_scan(crisv32_mtd, 1)) { - err = -ENXIO; - goto out_ior; - } - - return crisv32_mtd; - -out_ior: - iounmap((void *)read_cs); - iounmap((void *)write_cs); -out_mtd: - kfree(wrapper); - return NULL; -} - diff --git a/arch/cris/arch-v32/drivers/pci/Makefile b/arch/cris/arch-v32/drivers/pci/Makefile deleted file mode 100644 index 93c8be6170b1..000000000000 --- a/arch/cris/arch-v32/drivers/pci/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for Etrax cardbus driver -# - -obj-$(CONFIG_ETRAX_CARDBUS) += bios.o diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c deleted file mode 100644 index 6b9e6cfaa29e..000000000000 --- a/arch/cris/arch-v32/drivers/pci/bios.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -void pcibios_set_master(struct pci_dev *dev) -{ - u8 lat; - pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); - printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat); - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); -} - -resource_size_t -pcibios_align_resource(void *data, const struct resource *res, - resource_size_t size, resource_size_t align) -{ - resource_size_t start = res->start; - - if ((res->flags & IORESOURCE_IO) && (start & 0x300)) - start = (start + 0x3ff) & ~0x3ff; - - return start; -} - -int pcibios_enable_resources(struct pci_dev *dev, int mask) -{ - u16 cmd, old_cmd; - int idx; - struct resource *r; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for(idx=0; idx<6; idx++) { - /* Only set up the requested stuff */ - if (!(mask & (1<resource[idx]; - if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (dev->resource[PCI_ROM_RESOURCE].start) - cmd |= PCI_COMMAND_MEMORY; - if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; -} - -int pcibios_enable_irq(struct pci_dev *dev) -{ - dev->irq = EXT_INTR_VECT; - return 0; -} - -int pcibios_enable_device(struct pci_dev *dev, int mask) -{ - int err; - - if ((err = pcibios_enable_resources(dev, mask)) < 0) - return err; - - if (!dev->msi_enabled) - pcibios_enable_irq(dev); - return 0; -} diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c deleted file mode 100644 index 1b0ce8a8af16..000000000000 --- a/arch/cris/arch-v32/drivers/sync_serial.c +++ /dev/null @@ -1,1715 +0,0 @@ -/* - * Simple synchronous serial port driver for ETRAX FS and ARTPEC-3. - * - * Copyright (c) 2005, 2008 Axis Communications AB - * Author: Mikael Starvik - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/* The receiver is a bit tricky because of the continuous stream of data.*/ -/* */ -/* Three DMA descriptors are linked together. Each DMA descriptor is */ -/* responsible for port->bufchunk of a common buffer. */ -/* */ -/* +---------------------------------------------+ */ -/* | +----------+ +----------+ +----------+ | */ -/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ -/* +----------+ +----------+ +----------+ */ -/* | | | */ -/* v v v */ -/* +-------------------------------------+ */ -/* | BUFFER | */ -/* +-------------------------------------+ */ -/* |<- data_avail ->| */ -/* readp writep */ -/* */ -/* If the application keeps up the pace readp will be right after writep.*/ -/* If the application can't keep the pace we have to throw away data. */ -/* The idea is that readp should be ready with the data pointed out by */ -/* Descr[i] when the DMA has filled in Descr[i+1]. */ -/* Otherwise we will discard */ -/* the rest of the data pointed out by Descr1 and set readp to the start */ -/* of Descr2 */ - -/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ -/* words can be handled */ -#define IN_DESCR_SIZE SSP_INPUT_CHUNK_SIZE -#define NBR_IN_DESCR (8*6) -#define IN_BUFFER_SIZE (IN_DESCR_SIZE * NBR_IN_DESCR) - -#define NBR_OUT_DESCR 8 -#define OUT_BUFFER_SIZE (1024 * NBR_OUT_DESCR) - -#define DEFAULT_FRAME_RATE 0 -#define DEFAULT_WORD_RATE 7 - -/* To be removed when we move to pure udev. */ -#define SYNC_SERIAL_MAJOR 125 - -/* NOTE: Enabling some debug will likely cause overrun or underrun, - * especially if manual mode is used. - */ -#define DEBUG(x) -#define DEBUGREAD(x) -#define DEBUGWRITE(x) -#define DEBUGPOLL(x) -#define DEBUGRXINT(x) -#define DEBUGTXINT(x) -#define DEBUGTRDMA(x) -#define DEBUGOUTBUF(x) - -enum syncser_irq_setup { - no_irq_setup = 0, - dma_irq_setup = 1, - manual_irq_setup = 2, -}; - -struct sync_port { - unsigned long regi_sser; - unsigned long regi_dmain; - unsigned long regi_dmaout; - - /* Interrupt vectors. */ - unsigned long dma_in_intr_vect; /* Used for DMA in. */ - unsigned long dma_out_intr_vect; /* Used for DMA out. */ - unsigned long syncser_intr_vect; /* Used when no DMA. */ - - /* DMA number for in and out. */ - unsigned int dma_in_nbr; - unsigned int dma_out_nbr; - - /* DMA owner. */ - enum dma_owner req_dma; - - char started; /* 1 if port has been started */ - char port_nbr; /* Port 0 or 1 */ - char busy; /* 1 if port is busy */ - - char enabled; /* 1 if port is enabled */ - char use_dma; /* 1 if port uses dma */ - char tr_running; - - enum syncser_irq_setup init_irqs; - int output; - int input; - - /* Next byte to be read by application */ - unsigned char *readp; - /* Next byte to be written by etrax */ - unsigned char *writep; - - unsigned int in_buffer_size; - unsigned int in_buffer_len; - unsigned int inbufchunk; - /* Data buffers for in and output. */ - unsigned char out_buffer[OUT_BUFFER_SIZE] __aligned(32); - unsigned char in_buffer[IN_BUFFER_SIZE] __aligned(32); - unsigned char flip[IN_BUFFER_SIZE] __aligned(32); - struct timespec timestamp[NBR_IN_DESCR]; - struct dma_descr_data *next_rx_desc; - struct dma_descr_data *prev_rx_desc; - - struct timeval last_timestamp; - int read_ts_idx; - int write_ts_idx; - - /* Pointer to the first available descriptor in the ring, - * unless active_tr_descr == catch_tr_descr and a dma - * transfer is active */ - struct dma_descr_data *active_tr_descr; - - /* Pointer to the first allocated descriptor in the ring */ - struct dma_descr_data *catch_tr_descr; - - /* Pointer to the descriptor with the current end-of-list */ - struct dma_descr_data *prev_tr_descr; - int full; - - /* Pointer to the first byte being read by DMA - * or current position in out_buffer if not using DMA. */ - unsigned char *out_rd_ptr; - - /* Number of bytes currently locked for being read by DMA */ - int out_buf_count; - - dma_descr_context in_context __aligned(32); - dma_descr_context out_context __aligned(32); - dma_descr_data in_descr[NBR_IN_DESCR] __aligned(16); - dma_descr_data out_descr[NBR_OUT_DESCR] __aligned(16); - - wait_queue_head_t out_wait_q; - wait_queue_head_t in_wait_q; - - spinlock_t lock; -}; - -static DEFINE_MUTEX(sync_serial_mutex); -static int etrax_sync_serial_init(void); -static void initialize_port(int portnbr); -static inline int sync_data_avail(struct sync_port *port); - -static int sync_serial_open(struct inode *, struct file *); -static int sync_serial_release(struct inode *, struct file *); -static __poll_t sync_serial_poll(struct file *filp, poll_table *wait); - -static long sync_serial_ioctl(struct file *file, - unsigned int cmd, unsigned long arg); -static int sync_serial_ioctl_unlocked(struct file *file, - unsigned int cmd, unsigned long arg); -static ssize_t sync_serial_write(struct file *file, const char __user *buf, - size_t count, loff_t *ppos); -static ssize_t sync_serial_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos); - -#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ - (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ - defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) -#define SYNC_SER_DMA -#else -#define SYNC_SER_MANUAL -#endif - -#ifdef SYNC_SER_DMA -static void start_dma_out(struct sync_port *port, const char *data, int count); -static void start_dma_in(struct sync_port *port); -static irqreturn_t tr_interrupt(int irq, void *dev_id); -static irqreturn_t rx_interrupt(int irq, void *dev_id); -#endif -#ifdef SYNC_SER_MANUAL -static void send_word(struct sync_port *port); -static irqreturn_t manual_interrupt(int irq, void *dev_id); -#endif - -#define artpec_pinmux_alloc_fixed crisv32_pinmux_alloc_fixed -#define artpec_request_dma crisv32_request_dma -#define artpec_free_dma crisv32_free_dma - -#ifdef CONFIG_ETRAXFS -/* ETRAX FS */ -#define DMA_OUT_NBR0 SYNC_SER0_TX_DMA_NBR -#define DMA_IN_NBR0 SYNC_SER0_RX_DMA_NBR -#define DMA_OUT_NBR1 SYNC_SER1_TX_DMA_NBR -#define DMA_IN_NBR1 SYNC_SER1_RX_DMA_NBR -#define PINMUX_SSER0 pinmux_sser0 -#define PINMUX_SSER1 pinmux_sser1 -#define SYNCSER_INST0 regi_sser0 -#define SYNCSER_INST1 regi_sser1 -#define SYNCSER_INTR_VECT0 SSER0_INTR_VECT -#define SYNCSER_INTR_VECT1 SSER1_INTR_VECT -#define OUT_DMA_INST0 regi_dma4 -#define IN_DMA_INST0 regi_dma5 -#define DMA_OUT_INTR_VECT0 DMA4_INTR_VECT -#define DMA_OUT_INTR_VECT1 DMA7_INTR_VECT -#define DMA_IN_INTR_VECT0 DMA5_INTR_VECT -#define DMA_IN_INTR_VECT1 DMA6_INTR_VECT -#define REQ_DMA_SYNCSER0 dma_sser0 -#define REQ_DMA_SYNCSER1 dma_sser1 -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) -#define PORT1_DMA 1 -#else -#define PORT1_DMA 0 -#endif -#elif defined(CONFIG_CRIS_MACH_ARTPEC3) -/* ARTPEC-3 */ -#define DMA_OUT_NBR0 SYNC_SER_TX_DMA_NBR -#define DMA_IN_NBR0 SYNC_SER_RX_DMA_NBR -#define PINMUX_SSER0 pinmux_sser -#define SYNCSER_INST0 regi_sser -#define SYNCSER_INTR_VECT0 SSER_INTR_VECT -#define OUT_DMA_INST0 regi_dma6 -#define IN_DMA_INST0 regi_dma7 -#define DMA_OUT_INTR_VECT0 DMA6_INTR_VECT -#define DMA_IN_INTR_VECT0 DMA7_INTR_VECT -#define REQ_DMA_SYNCSER0 dma_sser -#define REQ_DMA_SYNCSER1 dma_sser -#endif - -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) -#define PORT0_DMA 1 -#else -#define PORT0_DMA 0 -#endif - -/* The ports */ -static struct sync_port ports[] = { - { - .regi_sser = SYNCSER_INST0, - .regi_dmaout = OUT_DMA_INST0, - .regi_dmain = IN_DMA_INST0, - .use_dma = PORT0_DMA, - .dma_in_intr_vect = DMA_IN_INTR_VECT0, - .dma_out_intr_vect = DMA_OUT_INTR_VECT0, - .dma_in_nbr = DMA_IN_NBR0, - .dma_out_nbr = DMA_OUT_NBR0, - .req_dma = REQ_DMA_SYNCSER0, - .syncser_intr_vect = SYNCSER_INTR_VECT0, - }, -#ifdef CONFIG_ETRAXFS - { - .regi_sser = SYNCSER_INST1, - .regi_dmaout = regi_dma6, - .regi_dmain = regi_dma7, - .use_dma = PORT1_DMA, - .dma_in_intr_vect = DMA_IN_INTR_VECT1, - .dma_out_intr_vect = DMA_OUT_INTR_VECT1, - .dma_in_nbr = DMA_IN_NBR1, - .dma_out_nbr = DMA_OUT_NBR1, - .req_dma = REQ_DMA_SYNCSER1, - .syncser_intr_vect = SYNCSER_INTR_VECT1, - }, -#endif -}; - -#define NBR_PORTS ARRAY_SIZE(ports) - -static const struct file_operations syncser_fops = { - .owner = THIS_MODULE, - .write = sync_serial_write, - .read = sync_serial_read, - .poll = sync_serial_poll, - .unlocked_ioctl = sync_serial_ioctl, - .open = sync_serial_open, - .release = sync_serial_release, - .llseek = noop_llseek, -}; - -static dev_t syncser_first; -static int minor_count = NBR_PORTS; -#define SYNCSER_NAME "syncser" -static struct cdev *syncser_cdev; -static struct class *syncser_class; - -static void sync_serial_start_port(struct sync_port *port) -{ - reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); - reg_sser_rw_tr_cfg tr_cfg = - REG_RD(sser, port->regi_sser, rw_tr_cfg); - reg_sser_rw_rec_cfg rec_cfg = - REG_RD(sser, port->regi_sser, rw_rec_cfg); - cfg.en = regk_sser_yes; - tr_cfg.tr_en = regk_sser_yes; - rec_cfg.rec_en = regk_sser_yes; - REG_WR(sser, port->regi_sser, rw_cfg, cfg); - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - port->started = 1; -} - -static void __init initialize_port(int portnbr) -{ - struct sync_port *port = &ports[portnbr]; - reg_sser_rw_cfg cfg = { 0 }; - reg_sser_rw_frm_cfg frm_cfg = { 0 }; - reg_sser_rw_tr_cfg tr_cfg = { 0 }; - reg_sser_rw_rec_cfg rec_cfg = { 0 }; - - DEBUG(pr_info("Init sync serial port %d\n", portnbr)); - - port->port_nbr = portnbr; - port->init_irqs = no_irq_setup; - - port->out_rd_ptr = port->out_buffer; - port->out_buf_count = 0; - - port->output = 1; - port->input = 0; - - port->readp = port->flip; - port->writep = port->flip; - port->in_buffer_size = IN_BUFFER_SIZE; - port->in_buffer_len = 0; - port->inbufchunk = IN_DESCR_SIZE; - - port->read_ts_idx = 0; - port->write_ts_idx = 0; - - init_waitqueue_head(&port->out_wait_q); - init_waitqueue_head(&port->in_wait_q); - - spin_lock_init(&port->lock); - - cfg.out_clk_src = regk_sser_intern_clk; - cfg.out_clk_pol = regk_sser_pos; - cfg.clk_od_mode = regk_sser_no; - cfg.clk_dir = regk_sser_out; - cfg.gate_clk = regk_sser_no; - cfg.base_freq = regk_sser_f29_493; - cfg.clk_div = 256; - REG_WR(sser, port->regi_sser, rw_cfg, cfg); - - frm_cfg.wordrate = DEFAULT_WORD_RATE; - frm_cfg.type = regk_sser_edge; - frm_cfg.frame_pin_dir = regk_sser_out; - frm_cfg.frame_pin_use = regk_sser_frm; - frm_cfg.status_pin_dir = regk_sser_in; - frm_cfg.status_pin_use = regk_sser_hold; - frm_cfg.out_on = regk_sser_tr; - frm_cfg.tr_delay = 1; - REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); - - tr_cfg.urun_stop = regk_sser_no; - tr_cfg.sample_size = 7; - tr_cfg.sh_dir = regk_sser_msbfirst; - tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no; -#if 0 - tr_cfg.rate_ctrl = regk_sser_bulk; - tr_cfg.data_pin_use = regk_sser_dout; -#else - tr_cfg.rate_ctrl = regk_sser_iso; - tr_cfg.data_pin_use = regk_sser_dout; -#endif - tr_cfg.bulk_wspace = 1; - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - - rec_cfg.sample_size = 7; - rec_cfg.sh_dir = regk_sser_msbfirst; - rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no; - rec_cfg.fifo_thr = regk_sser_inf; - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - -#ifdef SYNC_SER_DMA - { - int i; - /* Setup the descriptor ring for dma out/transmit. */ - for (i = 0; i < NBR_OUT_DESCR; i++) { - dma_descr_data *descr = &port->out_descr[i]; - descr->wait = 0; - descr->intr = 1; - descr->eol = 0; - descr->out_eop = 0; - descr->next = - (dma_descr_data *)virt_to_phys(&descr[i+1]); - } - } - - /* Create a ring from the list. */ - port->out_descr[NBR_OUT_DESCR-1].next = - (dma_descr_data *)virt_to_phys(&port->out_descr[0]); - - /* Setup context for traversing the ring. */ - port->active_tr_descr = &port->out_descr[0]; - port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1]; - port->catch_tr_descr = &port->out_descr[0]; -#endif -} - -static inline int sync_data_avail(struct sync_port *port) -{ - return port->in_buffer_len; -} - -static int sync_serial_open(struct inode *inode, struct file *file) -{ - int ret = 0; - int dev = iminor(inode); - struct sync_port *port; -#ifdef SYNC_SER_DMA - reg_dma_rw_cfg cfg = { .en = regk_dma_yes }; - reg_dma_rw_intr_mask intr_mask = { .data = regk_dma_yes }; -#endif - - DEBUG(pr_debug("Open sync serial port %d\n", dev)); - - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { - DEBUG(pr_info("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - /* Allow open this device twice (assuming one reader and one writer) */ - if (port->busy == 2) { - DEBUG(pr_info("syncser%d is busy\n", dev)); - return -EBUSY; - } - - mutex_lock(&sync_serial_mutex); - - /* Clear any stale date left in the flip buffer */ - port->readp = port->writep = port->flip; - port->in_buffer_len = 0; - port->read_ts_idx = 0; - port->write_ts_idx = 0; - - if (port->init_irqs != no_irq_setup) { - /* Init only on first call. */ - port->busy++; - mutex_unlock(&sync_serial_mutex); - return 0; - } - if (port->use_dma) { -#ifdef SYNC_SER_DMA - const char *tmp; - DEBUG(pr_info("Using DMA for syncser%d\n", dev)); - - tmp = dev == 0 ? "syncser0 tx" : "syncser1 tx"; - if (request_irq(port->dma_out_intr_vect, tr_interrupt, 0, - tmp, port)) { - pr_err("Can't alloc syncser%d TX IRQ", dev); - ret = -EBUSY; - goto unlock_and_exit; - } - if (artpec_request_dma(port->dma_out_nbr, tmp, - DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) { - free_irq(port->dma_out_intr_vect, port); - pr_err("Can't alloc syncser%d TX DMA", dev); - ret = -EBUSY; - goto unlock_and_exit; - } - tmp = dev == 0 ? "syncser0 rx" : "syncser1 rx"; - if (request_irq(port->dma_in_intr_vect, rx_interrupt, 0, - tmp, port)) { - artpec_free_dma(port->dma_out_nbr); - free_irq(port->dma_out_intr_vect, port); - pr_err("Can't alloc syncser%d RX IRQ", dev); - ret = -EBUSY; - goto unlock_and_exit; - } - if (artpec_request_dma(port->dma_in_nbr, tmp, - DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) { - artpec_free_dma(port->dma_out_nbr); - free_irq(port->dma_out_intr_vect, port); - free_irq(port->dma_in_intr_vect, port); - pr_err("Can't alloc syncser%d RX DMA", dev); - ret = -EBUSY; - goto unlock_and_exit; - } - /* Enable DMAs */ - REG_WR(dma, port->regi_dmain, rw_cfg, cfg); - REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); - /* Enable DMA IRQs */ - REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); - REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); - /* Set up wordsize = 1 for DMAs. */ - DMA_WR_CMD(port->regi_dmain, regk_dma_set_w_size1); - DMA_WR_CMD(port->regi_dmaout, regk_dma_set_w_size1); - - start_dma_in(port); - port->init_irqs = dma_irq_setup; -#endif - } else { /* !port->use_dma */ -#ifdef SYNC_SER_MANUAL - const char *tmp = dev == 0 ? "syncser0 manual irq" : - "syncser1 manual irq"; - if (request_irq(port->syncser_intr_vect, manual_interrupt, - 0, tmp, port)) { - pr_err("Can't alloc syncser%d manual irq", - dev); - ret = -EBUSY; - goto unlock_and_exit; - } - port->init_irqs = manual_irq_setup; -#else - panic("sync_serial: Manual mode not supported\n"); -#endif /* SYNC_SER_MANUAL */ - } - port->busy++; - ret = 0; - -unlock_and_exit: - mutex_unlock(&sync_serial_mutex); - return ret; -} - -static int sync_serial_release(struct inode *inode, struct file *file) -{ - int dev = iminor(inode); - struct sync_port *port; - - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { - DEBUG(pr_info("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - if (port->busy) - port->busy--; - if (!port->busy) - /* XXX */; - return 0; -} - -static __poll_t sync_serial_poll(struct file *file, poll_table *wait) -{ - int dev = iminor(file_inode(file)); - __poll_t mask = 0; - struct sync_port *port; - DEBUGPOLL( - static __poll_t prev_mask; - ); - - port = &ports[dev]; - - if (!port->started) - sync_serial_start_port(port); - - poll_wait(file, &port->out_wait_q, wait); - poll_wait(file, &port->in_wait_q, wait); - - /* No active transfer, descriptors are available */ - if (port->output && !port->tr_running) - mask |= EPOLLOUT | EPOLLWRNORM; - - /* Descriptor and buffer space available. */ - if (port->output && - port->active_tr_descr != port->catch_tr_descr && - port->out_buf_count < OUT_BUFFER_SIZE) - mask |= EPOLLOUT | EPOLLWRNORM; - - /* At least an inbufchunk of data */ - if (port->input && sync_data_avail(port) >= port->inbufchunk) - mask |= EPOLLIN | EPOLLRDNORM; - - DEBUGPOLL( - if (mask != prev_mask) - pr_info("sync_serial_poll: mask 0x%08X %s %s\n", - mask, - mask & EPOLLOUT ? "POLLOUT" : "", - mask & EPOLLIN ? "POLLIN" : ""); - prev_mask = mask; - ); - return mask; -} - -static ssize_t __sync_serial_read(struct file *file, - char __user *buf, - size_t count, - loff_t *ppos, - struct timespec *ts) -{ - unsigned long flags; - int dev = MINOR(file_inode(file)->i_rdev); - int avail; - struct sync_port *port; - unsigned char *start; - unsigned char *end; - - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { - DEBUG(pr_info("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - - if (!port->started) - sync_serial_start_port(port); - - /* Calculate number of available bytes */ - /* Save pointers to avoid that they are modified by interrupt */ - spin_lock_irqsave(&port->lock, flags); - start = port->readp; - end = port->writep; - spin_unlock_irqrestore(&port->lock, flags); - - while ((start == end) && !port->in_buffer_len) { - if (file->f_flags & O_NONBLOCK) - return -EAGAIN; - - wait_event_interruptible(port->in_wait_q, - !(start == end && !port->full)); - - if (signal_pending(current)) - return -EINTR; - - spin_lock_irqsave(&port->lock, flags); - start = port->readp; - end = port->writep; - spin_unlock_irqrestore(&port->lock, flags); - } - - DEBUGREAD(pr_info("R%d c %d ri %u wi %u /%u\n", - dev, count, - start - port->flip, end - port->flip, - port->in_buffer_size)); - - /* Lazy read, never return wrapped data. */ - if (end > start) - avail = end - start; - else - avail = port->flip + port->in_buffer_size - start; - - count = count > avail ? avail : count; - if (copy_to_user(buf, start, count)) - return -EFAULT; - - /* If timestamp requested, find timestamp of first returned byte - * and copy it. - * N.B: Applications that request timstamps MUST read data in - * chunks that are multiples of IN_DESCR_SIZE. - * Otherwise the timestamps will not be aligned to the data read. - */ - if (ts != NULL) { - int idx = port->read_ts_idx; - memcpy(ts, &port->timestamp[idx], sizeof(struct timespec)); - port->read_ts_idx += count / IN_DESCR_SIZE; - if (port->read_ts_idx >= NBR_IN_DESCR) - port->read_ts_idx = 0; - } - - spin_lock_irqsave(&port->lock, flags); - port->readp += count; - /* Check for wrap */ - if (port->readp >= port->flip + port->in_buffer_size) - port->readp = port->flip; - port->in_buffer_len -= count; - port->full = 0; - spin_unlock_irqrestore(&port->lock, flags); - - DEBUGREAD(pr_info("r %d\n", count)); - - return count; -} - -static ssize_t sync_serial_input(struct file *file, unsigned long arg) -{ - struct ssp_request req; - int count; - int ret; - - /* Copy the request structure from user-mode. */ - ret = copy_from_user(&req, (struct ssp_request __user *)arg, - sizeof(struct ssp_request)); - - if (ret) { - DEBUG(pr_info("sync_serial_input copy from user failed\n")); - return -EFAULT; - } - - /* To get the timestamps aligned, make sure that 'len' - * is a multiple of IN_DESCR_SIZE. - */ - if ((req.len % IN_DESCR_SIZE) != 0) { - DEBUG(pr_info("sync_serial: req.len %x, IN_DESCR_SIZE %x\n", - req.len, IN_DESCR_SIZE)); - return -EFAULT; - } - - /* Do the actual read. */ - /* Note that req.buf is actually a pointer to user space. */ - count = __sync_serial_read(file, req.buf, req.len, - NULL, &req.ts); - - if (count < 0) { - DEBUG(pr_info("sync_serial_input read failed\n")); - return count; - } - - /* Copy the request back to user-mode. */ - ret = copy_to_user((struct ssp_request __user *)arg, &req, - sizeof(struct ssp_request)); - - if (ret) { - DEBUG(pr_info("syncser input copy2user failed\n")); - return -EFAULT; - } - - /* Return the number of bytes read. */ - return count; -} - - -static int sync_serial_ioctl_unlocked(struct file *file, - unsigned int cmd, unsigned long arg) -{ - int return_val = 0; - int dma_w_size = regk_dma_set_w_size1; - int dev = iminor(file_inode(file)); - struct sync_port *port; - reg_sser_rw_tr_cfg tr_cfg; - reg_sser_rw_rec_cfg rec_cfg; - reg_sser_rw_frm_cfg frm_cfg; - reg_sser_rw_cfg gen_cfg; - reg_sser_rw_intr_mask intr_mask; - - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { - DEBUG(pr_info("Invalid minor %d\n", dev)); - return -1; - } - - if (cmd == SSP_INPUT) - return sync_serial_input(file, arg); - - port = &ports[dev]; - spin_lock_irq(&port->lock); - - tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg); - frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg); - gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg); - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); - - switch (cmd) { - case SSP_SPEED: - if (GET_SPEED(arg) == CODEC) { - unsigned int freq; - - gen_cfg.base_freq = regk_sser_f32; - - /* Clock divider will internally be - * gen_cfg.clk_div + 1. - */ - - freq = GET_FREQ(arg); - switch (freq) { - case FREQ_32kHz: - case FREQ_64kHz: - case FREQ_128kHz: - case FREQ_256kHz: - gen_cfg.clk_div = 125 * - (1 << (freq - FREQ_256kHz)) - 1; - break; - case FREQ_512kHz: - gen_cfg.clk_div = 62; - break; - case FREQ_1MHz: - case FREQ_2MHz: - case FREQ_4MHz: - gen_cfg.clk_div = 8 * (1 << freq) - 1; - break; - } - } else if (GET_SPEED(arg) == CODEC_f32768) { - gen_cfg.base_freq = regk_sser_f32_768; - switch (GET_FREQ(arg)) { - case FREQ_4096kHz: - gen_cfg.clk_div = 7; - break; - default: - spin_unlock_irq(&port->lock); - return -EINVAL; - } - } else { - gen_cfg.base_freq = regk_sser_f29_493; - switch (GET_SPEED(arg)) { - case SSP150: - gen_cfg.clk_div = 29493000 / (150 * 8) - 1; - break; - case SSP300: - gen_cfg.clk_div = 29493000 / (300 * 8) - 1; - break; - case SSP600: - gen_cfg.clk_div = 29493000 / (600 * 8) - 1; - break; - case SSP1200: - gen_cfg.clk_div = 29493000 / (1200 * 8) - 1; - break; - case SSP2400: - gen_cfg.clk_div = 29493000 / (2400 * 8) - 1; - break; - case SSP4800: - gen_cfg.clk_div = 29493000 / (4800 * 8) - 1; - break; - case SSP9600: - gen_cfg.clk_div = 29493000 / (9600 * 8) - 1; - break; - case SSP19200: - gen_cfg.clk_div = 29493000 / (19200 * 8) - 1; - break; - case SSP28800: - gen_cfg.clk_div = 29493000 / (28800 * 8) - 1; - break; - case SSP57600: - gen_cfg.clk_div = 29493000 / (57600 * 8) - 1; - break; - case SSP115200: - gen_cfg.clk_div = 29493000 / (115200 * 8) - 1; - break; - case SSP230400: - gen_cfg.clk_div = 29493000 / (230400 * 8) - 1; - break; - case SSP460800: - gen_cfg.clk_div = 29493000 / (460800 * 8) - 1; - break; - case SSP921600: - gen_cfg.clk_div = 29493000 / (921600 * 8) - 1; - break; - case SSP3125000: - gen_cfg.base_freq = regk_sser_f100; - gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1; - break; - - } - } - frm_cfg.wordrate = GET_WORD_RATE(arg); - - break; - case SSP_MODE: - switch (arg) { - case MASTER_OUTPUT: - port->output = 1; - port->input = 0; - frm_cfg.out_on = regk_sser_tr; - frm_cfg.frame_pin_dir = regk_sser_out; - gen_cfg.clk_dir = regk_sser_out; - break; - case SLAVE_OUTPUT: - port->output = 1; - port->input = 0; - frm_cfg.frame_pin_dir = regk_sser_in; - gen_cfg.clk_dir = regk_sser_in; - break; - case MASTER_INPUT: - port->output = 0; - port->input = 1; - frm_cfg.frame_pin_dir = regk_sser_out; - frm_cfg.out_on = regk_sser_intern_tb; - gen_cfg.clk_dir = regk_sser_out; - break; - case SLAVE_INPUT: - port->output = 0; - port->input = 1; - frm_cfg.frame_pin_dir = regk_sser_in; - gen_cfg.clk_dir = regk_sser_in; - break; - case MASTER_BIDIR: - port->output = 1; - port->input = 1; - frm_cfg.frame_pin_dir = regk_sser_out; - frm_cfg.out_on = regk_sser_intern_tb; - gen_cfg.clk_dir = regk_sser_out; - break; - case SLAVE_BIDIR: - port->output = 1; - port->input = 1; - frm_cfg.frame_pin_dir = regk_sser_in; - gen_cfg.clk_dir = regk_sser_in; - break; - default: - spin_unlock_irq(&port->lock); - return -EINVAL; - } - if (!port->use_dma || arg == MASTER_OUTPUT || - arg == SLAVE_OUTPUT) - intr_mask.rdav = regk_sser_yes; - break; - case SSP_FRAME_SYNC: - if (arg & NORMAL_SYNC) { - frm_cfg.rec_delay = 1; - frm_cfg.tr_delay = 1; - } else if (arg & EARLY_SYNC) - frm_cfg.rec_delay = frm_cfg.tr_delay = 0; - else if (arg & LATE_SYNC) { - frm_cfg.tr_delay = 2; - frm_cfg.rec_delay = 2; - } else if (arg & SECOND_WORD_SYNC) { - frm_cfg.rec_delay = 7; - frm_cfg.tr_delay = 1; - } - - tr_cfg.bulk_wspace = frm_cfg.tr_delay; - frm_cfg.early_wend = regk_sser_yes; - if (arg & BIT_SYNC) - frm_cfg.type = regk_sser_edge; - else if (arg & WORD_SYNC) - frm_cfg.type = regk_sser_level; - else if (arg & EXTENDED_SYNC) - frm_cfg.early_wend = regk_sser_no; - - if (arg & SYNC_ON) - frm_cfg.frame_pin_use = regk_sser_frm; - else if (arg & SYNC_OFF) - frm_cfg.frame_pin_use = regk_sser_gio0; - - dma_w_size = regk_dma_set_w_size2; - if (arg & WORD_SIZE_8) { - rec_cfg.sample_size = tr_cfg.sample_size = 7; - dma_w_size = regk_dma_set_w_size1; - } else if (arg & WORD_SIZE_12) - rec_cfg.sample_size = tr_cfg.sample_size = 11; - else if (arg & WORD_SIZE_16) - rec_cfg.sample_size = tr_cfg.sample_size = 15; - else if (arg & WORD_SIZE_24) - rec_cfg.sample_size = tr_cfg.sample_size = 23; - else if (arg & WORD_SIZE_32) - rec_cfg.sample_size = tr_cfg.sample_size = 31; - - if (arg & BIT_ORDER_MSB) - rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst; - else if (arg & BIT_ORDER_LSB) - rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst; - - if (arg & FLOW_CONTROL_ENABLE) { - frm_cfg.status_pin_use = regk_sser_frm; - rec_cfg.fifo_thr = regk_sser_thr16; - } else if (arg & FLOW_CONTROL_DISABLE) { - frm_cfg.status_pin_use = regk_sser_gio0; - rec_cfg.fifo_thr = regk_sser_inf; - } - - if (arg & CLOCK_NOT_GATED) - gen_cfg.gate_clk = regk_sser_no; - else if (arg & CLOCK_GATED) - gen_cfg.gate_clk = regk_sser_yes; - - break; - case SSP_IPOLARITY: - /* NOTE!! negedge is considered NORMAL */ - if (arg & CLOCK_NORMAL) - rec_cfg.clk_pol = regk_sser_neg; - else if (arg & CLOCK_INVERT) - rec_cfg.clk_pol = regk_sser_pos; - - if (arg & FRAME_NORMAL) - frm_cfg.level = regk_sser_pos_hi; - else if (arg & FRAME_INVERT) - frm_cfg.level = regk_sser_neg_lo; - - if (arg & STATUS_NORMAL) - gen_cfg.hold_pol = regk_sser_pos; - else if (arg & STATUS_INVERT) - gen_cfg.hold_pol = regk_sser_neg; - break; - case SSP_OPOLARITY: - if (arg & CLOCK_NORMAL) - gen_cfg.out_clk_pol = regk_sser_pos; - else if (arg & CLOCK_INVERT) - gen_cfg.out_clk_pol = regk_sser_neg; - - if (arg & FRAME_NORMAL) - frm_cfg.level = regk_sser_pos_hi; - else if (arg & FRAME_INVERT) - frm_cfg.level = regk_sser_neg_lo; - - if (arg & STATUS_NORMAL) - gen_cfg.hold_pol = regk_sser_pos; - else if (arg & STATUS_INVERT) - gen_cfg.hold_pol = regk_sser_neg; - break; - case SSP_SPI: - rec_cfg.fifo_thr = regk_sser_inf; - rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst; - rec_cfg.sample_size = tr_cfg.sample_size = 7; - frm_cfg.frame_pin_use = regk_sser_frm; - frm_cfg.type = regk_sser_level; - frm_cfg.tr_delay = 1; - frm_cfg.level = regk_sser_neg_lo; - if (arg & SPI_SLAVE) { - rec_cfg.clk_pol = regk_sser_neg; - gen_cfg.clk_dir = regk_sser_in; - port->input = 1; - port->output = 0; - } else { - gen_cfg.out_clk_pol = regk_sser_pos; - port->input = 0; - port->output = 1; - gen_cfg.clk_dir = regk_sser_out; - } - break; - case SSP_INBUFCHUNK: - break; - default: - return_val = -1; - } - - - if (port->started) { - rec_cfg.rec_en = port->input; - gen_cfg.en = (port->output | port->input); - } - - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); - REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); - - - if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 | - WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) { - int en = gen_cfg.en; - gen_cfg.en = 0; - REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); - /* ##### Should DMA be stoped before we change dma size? */ - DMA_WR_CMD(port->regi_dmain, dma_w_size); - DMA_WR_CMD(port->regi_dmaout, dma_w_size); - gen_cfg.en = en; - REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); - } - - spin_unlock_irq(&port->lock); - return return_val; -} - -static long sync_serial_ioctl(struct file *file, - unsigned int cmd, unsigned long arg) -{ - long ret; - - mutex_lock(&sync_serial_mutex); - ret = sync_serial_ioctl_unlocked(file, cmd, arg); - mutex_unlock(&sync_serial_mutex); - - return ret; -} - -/* NOTE: sync_serial_write does not support concurrency */ -static ssize_t sync_serial_write(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) -{ - int dev = iminor(file_inode(file)); - DECLARE_WAITQUEUE(wait, current); - struct sync_port *port; - int trunc_count; - unsigned long flags; - int bytes_free; - int out_buf_count; - - unsigned char *rd_ptr; /* First allocated byte in the buffer */ - unsigned char *wr_ptr; /* First free byte in the buffer */ - unsigned char *buf_stop_ptr; /* Last byte + 1 */ - - if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) { - DEBUG(pr_info("Invalid minor %d\n", dev)); - return -ENODEV; - } - port = &ports[dev]; - - /* |<- OUT_BUFFER_SIZE ->| - * |<- out_buf_count ->| - * |<- trunc_count ->| ...->| - * ______________________________________________________ - * | free | data | free | - * |_________|___________________|________________________| - * ^ rd_ptr ^ wr_ptr - */ - DEBUGWRITE(pr_info("W d%d c %u a: %p c: %p\n", - port->port_nbr, count, port->active_tr_descr, - port->catch_tr_descr)); - - /* Read variables that may be updated by interrupts */ - spin_lock_irqsave(&port->lock, flags); - rd_ptr = port->out_rd_ptr; - out_buf_count = port->out_buf_count; - spin_unlock_irqrestore(&port->lock, flags); - - /* Check if resources are available */ - if (port->tr_running && - ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) || - out_buf_count >= OUT_BUFFER_SIZE)) { - DEBUGWRITE(pr_info("sser%d full\n", dev)); - return -EAGAIN; - } - - buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE; - - /* Determine pointer to the first free byte, before copying. */ - wr_ptr = rd_ptr + out_buf_count; - if (wr_ptr >= buf_stop_ptr) - wr_ptr -= OUT_BUFFER_SIZE; - - /* If we wrap the ring buffer, let the user space program handle it by - * truncating the data. This could be more elegant, small buffer - * fragments may occur. - */ - bytes_free = OUT_BUFFER_SIZE - out_buf_count; - if (wr_ptr + bytes_free > buf_stop_ptr) - bytes_free = buf_stop_ptr - wr_ptr; - trunc_count = (count < bytes_free) ? count : bytes_free; - - if (copy_from_user(wr_ptr, buf, trunc_count)) - return -EFAULT; - - DEBUGOUTBUF(pr_info("%-4d + %-4d = %-4d %p %p %p\n", - out_buf_count, trunc_count, - port->out_buf_count, port->out_buffer, - wr_ptr, buf_stop_ptr)); - - /* Make sure transmitter/receiver is running */ - if (!port->started) { - reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg); - reg_sser_rw_rec_cfg rec_cfg = - REG_RD(sser, port->regi_sser, rw_rec_cfg); - cfg.en = regk_sser_yes; - rec_cfg.rec_en = port->input; - REG_WR(sser, port->regi_sser, rw_cfg, cfg); - REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); - port->started = 1; - } - - /* Setup wait if blocking */ - if (!(file->f_flags & O_NONBLOCK)) { - add_wait_queue(&port->out_wait_q, &wait); - set_current_state(TASK_INTERRUPTIBLE); - } - - spin_lock_irqsave(&port->lock, flags); - port->out_buf_count += trunc_count; - if (port->use_dma) { -#ifdef SYNC_SER_DMA - start_dma_out(port, wr_ptr, trunc_count); -#endif - } else if (!port->tr_running) { -#ifdef SYNC_SER_MANUAL - reg_sser_rw_intr_mask intr_mask; - intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask); - /* Start sender by writing data */ - send_word(port); - /* and enable transmitter ready IRQ */ - intr_mask.trdy = 1; - REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); -#endif - } - spin_unlock_irqrestore(&port->lock, flags); - - /* Exit if non blocking */ - if (file->f_flags & O_NONBLOCK) { - DEBUGWRITE(pr_info("w d%d c %u %08x\n", - port->port_nbr, trunc_count, - REG_RD_INT(dma, port->regi_dmaout, r_intr))); - return trunc_count; - } - - schedule(); - remove_wait_queue(&port->out_wait_q, &wait); - - if (signal_pending(current)) - return -EINTR; - - DEBUGWRITE(pr_info("w d%d c %u\n", port->port_nbr, trunc_count)); - return trunc_count; -} - -static ssize_t sync_serial_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) -{ - return __sync_serial_read(file, buf, count, ppos, NULL); -} - -#ifdef SYNC_SER_MANUAL -static void send_word(struct sync_port *port) -{ - reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - reg_sser_rw_tr_data tr_data = {0}; - - switch (tr_cfg.sample_size) { - case 8: - port->out_buf_count--; - tr_data.data = *port->out_rd_ptr++; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) - port->out_rd_ptr = port->out_buffer; - break; - case 12: - { - int data = (*port->out_rd_ptr++) << 8; - data |= *port->out_rd_ptr++; - port->out_buf_count -= 2; - tr_data.data = data; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) - port->out_rd_ptr = port->out_buffer; - break; - } - case 16: - port->out_buf_count -= 2; - tr_data.data = *(unsigned short *)port->out_rd_ptr; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->out_rd_ptr += 2; - if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) - port->out_rd_ptr = port->out_buffer; - break; - case 24: - port->out_buf_count -= 3; - tr_data.data = *(unsigned short *)port->out_rd_ptr; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->out_rd_ptr += 2; - tr_data.data = *port->out_rd_ptr++; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) - port->out_rd_ptr = port->out_buffer; - break; - case 32: - port->out_buf_count -= 4; - tr_data.data = *(unsigned short *)port->out_rd_ptr; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->out_rd_ptr += 2; - tr_data.data = *(unsigned short *)port->out_rd_ptr; - REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); - port->out_rd_ptr += 2; - if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE) - port->out_rd_ptr = port->out_buffer; - break; - } -} -#endif - -#ifdef SYNC_SER_DMA -static void start_dma_out(struct sync_port *port, const char *data, int count) -{ - port->active_tr_descr->buf = (char *)virt_to_phys((char *)data); - port->active_tr_descr->after = port->active_tr_descr->buf + count; - port->active_tr_descr->intr = 1; - - port->active_tr_descr->eol = 1; - port->prev_tr_descr->eol = 0; - - DEBUGTRDMA(pr_info("Inserting eolr:%p eol@:%p\n", - port->prev_tr_descr, port->active_tr_descr)); - port->prev_tr_descr = port->active_tr_descr; - port->active_tr_descr = phys_to_virt((int)port->active_tr_descr->next); - - if (!port->tr_running) { - reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, - rw_tr_cfg); - - port->out_context.next = NULL; - port->out_context.saved_data = - (dma_descr_data *)virt_to_phys(port->prev_tr_descr); - port->out_context.saved_data_buf = port->prev_tr_descr->buf; - - DMA_START_CONTEXT(port->regi_dmaout, - virt_to_phys((char *)&port->out_context)); - - tr_cfg.tr_en = regk_sser_yes; - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - DEBUGTRDMA(pr_info("dma s\n");); - } else { - DMA_CONTINUE_DATA(port->regi_dmaout); - DEBUGTRDMA(pr_info("dma c\n");); - } - - port->tr_running = 1; -} - -static void start_dma_in(struct sync_port *port) -{ - int i; - char *buf; - unsigned long flags; - spin_lock_irqsave(&port->lock, flags); - port->writep = port->flip; - spin_unlock_irqrestore(&port->lock, flags); - - buf = (char *)virt_to_phys(port->in_buffer); - for (i = 0; i < NBR_IN_DESCR; i++) { - port->in_descr[i].buf = buf; - port->in_descr[i].after = buf + port->inbufchunk; - port->in_descr[i].intr = 1; - port->in_descr[i].next = - (dma_descr_data *)virt_to_phys(&port->in_descr[i+1]); - port->in_descr[i].buf = buf; - buf += port->inbufchunk; - } - /* Link the last descriptor to the first */ - port->in_descr[i-1].next = - (dma_descr_data *)virt_to_phys(&port->in_descr[0]); - port->in_descr[i-1].eol = regk_sser_yes; - port->next_rx_desc = &port->in_descr[0]; - port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1]; - port->in_context.saved_data = - (dma_descr_data *)virt_to_phys(&port->in_descr[0]); - port->in_context.saved_data_buf = port->in_descr[0].buf; - DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context)); -} - -static irqreturn_t tr_interrupt(int irq, void *dev_id) -{ - reg_dma_r_masked_intr masked; - reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes }; - reg_dma_rw_stat stat; - int i; - int found = 0; - int stop_sser = 0; - - for (i = 0; i < NBR_PORTS; i++) { - struct sync_port *port = &ports[i]; - if (!port->enabled || !port->use_dma) - continue; - - /* IRQ active for the port? */ - masked = REG_RD(dma, port->regi_dmaout, r_masked_intr); - if (!masked.data) - continue; - - found = 1; - - /* Check if we should stop the DMA transfer */ - stat = REG_RD(dma, port->regi_dmaout, rw_stat); - if (stat.list_state == regk_dma_data_at_eol) - stop_sser = 1; - - /* Clear IRQ */ - REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr); - - if (!stop_sser) { - /* The DMA has completed a descriptor, EOL was not - * encountered, so step relevant descriptor and - * datapointers forward. */ - int sent; - sent = port->catch_tr_descr->after - - port->catch_tr_descr->buf; - DEBUGTXINT(pr_info("%-4d - %-4d = %-4d\t" - "in descr %p (ac: %p)\n", - port->out_buf_count, sent, - port->out_buf_count - sent, - port->catch_tr_descr, - port->active_tr_descr);); - port->out_buf_count -= sent; - port->catch_tr_descr = - phys_to_virt((int) port->catch_tr_descr->next); - port->out_rd_ptr = - phys_to_virt((int) port->catch_tr_descr->buf); - } else { - reg_sser_rw_tr_cfg tr_cfg; - int j, sent; - /* EOL handler. - * Note that if an EOL was encountered during the irq - * locked section of sync_ser_write the DMA will be - * restarted and the eol flag will be cleared. - * The remaining descriptors will be traversed by - * the descriptor interrupts as usual. - */ - j = 0; - while (!port->catch_tr_descr->eol) { - sent = port->catch_tr_descr->after - - port->catch_tr_descr->buf; - DEBUGOUTBUF(pr_info( - "traversing descr %p -%d (%d)\n", - port->catch_tr_descr, - sent, - port->out_buf_count)); - port->out_buf_count -= sent; - port->catch_tr_descr = phys_to_virt( - (int)port->catch_tr_descr->next); - j++; - if (j >= NBR_OUT_DESCR) { - /* TODO: Reset and recover */ - panic("sync_serial: missing eol"); - } - } - sent = port->catch_tr_descr->after - - port->catch_tr_descr->buf; - DEBUGOUTBUF(pr_info("eol at descr %p -%d (%d)\n", - port->catch_tr_descr, - sent, - port->out_buf_count)); - - port->out_buf_count -= sent; - - /* Update read pointer to first free byte, we - * may already be writing data there. */ - port->out_rd_ptr = - phys_to_virt((int) port->catch_tr_descr->after); - if (port->out_rd_ptr > port->out_buffer + - OUT_BUFFER_SIZE) - port->out_rd_ptr = port->out_buffer; - - tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg); - DEBUGTXINT(pr_info( - "tr_int DMA stop %d, set catch @ %p\n", - port->out_buf_count, - port->active_tr_descr)); - if (port->out_buf_count != 0) - pr_err("sync_ser: buf not empty after eol\n"); - port->catch_tr_descr = port->active_tr_descr; - port->tr_running = 0; - tr_cfg.tr_en = regk_sser_no; - REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); - } - /* wake up the waiting process */ - wake_up_interruptible(&port->out_wait_q); - } - return IRQ_RETVAL(found); -} /* tr_interrupt */ - - -static inline void handle_rx_packet(struct sync_port *port) -{ - int idx; - reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes }; - unsigned long flags; - - DEBUGRXINT(pr_info("!")); - spin_lock_irqsave(&port->lock, flags); - - /* If we overrun the user experience is crap regardless if we - * drop new or old data. Its much easier to get it right when - * dropping new data so lets do that. - */ - if ((port->writep + port->inbufchunk <= - port->flip + port->in_buffer_size) && - (port->in_buffer_len + port->inbufchunk < IN_BUFFER_SIZE)) { - memcpy(port->writep, - phys_to_virt((unsigned)port->next_rx_desc->buf), - port->inbufchunk); - port->writep += port->inbufchunk; - if (port->writep >= port->flip + port->in_buffer_size) - port->writep = port->flip; - - /* Timestamp the new data chunk. */ - if (port->write_ts_idx == NBR_IN_DESCR) - port->write_ts_idx = 0; - idx = port->write_ts_idx++; - ktime_get_ts(&port->timestamp[idx]); - port->in_buffer_len += port->inbufchunk; - } - spin_unlock_irqrestore(&port->lock, flags); - - port->next_rx_desc->eol = 1; - port->prev_rx_desc->eol = 0; - /* Cache bug workaround */ - flush_dma_descr(port->prev_rx_desc, 0); - port->prev_rx_desc = port->next_rx_desc; - port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next); - /* Cache bug workaround */ - flush_dma_descr(port->prev_rx_desc, 1); - /* wake up the waiting process */ - wake_up_interruptible(&port->in_wait_q); - DMA_CONTINUE(port->regi_dmain); - REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr); - -} - -static irqreturn_t rx_interrupt(int irq, void *dev_id) -{ - reg_dma_r_masked_intr masked; - - int i; - int found = 0; - - DEBUG(pr_info("rx_interrupt\n")); - - for (i = 0; i < NBR_PORTS; i++) { - struct sync_port *port = &ports[i]; - - if (!port->enabled || !port->use_dma) - continue; - - masked = REG_RD(dma, port->regi_dmain, r_masked_intr); - - if (!masked.data) - continue; - - /* Descriptor interrupt */ - found = 1; - while (REG_RD(dma, port->regi_dmain, rw_data) != - virt_to_phys(port->next_rx_desc)) - handle_rx_packet(port); - } - return IRQ_RETVAL(found); -} /* rx_interrupt */ -#endif /* SYNC_SER_DMA */ - -#ifdef SYNC_SER_MANUAL -static irqreturn_t manual_interrupt(int irq, void *dev_id) -{ - unsigned long flags; - int i; - int found = 0; - reg_sser_r_masked_intr masked; - - for (i = 0; i < NBR_PORTS; i++) { - struct sync_port *port = &ports[i]; - - if (!port->enabled || port->use_dma) - continue; - - masked = REG_RD(sser, port->regi_sser, r_masked_intr); - /* Data received? */ - if (masked.rdav) { - reg_sser_rw_rec_cfg rec_cfg = - REG_RD(sser, port->regi_sser, rw_rec_cfg); - reg_sser_r_rec_data data = REG_RD(sser, - port->regi_sser, r_rec_data); - found = 1; - /* Read data */ - spin_lock_irqsave(&port->lock, flags); - switch (rec_cfg.sample_size) { - case 8: - *port->writep++ = data.data & 0xff; - break; - case 12: - *port->writep = (data.data & 0x0ff0) >> 4; - *(port->writep + 1) = data.data & 0x0f; - port->writep += 2; - break; - case 16: - *(unsigned short *)port->writep = data.data; - port->writep += 2; - break; - case 24: - *(unsigned int *)port->writep = data.data; - port->writep += 3; - break; - case 32: - *(unsigned int *)port->writep = data.data; - port->writep += 4; - break; - } - - /* Wrap? */ - if (port->writep >= port->flip + port->in_buffer_size) - port->writep = port->flip; - if (port->writep == port->readp) { - /* Receive buf overrun, discard oldest data */ - port->readp++; - /* Wrap? */ - if (port->readp >= port->flip + - port->in_buffer_size) - port->readp = port->flip; - } - spin_unlock_irqrestore(&port->lock, flags); - if (sync_data_avail(port) >= port->inbufchunk) - /* Wake up application */ - wake_up_interruptible(&port->in_wait_q); - } - - /* Transmitter ready? */ - if (masked.trdy) { - found = 1; - /* More data to send */ - if (port->out_buf_count > 0) - send_word(port); - else { - /* Transmission finished */ - reg_sser_rw_intr_mask intr_mask; - intr_mask = REG_RD(sser, port->regi_sser, - rw_intr_mask); - intr_mask.trdy = 0; - REG_WR(sser, port->regi_sser, - rw_intr_mask, intr_mask); - /* Wake up application */ - wake_up_interruptible(&port->out_wait_q); - } - } - } - return IRQ_RETVAL(found); -} -#endif - -static int __init etrax_sync_serial_init(void) -{ -#if 1 - /* This code will be removed when we move to udev for all devices. */ - syncser_first = MKDEV(SYNC_SERIAL_MAJOR, 0); - if (register_chrdev_region(syncser_first, minor_count, SYNCSER_NAME)) { - pr_err("Failed to register major %d\n", SYNC_SERIAL_MAJOR); - return -1; - } -#else - /* Allocate dynamic major number. */ - if (alloc_chrdev_region(&syncser_first, 0, minor_count, SYNCSER_NAME)) { - pr_err("Failed to allocate character device region\n"); - return -1; - } -#endif - syncser_cdev = cdev_alloc(); - if (!syncser_cdev) { - pr_err("Failed to allocate cdev for syncser\n"); - unregister_chrdev_region(syncser_first, minor_count); - return -1; - } - cdev_init(syncser_cdev, &syncser_fops); - - /* Create a sysfs class for syncser */ - syncser_class = class_create(THIS_MODULE, "syncser_class"); - if (IS_ERR(syncser_class)) { - pr_err("Failed to create a sysfs class for syncser\n"); - unregister_chrdev_region(syncser_first, minor_count); - cdev_del(syncser_cdev); - return -1; - } - - /* Initialize Ports */ -#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) - if (artpec_pinmux_alloc_fixed(PINMUX_SSER0)) { - pr_warn("Unable to alloc pins for synchronous serial port 0\n"); - unregister_chrdev_region(syncser_first, minor_count); - return -EIO; - } - initialize_port(0); - ports[0].enabled = 1; - /* Register with sysfs so udev can pick it up. */ - device_create(syncser_class, NULL, syncser_first, NULL, - "%s%d", SYNCSER_NAME, 0); -#endif - -#if defined(CONFIG_ETRAXFS) && defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) - if (artpec_pinmux_alloc_fixed(PINMUX_SSER1)) { - pr_warn("Unable to alloc pins for synchronous serial port 1\n"); - unregister_chrdev_region(syncser_first, minor_count); - class_destroy(syncser_class); - return -EIO; - } - initialize_port(1); - ports[1].enabled = 1; - /* Register with sysfs so udev can pick it up. */ - device_create(syncser_class, NULL, syncser_first, NULL, - "%s%d", SYNCSER_NAME, 0); -#endif - - /* Add it to system */ - if (cdev_add(syncser_cdev, syncser_first, minor_count) < 0) { - pr_err("Failed to add syncser as char device\n"); - device_destroy(syncser_class, syncser_first); - class_destroy(syncser_class); - cdev_del(syncser_cdev); - unregister_chrdev_region(syncser_first, minor_count); - return -1; - } - - - pr_info("ARTPEC synchronous serial port (%s: %d, %d)\n", - SYNCSER_NAME, MAJOR(syncser_first), MINOR(syncser_first)); - - return 0; -} - -static void __exit etrax_sync_serial_exit(void) -{ - int i; - device_destroy(syncser_class, syncser_first); - class_destroy(syncser_class); - - if (syncser_cdev) { - cdev_del(syncser_cdev); - unregister_chrdev_region(syncser_first, minor_count); - } - for (i = 0; i < NBR_PORTS; i++) { - struct sync_port *port = &ports[i]; - if (port->init_irqs == dma_irq_setup) { - /* Free dma irqs and dma channels. */ -#ifdef SYNC_SER_DMA - artpec_free_dma(port->dma_in_nbr); - artpec_free_dma(port->dma_out_nbr); - free_irq(port->dma_out_intr_vect, port); - free_irq(port->dma_in_intr_vect, port); -#endif - } else if (port->init_irqs == manual_irq_setup) { - /* Free manual irq. */ - free_irq(port->syncser_intr_vect, port); - } - } - - pr_info("ARTPEC synchronous serial port unregistered\n"); -} - -module_init(etrax_sync_serial_init); -module_exit(etrax_sync_serial_exit); - -MODULE_LICENSE("GPL"); - diff --git a/arch/cris/arch-v32/kernel/Makefile b/arch/cris/arch-v32/kernel/Makefile deleted file mode 100644 index 2db7e4f7c1fa..000000000000 --- a/arch/cris/arch-v32/kernel/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -extra-y := head.o - - -obj-y := entry.o traps.o irq.o debugport.o \ - process.o ptrace.o setup.o signal.o traps.o time.o \ - cache.o cacheflush.o - -obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o -obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o -obj-$(CONFIG_MODULES) += crisksyms.o - -clean: - diff --git a/arch/cris/arch-v32/kernel/cache.c b/arch/cris/arch-v32/kernel/cache.c deleted file mode 100644 index a080d2fa4803..000000000000 --- a/arch/cris/arch-v32/kernel/cache.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include - -/* This file is used to workaround a cache bug, Guinness TR 106. */ - -inline void flush_dma_descr(struct dma_descr_data *descr, int flush_buf) -{ - /* Flush descriptor to make sure we get correct in_eop and after. */ - asm volatile ("ftagd [%0]" :: "r" (descr)); - /* Flush buffer pointed out by descriptor. */ - if (flush_buf) - cris_flush_cache_range(phys_to_virt((unsigned)descr->buf), - (unsigned)(descr->after - descr->buf)); -} -EXPORT_SYMBOL(flush_dma_descr); - -void flush_dma_list(struct dma_descr_data *descr) -{ - while (1) { - flush_dma_descr(descr, 1); - if (descr->eol) - break; - descr = phys_to_virt((unsigned)descr->next); - } -} -EXPORT_SYMBOL(flush_dma_list); - -/* From cacheflush.S */ -EXPORT_SYMBOL(cris_flush_cache); -/* From cacheflush.S */ -EXPORT_SYMBOL(cris_flush_cache_range); diff --git a/arch/cris/arch-v32/kernel/cacheflush.S b/arch/cris/arch-v32/kernel/cacheflush.S deleted file mode 100644 index 2a54d793f96c..000000000000 --- a/arch/cris/arch-v32/kernel/cacheflush.S +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - .global cris_flush_cache_range - .type cris_flush_cache_range, @function -cris_flush_cache_range: - move.d 1024, $r12 - cmp.d $r11, $r12 - bhi cris_flush_1KB - nop - add.d $r10, $r11 - ftagd [$r10] -cris_flush_last: - addq 32, $r10 - cmp.d $r11, $r10 - blt cris_flush_last - ftagd [$r10] - ret - nop -cris_flush_1KB: - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ftagd [$r10] - addq 32, $r10 - ba cris_flush_cache_range - sub.d $r12, $r11 - .size cris_flush_cache_range, . - cris_flush_cache_range - - .global cris_flush_cache - .type cris_flush_cache, @function -cris_flush_cache: - moveq 0, $r10 -cris_flush_line: - move.d 16*1024, $r11 - addq 16, $r10 - cmp.d $r10, $r11 - blt cris_flush_line - fidxd [$r10] - ret - nop - .size cris_flush_cache, . - cris_flush_cache - diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c deleted file mode 100644 index 8cc8ad1cb532..000000000000 --- a/arch/cris/arch-v32/kernel/crisksyms.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include - -/* Functions for allocating DMA channels */ -EXPORT_SYMBOL(crisv32_request_dma); -EXPORT_SYMBOL(crisv32_free_dma); - -/* Functions for handling internal RAM */ -EXPORT_SYMBOL(crisv32_intmem_alloc); -EXPORT_SYMBOL(crisv32_intmem_free); -EXPORT_SYMBOL(crisv32_intmem_phys_to_virt); -EXPORT_SYMBOL(crisv32_intmem_virt_to_phys); - -/* Functions for handling pinmux */ -EXPORT_SYMBOL(crisv32_pinmux_alloc); -EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed); -EXPORT_SYMBOL(crisv32_pinmux_dealloc); -EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed); - -/* Functions masking/unmasking interrupts */ -EXPORT_SYMBOL(crisv32_mask_irq); -EXPORT_SYMBOL(crisv32_unmask_irq); diff --git a/arch/cris/arch-v32/kernel/debugport.c b/arch/cris/arch-v32/kernel/debugport.c deleted file mode 100644 index 69247fd2090a..000000000000 --- a/arch/cris/arch-v32/kernel/debugport.c +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dbg_port -{ - unsigned char nbr; - unsigned long instance; - unsigned int started; - unsigned long baudrate; - unsigned char parity; - unsigned int bits; -}; - -struct dbg_port ports[] = -{ - { - 0, - regi_ser0, - 0, - 115200, - 'N', - 8 - }, - { - 1, - regi_ser1, - 0, - 115200, - 'N', - 8 - }, - { - 2, - regi_ser2, - 0, - 115200, - 'N', - 8 - }, - { - 3, - regi_ser3, - 0, - 115200, - 'N', - 8 - }, -#if CONFIG_ETRAX_SERIAL_PORTS == 5 - { - 4, - regi_ser4, - 0, - 115200, - 'N', - 8 - }, -#endif -}; - -static struct dbg_port *port = -#if defined(CONFIG_ETRAX_DEBUG_PORT0) - &ports[0]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) - &ports[1]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) - &ports[2]; -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) - &ports[3]; -#else - NULL; -#endif - -#ifdef CONFIG_ETRAX_KGDB -static struct dbg_port *kgdb_port = -#if defined(CONFIG_ETRAX_KGDB_PORT0) - &ports[0]; -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - &ports[1]; -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - &ports[2]; -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - &ports[3]; -#elif defined(CONFIG_ETRAX_KGDB_PORT4) - &ports[4]; -#else - NULL; -#endif -#endif - -static void start_port(struct dbg_port *p) -{ - /* Set up serial port registers */ - reg_ser_rw_tr_ctrl tr_ctrl = {0}; - reg_ser_rw_tr_dma_en tr_dma_en = {0}; - - reg_ser_rw_rec_ctrl rec_ctrl = {0}; - reg_ser_rw_tr_baud_div tr_baud_div = {0}; - reg_ser_rw_rec_baud_div rec_baud_div = {0}; - - if (!p || p->started) - return; - - p->started = 1; - - if (p->nbr == 1) - crisv32_pinmux_alloc_fixed(pinmux_ser1); - else if (p->nbr == 2) - crisv32_pinmux_alloc_fixed(pinmux_ser2); - else if (p->nbr == 3) - crisv32_pinmux_alloc_fixed(pinmux_ser3); -#if CONFIG_ETRAX_SERIAL_PORTS == 5 - else if (p->nbr == 4) - crisv32_pinmux_alloc_fixed(pinmux_ser4); -#endif - - tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493; - tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no; - tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8; - tr_ctrl.en = rec_ctrl.en = 1; - - if (p->parity == 'O') { - tr_ctrl.par_en = regk_ser_yes; - tr_ctrl.par = regk_ser_odd; - rec_ctrl.par_en = regk_ser_yes; - rec_ctrl.par = regk_ser_odd; - } else if (p->parity == 'E') { - tr_ctrl.par_en = regk_ser_yes; - tr_ctrl.par = regk_ser_even; - rec_ctrl.par_en = regk_ser_yes; - rec_ctrl.par = regk_ser_odd; - } - - if (p->bits == 7) { - tr_ctrl.data_bits = regk_ser_bits7; - rec_ctrl.data_bits = regk_ser_bits7; - } - - REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); - REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); - REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); - REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); - REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); -} - -#ifdef CONFIG_ETRAX_KGDB -/* Use polling to get a single character from the kernel debug port */ -int getDebugChar(void) -{ - reg_ser_rs_stat_din stat; - reg_ser_rw_ack_intr ack_intr = { 0 }; - - do { - stat = REG_RD(ser, kgdb_port->instance, rs_stat_din); - } while (!stat.dav); - - /* Ack the data_avail interrupt. */ - ack_intr.dav = 1; - REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr); - - return stat.data; -} - -/* Use polling to put a single character to the kernel debug port */ -void putDebugChar(int val) -{ - reg_ser_r_stat_din stat; - do { - stat = REG_RD(ser, kgdb_port->instance, r_stat_din); - } while (!stat.tr_rdy); - REG_WR_INT(ser, kgdb_port->instance, rw_dout, val); -} -#endif /* CONFIG_ETRAX_KGDB */ - -static void __init early_putch(int c) -{ - reg_ser_r_stat_din stat; - /* Wait until transmitter is ready and send. */ - do - stat = REG_RD(ser, port->instance, r_stat_din); - while (!stat.tr_rdy); - REG_WR_INT(ser, port->instance, rw_dout, c); -} - -static void __init -early_console_write(struct console *con, const char *s, unsigned n) -{ - extern void reset_watchdog(void); - int i; - - /* Send data. */ - for (i = 0; i < n; i++) { - /* TODO: the '\n' -> '\n\r' translation should be done at the - receiver. Remove it when the serial driver removes it. */ - if (s[i] == '\n') - early_putch('\r'); - early_putch(s[i]); - reset_watchdog(); - } -} - -static struct console early_console_dev __initdata = { - .name = "early", - .write = early_console_write, - .flags = CON_PRINTBUFFER | CON_BOOT, - .index = -1 -}; - -/* Register console for printk's, etc. */ -int __init init_etrax_debug(void) -{ - start_port(port); - - /* Register an early console if a debug port was chosen. */ - register_console(&early_console_dev); - -#ifdef CONFIG_ETRAX_KGDB - start_port(kgdb_port); -#endif /* CONFIG_ETRAX_KGDB */ - return 0; -} diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S deleted file mode 100644 index 0793a52b2c34..000000000000 --- a/arch/cris/arch-v32/kernel/entry.S +++ /dev/null @@ -1,909 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2000-2003 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * Tobias Anderberg (tobiasa@axis.com), CRISv32 port. - * - * Code for the system-call and fault low-level handling routines. - * - * NOTE: This code handles signal-recognition, which happens every time - * after a timer-interrupt and after each system call. - * - * Stack layout in 'ret_from_system_call': - * ptrace needs to have all regs on the stack. - * if the order here is changed, it needs to be - * updated in fork.c:copy_process, signal.c:do_signal, - * ptrace.c and ptrace.h - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - - ;; Exported functions. - .globl system_call - .globl ret_from_intr - .globl ret_from_fork - .globl ret_from_kernel_thread - .globl resume - .globl multiple_interrupt - .globl nmi_interrupt - .globl spurious_interrupt - .globl do_sigtrap - .globl gdb_handle_exception - .globl sys_call_table - - ; Check if preemptive kernel scheduling should be done. -#ifdef CONFIG_PREEMPT -_resume_kernel: - di - ; Load current task struct. - movs.w -8192, $r0 ; THREAD_SIZE = 8192 - and.d $sp, $r0 - - addoq +TI_preempt_count, $r0, $acr - move.d [$acr], $r10 ; Preemption disabled? - bne _Rexit - nop - -_need_resched: - addoq +TI_flags, $r0, $acr - move.d [$acr], $r10 - btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set. - bpl _Rexit - nop - - ; Do preemptive kernel scheduling. - jsr preempt_schedule_irq - nop - - ; Load new task struct. - movs.w -8192, $r0 ; THREAD_SIZE = 8192. - and.d $sp, $r0 - - ; One more time with new task. - ba _need_resched - nop -#else -#define _resume_kernel _Rexit -#endif - - ; Called at exit from fork. schedule_tail must be called to drop - ; spinlock if CONFIG_PREEMPT. - .type ret_from_fork,@function -ret_from_fork: - jsr schedule_tail - nop - ba ret_from_sys_call - nop - .size ret_from_fork, . - ret_from_fork - - .type ret_from_kernel_thread,@function -ret_from_kernel_thread: - jsr schedule_tail - nop - move.d $r2, $r10 - jsr $r1 - nop - moveq 0, $r9 ; no syscall restarts, TYVM... - ba ret_from_sys_call - nop - .size ret_from_kernel_thread, . - ret_from_kernel_thread - - .type ret_from_intr,@function -ret_from_intr: - moveq 0, $r9 ; not a syscall - - ;; Check for resched if preemptive kernel, or if we're going back to - ;; user-mode. This test matches the user_regs(regs) macro. Don't simply - ;; test CCS since that doesn't necessarily reflect what mode we'll - ;; return into. - addoq +PT_ccs, $sp, $acr - move.d [$acr], $r0 - btstq 16, $r0 ; User-mode flag. - bpl _resume_kernel - .size ret_from_intr, . - ret_from_intr + 2 ; +2 includes the dslot. - - ; Note that di below is in delay slot. - .type _resume_userspace,@function -_resume_userspace: - di ; So need_resched and sigpending don't change. - - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - addoq +TI_flags, $r0, $acr ; current->work - move.d [$acr], $r10 - and.d _TIF_WORK_MASK, $r10 ; Work to be done on return? - bne _work_pending - nop - ba _Rexit - nop - .size _resume_userspace, . - _resume_userspace - - ;; The system_call is called by a BREAK instruction, which looks pretty - ;; much like any other exception. - ;; - ;; System calls can't be made from interrupts but we still stack ERP - ;; to have a complete stack frame. - ;; - ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12, - ;; r13,mof,srp - ;; - ;; This function looks on the _surface_ like spaghetti programming, but it's - ;; really designed so that the fast-path does not force cache-loading of - ;; non-used instructions. Only the non-common cases cause the outlined code - ;; to run.. - - .type system_call,@function -system_call: - ;; Stack-frame similar to the irq heads, which is reversed in - ;; ret_from_sys_call. - - sub.d 92, $sp ; Skip EDA. - movem $r13, [$sp] - move.d $sp, $r8 - addq 14*4, $r8 - move.d $acr, $r0 - move $srs, $r1 - move $mof, $r2 - move $spc, $r3 - move $ccs, $r4 - move $srp, $r5 - move $erp, $r6 - move.d $r9, $r7 ; Store syscall number in EXS - subq 4, $sp - movem $r7, [$r8] - ei ; Enable interrupts while processing syscalls. - move.d $r10, [$sp] - - ; Set S-bit when kernel debugging to keep hardware breakpoints active. -#ifdef CONFIG_ETRAX_KGDB - move $ccs, $r0 - or.d (1<<9), $r0 - move $r0, $ccs -#endif - - movs.w -ENOSYS, $r0 - addoq +PT_r10, $sp, $acr - move.d $r0, [$acr] - - ;; Check if this process is syscall-traced. - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r0 - btstq TIF_SYSCALL_TRACE, $r0 - bmi _syscall_trace_entry - nop - -_syscall_traced: - ;; Check for sanity in the requested syscall number. - cmpu.w NR_syscalls, $r9 - bhs ret_from_sys_call - lslq 2, $r9 ; Multiply by 4, in the delay slot. - - ;; The location on the stack for the register structure is passed as a - ;; seventh argument. Some system calls need this. - move.d $sp, $r0 - subq 4, $sp - move.d $r0, [$sp] - - ;; The registers carrying parameters (R10-R13) are intact. The optional - ;; fifth and sixth parameters is in MOF and SRP respectively. Put them - ;; back on the stack. - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $mof, [$sp] - - ;; Actually to the system call. - addo.d +sys_call_table, $r9, $acr - move.d [$acr], $acr - jsr $acr - nop - - addq 3*4, $sp ; Pop the mof, srp and regs parameters. - addoq +PT_r10, $sp, $acr - move.d $r10, [$acr] ; Save the return value. - - moveq 1, $r9 ; "Parameter" to ret_from_sys_call to - ; show it was a sys call. - - ;; Fall through into ret_from_sys_call to return. - -ret_from_sys_call: - ;; R9 is a parameter: - ;; >= 1 from syscall - ;; 0 from irq - - ;; Get the current task-struct pointer. - movs.w -8192, $r0 ; THREAD_SIZE == 8192 - and.d $sp, $r0 - - di ; Make sure need_resched and sigpending don't change. - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r1 - and.d _TIF_ALLWORK_MASK, $r1 - bne _syscall_exit_work - nop - .size system_call, . - system_call - - .type _Rexit,@function -_Rexit: -#if defined(CONFIG_TRACE_IRQFLAGS) - addoq +PT_ccs, $sp, $acr - move.d [$acr], $r0 - btstq 15, $r0 ; I1 - bpl 1f - nop - jsr trace_hardirqs_on - nop -1: -#endif - - ;; This epilogue MUST match the prologues in multiple_interrupt, irq.h - ;; and ptregs.h. - addq 4, $sp ; Skip orig_r10. - movem [$sp+], $r13 ; Registers R0-R13. - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - move [$sp+], $mof - move [$sp+], $spc - move [$sp+], $ccs - move [$sp+], $srp - move [$sp+], $erp - addq 8, $sp ; Skip EXS, EDA. - jump $erp - rfe ; Restore condition code stack in delay-slot. - .size _Rexit, . - _Rexit - - ;; We get here after doing a syscall if extra work might need to be done - ;; perform syscall exit tracing if needed. - - .type _syscall_exit_work,@function -_syscall_exit_work: - ;; R0 contains current at this point and irq's are disabled. - - addoq +TI_flags, $r0, $acr - move.d [$acr], $r1 - btstq TIF_SYSCALL_TRACE, $r1 - bpl _work_pending - nop - ei - move.d $r9, $r1 ; Preserve R9. - jsr do_syscall_trace - nop - move.d $r1, $r9 - ba _resume_userspace - nop - .size _syscall_exit_work, . - _syscall_exit_work - - .type _work_pending,@function -_work_pending: - addoq +TI_flags, $r0, $acr - move.d [$acr], $r12 ; The thread_info_flags parameter. - move.d $sp, $r11 ; The regs param. - jsr do_work_pending - move.d $r9, $r10 ; The syscall/irq param. - - ba _Rexit - nop - .size _work_pending, . - _work_pending - - ;; We get here as a sidetrack when we've entered a syscall with the - ;; trace-bit set. We need to call do_syscall_trace and then continue - ;; with the call. - -_syscall_trace_entry: - ;; PT_r10 in the frame contains -ENOSYS as required, at this point. - - jsr do_syscall_trace - nop - - ;; Now re-enter the syscall code to do the syscall itself. We need to - ;; restore R9 here to contain the wanted syscall, and the other - ;; parameter-bearing registers. - addoq +PT_r9, $sp, $acr - move.d [$acr], $r9 - addoq +PT_orig_r10, $sp, $acr - move.d [$acr], $r10 ; PT_r10 is already -ENOSYS. - addoq +PT_r11, $sp, $acr - move.d [$acr], $r11 - addoq +PT_r12, $sp, $acr - move.d [$acr], $r12 - addoq +PT_r13, $sp, $acr - move.d [$acr], $r13 - addoq +PT_mof, $sp, $acr - move [$acr], $mof - addoq +PT_srp, $sp, $acr - move [$acr], $srp - - ba _syscall_traced - nop - - ;; Resume performs the actual task-switching, by switching stack - ;; pointers. Input arguments are: - ;; - ;; R10 = prev - ;; R11 = next - ;; R12 = thread offset in task struct. - ;; - ;; Returns old current in R10. - - .type resume,@function -resume: - subq 4, $sp ; Make space for srp. - - add.d $r12, $r10 ; R10 = current tasks tss. - addoq +THREAD_ccs, $r10, $acr - move $srp, [$sp] ; Keep old/new PC on the stack. - move $ccs, [$acr] ; Save IRQ enable state. - di - - addoq +THREAD_usp, $r10, $acr - subq 10*4, $sp ; Make room for R9. - move $usp, [$acr] ; Save user-mode stackpointer. - - ;; See copy_thread for the reason why register R9 is saved. - movem $r9, [$sp] ; Save non-scratch registers and R9. - - addoq +THREAD_ksp, $r10, $acr - move.d $sp, $r10 ; Return last running task in R10. - move.d $sp, [$acr] ; Save kernel SP for old task. - - and.d -8192, $r10 ; Get thread_info from stackpointer. - addoq +TI_task, $r10, $acr - add.d $r12, $r11 ; Find the new tasks tss. - move.d [$acr], $r10 ; Get task. - addoq +THREAD_ksp, $r11, $acr - move.d [$acr], $sp ; Switch to new stackframe. - addoq +THREAD_usp, $r11, $acr - movem [$sp+], $r9 ; Restore non-scratch registers and R9. - - move [$acr], $usp ; Restore user-mode stackpointer. - - addoq +THREAD_ccs, $r11, $acr - move.d [$sp+], $r11 - jump $r11 ; Restore PC. - move [$acr], $ccs ; Restore IRQ enable status. - .size resume, . - resume - -nmi_interrupt: - -;; If we receive a watchdog interrupt while it is not expected, then set -;; up a canonical frame and dump register contents before dying. - - ;; This prologue MUST match the one in irq.h and the struct in ptregs.h! - subq 12, $sp ; Skip EXS, EDA. - move $nrp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp ; Make room for R0-R13. - movem $r13, [$sp] ; Push R0-R13. - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - move.d REG_ADDR(intr_vect, regi_irq, r_nmi), $r0 - move.d [$r0], $r0 - btstq REG_BIT(intr_vect, r_nmi, watchdog), $r0 - bpl 1f - nop - jsr handle_watchdog_bite ; In time.c. - move.d $sp, $r10 ; Pointer to registers -1: btstq REG_BIT(intr_vect, r_nmi, ext), $r0 - bpl 1f - nop - jsr handle_nmi - move.d $sp, $r10 ; Pointer to registers -1: addq 4, $sp ; Skip orig_r10 - movem [$sp+], $r13 - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - move [$sp+], $mof - move [$sp+], $spc - move [$sp+], $ccs - move [$sp+], $srp - move [$sp+], $nrp - addq 8, $sp ; Skip EXS, EDA. - jump $nrp - rfn - - .comm cause_of_death, 4 ;; Don't declare this anywhere. - -spurious_interrupt: - di - jump hard_reset_now - nop - - ;; This handles the case when multiple interrupts arrive at the same - ;; time. Jump to the first set interrupt bit in a priority fashion. The - ;; hardware will call the unserved interrupts after the handler - ;; finishes. - .type multiple_interrupt, @function -multiple_interrupt: - ;; This prologue MUST match the one in irq.h and the struct in ptregs.h! - subq 12, $sp ; Skip EXS, EDA. - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp ; Make room for R0-R13. - movem $r13, [$sp] ; Push R0-R13. - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - -; Set S-bit when kernel debugging to keep hardware breakpoints active. -#ifdef CONFIG_ETRAX_KGDB - move $ccs, $r0 - or.d (1<<9), $r0 - move $r0, $ccs -#endif - - jsr crisv32_do_multiple - move.d $sp, $r10 - jump ret_from_intr - nop - .size multiple_interrupt, . - multiple_interrupt - -do_sigtrap: - ;; Sigtraps the process that executed the BREAK instruction. Creates a - ;; frame that Rexit expects. - subq 4, $sp - move $eda, [$sp] - subq 4, $sp - move $exs, [$sp] - subq 4, $sp - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - di ; Need to disable irq's at this point. - subq 14*4, $sp ; Make room for r0-r13. - movem $r13, [$sp] ; Push the r0-r13 registers. - subq 4, $sp - move.d $r10, [$sp] ; Push orig_r10. - - movs.w -8192, $r9 ; THREAD_SIZE == 8192 - and.d $sp, $r9 - - ;; thread_info as first parameter - move.d $r9, $r10 - moveq 5, $r11 ; SIGTRAP as second argument. - jsr ugdb_trap_user - nop - jump ret_from_intr ; Use the return routine for interrupts. - nop - -gdb_handle_exception: - subq 4, $sp - move.d $r0, [$sp] -#ifdef CONFIG_ETRAX_KGDB - move $ccs, $r0 ; U-flag not affected by previous insns. - btstq 16, $r0 ; Test the U-flag. - bmi _ugdb_handle_exception ; Go to user mode debugging. - nop ; Empty delay-slot (cannot pop R0 here). - ba kgdb_handle_exception ; Go to kernel debugging. - move.d [$sp+], $r0 ; Restore R0 in delay slot. -#endif - -_ugdb_handle_exception: - ba do_sigtrap ; SIGTRAP the offending process. - move.d [$sp+], $r0 ; Restore R0 in delay slot. - - .data - - .section .rodata,"a" -sys_call_table: - .long sys_restart_syscall ; 0 - old "setup()" system call, used - ; for restarting. - .long sys_exit - .long sys_fork - .long sys_read - .long sys_write - .long sys_open /* 5 */ - .long sys_close - .long sys_waitpid - .long sys_creat - .long sys_link - .long sys_unlink /* 10 */ - .long sys_execve - .long sys_chdir - .long sys_time - .long sys_mknod - .long sys_chmod /* 15 */ - .long sys_lchown16 - .long sys_ni_syscall /* old break syscall holder */ - .long sys_stat - .long sys_lseek - .long sys_getpid /* 20 */ - .long sys_mount - .long sys_oldumount - .long sys_setuid16 - .long sys_getuid16 - .long sys_stime /* 25 */ - .long sys_ptrace - .long sys_alarm - .long sys_fstat - .long sys_pause - .long sys_utime /* 30 */ - .long sys_ni_syscall /* old stty syscall holder */ - .long sys_ni_syscall /* old gtty syscall holder */ - .long sys_access - .long sys_nice - .long sys_ni_syscall /* 35 old ftime syscall holder */ - .long sys_sync - .long sys_kill - .long sys_rename - .long sys_mkdir - .long sys_rmdir /* 40 */ - .long sys_dup - .long sys_pipe - .long sys_times - .long sys_ni_syscall /* old prof syscall holder */ - .long sys_brk /* 45 */ - .long sys_setgid16 - .long sys_getgid16 - .long sys_signal - .long sys_geteuid16 - .long sys_getegid16 /* 50 */ - .long sys_acct - .long sys_umount /* recycled never used phys( */ - .long sys_ni_syscall /* old lock syscall holder */ - .long sys_ioctl - .long sys_fcntl /* 55 */ - .long sys_ni_syscall /* old mpx syscall holder */ - .long sys_setpgid - .long sys_ni_syscall /* old ulimit syscall holder */ - .long sys_ni_syscall /* old sys_olduname holder */ - .long sys_umask /* 60 */ - .long sys_chroot - .long sys_ustat - .long sys_dup2 - .long sys_getppid - .long sys_getpgrp /* 65 */ - .long sys_setsid - .long sys_sigaction - .long sys_sgetmask - .long sys_ssetmask - .long sys_setreuid16 /* 70 */ - .long sys_setregid16 - .long sys_sigsuspend - .long sys_sigpending - .long sys_sethostname - .long sys_setrlimit /* 75 */ - .long sys_old_getrlimit - .long sys_getrusage - .long sys_gettimeofday - .long sys_settimeofday - .long sys_getgroups16 /* 80 */ - .long sys_setgroups16 - .long sys_select /* was old_select in Linux/E100 */ - .long sys_symlink - .long sys_lstat - .long sys_readlink /* 85 */ - .long sys_uselib - .long sys_swapon - .long sys_reboot - .long sys_old_readdir - .long sys_old_mmap /* 90 */ - .long sys_munmap - .long sys_truncate - .long sys_ftruncate - .long sys_fchmod - .long sys_fchown16 /* 95 */ - .long sys_getpriority - .long sys_setpriority - .long sys_ni_syscall /* old profil syscall holder */ - .long sys_statfs - .long sys_fstatfs /* 100 */ - .long sys_ni_syscall /* sys_ioperm in i386 */ - .long sys_socketcall - .long sys_syslog - .long sys_setitimer - .long sys_getitimer /* 105 */ - .long sys_newstat - .long sys_newlstat - .long sys_newfstat - .long sys_ni_syscall /* old sys_uname holder */ - .long sys_ni_syscall /* sys_iopl in i386 */ - .long sys_vhangup - .long sys_ni_syscall /* old "idle" system call */ - .long sys_ni_syscall /* vm86old in i386 */ - .long sys_wait4 - .long sys_swapoff /* 115 */ - .long sys_sysinfo - .long sys_ipc - .long sys_fsync - .long sys_sigreturn - .long sys_clone /* 120 */ - .long sys_setdomainname - .long sys_newuname - .long sys_ni_syscall /* sys_modify_ldt */ - .long sys_adjtimex - .long sys_mprotect /* 125 */ - .long sys_sigprocmask - .long sys_ni_syscall /* old "create_module" */ - .long sys_init_module - .long sys_delete_module - .long sys_ni_syscall /* 130: old "get_kernel_syms" */ - .long sys_quotactl - .long sys_getpgid - .long sys_fchdir - .long sys_bdflush - .long sys_sysfs /* 135 */ - .long sys_personality - .long sys_ni_syscall /* for afs_syscall */ - .long sys_setfsuid16 - .long sys_setfsgid16 - .long sys_llseek /* 140 */ - .long sys_getdents - .long sys_select - .long sys_flock - .long sys_msync - .long sys_readv /* 145 */ - .long sys_writev - .long sys_getsid - .long sys_fdatasync - .long sys_sysctl - .long sys_mlock /* 150 */ - .long sys_munlock - .long sys_mlockall - .long sys_munlockall - .long sys_sched_setparam - .long sys_sched_getparam /* 155 */ - .long sys_sched_setscheduler - .long sys_sched_getscheduler - .long sys_sched_yield - .long sys_sched_get_priority_max - .long sys_sched_get_priority_min /* 160 */ - .long sys_sched_rr_get_interval - .long sys_nanosleep - .long sys_mremap - .long sys_setresuid16 - .long sys_getresuid16 /* 165 */ - .long sys_ni_syscall /* sys_vm86 */ - .long sys_ni_syscall /* Old sys_query_module */ - .long sys_poll - .long sys_ni_syscall /* Old nfsservctl */ - .long sys_setresgid16 /* 170 */ - .long sys_getresgid16 - .long sys_prctl - .long sys_rt_sigreturn - .long sys_rt_sigaction - .long sys_rt_sigprocmask /* 175 */ - .long sys_rt_sigpending - .long sys_rt_sigtimedwait - .long sys_rt_sigqueueinfo - .long sys_rt_sigsuspend - .long sys_pread64 /* 180 */ - .long sys_pwrite64 - .long sys_chown16 - .long sys_getcwd - .long sys_capget - .long sys_capset /* 185 */ - .long sys_sigaltstack - .long sys_sendfile - .long sys_ni_syscall /* streams1 */ - .long sys_ni_syscall /* streams2 */ - .long sys_vfork /* 190 */ - .long sys_getrlimit - .long sys_mmap2 - .long sys_truncate64 - .long sys_ftruncate64 - .long sys_stat64 /* 195 */ - .long sys_lstat64 - .long sys_fstat64 - .long sys_lchown - .long sys_getuid - .long sys_getgid /* 200 */ - .long sys_geteuid - .long sys_getegid - .long sys_setreuid - .long sys_setregid - .long sys_getgroups /* 205 */ - .long sys_setgroups - .long sys_fchown - .long sys_setresuid - .long sys_getresuid - .long sys_setresgid /* 210 */ - .long sys_getresgid - .long sys_chown - .long sys_setuid - .long sys_setgid - .long sys_setfsuid /* 215 */ - .long sys_setfsgid - .long sys_pivot_root - .long sys_mincore - .long sys_madvise - .long sys_getdents64 /* 220 */ - .long sys_fcntl64 - .long sys_ni_syscall /* reserved for TUX */ - .long sys_ni_syscall - .long sys_gettid - .long sys_readahead /* 225 */ - .long sys_setxattr - .long sys_lsetxattr - .long sys_fsetxattr - .long sys_getxattr - .long sys_lgetxattr /* 230 */ - .long sys_fgetxattr - .long sys_listxattr - .long sys_llistxattr - .long sys_flistxattr - .long sys_removexattr /* 235 */ - .long sys_lremovexattr - .long sys_fremovexattr - .long sys_tkill - .long sys_sendfile64 - .long sys_futex /* 240 */ - .long sys_sched_setaffinity - .long sys_sched_getaffinity - .long sys_ni_syscall /* sys_set_thread_area */ - .long sys_ni_syscall /* sys_get_thread_area */ - .long sys_io_setup /* 245 */ - .long sys_io_destroy - .long sys_io_getevents - .long sys_io_submit - .long sys_io_cancel - .long sys_fadvise64 /* 250 */ - .long sys_ni_syscall - .long sys_exit_group - .long sys_lookup_dcookie - .long sys_epoll_create - .long sys_epoll_ctl /* 255 */ - .long sys_epoll_wait - .long sys_remap_file_pages - .long sys_set_tid_address - .long sys_timer_create - .long sys_timer_settime /* 260 */ - .long sys_timer_gettime - .long sys_timer_getoverrun - .long sys_timer_delete - .long sys_clock_settime - .long sys_clock_gettime /* 265 */ - .long sys_clock_getres - .long sys_clock_nanosleep - .long sys_statfs64 - .long sys_fstatfs64 - .long sys_tgkill /* 270 */ - .long sys_utimes - .long sys_fadvise64_64 - .long sys_ni_syscall /* sys_vserver */ - .long sys_ni_syscall /* sys_mbind */ - .long sys_ni_syscall /* 275 sys_get_mempolicy */ - .long sys_ni_syscall /* sys_set_mempolicy */ - .long sys_mq_open - .long sys_mq_unlink - .long sys_mq_timedsend - .long sys_mq_timedreceive /* 280 */ - .long sys_mq_notify - .long sys_mq_getsetattr - .long sys_ni_syscall /* reserved for kexec */ - .long sys_waitid - .long sys_ni_syscall /* 285 */ /* available */ - .long sys_add_key - .long sys_request_key - .long sys_keyctl - .long sys_ioprio_set - .long sys_ioprio_get /* 290 */ - .long sys_inotify_init - .long sys_inotify_add_watch - .long sys_inotify_rm_watch - .long sys_migrate_pages - .long sys_openat /* 295 */ - .long sys_mkdirat - .long sys_mknodat - .long sys_fchownat - .long sys_futimesat - .long sys_fstatat64 /* 300 */ - .long sys_unlinkat - .long sys_renameat - .long sys_linkat - .long sys_symlinkat - .long sys_readlinkat /* 305 */ - .long sys_fchmodat - .long sys_faccessat - .long sys_pselect6 - .long sys_ppoll - .long sys_unshare /* 310 */ - .long sys_set_robust_list - .long sys_get_robust_list - .long sys_splice - .long sys_sync_file_range - .long sys_tee /* 315 */ - .long sys_vmsplice - .long sys_move_pages - .long sys_getcpu - .long sys_epoll_pwait - .long sys_utimensat /* 320 */ - .long sys_signalfd - .long sys_timerfd_create - .long sys_eventfd - .long sys_fallocate - .long sys_timerfd_settime /* 325 */ - .long sys_timerfd_gettime - .long sys_signalfd4 - .long sys_eventfd2 - .long sys_epoll_create1 - .long sys_dup3 /* 330 */ - .long sys_pipe2 - .long sys_inotify_init1 - .long sys_preadv - .long sys_pwritev - .long sys_setns /* 335 */ - .long sys_name_to_handle_at - .long sys_open_by_handle_at - .long sys_rt_tgsigqueueinfo - .long sys_perf_event_open - .long sys_recvmmsg /* 340 */ - .long sys_accept4 - .long sys_fanotify_init - .long sys_fanotify_mark - .long sys_prlimit64 - .long sys_clock_adjtime /* 345 */ - .long sys_syncfs - .long sys_sendmmsg - .long sys_process_vm_readv - .long sys_process_vm_writev - .long sys_kcmp /* 350 */ - .long sys_finit_module - .long sys_sched_setattr - .long sys_sched_getattr - .long sys_renameat2 - .long sys_seccomp /* 355 */ - .long sys_getrandom - .long sys_memfd_create - .long sys_bpf - .long sys_execveat - - /* - * NOTE!! This doesn't have to be exact - we just have - * to make sure we have _enough_ of the "sys_ni_syscall" - * entries. Don't panic if you notice that this hasn't - * been shrunk every time we add a new system call. - */ - - .rept NR_syscalls - (.-sys_call_table) / 4 - .long sys_ni_syscall - .endr - diff --git a/arch/cris/arch-v32/kernel/fasttimer.c b/arch/cris/arch-v32/kernel/fasttimer.c deleted file mode 100644 index 7452c70f61ff..000000000000 --- a/arch/cris/arch-v32/kernel/fasttimer.c +++ /dev/null @@ -1,793 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/fasttimer.c - * - * Fast timers for ETRAX FS - * - * Copyright (C) 2000-2006 Axis Communications AB, Lund, Sweden - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -/* - * timer0 is running at 100MHz and generating jiffies timer ticks - * at 100 or 1000 HZ. - * fasttimer gives an API that gives timers that expire "between" the jiffies - * giving microsecond resolution (10 ns). - * fasttimer uses reg_timer_rw_trig register to get interrupt when - * r_time reaches a certain value. - */ - - -#define DEBUG_LOG_INCLUDED -#define FAST_TIMER_LOG -/* #define FAST_TIMER_TEST */ - -#define FAST_TIMER_SANITY_CHECKS - -#ifdef FAST_TIMER_SANITY_CHECKS -static int sanity_failed; -#endif - -#define D1(x) -#define D2(x) -#define DP(x) - -static unsigned int fast_timer_running; -static unsigned int fast_timers_added; -static unsigned int fast_timers_started; -static unsigned int fast_timers_expired; -static unsigned int fast_timers_deleted; -static unsigned int fast_timer_is_init; -static unsigned int fast_timer_ints; - -struct fast_timer *fast_timer_list = NULL; - -#ifdef DEBUG_LOG_INCLUDED -#define DEBUG_LOG_MAX 128 -static const char * debug_log_string[DEBUG_LOG_MAX]; -static unsigned long debug_log_value[DEBUG_LOG_MAX]; -static unsigned int debug_log_cnt; -static unsigned int debug_log_cnt_wrapped; - -#define DEBUG_LOG(string, value) \ -{ \ - unsigned long log_flags; \ - local_irq_save(log_flags); \ - debug_log_string[debug_log_cnt] = (string); \ - debug_log_value[debug_log_cnt] = (unsigned long)(value); \ - if (++debug_log_cnt >= DEBUG_LOG_MAX) \ - { \ - debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \ - debug_log_cnt_wrapped = 1; \ - } \ - local_irq_restore(log_flags); \ -} -#else -#define DEBUG_LOG(string, value) -#endif - - -#define NUM_TIMER_STATS 16 -#ifdef FAST_TIMER_LOG -struct fast_timer timer_added_log[NUM_TIMER_STATS]; -struct fast_timer timer_started_log[NUM_TIMER_STATS]; -struct fast_timer timer_expired_log[NUM_TIMER_STATS]; -#endif - -int timer_div_settings[NUM_TIMER_STATS]; -int timer_delay_settings[NUM_TIMER_STATS]; - -struct work_struct fast_work; - -static void -timer_trig_handler(struct work_struct *work); - - - -/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */ -inline void do_gettimeofday_fast(struct fasttime_t *tv) -{ - tv->tv_jiff = jiffies; - tv->tv_usec = GET_JIFFIES_USEC(); -} - -inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1) -{ - /* Compare jiffies. Takes care of wrapping */ - if (time_before(t0->tv_jiff, t1->tv_jiff)) - return -1; - else if (time_after(t0->tv_jiff, t1->tv_jiff)) - return 1; - - /* Compare us */ - if (t0->tv_usec < t1->tv_usec) - return -1; - else if (t0->tv_usec > t1->tv_usec) - return 1; - return 0; -} - -/* Called with ints off */ -inline void start_timer_trig(unsigned long delay_us) -{ - reg_timer_rw_ack_intr ack_intr = { 0 }; - reg_timer_rw_intr_mask intr_mask; - reg_timer_rw_trig trig; - reg_timer_rw_trig_cfg trig_cfg = { 0 }; - reg_timer_r_time r_time0; - reg_timer_r_time r_time1; - unsigned char trig_wrap; - unsigned char time_wrap; - - r_time0 = REG_RD(timer, regi_timer0, r_time); - - D1(printk("start_timer_trig : %d us freq: %i div: %i\n", - delay_us, freq_index, div)); - /* Clear trig irq */ - intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); - intr_mask.trig = 0; - REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); - - /* Set timer values and check if trigger wraps. */ - /* r_time is 100MHz (10 ns resolution) */ - trig_wrap = (trig = r_time0 + delay_us*(1000/10)) < r_time0; - - timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig; - timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us; - - /* Ack interrupt */ - ack_intr.trig = 1; - REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); - - /* Start timer */ - REG_WR(timer, regi_timer0, rw_trig, trig); - trig_cfg.tmr = regk_timer_time; - REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); - - /* Check if we have already passed the trig time */ - r_time1 = REG_RD(timer, regi_timer0, r_time); - time_wrap = r_time1 < r_time0; - - if ((trig_wrap && !time_wrap) || (r_time1 < trig)) { - /* No, Enable trig irq */ - intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); - intr_mask.trig = 1; - REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); - fast_timers_started++; - fast_timer_running = 1; - } else { - /* We have passed the time, disable trig point, ack intr */ - trig_cfg.tmr = regk_timer_off; - REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); - REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); - /* call the int routine */ - INIT_WORK(&fast_work, timer_trig_handler); - schedule_work(&fast_work); - } - -} - -/* In version 1.4 this function takes 27 - 50 us */ -void start_one_shot_timer(struct fast_timer *t, - fast_timer_function_type *function, - unsigned long data, - unsigned long delay_us, - const char *name) -{ - unsigned long flags; - struct fast_timer *tmp; - - D1(printk("sft %s %d us\n", name, delay_us)); - - local_irq_save(flags); - - do_gettimeofday_fast(&t->tv_set); - tmp = fast_timer_list; - -#ifdef FAST_TIMER_SANITY_CHECKS - /* Check so this is not in the list already... */ - while (tmp != NULL) { - if (tmp == t) { - printk(KERN_DEBUG - "timer name: %s data: 0x%08lX already " - "in list!\n", name, data); - sanity_failed++; - goto done; - } else - tmp = tmp->next; - } - tmp = fast_timer_list; -#endif - - t->delay_us = delay_us; - t->function = function; - t->data = data; - t->name = name; - - t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000; - t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ; - if (t->tv_expires.tv_usec > 1000000) { - t->tv_expires.tv_usec -= 1000000; - t->tv_expires.tv_jiff += HZ; - } -#ifdef FAST_TIMER_LOG - timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t; -#endif - fast_timers_added++; - - /* Check if this should timeout before anything else */ - if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) { - /* Put first in list and modify the timer value */ - t->prev = NULL; - t->next = fast_timer_list; - if (fast_timer_list) - fast_timer_list->prev = t; - fast_timer_list = t; -#ifdef FAST_TIMER_LOG - timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; -#endif - start_timer_trig(delay_us); - } else { - /* Put in correct place in list */ - while (tmp->next && - fasttime_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0) - tmp = tmp->next; - /* Insert t after tmp */ - t->prev = tmp; - t->next = tmp->next; - if (tmp->next) - { - tmp->next->prev = t; - } - tmp->next = t; - } - - D2(printk("start_one_shot_timer: %d us done\n", delay_us)); - -done: - local_irq_restore(flags); -} /* start_one_shot_timer */ - -static inline int fast_timer_pending (const struct fast_timer * t) -{ - return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list); -} - -static inline int detach_fast_timer (struct fast_timer *t) -{ - struct fast_timer *next, *prev; - if (!fast_timer_pending(t)) - return 0; - next = t->next; - prev = t->prev; - if (next) - next->prev = prev; - if (prev) - prev->next = next; - else - fast_timer_list = next; - fast_timers_deleted++; - return 1; -} - -int del_fast_timer(struct fast_timer * t) -{ - unsigned long flags; - int ret; - - local_irq_save(flags); - ret = detach_fast_timer(t); - t->next = t->prev = NULL; - local_irq_restore(flags); - return ret; -} /* del_fast_timer */ - - -/* Interrupt routines or functions called in interrupt context */ - -/* Timer interrupt handler for trig interrupts */ - -static irqreturn_t -timer_trig_interrupt(int irq, void *dev_id) -{ - reg_timer_r_masked_intr masked_intr; - /* Check if the timer interrupt is for us (a trig int) */ - masked_intr = REG_RD(timer, regi_timer0, r_masked_intr); - if (!masked_intr.trig) - return IRQ_NONE; - timer_trig_handler(NULL); - return IRQ_HANDLED; -} - -static void timer_trig_handler(struct work_struct *work) -{ - reg_timer_rw_ack_intr ack_intr = { 0 }; - reg_timer_rw_intr_mask intr_mask; - reg_timer_rw_trig_cfg trig_cfg = { 0 }; - struct fast_timer *t; - fast_timer_function_type *f; - unsigned long d; - unsigned long flags; - - /* We keep interrupts disabled not only when we modify the - * fast timer list, but any time we hold a reference to a - * timer in the list, since del_fast_timer may be called - * from (another) interrupt context. Thus, the only time - * when interrupts are enabled is when calling the timer - * callback function. - */ - local_irq_save(flags); - - /* Clear timer trig interrupt */ - intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask); - intr_mask.trig = 0; - REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); - - /* First stop timer, then ack interrupt */ - /* Stop timer */ - trig_cfg.tmr = regk_timer_off; - REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); - - /* Ack interrupt */ - ack_intr.trig = 1; - REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); - - fast_timer_running = 0; - fast_timer_ints++; - - t = fast_timer_list; - while (t) { - struct fasttime_t tv; - - /* Has it really expired? */ - do_gettimeofday_fast(&tv); - D1(printk(KERN_DEBUG - "t: %is %06ius\n", tv.tv_jiff, tv.tv_usec)); - - if (fasttime_cmp(&t->tv_expires, &tv) <= 0) { - /* Yes it has expired */ -#ifdef FAST_TIMER_LOG - timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t; -#endif - fast_timers_expired++; - - /* Remove this timer before call, since it may reuse the timer */ - if (t->prev) - t->prev->next = t->next; - else - fast_timer_list = t->next; - if (t->next) - t->next->prev = t->prev; - t->prev = NULL; - t->next = NULL; - - /* Save function callback data before enabling - * interrupts, since the timer may be removed and we - * don't know how it was allocated (e.g. ->function - * and ->data may become overwritten after deletion - * if the timer was stack-allocated). - */ - f = t->function; - d = t->data; - - if (f != NULL) { - /* Run the callback function with interrupts - * enabled. */ - local_irq_restore(flags); - f(d); - local_irq_save(flags); - } else - DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints); - } else { - /* Timer is to early, let's set it again using the normal routines */ - D1(printk(".\n")); - } - - t = fast_timer_list; - if (t != NULL) { - /* Start next timer.. */ - long us = 0; - struct fasttime_t tv; - - do_gettimeofday_fast(&tv); - - /* time_after_eq takes care of wrapping */ - if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff)) - us = ((t->tv_expires.tv_jiff - tv.tv_jiff) * - 1000000 / HZ + t->tv_expires.tv_usec - - tv.tv_usec); - - if (us > 0) { - if (!fast_timer_running) { -#ifdef FAST_TIMER_LOG - timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t; -#endif - start_timer_trig(us); - } - break; - } else { - /* Timer already expired, let's handle it better late than never. - * The normal loop handles it - */ - D1(printk("e! %d\n", us)); - } - } - } - - local_irq_restore(flags); - - if (!t) - D1(printk("ttrig stop!\n")); -} - -static void wake_up_func(unsigned long data) -{ - wait_queue_head_t *sleep_wait_p = (wait_queue_head_t*)data; - wake_up(sleep_wait_p); -} - - -/* Useful API */ - -void schedule_usleep(unsigned long us) -{ - struct fast_timer t; - wait_queue_head_t sleep_wait; - init_waitqueue_head(&sleep_wait); - - D1(printk("schedule_usleep(%d)\n", us)); - start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us, - "usleep"); - /* Uninterruptible sleep on the fast timer. (The condition is - * somewhat redundant since the timer is what wakes us up.) */ - wait_event(sleep_wait, !fast_timer_pending(&t)); - - D1(printk("done schedule_usleep(%d)\n", us)); -} - -#ifdef CONFIG_PROC_FS -/* This value is very much based on testing */ -#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300) - -static int proc_fasttimer_show(struct seq_file *m, void *v) -{ - unsigned long flags; - int i = 0; - int num_to_show; - struct fasttime_t tv; - struct fast_timer *t, *nextt; - - do_gettimeofday_fast(&tv); - - seq_printf(m, "Fast timers added: %i\n", fast_timers_added); - seq_printf(m, "Fast timers started: %i\n", fast_timers_started); - seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints); - seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired); - seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted); - seq_printf(m, "Fast timer running: %s\n", - fast_timer_running ? "yes" : "no"); - seq_printf(m, "Current time: %lu.%06lu\n", - (unsigned long)tv.tv_jiff, - (unsigned long)tv.tv_usec); -#ifdef FAST_TIMER_SANITY_CHECKS - seq_printf(m, "Sanity failed: %i\n", sanity_failed); -#endif - seq_putc(m, '\n'); - -#ifdef DEBUG_LOG_INCLUDED - { - int end_i = debug_log_cnt; - i = 0; - - if (debug_log_cnt_wrapped) - i = debug_log_cnt; - - while ((i != end_i || debug_log_cnt_wrapped)) { - seq_printf(m, debug_log_string[i], debug_log_value[i]); - if (seq_has_overflowed(m)) - return 0; - i = (i+1) % DEBUG_LOG_MAX; - } - } - seq_putc(m, '\n'); -#endif - - num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started: - NUM_TIMER_STATS); - seq_printf(m, "Timers started: %i\n", fast_timers_started); - for (i = 0; i < num_to_show; i++) { - int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS; - -#if 1 //ndef FAST_TIMER_LOG - seq_printf(m, "div: %i delay: %i\n", - timer_div_settings[cur], - timer_delay_settings[cur]); -#endif -#ifdef FAST_TIMER_LOG - t = &timer_started_log[cur]; - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; -#endif - } - seq_putc(m, '\n'); - -#ifdef FAST_TIMER_LOG - num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added: - NUM_TIMER_STATS); - seq_printf(m, "Timers added: %i\n", fast_timers_added); - for (i = 0; i < num_to_show; i++) { - t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS]; - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; - } - seq_putc(m, '\n'); - - num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired: - NUM_TIMER_STATS); - seq_printf(m, "Timers expired: %i\n", fast_timers_expired); - for (i = 0; i < num_to_show; i++){ - t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS]; - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; - } - seq_putc(m, '\n'); -#endif - - seq_puts(m, "Active timers:\n"); - local_irq_save(flags); - t = fast_timer_list; - while (t != NULL){ - nextt = t->next; - local_irq_restore(flags); - seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n", - t->name, - (unsigned long)t->tv_set.tv_jiff, - (unsigned long)t->tv_set.tv_usec, - (unsigned long)t->tv_expires.tv_jiff, - (unsigned long)t->tv_expires.tv_usec, - t->delay_us, - t->data); - if (seq_has_overflowed(m)) - return 0; - local_irq_save(flags); - if (t->next != nextt) - printk("timer removed!\n"); - t = nextt; - } - local_irq_restore(flags); - return 0; -} - -static int proc_fasttimer_open(struct inode *inode, struct file *file) -{ - return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE); -} - -static const struct file_operations proc_fasttimer_fops = { - .open = proc_fasttimer_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -#endif /* PROC_FS */ - -#ifdef FAST_TIMER_TEST -static volatile unsigned long i = 0; -static volatile int num_test_timeout = 0; -static struct fast_timer tr[10]; -static int exp_num[10]; - -static struct fasttime_t tv_exp[100]; - -static void test_timeout(unsigned long data) -{ - do_gettimeofday_fast(&tv_exp[data]); - exp_num[data] = num_test_timeout; - - num_test_timeout++; -} - -static void test_timeout1(unsigned long data) -{ - do_gettimeofday_fast(&tv_exp[data]); - exp_num[data] = num_test_timeout; - if (data < 7) - { - start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1"); - i++; - } - num_test_timeout++; -} - -DP( -static char buf0[2000]; -static char buf1[2000]; -static char buf2[2000]; -static char buf3[2000]; -static char buf4[2000]; -); - -static char buf5[6000]; -static int j_u[1000]; - -static void fast_timer_test(void) -{ - int prev_num; - int j; - - struct fasttime_t tv, tv0, tv1, tv2; - - printk("fast_timer_test() start\n"); - do_gettimeofday_fast(&tv); - - for (j = 0; j < 1000; j++) - { - j_u[j] = GET_JIFFIES_USEC(); - } - for (j = 0; j < 100; j++) - { - do_gettimeofday_fast(&tv_exp[j]); - } - printk(KERN_DEBUG "fast_timer_test() %is %06i\n", tv.tv_jiff, tv.tv_usec); - - for (j = 0; j < 1000; j++) - { - printk(KERN_DEBUG "%i %i %i %i %i\n", - j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]); - j += 4; - } - for (j = 0; j < 100; j++) - { - printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n", - tv_exp[j].tv_jiff, tv_exp[j].tv_usec, - tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec, - tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec, - tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec, - tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec); - j += 4; - } - do_gettimeofday_fast(&tv0); - start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0"); - DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1"); - DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2"); - DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3"); - DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0)); - i++; - start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx"); - DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0)); - i++; - do_gettimeofday_fast(&tv1); - - proc_fasttimer_read(buf5, NULL, 0, 0, 0); - - prev_num = num_test_timeout; - while (num_test_timeout < i) - { - if (num_test_timeout != prev_num) - prev_num = num_test_timeout; - } - do_gettimeofday_fast(&tv2); - printk(KERN_INFO "Timers started %is %06i\n", - tv0.tv_jiff, tv0.tv_usec); - printk(KERN_INFO "Timers started at %is %06i\n", - tv1.tv_jiff, tv1.tv_usec); - printk(KERN_INFO "Timers done %is %06i\n", - tv2.tv_jiff, tv2.tv_usec); - DP(printk("buf0:\n"); - printk(buf0); - printk("buf1:\n"); - printk(buf1); - printk("buf2:\n"); - printk(buf2); - printk("buf3:\n"); - printk(buf3); - printk("buf4:\n"); - printk(buf4); - ); - printk("buf5:\n"); - printk(buf5); - - printk("timers set:\n"); - for(j = 0; jname, - t->tv_set.tv_jiff, - t->tv_set.tv_usec, - t->tv_expires.tv_jiff, - t->tv_expires.tv_usec, - t->data, - t->function - ); - - printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n", - t->delay_us, - tv_exp[j].tv_jiff, - tv_exp[j].tv_usec, - exp_num[j], - (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) * - 1000000 + tv_exp[j].tv_usec - - t->tv_expires.tv_usec); - } - proc_fasttimer_read(buf5, NULL, 0, 0, 0); - printk("buf5 after all done:\n"); - printk(buf5); - printk("fast_timer_test() done\n"); -} -#endif - - -int fast_timer_init(void) -{ - /* For some reason, request_irq() hangs when called froom time_init() */ - if (!fast_timer_is_init) - { - printk("fast_timer_init()\n"); - -#ifdef CONFIG_PROC_FS - proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops); -#endif /* PROC_FS */ - if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt, - IRQF_SHARED, - "fast timer int", &fast_timer_list)) - printk(KERN_ERR "err: fasttimer irq\n"); - fast_timer_is_init = 1; -#ifdef FAST_TIMER_TEST - printk("do test\n"); - fast_timer_test(); -#endif - } - return 0; -} -__initcall(fast_timer_init); diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S deleted file mode 100644 index 92f9fb1f6845..000000000000 --- a/arch/cris/arch-v32/kernel/head.S +++ /dev/null @@ -1,439 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * CRISv32 kernel startup code. - * - * Copyright (C) 2003, Axis Communications AB - */ - -#include - -#define ASSEMBLER_MACROS_ONLY - -/* - * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so - * -traditional must not be used when assembling this file. - */ -#include -#include -#include -#include -#include -#include - -#define CRAMFS_MAGIC 0x28cd3d45 -#define JHEAD_MAGIC 0x1FF528A6 -#define JHEAD_SIZE 8 -#define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 -#define NAND_BOOT_MAGIC 0x9a9db001 - - ;; NOTE: R8 and R9 carry information from the decompressor (if the - ;; kernel was compressed). They must not be used in the code below - ;; until they are read! - - ;; Exported symbols. - .global etrax_irv - .global romfs_start - .global romfs_length - .global romfs_in_flash - .global nand_boot - .global swapper_pg_dir - - __HEAD -tstart: - ;; This is the entry point of the kernel. The CPU is currently in - ;; supervisor mode. - ;; - ;; 0x00000000 if flash. - ;; 0x40004000 if DRAM. - ;; - di - - START_CLOCKS - - SETUP_WAIT_STATES - - GIO_INIT - - ;; Setup and enable the MMU. Use same configuration for both the data - ;; and the instruction MMU. - ;; - ;; Note; 3 cycles is needed for a bank-select to take effect. Further; - ;; bank 1 is the instruction MMU, bank 2 is the data MMU. - -#ifdef CONFIG_CRIS_MACH_ARTPEC3 - move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 5) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0 -#else - move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \ - | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0 -#endif - - ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00. - move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \ - | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1 - - ;; Enable certain page protections and setup linear mapping - ;; for f,e,c,b,4,0. - - ;; ARTPEC-3: - ;; c,d used for linear kernel mapping, up to 512 MB - ;; e used for vmalloc - ;; f unused, but page mapped to get page faults - - ;; ETRAX FS: - ;; c used for linear kernel mapping, up to 256 MB - ;; d used for vmalloc - ;; e,f used for memory-mapped NOR flash - -#ifdef CONFIG_CRIS_MACH_ARTPEC3 - move.d REG_STATE(mmu, rw_mm_cfg, we, on) \ - | REG_STATE(mmu, rw_mm_cfg, acc, on) \ - | REG_STATE(mmu, rw_mm_cfg, ex, on) \ - | REG_STATE(mmu, rw_mm_cfg, inv, on) \ - | REG_STATE(mmu, rw_mm_cfg, seg_f, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_e, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_d, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2 -#else - move.d REG_STATE(mmu, rw_mm_cfg, we, on) \ - | REG_STATE(mmu, rw_mm_cfg, acc, on) \ - | REG_STATE(mmu, rw_mm_cfg, ex, on) \ - | REG_STATE(mmu, rw_mm_cfg, inv, on) \ - | REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_d, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \ - | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \ - | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2 -#endif - - ;; Update instruction MMU. - move 1, $srs - nop - nop - nop - move $r0, $s2 ; kbase_hi. - move $r1, $s1 ; kbase_lo. - move $r2, $s0 ; mm_cfg, virtual memory configuration. - - ;; Update data MMU. - move 2, $srs - nop - nop - nop - move $r0, $s2 ; kbase_hi. - move $r1, $s1 ; kbase_lo - move $r2, $s0 ; mm_cfg, virtual memory configuration. - - ;; Enable data and instruction MMU. - move 0, $srs - moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on - nop - nop - nop - move $r0, $s0 - nop - nop - nop - - ; Check if starting from DRAM (network->RAM boot or unpacked - ; compressed kernel), or directly from flash. - lapcq ., $r0 - and.d 0x7fffffff, $r0 ; Mask off the non-cache bit. - cmp.d 0x10000, $r0 ; Arbitrary, something above this code. - blo _inflash0 - nop - - jump _inram ; Jump to cached RAM. - nop - - ;; Jumpgate. -_inflash0: - jump _inflash - nop - - ;; Put the following in a section so that storage for it can be - ;; reclaimed after init is finished. - __INIT - -_inflash: - - ;; Initialize DRAM. - cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? - beq _dram_initialized - nop - -#if defined CONFIG_ETRAXFS -#include "../mach-fs/dram_init.S" -#elif defined CONFIG_CRIS_MACH_ARTPEC3 -#include "../mach-a3/dram_init.S" -#else -#error Only ETRAXFS and ARTPEC-3 supported! -#endif - - -_dram_initialized: - ;; Copy the text and data section to DRAM. This depends on that the - ;; variables used below are correctly set up by the linker script. - ;; The calculated value stored in R4 is used below. - ;; Leave the cramfs file system (piggybacked after the kernel) in flash. - moveq 0, $r0 ; Source. - move.d text_start, $r1 ; Destination. - move.d __vmlinux_end, $r2 - move.d $r2, $r4 - sub.d $r1, $r4 -1: move.w [$r0+], $r3 - move.w $r3, [$r1+] - cmp.d $r2, $r1 - blo 1b - nop - - ;; Check for cramfs. - moveq 0, $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - move.d [$r4], $r0 ; cramfs_super.magic - cmp.d CRAMFS_MAGIC, $r0 - bne 1f - nop - - ;; Set length and start of cramfs, set romfs_in_flash flag - addoq +4, $r4, $acr - move.d [$acr], $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory. - move.d romfs_start, $r1 - move.d $r4, [$r1] -1: moveq 1, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - - jump _start_it ; Jump to cached code. - nop - -_inram: - ;; Check if booting from NAND flash; if so, set appropriate flags - ;; and move on. - cmp.d NAND_BOOT_MAGIC, $r12 - bne move_cramfs ; not nand, jump - moveq 1, $r0 - move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND - move.d $r0, [$r1] - moveq 0, $r0 ; tell axisflashmap romfs is not in - move.d romfs_in_flash, $r1 ; (directly accessed) flash - move.d $r0, [$r1] - jump _start_it ; continue with boot - nop - -move_cramfs: - ;; kernel is in DRAM. - ;; Must figure out if there is a piggybacked rootfs image or not. - ;; Set romfs_length to 0 => no rootfs image available by default. - moveq 0, $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - - ;; The kernel could have been unpacked to DRAM by the loader, but - ;; the cramfs image could still be in the flash immediately - ;; following the compressed kernel image. The loader passes the address - ;; of the byte succeeding the last compressed byte in the flash in - ;; register R9 when starting the kernel. - cmp.d 0x0ffffff8, $r9 - bhs _no_romfs_in_flash ; R9 points outside the flash area. - nop - ;; cramfs rootfs might to be in flash. Check for it. - move.d [$r9], $r0 ; cramfs_super.magic - cmp.d CRAMFS_MAGIC, $r0 - bne _no_romfs_in_flash - nop - - ;; found cramfs in flash. set address and size, and romfs_in_flash flag. - addoq +4, $r9, $acr - move.d [$acr], $r0 - move.d romfs_length, $r1 - move.d $r0, [$r1] - add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory. - move.d romfs_start, $r1 - move.d $r9, [$r1] - moveq 1, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - - jump _start_it ; Jump to cached code. - nop - -_no_romfs_in_flash: - ;; No romfs in flash, so look for cramfs, or jffs2 with jhead, - ;; after kernel in RAM, as is the case with network->RAM boot. - ;; For cramfs, partition starts with magic and length. - ;; For jffs2, a jhead is prepended which contains with magic and length. - ;; The jhead is not part of the jffs2 partition however. - move.d __bss_start, $r0 - move.d [$r0], $r1 - cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic? - beq 2f ; yes, jump - nop - cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic? - bne 4f ; no, skip copy - nop - addq 4, $r0 ; location of jffs2 size - move.d [$r0+], $r2 ; fetch jffs2 size -> r2 - ; r0 now points to start of jffs2 - ba 3f - nop -2: - addoq +4, $r0, $acr ; location of cramfs size - move.d [$acr], $r2 ; fetch cramfs size -> r2 - ; r0 still points to start of cramfs -3: - ;; Now, move the root fs to after kernel's BSS - - move.d _end, $r1 ; start of cramfs -> r1 - move.d romfs_start, $r3 - move.d $r1, [$r3] ; store at romfs_start (for axisflashmap) - move.d romfs_length, $r3 - move.d $r2, [$r3] ; store size at romfs_length - - add.d $r2, $r0 ; copy from end and downwards - add.d $r2, $r1 - - lsrq 1, $r2 ; Size is in bytes, we copy words. - addq 1, $r2 -1: - move.w [$r0], $r3 - move.w $r3, [$r1] - subq 2, $r0 - subq 2, $r1 - subq 1, $r2 - bne 1b - nop - -4: - ;; BSS move done. - ;; Clear romfs_in_flash flag, as we now know romfs is in DRAM - ;; Also clear nand_boot flag; if we got here, we know we've not - ;; booted from NAND flash. - moveq 0, $r0 - move.d romfs_in_flash, $r1 - move.d $r0, [$r1] - moveq 0, $r0 - move.d nand_boot, $r1 - move.d $r0, [$r1] - - jump _start_it ; Jump to cached code. - nop - -_start_it: - - ;; Check if kernel command line is supplied - cmp.d COMMAND_LINE_MAGIC, $r10 - bne no_command_line - nop - - move.d 256, $r13 - move.d cris_command_line, $r10 - or.d 0x80000000, $r11 ; Make it virtual -1: - move.b [$r11+], $r1 - move.b $r1, [$r10+] - subq 1, $r13 - bne 1b - nop - -no_command_line: - - ;; The kernel stack contains a task structure for each task. This - ;; the initial kernel stack is in the same page as the init_task, - ;; but starts at the top of the page, i.e. + 8192 bytes. - move.d init_thread_union + 8192, $sp - move.d ebp_start, $r0 ; Defined in linker-script. - move $r0, $ebp - move.d etrax_irv, $r1 ; Set the exception base register and pointer. - move.d $r0, [$r1] - - ;; Clear the BSS region from _bss_start to _end. - move.d __bss_start, $r0 - move.d _end, $r1 -1: clear.d [$r0+] - cmp.d $r1, $r0 - blo 1b - nop - - ; Initialize registers to increase determinism - move.d __bss_start, $r0 - movem [$r0], $r13 - -#ifdef CONFIG_ETRAX_L2CACHE - jsr l2cache_init - nop -#endif - - jump start_kernel ; Jump to start_kernel() in init/main.c. - nop - - .data -etrax_irv: - .dword 0 - -; Variables for communication with the Axis flash map driver (axisflashmap), -; and for setting up memory in arch/cris/kernel/setup.c . - -; romfs_start is set to the start of the root file system, if it exists -; in directly accessible memory (i.e. NOR Flash when booting from Flash, -; or RAM when booting directly from a network-downloaded RAM image) -romfs_start: - .dword 0 - -; romfs_length is set to the size of the root file system image, if it exists -; in directly accessible memory (see romfs_start). Otherwise it is set to 0. -romfs_length: - .dword 0 - -; romfs_in_flash is set to 1 if the root file system resides in directly -; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot -; or NAND flash boot. -romfs_in_flash: - .dword 0 - -; nand_boot is set to 1 when the kernel has been booted from NAND flash -nand_boot: - .dword 0 - -swapper_pg_dir = 0xc0002000 - - .section ".init.data", "aw" - -#if defined CONFIG_ETRAXFS -#include "../mach-fs/hw_settings.S" -#elif defined CONFIG_CRIS_MACH_ARTPEC3 -#include "../mach-a3/hw_settings.S" -#else -#error Only ETRAXFS and ARTPEC-3 supported! -#endif diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c deleted file mode 100644 index 414afd543232..000000000000 --- a/arch/cris/arch-v32/kernel/irq.c +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CPU_FIXED -1 - -/* IRQ masks (refer to comment for crisv32_do_multiple) */ -#if TIMER0_INTR_VECT - FIRST_IRQ < 32 -#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ)) -#undef TIMER_VECT1 -#else -#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32)) -#define TIMER_VECT1 -#endif -#ifdef CONFIG_ETRAX_KGDB -#if defined(CONFIG_ETRAX_KGDB_PORT0) -#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ)) -#elif defined(CONFIG_ETRAX_KGDB_PORT1) -#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ)) -#elif defined(CONFIG_ETRAX_KGDB_PORT2) -#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ)) -#elif defined(CONFIG_ETRAX_KGDB_PORT3) -#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ)) -#endif -#endif - -DEFINE_SPINLOCK(irq_lock); - -struct cris_irq_allocation -{ - int cpu; /* The CPU to which the IRQ is currently allocated. */ - cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */ -}; - -struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] = - { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} }; - -static unsigned long irq_regs[NR_CPUS] = -{ - regi_irq, -}; - -#if NR_REAL_IRQS > 32 -#define NBR_REGS 2 -#else -#define NBR_REGS 1 -#endif - -unsigned long cpu_irq_counters[NR_CPUS]; -unsigned long irq_counters[NR_REAL_IRQS]; - -/* From irq.c. */ -extern void weird_irq(void); - -/* From entry.S. */ -extern void system_call(void); -extern void nmi_interrupt(void); -extern void multiple_interrupt(void); -extern void gdb_handle_exception(void); -extern void i_mmu_refill(void); -extern void i_mmu_invalid(void); -extern void i_mmu_access(void); -extern void i_mmu_execute(void); -extern void d_mmu_refill(void); -extern void d_mmu_invalid(void); -extern void d_mmu_access(void); -extern void d_mmu_write(void); - -/* From kgdb.c. */ -extern void kgdb_init(void); -extern void breakpoint(void); - -/* From traps.c. */ -extern void breakh_BUG(void); - -/* - * Build the IRQ handler stubs using macros from irq.h. - */ -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -BUILD_TIMER_IRQ(0x31, 0) -#else -BUILD_IRQ(0x31) -#endif -BUILD_IRQ(0x32) -BUILD_IRQ(0x33) -BUILD_IRQ(0x34) -BUILD_IRQ(0x35) -BUILD_IRQ(0x36) -BUILD_IRQ(0x37) -BUILD_IRQ(0x38) -BUILD_IRQ(0x39) -BUILD_IRQ(0x3a) -BUILD_IRQ(0x3b) -BUILD_IRQ(0x3c) -BUILD_IRQ(0x3d) -BUILD_IRQ(0x3e) -BUILD_IRQ(0x3f) -BUILD_IRQ(0x40) -BUILD_IRQ(0x41) -BUILD_IRQ(0x42) -BUILD_IRQ(0x43) -BUILD_IRQ(0x44) -BUILD_IRQ(0x45) -BUILD_IRQ(0x46) -BUILD_IRQ(0x47) -BUILD_IRQ(0x48) -BUILD_IRQ(0x49) -BUILD_IRQ(0x4a) -#ifdef CONFIG_ETRAXFS -BUILD_TIMER_IRQ(0x4b, 0) -#else -BUILD_IRQ(0x4b) -#endif -BUILD_IRQ(0x4c) -BUILD_IRQ(0x4d) -BUILD_IRQ(0x4e) -BUILD_IRQ(0x4f) -BUILD_IRQ(0x50) -#if MACH_IRQS > 32 -BUILD_IRQ(0x51) -BUILD_IRQ(0x52) -BUILD_IRQ(0x53) -BUILD_IRQ(0x54) -BUILD_IRQ(0x55) -BUILD_IRQ(0x56) -BUILD_IRQ(0x57) -BUILD_IRQ(0x58) -BUILD_IRQ(0x59) -BUILD_IRQ(0x5a) -BUILD_IRQ(0x5b) -BUILD_IRQ(0x5c) -BUILD_IRQ(0x5d) -BUILD_IRQ(0x5e) -BUILD_IRQ(0x5f) -BUILD_IRQ(0x60) -BUILD_IRQ(0x61) -BUILD_IRQ(0x62) -BUILD_IRQ(0x63) -BUILD_IRQ(0x64) -BUILD_IRQ(0x65) -BUILD_IRQ(0x66) -BUILD_IRQ(0x67) -BUILD_IRQ(0x68) -BUILD_IRQ(0x69) -BUILD_IRQ(0x6a) -BUILD_IRQ(0x6b) -BUILD_IRQ(0x6c) -BUILD_IRQ(0x6d) -BUILD_IRQ(0x6e) -BUILD_IRQ(0x6f) -BUILD_IRQ(0x70) -#endif - -/* Pointers to the low-level handlers. */ -static void (*interrupt[MACH_IRQS])(void) = { - IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt, - IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt, - IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt, - IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt, - IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt, - IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt, - IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt, - IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt, - IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt, - IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt, - IRQ0x4f_interrupt, IRQ0x50_interrupt, -#if MACH_IRQS > 32 - IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt, - IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt, - IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt, - IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt, - IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt, - IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt, - IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt, - IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt, - IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt, - IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt, - IRQ0x6f_interrupt, IRQ0x70_interrupt, -#endif -}; - -void -block_irq(int irq, int cpu) -{ - int intr_mask; - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - /* Remember, 1 let thru, 0 block. */ - if (irq - FIRST_IRQ < 32) { - intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], - rw_mask, 0); - intr_mask &= ~(1 << (irq - FIRST_IRQ)); - REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, - 0, intr_mask); - } else { - intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], - rw_mask, 1); - intr_mask &= ~(1 << (irq - FIRST_IRQ - 32)); - REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, - 1, intr_mask); - } - spin_unlock_irqrestore(&irq_lock, flags); -} - -void -unblock_irq(int irq, int cpu) -{ - int intr_mask; - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - /* Remember, 1 let thru, 0 block. */ - if (irq - FIRST_IRQ < 32) { - intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], - rw_mask, 0); - intr_mask |= (1 << (irq - FIRST_IRQ)); - REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, - 0, intr_mask); - } else { - intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], - rw_mask, 1); - intr_mask |= (1 << (irq - FIRST_IRQ - 32)); - REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, - 1, intr_mask); - } - spin_unlock_irqrestore(&irq_lock, flags); -} - -/* Find out which CPU the irq should be allocated to. */ -static int irq_cpu(int irq) -{ - int cpu; - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - cpu = irq_allocations[irq - FIRST_IRQ].cpu; - - /* Fixed interrupts stay on the local CPU. */ - if (cpu == CPU_FIXED) - { - spin_unlock_irqrestore(&irq_lock, flags); - return smp_processor_id(); - } - - - /* Let the interrupt stay if possible */ - if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask)) - goto out; - - /* IRQ must be moved to another CPU. */ - cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask); - irq_allocations[irq - FIRST_IRQ].cpu = cpu; -out: - spin_unlock_irqrestore(&irq_lock, flags); - return cpu; -} - -void crisv32_mask_irq(int irq) -{ - int cpu; - - for (cpu = 0; cpu < NR_CPUS; cpu++) - block_irq(irq, cpu); -} - -void crisv32_unmask_irq(int irq) -{ - unblock_irq(irq, irq_cpu(irq)); -} - - -static void enable_crisv32_irq(struct irq_data *data) -{ - crisv32_unmask_irq(data->irq); -} - -static void disable_crisv32_irq(struct irq_data *data) -{ - crisv32_mask_irq(data->irq); -} - -static int set_affinity_crisv32_irq(struct irq_data *data, - const struct cpumask *dest, bool force) -{ - unsigned long flags; - - spin_lock_irqsave(&irq_lock, flags); - irq_allocations[data->irq - FIRST_IRQ].mask = *dest; - spin_unlock_irqrestore(&irq_lock, flags); - return 0; -} - -static struct irq_chip crisv32_irq_type = { - .name = "CRISv32", - .irq_shutdown = disable_crisv32_irq, - .irq_enable = enable_crisv32_irq, - .irq_disable = disable_crisv32_irq, - .irq_set_affinity = set_affinity_crisv32_irq, -}; - -void -set_exception_vector(int n, irqvectptr addr) -{ - etrax_irv->v[n] = (irqvectptr) addr; -} - -extern void do_IRQ(int irq, struct pt_regs * regs); - -void -crisv32_do_IRQ(int irq, int block, struct pt_regs* regs) -{ - /* Interrupts that may not be moved to another CPU may - * skip blocking. This is currently only valid for the - * timer IRQ and the IPI and is used for the timer - * interrupt to avoid watchdog starvation. - */ - if (!block) { - do_IRQ(irq, regs); - return; - } - - block_irq(irq, smp_processor_id()); - do_IRQ(irq, regs); - - unblock_irq(irq, irq_cpu(irq)); -} - -/* If multiple interrupts occur simultaneously we get a multiple - * interrupt from the CPU and software has to sort out which - * interrupts that happened. There are two special cases here: - * - * 1. Timer interrupts may never be blocked because of the - * watchdog (refer to comment in include/asr/arch/irq.h) - * 2. GDB serial port IRQs are unhandled here and will be handled - * as a single IRQ when it strikes again because the GDB - * stubb wants to save the registers in its own fashion. - */ -void -crisv32_do_multiple(struct pt_regs* regs) -{ - int cpu; - int mask; - int masked[NBR_REGS]; - int bit; - int i; - - cpu = smp_processor_id(); - - /* An extra irq_enter here to prevent softIRQs to run after - * each do_IRQ. This will decrease the interrupt latency. - */ - irq_enter(); - - for (i = 0; i < NBR_REGS; i++) { - /* Get which IRQs that happened. */ - masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], - r_masked_vect, i); - - /* Calculate new IRQ mask with these IRQs disabled. */ - mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i); - mask &= ~masked[i]; - - /* Timer IRQ is never masked */ -#ifdef TIMER_VECT1 - if ((i == 1) && (masked[0] & TIMER_MASK)) - mask |= TIMER_MASK; -#else - if ((i == 0) && (masked[0] & TIMER_MASK)) - mask |= TIMER_MASK; -#endif - /* Block all the IRQs */ - REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask); - - /* Check for timer IRQ and handle it special. */ -#ifdef TIMER_VECT1 - if ((i == 1) && (masked[i] & TIMER_MASK)) { - masked[i] &= ~TIMER_MASK; - do_IRQ(TIMER0_INTR_VECT, regs); - } -#else - if ((i == 0) && (masked[i] & TIMER_MASK)) { - masked[i] &= ~TIMER_MASK; - do_IRQ(TIMER0_INTR_VECT, regs); - } -#endif - } - -#ifdef IGNORE_MASK - /* Remove IRQs that can't be handled as multiple. */ - masked[0] &= ~IGNORE_MASK; -#endif - - /* Handle the rest of the IRQs. */ - for (i = 0; i < NBR_REGS; i++) { - for (bit = 0; bit < 32; bit++) { - if (masked[i] & (1 << bit)) - do_IRQ(bit + FIRST_IRQ + i*32, regs); - } - } - - /* Unblock all the IRQs. */ - for (i = 0; i < NBR_REGS; i++) { - mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i); - mask |= masked[i]; - REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask); - } - - /* This irq_exit() will trigger the soft IRQs. */ - irq_exit(); -} - -static int crisv32_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw_irq_num) -{ - irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq); - - return 0; -} - -static struct irq_domain_ops crisv32_irq_ops = { - .map = crisv32_irq_map, - .xlate = irq_domain_xlate_onecell, -}; - -/* - * This is called by start_kernel. It fixes the IRQ masks and setup the - * interrupt vector table to point to bad_interrupt pointers. - */ -void __init -init_IRQ(void) -{ - int i; - int j; - reg_intr_vect_rw_mask vect_mask = {0}; - struct device_node *np; - struct irq_domain *domain; - - /* Clear all interrupts masks. */ - for (i = 0; i < NBR_REGS; i++) - REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask); - - for (i = 0; i < 256; i++) - etrax_irv->v[i] = weird_irq; - - np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc"); - domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ, - FIRST_IRQ, FIRST_IRQ, - &crisv32_irq_ops, NULL); - BUG_ON(!domain); - irq_set_default_host(domain); - of_node_put(np); - - for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT && j < MACH_IRQS; i++, j++) - set_exception_vector(i, interrupt[j]); - - /* Mark Timer and IPI IRQs as CPU local */ - irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED; - irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU); - irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED; - irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU); - - set_exception_vector(0x00, nmi_interrupt); - set_exception_vector(0x30, multiple_interrupt); - - /* Set up handler for various MMU bus faults. */ - set_exception_vector(0x04, i_mmu_refill); - set_exception_vector(0x05, i_mmu_invalid); - set_exception_vector(0x06, i_mmu_access); - set_exception_vector(0x07, i_mmu_execute); - set_exception_vector(0x08, d_mmu_refill); - set_exception_vector(0x09, d_mmu_invalid); - set_exception_vector(0x0a, d_mmu_access); - set_exception_vector(0x0b, d_mmu_write); - -#ifdef CONFIG_BUG - /* Break 14 handler, used to implement cheap BUG(). */ - set_exception_vector(0x1e, breakh_BUG); -#endif - - /* The system-call trap is reached by "break 13". */ - set_exception_vector(0x1d, system_call); - - /* Exception handlers for debugging, both user-mode and kernel-mode. */ - - /* Break 8. */ - set_exception_vector(0x18, gdb_handle_exception); - /* Hardware single step. */ - set_exception_vector(0x3, gdb_handle_exception); - /* Hardware breakpoint. */ - set_exception_vector(0xc, gdb_handle_exception); - -#ifdef CONFIG_ETRAX_KGDB - kgdb_init(); - /* Everything is set up; now trap the kernel. */ - breakpoint(); -#endif -} - diff --git a/arch/cris/arch-v32/kernel/kgdb.c b/arch/cris/arch-v32/kernel/kgdb.c deleted file mode 100644 index 3d6f516763a5..000000000000 --- a/arch/cris/arch-v32/kernel/kgdb.c +++ /dev/null @@ -1,1593 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * arch/cris/arch-v32/kernel/kgdb.c - * - * CRIS v32 version by Orjan Friberg, Axis Communications AB. - * - * S390 version - * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation - * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), - * - * Originally written by Glenn Engel, Lake Stevens Instrument Division - * - * Contributed by HP Systems - * - * Modified for SPARC by Stu Grossman, Cygnus Support. - * - * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse - * Send complaints, suggestions etc. to - * - * Copyright (C) 1995 Andreas Busse - */ - -/* FIXME: Check the documentation. */ - -/* - * kgdb usage notes: - * ----------------- - * - * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be - * built with different gcc flags: "-g" is added to get debug infos, and - * "-fomit-frame-pointer" is omitted to make debugging easier. Since the - * resulting kernel will be quite big (approx. > 7 MB), it will be stripped - * before compresion. Such a kernel will behave just as usually, except if - * given a "debug=" command line option. (Only serial devices are - * allowed for , i.e. no printers or the like; possible values are - * machine depedend and are the same as for the usual debug device, the one - * for logging kernel messages.) If that option is given and the device can be - * initialized, the kernel will connect to the remote gdb in trap_init(). The - * serial parameters are fixed to 8N1 and 115200 bps, for easyness of - * implementation. - * - * To start a debugging session, start that gdb with the debugging kernel - * image (the one with the symbols, vmlinux.debug) named on the command line. - * This file will be used by gdb to get symbol and debugging infos about the - * kernel. Next, select remote debug mode by - * target remote - * where is the name of the serial device over which the debugged - * machine is connected. Maybe you have to adjust the baud rate by - * set remotebaud - * or also other parameters with stty: - * shell stty ... #. - * - * where - * :: - * :: < two hex digits computed as modulo 256 sum of > - * - * When a packet is received, it is first acknowledged with either '+' or '-'. - * '+' indicates a successful transfer. '-' indicates a failed transfer. - * - * Example: - * - * Host: Reply: - * $m0,10#2a +$00010203040506070809101112131415#42 - * - */ - - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -/* From entry.S. */ -extern void gdb_handle_exception(void); -/* From kgdb_asm.S. */ -extern void kgdb_handle_exception(void); - -static int kgdb_started = 0; - -/********************************* Register image ****************************/ - -typedef -struct register_image -{ - /* Offset */ - unsigned int r0; /* 0x00 */ - unsigned int r1; /* 0x04 */ - unsigned int r2; /* 0x08 */ - unsigned int r3; /* 0x0C */ - unsigned int r4; /* 0x10 */ - unsigned int r5; /* 0x14 */ - unsigned int r6; /* 0x18 */ - unsigned int r7; /* 0x1C */ - unsigned int r8; /* 0x20; Frame pointer (if any) */ - unsigned int r9; /* 0x24 */ - unsigned int r10; /* 0x28 */ - unsigned int r11; /* 0x2C */ - unsigned int r12; /* 0x30 */ - unsigned int r13; /* 0x34 */ - unsigned int sp; /* 0x38; R14, Stack pointer */ - unsigned int acr; /* 0x3C; R15, Address calculation register. */ - - unsigned char bz; /* 0x40; P0, 8-bit zero register */ - unsigned char vr; /* 0x41; P1, Version register (8-bit) */ - unsigned int pid; /* 0x42; P2, Process ID */ - unsigned char srs; /* 0x46; P3, Support register select (8-bit) */ - unsigned short wz; /* 0x47; P4, 16-bit zero register */ - unsigned int exs; /* 0x49; P5, Exception status */ - unsigned int eda; /* 0x4D; P6, Exception data address */ - unsigned int mof; /* 0x51; P7, Multiply overflow register */ - unsigned int dz; /* 0x55; P8, 32-bit zero register */ - unsigned int ebp; /* 0x59; P9, Exception base pointer */ - unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */ - unsigned int srp; /* 0x61; P11, Subroutine return pointer */ - unsigned int nrp; /* 0x65; P12, NMI return pointer */ - unsigned int ccs; /* 0x69; P13, Condition code stack */ - unsigned int usp; /* 0x6D; P14, User mode stack pointer */ - unsigned int spc; /* 0x71; P15, Single step PC */ - unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */ - -} registers; - -typedef -struct bp_register_image -{ - /* Support register bank 0. */ - unsigned int s0_0; - unsigned int s1_0; - unsigned int s2_0; - unsigned int s3_0; - unsigned int s4_0; - unsigned int s5_0; - unsigned int s6_0; - unsigned int s7_0; - unsigned int s8_0; - unsigned int s9_0; - unsigned int s10_0; - unsigned int s11_0; - unsigned int s12_0; - unsigned int s13_0; - unsigned int s14_0; - unsigned int s15_0; - - /* Support register bank 1. */ - unsigned int s0_1; - unsigned int s1_1; - unsigned int s2_1; - unsigned int s3_1; - unsigned int s4_1; - unsigned int s5_1; - unsigned int s6_1; - unsigned int s7_1; - unsigned int s8_1; - unsigned int s9_1; - unsigned int s10_1; - unsigned int s11_1; - unsigned int s12_1; - unsigned int s13_1; - unsigned int s14_1; - unsigned int s15_1; - - /* Support register bank 2. */ - unsigned int s0_2; - unsigned int s1_2; - unsigned int s2_2; - unsigned int s3_2; - unsigned int s4_2; - unsigned int s5_2; - unsigned int s6_2; - unsigned int s7_2; - unsigned int s8_2; - unsigned int s9_2; - unsigned int s10_2; - unsigned int s11_2; - unsigned int s12_2; - unsigned int s13_2; - unsigned int s14_2; - unsigned int s15_2; - - /* Support register bank 3. */ - unsigned int s0_3; /* BP_CTRL */ - unsigned int s1_3; /* BP_I0_START */ - unsigned int s2_3; /* BP_I0_END */ - unsigned int s3_3; /* BP_D0_START */ - unsigned int s4_3; /* BP_D0_END */ - unsigned int s5_3; /* BP_D1_START */ - unsigned int s6_3; /* BP_D1_END */ - unsigned int s7_3; /* BP_D2_START */ - unsigned int s8_3; /* BP_D2_END */ - unsigned int s9_3; /* BP_D3_START */ - unsigned int s10_3; /* BP_D3_END */ - unsigned int s11_3; /* BP_D4_START */ - unsigned int s12_3; /* BP_D4_END */ - unsigned int s13_3; /* BP_D5_START */ - unsigned int s14_3; /* BP_D5_END */ - unsigned int s15_3; /* BP_RESERVED */ - -} support_registers; - -enum register_name -{ - R0, R1, R2, R3, - R4, R5, R6, R7, - R8, R9, R10, R11, - R12, R13, SP, ACR, - - BZ, VR, PID, SRS, - WZ, EXS, EDA, MOF, - DZ, EBP, ERP, SRP, - NRP, CCS, USP, SPC, - PC, - - S0, S1, S2, S3, - S4, S5, S6, S7, - S8, S9, S10, S11, - S12, S13, S14, S15 - -}; - -/* The register sizes of the registers in register_name. An unimplemented register - is designated by size 0 in this array. */ -static int register_size[] = -{ - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - - 1, 1, 4, 1, - 2, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - - 4, - - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4, 4, - 4, 4, 4 - -}; - -/* Contains the register image of the kernel. - (Global so that they can be reached from assembler code.) */ -registers reg; -support_registers sreg; - -/************** Prototypes for local library functions ***********************/ - -/* Copy of strcpy from libc. */ -static char *gdb_cris_strcpy(char *s1, const char *s2); - -/* Copy of strlen from libc. */ -static int gdb_cris_strlen(const char *s); - -/* Copy of memchr from libc. */ -static void *gdb_cris_memchr(const void *s, int c, int n); - -/* Copy of strtol from libc. Does only support base 16. */ -static int gdb_cris_strtol(const char *s, char **endptr, int base); - -/********************** Prototypes for local functions. **********************/ - -/* Write a value to a specified register regno in the register image - of the current thread. */ -static int write_register(int regno, char *val); - -/* Read a value from a specified register in the register image. Returns the - status of the read operation. The register value is returned in valptr. */ -static int read_register(char regno, unsigned int *valptr); - -/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */ -int getDebugChar(void); - -/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */ -void putDebugChar(int val); - -/* Convert the memory, pointed to by mem into hexadecimal representation. - Put the result in buf, and return a pointer to the last character - in buf (null). */ -static char *mem2hex(char *buf, unsigned char *mem, int count); - -/* Put the content of the array, in binary representation, pointed to by buf - into memory pointed to by mem, and return a pointer to - the character after the last byte written. */ -static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count); - -/* Await the sequence $# and store in the array buffer - returned. */ -static void getpacket(char *buffer); - -/* Send $# from the in the array buffer. */ -static void putpacket(char *buffer); - -/* Build and send a response packet in order to inform the host the - stub is stopped. */ -static void stub_is_stopped(int sigval); - -/* All expected commands are sent from remote.c. Send a response according - to the description in remote.c. Not static since it needs to be reached - from assembler code. */ -void handle_exception(int sigval); - -/* Performs a complete re-start from scratch. ETRAX specific. */ -static void kill_restart(void); - -/******************** Prototypes for global functions. ***********************/ - -/* The string str is prepended with the GDB printout token and sent. */ -void putDebugString(const unsigned char *str, int len); - -/* A static breakpoint to be used at startup. */ -void breakpoint(void); - -/* Avoid warning as the internal_stack is not used in the C-code. */ -#define USEDVAR(name) { if (name) { ; } } -#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) } - -/********************************** Packet I/O ******************************/ -/* BUFMAX defines the maximum number of characters in - inbound/outbound buffers */ -/* FIXME: How do we know it's enough? */ -#define BUFMAX 512 - -/* Run-length encoding maximum length. Send 64 at most. */ -#define RUNLENMAX 64 - -/* The inbound/outbound buffers used in packet I/O */ -static char input_buffer[BUFMAX]; -static char output_buffer[BUFMAX]; - -/* Error and warning messages. */ -enum error_type -{ - SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08 -}; - -static char *error_message[] = -{ - "", - "E01 Set current or general thread - H[c,g] - internal error.", - "E02 Change register content - P - cannot change read-only register.", - "E03 Thread is not alive.", /* T, not used. */ - "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.", - "E05 Change register content - P - the register is not implemented..", - "E06 Change memory content - M - internal error.", - "E07 Change register content - P - the register is not stored on the stack", - "E08 Invalid parameter" -}; - -/********************************** Breakpoint *******************************/ -/* Use an internal stack in the breakpoint and interrupt response routines. - FIXME: How do we know the size of this stack is enough? - Global so it can be reached from assembler code. */ -#define INTERNAL_STACK_SIZE 1024 -char internal_stack[INTERNAL_STACK_SIZE]; - -/* Due to the breakpoint return pointer, a state variable is needed to keep - track of whether it is a static (compiled) or dynamic (gdb-invoked) - breakpoint to be handled. A static breakpoint uses the content of register - ERP as it is whereas a dynamic breakpoint requires subtraction with 2 - in order to execute the instruction. The first breakpoint is static; all - following are assumed to be dynamic. */ -static int dynamic_bp = 0; - -/********************************* String library ****************************/ -/* Single-step over library functions creates trap loops. */ - -/* Copy char s2[] to s1[]. */ -static char* -gdb_cris_strcpy(char *s1, const char *s2) -{ - char *s = s1; - - for (s = s1; (*s++ = *s2++) != '\0'; ) - ; - return s1; -} - -/* Find length of s[]. */ -static int -gdb_cris_strlen(const char *s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; sc++) - ; - return (sc - s); -} - -/* Find first occurrence of c in s[n]. */ -static void* -gdb_cris_memchr(const void *s, int c, int n) -{ - const unsigned char uc = c; - const unsigned char *su; - - for (su = s; 0 < n; ++su, --n) - if (*su == uc) - return (void *)su; - return NULL; -} -/******************************* Standard library ****************************/ -/* Single-step over library functions creates trap loops. */ -/* Convert string to long. */ -static int -gdb_cris_strtol(const char *s, char **endptr, int base) -{ - char *s1; - char *sd; - int x = 0; - - for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1) - x = x * base + (sd - hex_asc); - - if (endptr) { - /* Unconverted suffix is stored in endptr unless endptr is NULL. */ - *endptr = s1; - } - - return x; -} - -/********************************* Register image ****************************/ - -/* Write a value to a specified register in the register image of the current - thread. Returns status code SUCCESS, E02, E05 or E08. */ -static int -write_register(int regno, char *val) -{ - int status = SUCCESS; - - if (regno >= R0 && regno <= ACR) { - /* Consecutive 32-bit registers. */ - if (hex2bin((unsigned char *)®.r0 + (regno - R0) * sizeof(unsigned int), - val, sizeof(unsigned int))) - status = E08; - - } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) { - /* Read-only registers. */ - status = E02; - - } else if (regno == PID) { - /* 32-bit register. (Even though we already checked SRS and WZ, we cannot - combine this with the EXS - SPC write since SRS and WZ have different size.) */ - if (hex2bin((unsigned char *)®.pid, val, sizeof(unsigned int))) - status = E08; - - } else if (regno == SRS) { - /* 8-bit register. */ - if (hex2bin((unsigned char *)®.srs, val, sizeof(unsigned char))) - status = E08; - - } else if (regno >= EXS && regno <= SPC) { - /* Consecutive 32-bit registers. */ - if (hex2bin((unsigned char *)®.exs + (regno - EXS) * sizeof(unsigned int), - val, sizeof(unsigned int))) - status = E08; - - } else if (regno == PC) { - /* Pseudo-register. Treat as read-only. */ - status = E02; - - } else if (regno >= S0 && regno <= S15) { - /* 32-bit registers. */ - if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), - val, sizeof(unsigned int))) - status = E08; - } else { - /* Non-existing register. */ - status = E05; - } - return status; -} - -/* Read a value from a specified register in the register image. Returns the - value in the register or -1 for non-implemented registers. */ -static int -read_register(char regno, unsigned int *valptr) -{ - int status = SUCCESS; - - /* We read the zero registers from the register struct (instead of just returning 0) - to catch errors. */ - - if (regno >= R0 && regno <= ACR) { - /* Consecutive 32-bit registers. */ - *valptr = *(unsigned int *)((char *)®.r0 + (regno - R0) * sizeof(unsigned int)); - - } else if (regno == BZ || regno == VR) { - /* Consecutive 8-bit registers. */ - *valptr = (unsigned int)(*(unsigned char *) - ((char *)®.bz + (regno - BZ) * sizeof(char))); - - } else if (regno == PID) { - /* 32-bit register. */ - *valptr = *(unsigned int *)((char *)®.pid); - - } else if (regno == SRS) { - /* 8-bit register. */ - *valptr = (unsigned int)(*(unsigned char *)((char *)®.srs)); - - } else if (regno == WZ) { - /* 16-bit register. */ - *valptr = (unsigned int)(*(unsigned short *)(char *)®.wz); - - } else if (regno >= EXS && regno <= PC) { - /* Consecutive 32-bit registers. */ - *valptr = *(unsigned int *)((char *)®.exs + (regno - EXS) * sizeof(unsigned int)); - - } else if (regno >= S0 && regno <= S15) { - /* Consecutive 32-bit registers, located elsewhere. */ - *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int)); - - } else { - /* Non-existing register. */ - status = E05; - } - return status; - -} - -/********************************** Packet I/O ******************************/ -/* Convert the memory, pointed to by mem into hexadecimal representation. - Put the result in buf, and return a pointer to the last character - in buf (null). */ - -static char * -mem2hex(char *buf, unsigned char *mem, int count) -{ - int i; - int ch; - - if (mem == NULL) { - /* Invalid address, caught by 'm' packet handler. */ - for (i = 0; i < count; i++) { - *buf++ = '0'; - *buf++ = '0'; - } - } else { - /* Valid mem address. */ - for (i = 0; i < count; i++) { - ch = *mem++; - buf = hex_byte_pack(buf, ch); - } - } - /* Terminate properly. */ - *buf = '\0'; - return buf; -} - -/* Same as mem2hex, but puts it in network byte order. */ -static char * -mem2hex_nbo(char *buf, unsigned char *mem, int count) -{ - int i; - int ch; - - mem += count - 1; - for (i = 0; i < count; i++) { - ch = *mem--; - buf = hex_byte_pack(buf, ch); - } - - /* Terminate properly. */ - *buf = '\0'; - return buf; -} - -/* Put the content of the array, in binary representation, pointed to by buf - into memory pointed to by mem, and return a pointer to the character after - the last byte written. - Gdb will escape $, #, and the escape char (0x7d). */ -static unsigned char* -bin2mem(unsigned char *mem, unsigned char *buf, int count) -{ - int i; - unsigned char *next; - for (i = 0; i < count; i++) { - /* Check for any escaped characters. Be paranoid and - only unescape chars that should be escaped. */ - if (*buf == 0x7d) { - next = buf + 1; - if (*next == 0x3 || *next == 0x4 || *next == 0x5D) { - /* #, $, ESC */ - buf++; - *buf += 0x20; - } - } - *mem++ = *buf++; - } - return mem; -} - -/* Await the sequence $# and store in the array buffer - returned. */ -static void -getpacket(char *buffer) -{ - unsigned char checksum; - unsigned char xmitcsum; - int i; - int count; - char ch; - - do { - while((ch = getDebugChar ()) != '$') - /* Wait for the start character $ and ignore all other characters */; - checksum = 0; - xmitcsum = -1; - count = 0; - /* Read until a # or the end of the buffer is reached */ - while (count < BUFMAX) { - ch = getDebugChar(); - if (ch == '#') - break; - checksum = checksum + ch; - buffer[count] = ch; - count = count + 1; - } - - if (count >= BUFMAX) - continue; - - buffer[count] = 0; - - if (ch == '#') { - xmitcsum = hex_to_bin(getDebugChar()) << 4; - xmitcsum += hex_to_bin(getDebugChar()); - if (checksum != xmitcsum) { - /* Wrong checksum */ - putDebugChar('-'); - } else { - /* Correct checksum */ - putDebugChar('+'); - /* If sequence characters are received, reply with them */ - if (buffer[2] == ':') { - putDebugChar(buffer[0]); - putDebugChar(buffer[1]); - /* Remove the sequence characters from the buffer */ - count = gdb_cris_strlen(buffer); - for (i = 3; i <= count; i++) - buffer[i - 3] = buffer[i]; - } - } - } - } while (checksum != xmitcsum); -} - -/* Send $# from the in the array buffer. */ - -static void -putpacket(char *buffer) -{ - int checksum; - int runlen; - int encode; - - do { - char *src = buffer; - putDebugChar('$'); - checksum = 0; - while (*src) { - /* Do run length encoding */ - putDebugChar(*src); - checksum += *src; - runlen = 0; - while (runlen < RUNLENMAX && *src == src[runlen]) { - runlen++; - } - if (runlen > 3) { - /* Got a useful amount */ - putDebugChar ('*'); - checksum += '*'; - encode = runlen + ' ' - 4; - putDebugChar(encode); - checksum += encode; - src += runlen; - } else { - src++; - } - } - putDebugChar('#'); - putDebugChar(hex_asc_hi(checksum)); - putDebugChar(hex_asc_lo(checksum)); - } while(kgdb_started && (getDebugChar() != '+')); -} - -/* The string str is prepended with the GDB printout token and sent. Required - in traditional implementations. */ -void -putDebugString(const unsigned char *str, int len) -{ - /* Move SPC forward if we are single-stepping. */ - asm("spchere:"); - asm("move $spc, $r10"); - asm("cmp.d spchere, $r10"); - asm("bne nosstep"); - asm("nop"); - asm("move.d spccont, $r10"); - asm("move $r10, $spc"); - asm("nosstep:"); - - output_buffer[0] = 'O'; - mem2hex(&output_buffer[1], (unsigned char *)str, len); - putpacket(output_buffer); - - asm("spccont:"); -} - -/********************************** Handle exceptions ************************/ -/* Build and send a response packet in order to inform the host the - stub is stopped. TAAn...:r...;n...:r...;n...:r...; - AA = signal number - n... = register number (hex) - r... = register contents - n... = `thread' - r... = thread process ID. This is a hex integer. - n... = other string not starting with valid hex digit. - gdb should ignore this n,r pair and go on to the next. - This way we can extend the protocol. */ -static void -stub_is_stopped(int sigval) -{ - char *ptr = output_buffer; - unsigned int reg_cont; - - /* Send trap type (converted to signal) */ - - *ptr++ = 'T'; - ptr = hex_byte_pack(ptr, sigval); - - if (((reg.exs & 0xff00) >> 8) == 0xc) { - - /* Some kind of hardware watchpoint triggered. Find which one - and determine its type (read/write/access). */ - int S, bp, trig_bits = 0, rw_bits = 0; - int trig_mask = 0; - unsigned int *bp_d_regs = &sreg.s3_3; - /* In a lot of cases, the stopped data address will simply be EDA. - In some cases, we adjust it to match the watched data range. - (We don't want to change the actual EDA though). */ - unsigned int stopped_data_address; - /* The S field of EXS. */ - S = (reg.exs & 0xffff0000) >> 16; - - if (S & 1) { - /* Instruction watchpoint. */ - /* FIXME: Check against, and possibly adjust reported EDA. */ - } else { - /* Data watchpoint. Find the one that triggered. */ - for (bp = 0; bp < 6; bp++) { - - /* Dx_RD, Dx_WR in the S field of EXS for this BP. */ - int bitpos_trig = 1 + bp * 2; - /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */ - int bitpos_config = 2 + bp * 4; - - /* Get read/write trig bits for this BP. */ - trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig; - - /* Read/write config bits for this BP. */ - rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config; - if (trig_bits) { - /* Sanity check: the BP shouldn't trigger for accesses - that it isn't configured for. */ - if ((rw_bits == 0x1 && trig_bits != 0x1) || - (rw_bits == 0x2 && trig_bits != 0x2)) - panic("Invalid r/w trigging for this BP"); - - /* Mark this BP as trigged for future reference. */ - trig_mask |= (1 << bp); - - if (reg.eda >= bp_d_regs[bp * 2] && - reg.eda <= bp_d_regs[bp * 2 + 1]) { - /* EDA within range for this BP; it must be the one - we're looking for. */ - stopped_data_address = reg.eda; - break; - } - } - } - if (bp < 6) { - /* Found a trigged BP with EDA within its configured data range. */ - } else if (trig_mask) { - /* Something triggered, but EDA doesn't match any BP's range. */ - for (bp = 0; bp < 6; bp++) { - /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */ - int bitpos_config = 2 + bp * 4; - - /* Read/write config bits for this BP (needed later). */ - rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config; - - if (trig_mask & (1 << bp)) { - /* EDA within 31 bytes of the configured start address? */ - if (reg.eda + 31 >= bp_d_regs[bp * 2]) { - /* Changing the reported address to match - the start address of the first applicable BP. */ - stopped_data_address = bp_d_regs[bp * 2]; - break; - } else { - /* We continue since we might find another useful BP. */ - printk("EDA doesn't match trigged BP's range"); - } - } - } - } - - /* No match yet? */ - BUG_ON(bp >= 6); - /* Note that we report the type according to what the BP is configured - for (otherwise we'd never report an 'awatch'), not according to how - it trigged. We did check that the trigged bits match what the BP is - configured for though. */ - if (rw_bits == 0x1) { - /* read */ - strncpy(ptr, "rwatch", 6); - ptr += 6; - } else if (rw_bits == 0x2) { - /* write */ - strncpy(ptr, "watch", 5); - ptr += 5; - } else if (rw_bits == 0x3) { - /* access */ - strncpy(ptr, "awatch", 6); - ptr += 6; - } else { - panic("Invalid r/w bits for this BP."); - } - - *ptr++ = ':'; - /* Note that we don't read_register(EDA, ...) */ - ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]); - *ptr++ = ';'; - } - } - /* Only send PC, frame and stack pointer. */ - read_register(PC, ®_cont); - ptr = hex_byte_pack(ptr, PC); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[PC]); - *ptr++ = ';'; - - read_register(R8, ®_cont); - ptr = hex_byte_pack(ptr, R8); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[R8]); - *ptr++ = ';'; - - read_register(SP, ®_cont); - ptr = hex_byte_pack(ptr, SP); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[SP]); - *ptr++ = ';'; - - /* Send ERP as well; this will save us an entire register fetch in some cases. */ - read_register(ERP, ®_cont); - ptr = hex_byte_pack(ptr, ERP); - *ptr++ = ':'; - ptr = mem2hex(ptr, (unsigned char *)®_cont, register_size[ERP]); - *ptr++ = ';'; - - /* null-terminate and send it off */ - *ptr = 0; - putpacket(output_buffer); -} - -/* Returns the size of an instruction that has a delay slot. */ - -int insn_size(unsigned long pc) -{ - unsigned short opcode = *(unsigned short *)pc; - int size = 0; - - switch ((opcode & 0x0f00) >> 8) { - case 0x0: - case 0x9: - case 0xb: - size = 2; - break; - case 0xe: - case 0xf: - size = 6; - break; - case 0xd: - /* Could be 4 or 6; check more bits. */ - if ((opcode & 0xff) == 0xff) - size = 4; - else - size = 6; - break; - default: - panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc); - } - - return size; -} - -void register_fixup(int sigval) -{ - /* Compensate for ACR push at the beginning of exception handler. */ - reg.sp += 4; - - /* Standard case. */ - reg.pc = reg.erp; - if (reg.erp & 0x1) { - /* Delay slot bit set. Report as stopped on proper instruction. */ - if (reg.spc) { - /* Rely on SPC if set. */ - reg.pc = reg.spc; - } else { - /* Calculate the PC from the size of the instruction - that the delay slot we're in belongs to. */ - reg.pc += insn_size(reg.erp & ~1) - 1 ; - } - } - - if ((reg.exs & 0x3) == 0x0) { - /* Bits 1 - 0 indicate the type of memory operation performed - by the interrupted instruction. 0 means no memory operation, - and EDA is undefined in that case. We zero it to avoid confusion. */ - reg.eda = 0; - } - - if (sigval == SIGTRAP) { - /* Break 8, single step or hardware breakpoint exception. */ - - /* Check IDX field of EXS. */ - if (((reg.exs & 0xff00) >> 8) == 0x18) { - - /* Break 8. */ - - /* Static (compiled) breakpoints must return to the next instruction - in order to avoid infinite loops (default value of ERP). Dynamic - (gdb-invoked) must subtract the size of the break instruction from - the ERP so that the instruction that was originally in the break - instruction's place will be run when we return from the exception. */ - if (!dynamic_bp) { - /* Assuming that all breakpoints are dynamic from now on. */ - dynamic_bp = 1; - } else { - - /* Only if not in a delay slot. */ - if (!(reg.erp & 0x1)) { - reg.erp -= 2; - reg.pc -= 2; - } - } - - } else if (((reg.exs & 0xff00) >> 8) == 0x3) { - /* Single step. */ - /* Don't fiddle with S1. */ - - } else if (((reg.exs & 0xff00) >> 8) == 0xc) { - - /* Hardware watchpoint exception. */ - - /* SPC has been updated so that we will get a single step exception - when we return, but we don't want that. */ - reg.spc = 0; - - /* Don't fiddle with S1. */ - } - - } else if (sigval == SIGINT) { - /* Nothing special. */ - } -} - -static void insert_watchpoint(char type, int addr, int len) -{ - /* Breakpoint/watchpoint types (GDB terminology): - 0 = memory breakpoint for instructions - (not supported; done via memory write instead) - 1 = hardware breakpoint for instructions (supported) - 2 = write watchpoint (supported) - 3 = read watchpoint (supported) - 4 = access watchpoint (supported) */ - - if (type < '1' || type > '4') { - output_buffer[0] = 0; - return; - } - - /* Read watchpoints are set as access watchpoints, because of GDB's - inability to deal with pure read watchpoints. */ - if (type == '3') - type = '4'; - - if (type == '1') { - /* Hardware (instruction) breakpoint. */ - /* Bit 0 in BP_CTRL holds the configuration for I0. */ - if (sreg.s0_3 & 0x1) { - /* Already in use. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - /* Configure. */ - sreg.s1_3 = addr; - sreg.s2_3 = (addr + len - 1); - sreg.s0_3 |= 1; - } else { - int bp; - unsigned int *bp_d_regs = &sreg.s3_3; - - /* The watchpoint allocation scheme is the simplest possible. - For example, if a region is watched for read and - a write watch is requested, a new watchpoint will - be used. Also, if a watch for a region that is already - covered by one or more existing watchpoints, a new - watchpoint will be used. */ - - /* First, find a free data watchpoint. */ - for (bp = 0; bp < 6; bp++) { - /* Each data watchpoint's control registers occupy 2 bits - (hence the 3), starting at bit 2 for D0 (hence the 2) - with 4 bits between for each watchpoint (yes, the 4). */ - if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) { - break; - } - } - - if (bp > 5) { - /* We're out of watchpoints. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - - /* Configure the control register first. */ - if (type == '3' || type == '4') { - /* Trigger on read. */ - sreg.s0_3 |= (1 << (2 + bp * 4)); - } - if (type == '2' || type == '4') { - /* Trigger on write. */ - sreg.s0_3 |= (2 << (2 + bp * 4)); - } - - /* Ugly pointer arithmetics to configure the watched range. */ - bp_d_regs[bp * 2] = addr; - bp_d_regs[bp * 2 + 1] = (addr + len - 1); - } - - /* Set the S1 flag to enable watchpoints. */ - reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - gdb_cris_strcpy(output_buffer, "OK"); -} - -static void remove_watchpoint(char type, int addr, int len) -{ - /* Breakpoint/watchpoint types: - 0 = memory breakpoint for instructions - (not supported; done via memory write instead) - 1 = hardware breakpoint for instructions (supported) - 2 = write watchpoint (supported) - 3 = read watchpoint (supported) - 4 = access watchpoint (supported) */ - if (type < '1' || type > '4') { - output_buffer[0] = 0; - return; - } - - /* Read watchpoints are set as access watchpoints, because of GDB's - inability to deal with pure read watchpoints. */ - if (type == '3') - type = '4'; - - if (type == '1') { - /* Hardware breakpoint. */ - /* Bit 0 in BP_CTRL holds the configuration for I0. */ - if (!(sreg.s0_3 & 0x1)) { - /* Not in use. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - /* Deconfigure. */ - sreg.s1_3 = 0; - sreg.s2_3 = 0; - sreg.s0_3 &= ~1; - } else { - int bp; - unsigned int *bp_d_regs = &sreg.s3_3; - /* Try to find a watchpoint that is configured for the - specified range, then check that read/write also matches. */ - - /* Ugly pointer arithmetic, since I cannot rely on a - single switch (addr) as there may be several watchpoints with - the same start address for example. */ - - for (bp = 0; bp < 6; bp++) { - if (bp_d_regs[bp * 2] == addr && - bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { - /* Matching range. */ - int bitpos = 2 + bp * 4; - int rw_bits; - - /* Read/write bits for this BP. */ - rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos; - - if ((type == '3' && rw_bits == 0x1) || - (type == '2' && rw_bits == 0x2) || - (type == '4' && rw_bits == 0x3)) { - /* Read/write matched. */ - break; - } - } - } - - if (bp > 5) { - /* No watchpoint matched. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - return; - } - - /* Found a matching watchpoint. Now, deconfigure it by - both disabling read/write in bp_ctrl and zeroing its - start/end addresses. */ - sreg.s0_3 &= ~(3 << (2 + (bp * 4))); - bp_d_regs[bp * 2] = 0; - bp_d_regs[bp * 2 + 1] = 0; - } - - /* Note that we don't clear the S1 flag here. It's done when continuing. */ - gdb_cris_strcpy(output_buffer, "OK"); -} - - - -/* All expected commands are sent from remote.c. Send a response according - to the description in remote.c. */ -void -handle_exception(int sigval) -{ - /* Avoid warning of not used. */ - - USEDFUN(handle_exception); - USEDVAR(internal_stack[0]); - - register_fixup(sigval); - - /* Send response. */ - stub_is_stopped(sigval); - - for (;;) { - output_buffer[0] = '\0'; - getpacket(input_buffer); - switch (input_buffer[0]) { - case 'g': - /* Read registers: g - Success: Each byte of register data is described by two hex digits. - Registers are in the internal order for GDB, and the bytes - in a register are in the same order the machine uses. - Failure: void. */ - { - char *buf; - /* General and special registers. */ - buf = mem2hex(output_buffer, (char *)®, sizeof(registers)); - /* Support registers. */ - /* -1 because of the null termination that mem2hex adds. */ - mem2hex(buf, - (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)), - 16 * sizeof(unsigned int)); - break; - } - case 'G': - /* Write registers. GXX..XX - Each byte of register data is described by two hex digits. - Success: OK - Failure: E08. */ - /* General and special registers. */ - if (hex2bin((char *)®, &input_buffer[1], sizeof(registers))) - gdb_cris_strcpy(output_buffer, error_message[E08]); - /* Support registers. */ - else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)), - &input_buffer[1] + sizeof(registers), - 16 * sizeof(unsigned int))) - gdb_cris_strcpy(output_buffer, error_message[E08]); - else - gdb_cris_strcpy(output_buffer, "OK"); - break; - - case 'P': - /* Write register. Pn...=r... - Write register n..., hex value without 0x, with value r..., - which contains a hex value without 0x and two hex digits - for each byte in the register (target byte order). P1f=11223344 means - set register 31 to 44332211. - Success: OK - Failure: E02, E05 */ - { - char *suffix; - int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16); - int status; - - status = write_register(regno, suffix+1); - - switch (status) { - case E02: - /* Do not support read-only registers. */ - gdb_cris_strcpy(output_buffer, error_message[E02]); - break; - case E05: - /* Do not support non-existing registers. */ - gdb_cris_strcpy(output_buffer, error_message[E05]); - break; - case E08: - /* Invalid parameter. */ - gdb_cris_strcpy(output_buffer, error_message[E08]); - break; - default: - /* Valid register number. */ - gdb_cris_strcpy(output_buffer, "OK"); - break; - } - } - break; - - case 'm': - /* Read from memory. mAA..AA,LLLL - AA..AA is the address and LLLL is the length. - Success: XX..XX is the memory content. Can be fewer bytes than - requested if only part of the data may be read. m6000120a,6c means - retrieve 108 byte from base address 6000120a. - Failure: void. */ - { - char *suffix; - unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1], - &suffix, 16); - int len = gdb_cris_strtol(suffix+1, 0, 16); - - /* Bogus read (i.e. outside the kernel's - segment)? . */ - if (!((unsigned int)addr >= 0xc0000000 && - (unsigned int)addr < 0xd0000000)) - addr = NULL; - - mem2hex(output_buffer, addr, len); - } - break; - - case 'X': - /* Write to memory. XAA..AA,LLLL:XX..XX - AA..AA is the start address, LLLL is the number of bytes, and - XX..XX is the binary data. - Success: OK - Failure: void. */ - case 'M': - /* Write to memory. MAA..AA,LLLL:XX..XX - AA..AA is the start address, LLLL is the number of bytes, and - XX..XX is the hexadecimal data. - Success: OK - Failure: E08. */ - { - char *lenptr; - char *dataptr; - unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1], - &lenptr, 16); - int len = gdb_cris_strtol(lenptr+1, &dataptr, 16); - if (*lenptr == ',' && *dataptr == ':') { - if (input_buffer[0] == 'M') { - if (hex2bin(addr, dataptr + 1, len)) - gdb_cris_strcpy(output_buffer, error_message[E08]); - else - gdb_cris_strcpy(output_buffer, "OK"); - } else /* X */ { - bin2mem(addr, dataptr + 1, len); - gdb_cris_strcpy(output_buffer, "OK"); - } - } else { - gdb_cris_strcpy(output_buffer, error_message[E06]); - } - } - break; - - case 'c': - /* Continue execution. cAA..AA - AA..AA is the address where execution is resumed. If AA..AA is - omitted, resume at the present address. - Success: return to the executing thread. - Failure: will never know. */ - - if (input_buffer[1] != '\0') { - /* FIXME: Doesn't handle address argument. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - break; - } - - /* Before continuing, make sure everything is set up correctly. */ - - /* Set the SPC to some unlikely value. */ - reg.spc = 0; - /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting - S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL - are reserved, so don't check against those). */ - if ((sreg.s0_3 & 0x3fff) == 0) { - reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT)); - } - - return; - - case 's': - /* Step. sAA..AA - AA..AA is the address where execution is resumed. If AA..AA is - omitted, resume at the present address. Success: return to the - executing thread. Failure: will never know. */ - - if (input_buffer[1] != '\0') { - /* FIXME: Doesn't handle address argument. */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - break; - } - - /* Set the SPC to PC, which is where we'll return - (deduced previously). */ - reg.spc = reg.pc; - - /* Set the S1 (first stacked, not current) flag, which will - kick into action when we rfe. */ - reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - return; - - case 'Z': - - /* Insert breakpoint or watchpoint, Ztype,addr,length. - Remote protocol says: A remote target shall return an empty string - for an unrecognized breakpoint or watchpoint packet type. */ - { - char *lenptr; - char *dataptr; - int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16); - int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16); - char type = input_buffer[1]; - - insert_watchpoint(type, addr, len); - break; - } - - case 'z': - /* Remove breakpoint or watchpoint, Ztype,addr,length. - Remote protocol says: A remote target shall return an empty string - for an unrecognized breakpoint or watchpoint packet type. */ - { - char *lenptr; - char *dataptr; - int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16); - int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16); - char type = input_buffer[1]; - - remove_watchpoint(type, addr, len); - break; - } - - - case '?': - /* The last signal which caused a stop. ? - Success: SAA, where AA is the signal number. - Failure: void. */ - output_buffer[0] = 'S'; - output_buffer[1] = hex_asc_hi(sigval); - output_buffer[2] = hex_asc_lo(sigval); - output_buffer[3] = 0; - break; - - case 'D': - /* Detach from host. D - Success: OK, and return to the executing thread. - Failure: will never know */ - putpacket("OK"); - return; - - case 'k': - case 'r': - /* kill request or reset request. - Success: restart of target. - Failure: will never know. */ - kill_restart(); - break; - - case 'C': - case 'S': - case '!': - case 'R': - case 'd': - /* Continue with signal sig. Csig;AA..AA - Step with signal sig. Ssig;AA..AA - Use the extended remote protocol. ! - Restart the target system. R0 - Toggle debug flag. d - Search backwards. tAA:PP,MM - Not supported: E04 */ - - /* FIXME: What's the difference between not supported - and ignored (below)? */ - gdb_cris_strcpy(output_buffer, error_message[E04]); - break; - - default: - /* The stub should ignore other request and send an empty - response ($#). This way we can extend the protocol and GDB - can tell whether the stub it is talking to uses the old or the new. */ - output_buffer[0] = 0; - break; - } - putpacket(output_buffer); - } -} - -void -kgdb_init(void) -{ - reg_intr_vect_rw_mask intr_mask; - reg_ser_rw_intr_mask ser_intr_mask; - - /* Configure the kgdb serial port. */ -#if defined(CONFIG_ETRAX_KGDB_PORT0) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser0 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask); - ser_intr_mask.dav = regk_ser_yes; - REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask); -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser1 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask); - ser_intr_mask.dav = regk_ser_yes; - REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask); -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser2 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask); - ser_intr_mask.dav = regk_ser_yes; - REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask); -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - /* Note: no shortcut registered (not handled by multiple_interrupt). - See entry.S. */ - set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception); - /* Enable the ser irq in the global config. */ - intr_mask = REG_RD(intr_vect, regi_irq, rw_mask); - intr_mask.ser3 = 1; - REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); - - ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask); - ser_intr_mask.dav = regk_ser_yes; - REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask); -#endif - -} -/* Performs a complete re-start from scratch. */ -static void -kill_restart(void) -{ - machine_restart(""); -} - -/* Use this static breakpoint in the start-up only. */ - -void -breakpoint(void) -{ - kgdb_started = 1; - dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */ - __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */ -} - -/****************************** End of file **********************************/ diff --git a/arch/cris/arch-v32/kernel/kgdb_asm.S b/arch/cris/arch-v32/kernel/kgdb_asm.S deleted file mode 100644 index c26ea6b0e334..000000000000 --- a/arch/cris/arch-v32/kernel/kgdb_asm.S +++ /dev/null @@ -1,552 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2004 Axis Communications AB - * - * Code for handling break 8, hardware breakpoint, single step, and serial - * port exceptions for kernel debugging purposes. - */ - -#include - - ;; Exported functions. - .globl kgdb_handle_exception - -kgdb_handle_exception: - -;; Create a register image of the caller. -;; -;; First of all, save the ACR on the stack since we need it for address calculations. -;; We put it into the register struct later. - - subq 4, $sp - move.d $acr, [$sp] - -;; Now we are free to use ACR all we want. -;; If we were running this handler with interrupts on, we would have to be careful -;; to save and restore CCS manually, but since we aren't we treat it like every other -;; register. - - move.d reg, $acr - move.d $r0, [$acr] ; Save R0 (start of register struct) - addq 4, $acr - move.d $r1, [$acr] ; Save R1 - addq 4, $acr - move.d $r2, [$acr] ; Save R2 - addq 4, $acr - move.d $r3, [$acr] ; Save R3 - addq 4, $acr - move.d $r4, [$acr] ; Save R4 - addq 4, $acr - move.d $r5, [$acr] ; Save R5 - addq 4, $acr - move.d $r6, [$acr] ; Save R6 - addq 4, $acr - move.d $r7, [$acr] ; Save R7 - addq 4, $acr - move.d $r8, [$acr] ; Save R8 - addq 4, $acr - move.d $r9, [$acr] ; Save R9 - addq 4, $acr - move.d $r10, [$acr] ; Save R10 - addq 4, $acr - move.d $r11, [$acr] ; Save R11 - addq 4, $acr - move.d $r12, [$acr] ; Save R12 - addq 4, $acr - move.d $r13, [$acr] ; Save R13 - addq 4, $acr - move.d $sp, [$acr] ; Save SP (R14) - addq 4, $acr - - ;; The ACR register is already saved on the stack, so pop it from there. - move.d [$sp],$r0 - move.d $r0, [$acr] - addq 4, $acr - - move $bz, [$acr] - addq 1, $acr - move $vr, [$acr] - addq 1, $acr - move $pid, [$acr] - addq 4, $acr - move $srs, [$acr] - addq 1, $acr - move $wz, [$acr] - addq 2, $acr - move $exs, [$acr] - addq 4, $acr - move $eda, [$acr] - addq 4, $acr - move $mof, [$acr] - addq 4, $acr - move $dz, [$acr] - addq 4, $acr - move $ebp, [$acr] - addq 4, $acr - move $erp, [$acr] - addq 4, $acr - move $srp, [$acr] - addq 4, $acr - move $nrp, [$acr] - addq 4, $acr - move $ccs, [$acr] - addq 4, $acr - move $usp, [$acr] - addq 4, $acr - move $spc, [$acr] - addq 4, $acr - -;; Skip the pseudo-PC. - addq 4, $acr - -;; Save the support registers in bank 0 - 3. - clear.d $r1 ; Bank counter - move.d sreg, $acr - -;; Bank 0 - move $r1, $srs - nop - nop - nop - move $s0, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s1, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s2, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s3, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s4, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s5, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s6, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s7, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s8, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s9, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s10, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s11, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s12, $r0 - move.d $r0, [$acr] - addq 4, $acr - - ;; Nothing in S13 - S15, bank 0 - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - -;; Bank 1 and bank 2 have the same layout, hence the loop. - addq 1, $r1 -1: - move $r1, $srs - nop - nop - nop - move $s0, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s1, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s2, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s3, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s4, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s5, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s6, $r0 - move.d $r0, [$acr] - addq 4, $acr - - ;; Nothing in S7 - S15, bank 1 and 2 - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - clear.d [$acr] - addq 4, $acr - - addq 1, $r1 - cmpq 3, $r1 - bne 1b - nop - -;; Bank 3 - move $r1, $srs - nop - nop - nop - move $s0, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s1, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s2, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s3, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s4, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s5, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s6, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s7, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s8, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s9, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s10, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s11, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s12, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s13, $r0 - move.d $r0, [$acr] - addq 4, $acr - move $s14, $r0 - move.d $r0, [$acr] - addq 4, $acr -;; Nothing in S15, bank 3 - clear.d [$acr] - addq 4, $acr - -;; Check what got us here: get IDX field of EXS. - move $exs, $r10 - and.d 0xff00, $r10 - lsrq 8, $r10 -#if defined(CONFIG_ETRAX_KGDB_PORT0) - cmp.d SER0_INTR_VECT, $r10 ; IRQ for serial port 0 - beq sigint - nop -#elif defined(CONFIG_ETRAX_KGDB_PORT1) - cmp.d SER1_INTR_VECT, $r10 ; IRQ for serial port 1 - beq sigint - nop -#elif defined(CONFIG_ETRAX_KGDB_PORT2) - cmp.d SER2_INTR_VECT, $r10 ; IRQ for serial port 2 - beq sigint - nop -#elif defined(CONFIG_ETRAX_KGDB_PORT3) - cmp.d SER3_INTR_VECT, $r10 ; IRQ for serial port 3 - beq sigint - nop -#endif -;; Multiple interrupt must be due to serial break. - cmp.d 0x30, $r10 ; Multiple interrupt - beq sigint - nop -;; Neither of those? Then it's a sigtrap. - ba handle_comm - moveq 5, $r10 ; Set SIGTRAP (delay slot) - -sigint: - ;; Serial interrupt; get character - jsr getDebugChar - nop ; Delay slot - cmp.b 3, $r10 ; \003 (Ctrl-C)? - bne return ; No, get out of here - nop - moveq 2, $r10 ; Set SIGINT - -;; -;; Handle the communication -;; -handle_comm: - move.d internal_stack+1020, $sp ; Use the internal stack which grows upwards - jsr handle_exception ; Interactive routine - nop - -;; -;; Return to the caller -;; -return: - -;; First of all, write the support registers. - clear.d $r1 ; Bank counter - move.d sreg, $acr - -;; Bank 0 - move $r1, $srs - nop - nop - nop - move.d [$acr], $r0 - move $r0, $s0 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s1 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s2 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s3 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s4 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s5 - addq 4, $acr - -;; Nothing in S6 - S7, bank 0. - addq 4, $acr - addq 4, $acr - - move.d [$acr], $r0 - move $r0, $s8 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s9 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s10 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s11 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s12 - addq 4, $acr - -;; Nothing in S13 - S15, bank 0 - addq 4, $acr - addq 4, $acr - addq 4, $acr - -;; Bank 1 and bank 2 have the same layout, hence the loop. - addq 1, $r1 -2: - move $r1, $srs - nop - nop - nop - move.d [$acr], $r0 - move $r0, $s0 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s1 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s2 - addq 4, $acr - -;; S3 (MM_CAUSE) is read-only. - addq 4, $acr - - move.d [$acr], $r0 - move $r0, $s4 - addq 4, $acr - -;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.) - addq 4, $acr - addq 4, $acr - -;; Nothing in S7 - S15, bank 1 and 2 - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - addq 4, $acr - - addq 1, $r1 - cmpq 3, $r1 - bne 2b - nop - -;; Bank 3 - move $r1, $srs - nop - nop - nop - move.d [$acr], $r0 - move $r0, $s0 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s1 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s2 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s3 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s4 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s5 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s6 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s7 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s8 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s9 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s10 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s11 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s12 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s13 - addq 4, $acr - move.d [$acr], $r0 - move $r0, $s14 - addq 4, $acr - -;; Nothing in S15, bank 3 - addq 4, $acr - -;; Now, move on to the regular register restoration process. - - move.d reg, $acr ; Reset ACR to point at the beginning of the register image - move.d [$acr], $r0 ; Restore R0 - addq 4, $acr - move.d [$acr], $r1 ; Restore R1 - addq 4, $acr - move.d [$acr], $r2 ; Restore R2 - addq 4, $acr - move.d [$acr], $r3 ; Restore R3 - addq 4, $acr - move.d [$acr], $r4 ; Restore R4 - addq 4, $acr - move.d [$acr], $r5 ; Restore R5 - addq 4, $acr - move.d [$acr], $r6 ; Restore R6 - addq 4, $acr - move.d [$acr], $r7 ; Restore R7 - addq 4, $acr - move.d [$acr], $r8 ; Restore R8 - addq 4, $acr - move.d [$acr], $r9 ; Restore R9 - addq 4, $acr - move.d [$acr], $r10 ; Restore R10 - addq 4, $acr - move.d [$acr], $r11 ; Restore R11 - addq 4, $acr - move.d [$acr], $r12 ; Restore R12 - addq 4, $acr - move.d [$acr], $r13 ; Restore R13 - -;; -;; We restore all registers, even though some of them probably haven't changed. -;; - - addq 4, $acr - move.d [$acr], $sp ; Restore SP (R14) - - ;; ACR cannot be restored just yet. - addq 8, $acr - - ;; Skip BZ, VR. - addq 2, $acr - - move [$acr], $pid ; Restore PID - addq 4, $acr - move [$acr], $srs ; Restore SRS - nop - nop - nop - addq 1, $acr - - ;; Skip WZ. - addq 2, $acr - - move [$acr], $exs ; Restore EXS. - addq 4, $acr - move [$acr], $eda ; Restore EDA. - addq 4, $acr - move [$acr], $mof ; Restore MOF. - - ;; Skip DZ. - addq 8, $acr - - move [$acr], $ebp ; Restore EBP. - addq 4, $acr - move [$acr], $erp ; Restore ERP. - addq 4, $acr - move [$acr], $srp ; Restore SRP. - addq 4, $acr - move [$acr], $nrp ; Restore NRP. - addq 4, $acr - move [$acr], $ccs ; Restore CCS like an ordinary register. - addq 4, $acr - move [$acr], $usp ; Restore USP - addq 4, $acr - move [$acr], $spc ; Restore SPC - ; No restoration of pseudo-PC of course. - - move.d reg, $acr ; Reset ACR to point at the beginning of the register image - add.d 15*4, $acr - move.d [$acr], $acr ; Finally, restore ACR. - rete ; Same as jump ERP - rfe ; Shifts CCS diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c deleted file mode 100644 index a02f276d0ed4..000000000000 --- a/arch/cris/arch-v32/kernel/process.c +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2000-2003 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * Mikael Starvik (starvik@axis.com) - * Tobias Anderberg (tobiasa@axis.com), CRISv32 port. - * - * This file handles the architecture-dependent parts of process handling.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void stop_watchdog(void); - -/* We use this if we don't have any better idle routine. */ -void default_idle(void) -{ - local_irq_enable(); - /* Halt until exception. */ - __asm__ volatile("halt"); -} - -/* - * Free current thread data structures etc.. - */ - -extern void deconfigure_bp(long pid); -void exit_thread(struct task_struct *tsk) -{ - deconfigure_bp(tsk->pid); -} - -/* - * If the watchdog is enabled, disable interrupts and enter an infinite loop. - * The watchdog will reset the CPU after 0.1s. If the watchdog isn't enabled - * then enable it and wait. - */ -extern void arch_enable_nmi(void); - -void -hard_reset_now(void) -{ - /* - * Don't declare this variable elsewhere. We don't want any other - * code to know about it than the watchdog handler in entry.S and - * this code, implementing hard reset through the watchdog. - */ -#if defined(CONFIG_ETRAX_WATCHDOG) - extern int cause_of_death; -#endif - - printk("*** HARD RESET ***\n"); - local_irq_disable(); - -#if defined(CONFIG_ETRAX_WATCHDOG) - cause_of_death = 0xbedead; -#else -{ - reg_timer_rw_wd_ctrl wd_ctrl = {0}; - - stop_watchdog(); - - wd_ctrl.key = 16; /* Arbitrary key. */ - wd_ctrl.cnt = 1; /* Minimum time. */ - wd_ctrl.cmd = regk_timer_start; - - arch_enable_nmi(); - REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); -} -#endif - - while (1) - ; /* Wait for reset. */ -} - -/* - * Setup the child's kernel stack with a pt_regs and call switch_stack() on it. - * It will be unnested during _resume and _ret_from_sys_call when the new thread - * is scheduled. - * - * Also setup the thread switching structure which is used to keep - * thread-specific data during _resumes. - */ - -extern asmlinkage void ret_from_fork(void); -extern asmlinkage void ret_from_kernel_thread(void); - -int -copy_thread(unsigned long clone_flags, unsigned long usp, - unsigned long arg, struct task_struct *p) -{ - struct pt_regs *childregs = task_pt_regs(p); - struct switch_stack *swstack = ((struct switch_stack *) childregs) - 1; - - /* - * Put the pt_regs structure at the end of the new kernel stack page and - * fix it up. Note: the task_struct doubles as the kernel stack for the - * task. - */ - if (unlikely(p->flags & PF_KTHREAD)) { - memset(swstack, 0, - sizeof(struct switch_stack) + sizeof(struct pt_regs)); - swstack->r1 = usp; - swstack->r2 = arg; - childregs->ccs = 1 << (I_CCS_BITNR + CCS_SHIFT); - swstack->return_ip = (unsigned long) ret_from_kernel_thread; - p->thread.ksp = (unsigned long) swstack; - p->thread.usp = 0; - return 0; - } - *childregs = *current_pt_regs(); /* Struct copy of pt_regs. */ - childregs->r10 = 0; /* Child returns 0 after a fork/clone. */ - - /* Set a new TLS ? - * The TLS is in $mof because it is the 5th argument to sys_clone. - */ - if (p->mm && (clone_flags & CLONE_SETTLS)) { - task_thread_info(p)->tls = childregs->mof; - } - - /* Put the switch stack right below the pt_regs. */ - - /* Parameter to ret_from_sys_call. 0 is don't restart the syscall. */ - swstack->r9 = 0; - - /* - * We want to return into ret_from_sys_call after the _resume. - * ret_from_fork will call ret_from_sys_call. - */ - swstack->return_ip = (unsigned long) ret_from_fork; - - /* Fix the user-mode and kernel-mode stackpointer. */ - p->thread.usp = usp ?: rdusp(); - p->thread.ksp = (unsigned long) swstack; - - return 0; -} - -unsigned long -get_wchan(struct task_struct *p) -{ - /* TODO */ - return 0; -} -#undef last_sched -#undef first_sched - -void show_regs(struct pt_regs * regs) -{ - unsigned long usp = rdusp(); - - show_regs_print_info(KERN_DEFAULT); - - printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n", - regs->erp, regs->srp, regs->ccs, usp, regs->mof); - - printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", - regs->r0, regs->r1, regs->r2, regs->r3); - - printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", - regs->r4, regs->r5, regs->r6, regs->r7); - - printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", - regs->r8, regs->r9, regs->r10, regs->r11); - - printk("r12: %08lx r13: %08lx oR10: %08lx\n", - regs->r12, regs->r13, regs->orig_r10); -} diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c deleted file mode 100644 index ccac1aaadc8a..000000000000 --- a/arch/cris/arch-v32/kernel/ptrace.c +++ /dev/null @@ -1,492 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2000-2007, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * Determines which bits in CCS the user has access to. - * 1 = access, 0 = no access. - */ -#define CCS_MASK 0x00087c00 /* SXNZVC */ - -#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT)) - -static int put_debugreg(long pid, unsigned int regno, long data); -static long get_debugreg(long pid, unsigned int regno); -static unsigned long get_pseudo_pc(struct task_struct *child); -void deconfigure_bp(long pid); - -extern unsigned long cris_signal_return_page; - -/* - * Get contents of register REGNO in task TASK. - */ -long get_reg(struct task_struct *task, unsigned int regno) -{ - /* USP is a special case, it's not in the pt_regs struct but - * in the tasks thread struct - */ - unsigned long ret; - - if (regno <= PT_EDA) - ret = ((unsigned long *)task_pt_regs(task))[regno]; - else if (regno == PT_USP) - ret = task->thread.usp; - else if (regno == PT_PPC) - ret = get_pseudo_pc(task); - else if (regno <= PT_MAX) - ret = get_debugreg(task->pid, regno); - else - ret = 0; - - return ret; -} - -/* - * Write contents of register REGNO in task TASK. - */ -int put_reg(struct task_struct *task, unsigned int regno, unsigned long data) -{ - if (regno <= PT_EDA) - ((unsigned long *)task_pt_regs(task))[regno] = data; - else if (regno == PT_USP) - task->thread.usp = data; - else if (regno == PT_PPC) { - /* Write pseudo-PC to ERP only if changed. */ - if (data != get_pseudo_pc(task)) - task_pt_regs(task)->erp = data; - } else if (regno <= PT_MAX) - return put_debugreg(task->pid, regno, data); - else - return -1; - return 0; -} - -void user_enable_single_step(struct task_struct *child) -{ - unsigned long tmp; - - /* - * Set up SPC if not set already (in which case we have no other - * choice but to trust it). - */ - if (!get_reg(child, PT_SPC)) { - /* In case we're stopped in a delay slot. */ - tmp = get_reg(child, PT_ERP) & ~1; - put_reg(child, PT_SPC, tmp); - } - tmp = get_reg(child, PT_CCS) | SBIT_USER; - put_reg(child, PT_CCS, tmp); -} - -void user_disable_single_step(struct task_struct *child) -{ - put_reg(child, PT_SPC, 0); - - if (!get_debugreg(child->pid, PT_BP_CTRL)) { - unsigned long tmp; - /* If no h/w bp configured, disable S bit. */ - tmp = get_reg(child, PT_CCS) & ~SBIT_USER; - put_reg(child, PT_CCS, tmp); - } -} - -/* - * Called by kernel/ptrace.c when detaching. - * - * Make sure the single step bit is not set. - */ -void -ptrace_disable(struct task_struct *child) -{ - /* Deconfigure SPC and S-bit. */ - user_disable_single_step(child); - put_reg(child, PT_SPC, 0); - - /* Deconfigure any watchpoints associated with the child. */ - deconfigure_bp(child->pid); -} - - -long arch_ptrace(struct task_struct *child, long request, - unsigned long addr, unsigned long data) -{ - int ret; - unsigned int regno = addr >> 2; - unsigned long __user *datap = (unsigned long __user *)data; - - switch (request) { - /* Read word at location address. */ - case PTRACE_PEEKTEXT: - case PTRACE_PEEKDATA: { - unsigned long tmp; - int copied; - - ret = -EIO; - - /* The signal trampoline page is outside the normal user-addressable - * space but still accessible. This is hack to make it possible to - * access the signal handler code in GDB. - */ - if ((addr & PAGE_MASK) == cris_signal_return_page) { - /* The trampoline page is globally mapped, no page table to traverse.*/ - tmp = *(unsigned long*)addr; - } else { - copied = ptrace_access_vm(child, addr, &tmp, sizeof(tmp), FOLL_FORCE); - - if (copied != sizeof(tmp)) - break; - } - - ret = put_user(tmp,datap); - break; - } - - /* Read the word at location address in the USER area. */ - case PTRACE_PEEKUSR: { - unsigned long tmp; - - ret = -EIO; - if ((addr & 3) || regno > PT_MAX) - break; - - tmp = get_reg(child, regno); - ret = put_user(tmp, datap); - break; - } - - /* Write the word at location address. */ - case PTRACE_POKETEXT: - case PTRACE_POKEDATA: - ret = generic_ptrace_pokedata(child, addr, data); - break; - - /* Write the word at location address in the USER area. */ - case PTRACE_POKEUSR: - ret = -EIO; - if ((addr & 3) || regno > PT_MAX) - break; - - if (regno == PT_CCS) { - /* don't allow the tracing process to change stuff like - * interrupt enable, kernel/user bit, dma enables etc. - */ - data &= CCS_MASK; - data |= get_reg(child, PT_CCS) & ~CCS_MASK; - } - if (put_reg(child, regno, data)) - break; - ret = 0; - break; - - /* Get all GP registers from the child. */ - case PTRACE_GETREGS: { - int i; - unsigned long tmp; - - for (i = 0; i <= PT_MAX; i++) { - tmp = get_reg(child, i); - - if (put_user(tmp, datap)) { - ret = -EFAULT; - goto out_tsk; - } - - datap++; - } - - ret = 0; - break; - } - - /* Set all GP registers in the child. */ - case PTRACE_SETREGS: { - int i; - unsigned long tmp; - - for (i = 0; i <= PT_MAX; i++) { - if (get_user(tmp, datap)) { - ret = -EFAULT; - goto out_tsk; - } - - if (i == PT_CCS) { - tmp &= CCS_MASK; - tmp |= get_reg(child, PT_CCS) & ~CCS_MASK; - } - - put_reg(child, i, tmp); - datap++; - } - - ret = 0; - break; - } - - default: - ret = ptrace_request(child, request, addr, data); - break; - } - -out_tsk: - return ret; -} - -void do_syscall_trace(void) -{ - if (!test_thread_flag(TIF_SYSCALL_TRACE)) - return; - - if (!(current->ptrace & PT_PTRACED)) - return; - - /* the 0x80 provides a way for the tracing parent to distinguish - between a syscall stop and SIGTRAP delivery */ - ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) - ? 0x80 : 0)); - - /* - * This isn't the same as continuing with a signal, but it will do for - * normal use. - */ - if (current->exit_code) { - send_sig(current->exit_code, current, 1); - current->exit_code = 0; - } -} - -/* Returns the size of an instruction that has a delay slot. */ - -static int insn_size(struct task_struct *child, unsigned long pc) -{ - unsigned long opcode; - int copied; - int opsize = 0; - - /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */ - copied = access_process_vm(child, pc, &opcode, sizeof(opcode), FOLL_FORCE); - if (copied != sizeof(opcode)) - return 0; - - switch ((opcode & 0x0f00) >> 8) { - case 0x0: - case 0x9: - case 0xb: - opsize = 2; - break; - case 0xe: - case 0xf: - opsize = 6; - break; - case 0xd: - /* Could be 4 or 6; check more bits. */ - if ((opcode & 0xff) == 0xff) - opsize = 4; - else - opsize = 6; - break; - default: - panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n", - opcode, pc); - } - - return opsize; -} - -static unsigned long get_pseudo_pc(struct task_struct *child) -{ - /* Default value for PC is ERP. */ - unsigned long pc = get_reg(child, PT_ERP); - - if (pc & 0x1) { - unsigned long spc = get_reg(child, PT_SPC); - /* Delay slot bit set. Report as stopped on proper - instruction. */ - if (spc) { - /* Rely on SPC if set. FIXME: We might want to check - that EXS indicates we stopped due to a single-step - exception. */ - pc = spc; - } else { - /* Calculate the PC from the size of the instruction - that the delay slot we're in belongs to. */ - pc += insn_size(child, pc & ~1) - 1; - } - } - return pc; -} - -static long bp_owner = 0; - -/* Reachable from exit_thread in signal.c, so not static. */ -void deconfigure_bp(long pid) -{ - int bp; - - /* Only deconfigure if the pid is the owner. */ - if (bp_owner != pid) - return; - - for (bp = 0; bp < 6; bp++) { - unsigned long tmp; - /* Deconfigure start and end address (also gets rid of ownership). */ - put_debugreg(pid, PT_BP + 3 + (bp * 2), 0); - put_debugreg(pid, PT_BP + 4 + (bp * 2), 0); - - /* Deconfigure relevant bits in control register. */ - tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4))); - put_debugreg(pid, PT_BP_CTRL, tmp); - } - /* No owner now. */ - bp_owner = 0; -} - -static int put_debugreg(long pid, unsigned int regno, long data) -{ - int ret = 0; - register int old_srs; - -#ifdef CONFIG_ETRAX_KGDB - /* Ignore write, but pretend it was ok if value is 0 - (we don't want POKEUSR/SETREGS failing unnessecarily). */ - return (data == 0) ? ret : -1; -#endif - - /* Simple owner management. */ - if (!bp_owner) - bp_owner = pid; - else if (bp_owner != pid) { - /* Ignore write, but pretend it was ok if value is 0 - (we don't want POKEUSR/SETREGS failing unnessecarily). */ - return (data == 0) ? ret : -1; - } - - /* Remember old SRS. */ - SPEC_REG_RD(SPEC_REG_SRS, old_srs); - /* Switch to BP bank. */ - SUPP_BANK_SEL(BANK_BP); - - switch (regno - PT_BP) { - case 0: - SUPP_REG_WR(0, data); break; - case 1: - case 2: - if (data) - ret = -1; - break; - case 3: - SUPP_REG_WR(3, data); break; - case 4: - SUPP_REG_WR(4, data); break; - case 5: - SUPP_REG_WR(5, data); break; - case 6: - SUPP_REG_WR(6, data); break; - case 7: - SUPP_REG_WR(7, data); break; - case 8: - SUPP_REG_WR(8, data); break; - case 9: - SUPP_REG_WR(9, data); break; - case 10: - SUPP_REG_WR(10, data); break; - case 11: - SUPP_REG_WR(11, data); break; - case 12: - SUPP_REG_WR(12, data); break; - case 13: - SUPP_REG_WR(13, data); break; - case 14: - SUPP_REG_WR(14, data); break; - default: - ret = -1; - break; - } - - /* Restore SRS. */ - SPEC_REG_WR(SPEC_REG_SRS, old_srs); - /* Just for show. */ - NOP(); - NOP(); - NOP(); - - return ret; -} - -static long get_debugreg(long pid, unsigned int regno) -{ - register int old_srs; - register long data; - - if (pid != bp_owner) { - return 0; - } - - /* Remember old SRS. */ - SPEC_REG_RD(SPEC_REG_SRS, old_srs); - /* Switch to BP bank. */ - SUPP_BANK_SEL(BANK_BP); - - switch (regno - PT_BP) { - case 0: - SUPP_REG_RD(0, data); break; - case 1: - case 2: - /* error return value? */ - data = 0; - break; - case 3: - SUPP_REG_RD(3, data); break; - case 4: - SUPP_REG_RD(4, data); break; - case 5: - SUPP_REG_RD(5, data); break; - case 6: - SUPP_REG_RD(6, data); break; - case 7: - SUPP_REG_RD(7, data); break; - case 8: - SUPP_REG_RD(8, data); break; - case 9: - SUPP_REG_RD(9, data); break; - case 10: - SUPP_REG_RD(10, data); break; - case 11: - SUPP_REG_RD(11, data); break; - case 12: - SUPP_REG_RD(12, data); break; - case 13: - SUPP_REG_RD(13, data); break; - case 14: - SUPP_REG_RD(14, data); break; - default: - /* error return value? */ - data = 0; - } - - /* Restore SRS. */ - SPEC_REG_WR(SPEC_REG_SRS, old_srs); - /* Just for show. */ - NOP(); - NOP(); - NOP(); - - return data; -} diff --git a/arch/cris/arch-v32/kernel/setup.c b/arch/cris/arch-v32/kernel/setup.c deleted file mode 100644 index a36372e35e96..000000000000 --- a/arch/cris/arch-v32/kernel/setup.c +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Display CPU info in /proc/cpuinfo. - * - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_PROC_FS - -#define HAS_FPU 0x0001 -#define HAS_MMU 0x0002 -#define HAS_ETHERNET100 0x0004 -#define HAS_TOKENRING 0x0008 -#define HAS_SCSI 0x0010 -#define HAS_ATA 0x0020 -#define HAS_USB 0x0040 -#define HAS_IRQ_BUG 0x0080 -#define HAS_MMU_BUG 0x0100 - -struct cpu_info { - char *cpu_model; - unsigned short rev; - unsigned short cache_size; - unsigned short flags; -}; - -/* Some of these model are here for historical reasons only. */ -static struct cpu_info cpinfo[] = { - {"ETRAX 1", 0, 0, 0}, - {"ETRAX 2", 1, 0, 0}, - {"ETRAX 3", 2, 0, 0}, - {"ETRAX 4", 3, 0, 0}, - {"Simulator", 7, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA}, - {"ETRAX 100", 8, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG}, - {"ETRAX 100", 9, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA}, - - {"ETRAX 100LX", 10, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB - | HAS_MMU | HAS_MMU_BUG}, - - {"ETRAX 100LX v2", 11, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB - | HAS_MMU}, -#ifdef CONFIG_ETRAXFS - {"ETRAX FS", 32, 32, HAS_ETHERNET100 | HAS_ATA | HAS_MMU}, -#else - {"ARTPEC-3", 32, 32, HAS_ETHERNET100 | HAS_MMU}, -#endif - {"Unknown", 0, 0, 0} -}; - -int show_cpuinfo(struct seq_file *m, void *v) -{ - int i; - int cpu = (int)v - 1; - unsigned long revision; - struct cpu_info *info; - - info = &cpinfo[ARRAY_SIZE(cpinfo) - 1]; - - revision = rdvr(); - - for (i = 0; i < ARRAY_SIZE(cpinfo); i++) { - if (cpinfo[i].rev == revision) { - info = &cpinfo[i]; - break; - } - } - - seq_printf(m, - "processor\t: %d\n" - "cpu\t\t: CRIS\n" - "cpu revision\t: %lu\n" - "cpu model\t: %s\n" - "cache size\t: %d KB\n" - "fpu\t\t: %s\n" - "mmu\t\t: %s\n" - "mmu DMA bug\t: %s\n" - "ethernet\t: %s Mbps\n" - "token ring\t: %s\n" - "scsi\t\t: %s\n" - "ata\t\t: %s\n" - "usb\t\t: %s\n" - "bogomips\t: %lu.%02lu\n\n", - - cpu, - revision, - info->cpu_model, - info->cache_size, - info->flags & HAS_FPU ? "yes" : "no", - info->flags & HAS_MMU ? "yes" : "no", - info->flags & HAS_MMU_BUG ? "yes" : "no", - info->flags & HAS_ETHERNET100 ? "10/100" : "10", - info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no", - info->flags & HAS_SCSI ? "yes" : "no", - info->flags & HAS_ATA ? "yes" : "no", - info->flags & HAS_USB ? "yes" : "no", - (loops_per_jiffy * HZ + 500) / 500000, - ((loops_per_jiffy * HZ + 500) / 5000) % 100); - - return 0; -} - -#endif /* CONFIG_PROC_FS */ - -void show_etrax_copyright(void) -{ -#ifdef CONFIG_ETRAXFS - printk(KERN_INFO "Linux/CRISv32 port on ETRAX FS " - "(C) 2003, 2004 Axis Communications AB\n"); -#else - printk(KERN_INFO "Linux/CRISv32 port on ARTPEC-3 " - "(C) 2003-2009 Axis Communications AB\n"); -#endif -} - -static struct i2c_board_info __initdata i2c_info[] = { - {I2C_BOARD_INFO("camblock", 0x43)}, - {I2C_BOARD_INFO("tmp100", 0x48)}, - {I2C_BOARD_INFO("tmp100", 0x4A)}, - {I2C_BOARD_INFO("tmp100", 0x4C)}, - {I2C_BOARD_INFO("tmp100", 0x4D)}, - {I2C_BOARD_INFO("tmp100", 0x4E)}, -#ifdef CONFIG_RTC_DRV_PCF8563 - {I2C_BOARD_INFO("pcf8563", 0x51)}, -#endif - {I2C_BOARD_INFO("pca9536", 0x41)}, - {I2C_BOARD_INFO("fnp300", 0x40)}, - {I2C_BOARD_INFO("fnp300", 0x42)}, - {I2C_BOARD_INFO("adc101", 0x54)}, -}; - -static struct i2c_board_info __initdata i2c_info2[] = { - {I2C_BOARD_INFO("camblock", 0x43)}, - {I2C_BOARD_INFO("tmp100", 0x48)}, - {I2C_BOARD_INFO("tmp100", 0x4A)}, - {I2C_BOARD_INFO("tmp100", 0x4C)}, - {I2C_BOARD_INFO("tmp100", 0x4D)}, - {I2C_BOARD_INFO("tmp100", 0x4E)}, - {I2C_BOARD_INFO("pca9536", 0x41)}, - {I2C_BOARD_INFO("fnp300", 0x40)}, - {I2C_BOARD_INFO("fnp300", 0x42)}, - {I2C_BOARD_INFO("adc101", 0x54)}, -}; - -static struct i2c_board_info __initdata i2c_info3[] = { - {I2C_BOARD_INFO("adc101", 0x54)}, -}; - -static int __init etrax_init(void) -{ - i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info)); - i2c_register_board_info(1, i2c_info2, ARRAY_SIZE(i2c_info2)); - i2c_register_board_info(2, i2c_info3, ARRAY_SIZE(i2c_info3)); - return 0; -} -arch_initcall(etrax_init); diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c deleted file mode 100644 index 4f2e3ba3bf40..000000000000 --- a/arch/cris/arch-v32/kernel/signal.c +++ /dev/null @@ -1,541 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2003, Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -extern unsigned long cris_signal_return_page; - -/* - * A syscall in CRIS is really a "break 13" instruction, which is 2 - * bytes. The registers is manipulated so upon return the instruction - * will be executed again. - * - * This relies on that PC points to the instruction after the break call. - */ -#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->erp -= 2; - -/* Signal frames. */ -struct signal_frame { - struct sigcontext sc; - unsigned long extramask[_NSIG_WORDS - 1]; - unsigned char retcode[8]; /* Trampoline code. */ -}; - -struct rt_signal_frame { - struct siginfo *pinfo; - void *puc; - struct siginfo info; - struct ucontext uc; - unsigned char retcode[8]; /* Trampoline code. */ -}; - -void do_signal(int restart, struct pt_regs *regs); -void keep_debug_flags(unsigned long oldccs, unsigned long oldspc, - struct pt_regs *regs); - -static int -restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) -{ - unsigned int err = 0; - unsigned long old_usp; - - /* Always make any pending restarted system calls return -EINTR */ - current->restart_block.fn = do_no_restart_syscall; - - /* - * Restore the registers from &sc->regs. sc is already checked - * for VERIFY_READ since the signal_frame was previously - * checked in sys_sigreturn(). - */ - if (__copy_from_user(regs, sc, sizeof(struct pt_regs))) - goto badframe; - - /* Make that the user-mode flag is set. */ - regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT)); - - /* Don't perform syscall restarting */ - regs->exs = -1; - - /* Restore the old USP. */ - err |= __get_user(old_usp, &sc->usp); - wrusp(old_usp); - - return err; - -badframe: - return 1; -} - -asmlinkage int sys_sigreturn(void) -{ - struct pt_regs *regs = current_pt_regs(); - sigset_t set; - struct signal_frame __user *frame; - unsigned long oldspc = regs->spc; - unsigned long oldccs = regs->ccs; - - frame = (struct signal_frame *) rdusp(); - - /* - * Since the signal is stacked on a dword boundary, the frame - * should be dword aligned here as well. It it's not, then the - * user is trying some funny business. - */ - if (((long)frame) & 3) - goto badframe; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - - if (__get_user(set.sig[0], &frame->sc.oldmask) || - (_NSIG_WORDS > 1 && __copy_from_user(&set.sig[1], - frame->extramask, - sizeof(frame->extramask)))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(regs, &frame->sc)) - goto badframe; - - keep_debug_flags(oldccs, oldspc, regs); - - return regs->r10; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -asmlinkage int sys_rt_sigreturn(void) -{ - struct pt_regs *regs = current_pt_regs(); - sigset_t set; - struct rt_signal_frame __user *frame; - unsigned long oldspc = regs->spc; - unsigned long oldccs = regs->ccs; - - frame = (struct rt_signal_frame *) rdusp(); - - /* - * Since the signal is stacked on a dword boundary, the frame - * should be dword aligned here as well. It it's not, then the - * user is trying some funny business. - */ - if (((long)frame) & 3) - goto badframe; - - if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) - goto badframe; - - if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) - goto badframe; - - set_current_blocked(&set); - - if (restore_sigcontext(regs, &frame->uc.uc_mcontext)) - goto badframe; - - if (restore_altstack(&frame->uc.uc_stack)) - goto badframe; - - keep_debug_flags(oldccs, oldspc, regs); - - return regs->r10; - -badframe: - force_sig(SIGSEGV, current); - return 0; -} - -/* Setup a signal frame. */ -static int -setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, - unsigned long mask) -{ - int err; - unsigned long usp; - - err = 0; - usp = rdusp(); - - /* - * Copy the registers. They are located first in sc, so it's - * possible to use sc directly. - */ - err |= __copy_to_user(sc, regs, sizeof(struct pt_regs)); - - err |= __put_user(mask, &sc->oldmask); - err |= __put_user(usp, &sc->usp); - - return err; -} - -/* Figure out where to put the new signal frame - usually on the stack. */ -static inline void __user * -get_sigframe(struct ksignal *ksig, size_t frame_size) -{ - unsigned long sp = sigsp(rdusp(), ksig); - - /* Make sure the frame is dword-aligned. */ - sp &= ~3; - - return (void __user *)(sp - frame_size); -} - -/* Grab and setup a signal frame. - * - * Basically a lot of state-info is stacked, and arranged for the - * user-mode program to return to the kernel using either a trampiline - * which performs the syscall sigreturn(), or a provided user-mode - * trampoline. - */ -static int -setup_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) -{ - int err; - unsigned long return_ip; - struct signal_frame __user *frame; - - err = 0; - frame = get_sigframe(ksig, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - err |= setup_sigcontext(&frame->sc, regs, set->sig[0]); - - if (err) - return -EFAULT; - - if (_NSIG_WORDS > 1) { - err |= __copy_to_user(frame->extramask, &set->sig[1], - sizeof(frame->extramask)); - } - - if (err) - return -EFAULT; - - /* - * Set up to return from user-space. If provided, use a stub - * already located in user-space. - */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { - return_ip = (unsigned long)ksig->ka.sa.sa_restorer; - } else { - /* Trampoline - the desired return ip is in the signal return page. */ - return_ip = cris_signal_return_page; - - /* - * This is movu.w __NR_sigreturn, r9; break 13; - * - * WE DO NOT USE IT ANY MORE! It's only left here for historical - * reasons and because gdb uses it as a signature to notice - * signal handler stack frames. - */ - err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); - err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2)); - err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); - } - - if (err) - return -EFAULT; - - /* - * Set up registers for signal handler. - * - * Where the code enters now. - * Where the code enter later. - * First argument, signo. - */ - regs->erp = (unsigned long) ksig->ka.sa.sa_handler; - regs->srp = return_ip; - regs->r10 = ksig->sig; - - /* Actually move the USP to reflect the stacked frame. */ - wrusp((unsigned long)frame); - - return 0; -} - -static int -setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) -{ - int err; - unsigned long return_ip; - struct rt_signal_frame __user *frame; - - err = 0; - frame = get_sigframe(ksig, sizeof(*frame)); - - if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame))) - return -EFAULT; - - err |= __put_user(&frame->info, &frame->pinfo); - err |= __put_user(&frame->uc, &frame->puc); - err |= copy_siginfo_to_user(&frame->info, &ksig->info); - - if (err) - return -EFAULT; - - /* Clear all the bits of the ucontext we don't use. */ - err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext)); - err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]); - err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)); - err |= __save_altstack(&frame->uc.uc_stack, rdusp()); - - if (err) - return -EFAULT; - - /* - * Set up to return from user-space. If provided, use a stub - * already located in user-space. - */ - if (ksig->ka.sa.sa_flags & SA_RESTORER) { - return_ip = (unsigned long) ksig->ka.sa.sa_restorer; - } else { - /* Trampoline - the desired return ip is in the signal return page. */ - return_ip = cris_signal_return_page + 6; - - /* - * This is movu.w __NR_rt_sigreturn, r9; break 13; - * - * WE DO NOT USE IT ANY MORE! It's only left here for historical - * reasons and because gdb uses it as a signature to notice - * signal handler stack frames. - */ - err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0)); - - err |= __put_user(__NR_rt_sigreturn, - (short __user*)(frame->retcode+2)); - - err |= __put_user(0xe93d, (short __user*)(frame->retcode+4)); - } - - if (err) - return -EFAULT; - - /* - * Set up registers for signal handler. - * - * Where the code enters now. - * Where the code enters later. - * First argument is signo. - * Second argument is (siginfo_t *). - * Third argument is unused. - */ - regs->erp = (unsigned long) ksig->ka.sa.sa_handler; - regs->srp = return_ip; - regs->r10 = ksig->sig; - regs->r11 = (unsigned long) &frame->info; - regs->r12 = 0; - - /* Actually move the usp to reflect the stacked frame. */ - wrusp((unsigned long)frame); - - return 0; -} - -/* Invoke a signal handler to, well, handle the signal. */ -static inline void -handle_signal(int canrestart, struct ksignal *ksig, struct pt_regs *regs) -{ - sigset_t *oldset = sigmask_to_save(); - int ret; - - /* Check if this got called from a system call. */ - if (canrestart) { - /* If so, check system call restarting. */ - switch (regs->r10) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - /* - * This means that the syscall should - * only be restarted if there was no - * handler for the signal, and since - * this point isn't reached unless - * there is a handler, there's no need - * to restart. - */ - regs->r10 = -EINTR; - break; - - case -ERESTARTSYS: - /* - * This means restart the syscall if - * there is no handler, or the handler - * was registered with SA_RESTART. - */ - if (!(ksig->ka.sa.sa_flags & SA_RESTART)) { - regs->r10 = -EINTR; - break; - } - - /* Fall through. */ - - case -ERESTARTNOINTR: - /* - * This means that the syscall should - * be called again after the signal - * handler returns. - */ - RESTART_CRIS_SYS(regs); - break; - } - } - - /* Set up the stack frame. */ - if (ksig->ka.sa.sa_flags & SA_SIGINFO) - ret = setup_rt_frame(ksig, oldset, regs); - else - ret = setup_frame(ksig, oldset, regs); - - signal_setup_done(ret, ksig, 0); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - * - * Also note that the regs structure given here as an argument, is the latest - * pushed pt_regs. It may or may not be the same as the first pushed registers - * when the initial usermode->kernelmode transition took place. Therefore - * we can use user_mode(regs) to see if we came directly from kernel or user - * mode below. - */ -void -do_signal(int canrestart, struct pt_regs *regs) -{ - struct ksignal ksig; - - canrestart = canrestart && ((int)regs->exs >= 0); - - /* - * The common case should go fast, which is why this point is - * reached from kernel-mode. If that's the case, just return - * without doing anything. - */ - if (!user_mode(regs)) - return; - - if (get_signal(&ksig)) { - /* Whee! Actually deliver the signal. */ - handle_signal(canrestart, &ksig, regs); - return; - } - - /* Got here from a system call? */ - if (canrestart) { - /* Restart the system call - no handlers present. */ - if (regs->r10 == -ERESTARTNOHAND || - regs->r10 == -ERESTARTSYS || - regs->r10 == -ERESTARTNOINTR) { - RESTART_CRIS_SYS(regs); - } - - if (regs->r10 == -ERESTART_RESTARTBLOCK){ - regs->r9 = __NR_restart_syscall; - regs->erp -= 2; - } - } - - /* if there's no signal to deliver, we just put the saved sigmask - * back */ - restore_saved_sigmask(); -} - -asmlinkage void -ugdb_trap_user(struct thread_info *ti, int sig) -{ - if (((user_regs(ti)->exs & 0xff00) >> 8) != SINGLE_STEP_INTR_VECT) { - /* Zero single-step PC if the reason we stopped wasn't a single - step exception. This is to avoid relying on it when it isn't - reliable. */ - user_regs(ti)->spc = 0; - } - /* FIXME: Filter out false h/w breakpoint hits (i.e. EDA - not within any configured h/w breakpoint range). Synchronize with - what already exists for kernel debugging. */ - if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) { - /* Break 8: subtract 2 from ERP unless in a delay slot. */ - if (!(user_regs(ti)->erp & 0x1)) - user_regs(ti)->erp -= 2; - } - sys_kill(ti->task->pid, sig); -} - -void -keep_debug_flags(unsigned long oldccs, unsigned long oldspc, - struct pt_regs *regs) -{ - if (oldccs & (1 << Q_CCS_BITNR)) { - /* Pending single step due to single-stepping the break 13 - in the signal trampoline: keep the Q flag. */ - regs->ccs |= (1 << Q_CCS_BITNR); - /* S flag should be set - complain if it's not. */ - if (!(oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT)))) { - printk("Q flag but no S flag?"); - } - regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - /* Assume the SPC is valid and interesting. */ - regs->spc = oldspc; - - } else if (oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT))) { - /* If a h/w bp was set in the signal handler we need - to keep the S flag. */ - regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT)); - /* Don't keep the old SPC though; if we got here due to - a single-step, the Q flag should have been set. */ - } else if (regs->spc) { - /* If we were single-stepping *before* the signal was taken, - we don't want to restore that state now, because GDB will - have forgotten all about it. */ - regs->spc = 0; - regs->ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT)); - } -} - -/* Set up the trampolines on the signal return page. */ -int __init -cris_init_signal(void) -{ - u16* data = kmalloc(PAGE_SIZE, GFP_KERNEL); - - /* This is movu.w __NR_sigreturn, r9; break 13; */ - data[0] = 0x9c5f; - data[1] = __NR_sigreturn; - data[2] = 0xe93d; - /* This is movu.w __NR_rt_sigreturn, r9; break 13; */ - data[3] = 0x9c5f; - data[4] = __NR_rt_sigreturn; - data[5] = 0xe93d; - - /* Map to userspace with appropriate permissions (no write access...) */ - cris_signal_return_page = (unsigned long) - __ioremap_prot(virt_to_phys(data), PAGE_SIZE, PAGE_SIGNAL_TRAMPOLINE); - - return 0; -} - -__initcall(cris_init_signal); diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c deleted file mode 100644 index d07a3912687e..000000000000 --- a/arch/cris/arch-v32/kernel/time.c +++ /dev/null @@ -1,345 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/arch-v32/kernel/time.c - * - * Copyright (C) 2003-2010 Axis Communications AB - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -#include -#endif - -/* Watchdog defines */ -#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */ -#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */ -/* Number of 763 counts before watchdog bites */ -#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) - -#define CRISV32_TIMER_FREQ (100000000lu) - -unsigned long timer_regs[NR_CPUS] = -{ - regi_timer0, -}; - -extern int set_rtc_mmss(unsigned long nowtime); - -#ifdef CONFIG_CPU_FREQ -static int cris_time_freq_notifier(struct notifier_block *nb, - unsigned long val, void *data); - -static struct notifier_block cris_time_freq_notifier_block = { - .notifier_call = cris_time_freq_notifier, -}; -#endif - -unsigned long get_ns_in_jiffie(void) -{ - reg_timer_r_tmr0_data data; - unsigned long ns; - - data = REG_RD(timer, regi_timer0, r_tmr0_data); - ns = (TIMER0_DIV - data) * 10; - return ns; -} - -/* From timer MDS describing the hardware watchdog: - * 4.3.1 Watchdog Operation - * The watchdog timer is an 8-bit timer with a configurable start value. - * Once started the watchdog counts downwards with a frequency of 763 Hz - * (100/131072 MHz). When the watchdog counts down to 1, it generates an - * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the - * chip. - */ -/* This gives us 1.3 ms to do something useful when the NMI comes */ - -/* Right now, starting the watchdog is the same as resetting it */ -#define start_watchdog reset_watchdog - -#if defined(CONFIG_ETRAX_WATCHDOG) -static short int watchdog_key = 42; /* arbitrary 7 bit number */ -#endif - -/* Number of pages to consider "out of memory". It is normal that the memory - * is used though, so set this really low. */ -#define WATCHDOG_MIN_FREE_PAGES 8 - -#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) -/* for reliable NICE_DOGGY behaviour */ -static int bite_in_progress; -#endif - -void reset_watchdog(void) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; - -#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) - if (unlikely(bite_in_progress)) - return; -#endif - /* Only keep watchdog happy as long as we have memory left! */ - if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { - /* Reset the watchdog with the inverse of the old key */ - /* Invert key, which is 7 bits */ - watchdog_key ^= ETRAX_WD_KEY_MASK; - wd_ctrl.cnt = ETRAX_WD_CNT; - wd_ctrl.cmd = regk_timer_start; - wd_ctrl.key = watchdog_key; - REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); - } -#endif -} - -/* stop the watchdog - we still need the correct key */ - -void stop_watchdog(void) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - reg_timer_rw_wd_ctrl wd_ctrl = { 0 }; - watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */ - wd_ctrl.cnt = ETRAX_WD_CNT; - wd_ctrl.cmd = regk_timer_stop; - wd_ctrl.key = watchdog_key; - REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); -#endif -} - -extern void show_registers(struct pt_regs *regs); - -void handle_watchdog_bite(struct pt_regs *regs) -{ -#if defined(CONFIG_ETRAX_WATCHDOG) - extern int cause_of_death; - - nmi_enter(); - oops_in_progress = 1; -#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY) - bite_in_progress = 1; -#endif - printk(KERN_WARNING "Watchdog bite\n"); - - /* Check if forced restart or unexpected watchdog */ - if (cause_of_death == 0xbedead) { -#ifdef CONFIG_CRIS_MACH_ARTPEC3 - /* There is a bug in Artpec-3 (voodoo TR 78) that requires - * us to go to lower frequency for the reset to be reliable - */ - reg_clkgen_rw_clk_ctrl ctrl = - REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); - ctrl.pll = 0; - REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); -#endif - while(1); - } - - /* Unexpected watchdog, stop the watchdog and dump registers. */ - stop_watchdog(); - printk(KERN_WARNING "Oops: bitten by watchdog\n"); - show_registers(regs); - oops_in_progress = 0; - printk("\n"); /* Flush mtdoops. */ -#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - reset_watchdog(); -#endif - while(1) /* nothing */; -#endif -} - -extern void cris_profile_sample(struct pt_regs *regs); -static void __iomem *timer_base; - -static int crisv32_clkevt_switch_state(struct clock_event_device *dev) -{ - reg_timer_rw_tmr0_ctrl ctrl = { - .op = regk_timer_hold, - .freq = regk_timer_f100, - }; - - REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); - return 0; -} - -static int crisv32_clkevt_next_event(unsigned long evt, - struct clock_event_device *dev) -{ - reg_timer_rw_tmr0_ctrl ctrl = { - .op = regk_timer_ld, - .freq = regk_timer_f100, - }; - - REG_WR(timer, timer_base, rw_tmr0_div, evt); - REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); - - ctrl.op = regk_timer_run; - REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); - - return 0; -} - -static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - reg_timer_rw_tmr0_ctrl ctrl = { - .op = regk_timer_hold, - .freq = regk_timer_f100, - }; - reg_timer_rw_ack_intr ack = { .tmr0 = 1 }; - reg_timer_r_masked_intr intr; - - intr = REG_RD(timer, timer_base, r_masked_intr); - if (!intr.tmr0) - return IRQ_NONE; - - REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); - REG_WR(timer, timer_base, rw_ack_intr, ack); - - reset_watchdog(); -#ifdef CONFIG_SYSTEM_PROFILER - cris_profile_sample(get_irq_regs()); -#endif - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct clock_event_device crisv32_clockevent = { - .name = "crisv32-timer", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_state_oneshot = crisv32_clkevt_switch_state, - .set_state_shutdown = crisv32_clkevt_switch_state, - .tick_resume = crisv32_clkevt_switch_state, - .set_next_event = crisv32_clkevt_next_event, -}; - -/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */ -static struct irqaction irq_timer = { - .handler = crisv32_timer_interrupt, - .flags = IRQF_TIMER | IRQF_SHARED, - .name = "crisv32-timer", - .dev_id = &crisv32_clockevent, -}; - -static u64 notrace crisv32_timer_sched_clock(void) -{ - return REG_RD(timer, timer_base, r_time); -} - -static void __init crisv32_timer_init(void) -{ - reg_timer_rw_intr_mask timer_intr_mask; - reg_timer_rw_tmr0_ctrl ctrl = { - .op = regk_timer_hold, - .freq = regk_timer_f100, - }; - - REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); - - timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask); - timer_intr_mask.tmr0 = 1; - REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask); -} - -void __init time_init(void) -{ - int irq; - int ret; - - /* Probe for the RTC and read it if it exists. - * Before the RTC can be probed the loops_per_usec variable needs - * to be initialized to make usleep work. A better value for - * loops_per_usec is calculated by the kernel later once the - * clock has started. - */ - loops_per_usec = 50; - - irq = TIMER0_INTR_VECT; - timer_base = (void __iomem *) regi_timer0; - - crisv32_timer_init(); - - sched_clock_register(crisv32_timer_sched_clock, 32, - CRISV32_TIMER_FREQ); - - clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time, - "crisv32-timer", CRISV32_TIMER_FREQ, - 300, 32, clocksource_mmio_readl_up); - - crisv32_clockevent.cpumask = cpu_possible_mask; - crisv32_clockevent.irq = irq; - - ret = setup_irq(irq, &irq_timer); - if (ret) - pr_warn("failed to setup irq %d\n", irq); - - clockevents_config_and_register(&crisv32_clockevent, - CRISV32_TIMER_FREQ, - 2, 0xffffffff); - - /* Enable watchdog if we should use one. */ - -#if defined(CONFIG_ETRAX_WATCHDOG) - printk(KERN_INFO "Enabling watchdog...\n"); - start_watchdog(); - - /* If we use the hardware watchdog, we want to trap it as an NMI - * and dump registers before it resets us. For this to happen, we - * must set the "m" NMI enable flag (which once set, is unset only - * when an NMI is taken). */ - { - unsigned long flags; - local_save_flags(flags); - flags |= (1<<30); /* NMI M flag is at bit 30 */ - local_irq_restore(flags); - } -#endif - -#ifdef CONFIG_CPU_FREQ - cpufreq_register_notifier(&cris_time_freq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); -#endif -} - -#ifdef CONFIG_CPU_FREQ -static int cris_time_freq_notifier(struct notifier_block *nb, - unsigned long val, void *data) -{ - struct cpufreq_freqs *freqs = data; - if (val == CPUFREQ_POSTCHANGE) { - reg_timer_r_tmr0_data data; - reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ; - do { - data = REG_RD(timer, timer_regs[freqs->cpu], - r_tmr0_data); - } while (data > 20); - REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div); - } - return 0; -} -#endif diff --git a/arch/cris/arch-v32/kernel/traps.c b/arch/cris/arch-v32/kernel/traps.c deleted file mode 100644 index ba54c7eccbaa..000000000000 --- a/arch/cris/arch-v32/kernel/traps.c +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2003-2006, Axis Communications AB. - */ - -#include -#include -#include -#include - -#include -#include -#include - -void show_registers(struct pt_regs *regs) -{ - /* - * It's possible to use either the USP register or current->thread.usp. - * USP might not correspond to the current process for all cases this - * function is called, and current->thread.usp isn't up to date for the - * current process. Experience shows that using USP is the way to go. - */ - unsigned long usp = rdusp(); - unsigned long d_mmu_cause; - unsigned long i_mmu_cause; - - printk("CPU: %d\n", smp_processor_id()); - - printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n", - regs->erp, regs->srp, regs->ccs, usp, regs->mof); - - printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n", - regs->r0, regs->r1, regs->r2, regs->r3); - - printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n", - regs->r4, regs->r5, regs->r6, regs->r7); - - printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n", - regs->r8, regs->r9, regs->r10, regs->r11); - - printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n", - regs->r12, regs->r13, regs->orig_r10, regs->acr); - - printk(" sp: %08lx\n", (unsigned long)regs); - - SUPP_BANK_SEL(BANK_IM); - SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause); - - SUPP_BANK_SEL(BANK_DM); - SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause); - - printk(" Data MMU Cause: %08lx\n", d_mmu_cause); - printk("Instruction MMU Cause: %08lx\n", i_mmu_cause); - - printk("Process %s (pid: %d, stackpage=%08lx)\n", - current->comm, current->pid, (unsigned long)current); - - /* - * When in-kernel, we also print out the stack and code at the - * time of the fault.. - */ - if (!user_mode(regs)) { - int i; - - show_stack(NULL, (unsigned long *)usp); - - /* - * If the previous stack-dump wasn't a kernel one, dump the - * kernel stack now. - */ - if (usp != 0) - show_stack(NULL, NULL); - - printk("\nCode: "); - - if (regs->erp < PAGE_OFFSET) - goto bad_value; - - /* - * Quite often the value at regs->erp doesn't point to the - * interesting instruction, which often is the previous - * instruction. So dump at an offset large enough that the - * instruction decoding should be in sync at the interesting - * point, but small enough to fit on a row. The regs->erp - * location is pointed out in a ksymoops-friendly way by - * wrapping the byte for that address in parenthesises. - */ - for (i = -12; i < 12; i++) { - unsigned char c; - - if (__get_user(c, &((unsigned char *)regs->erp)[i])) { -bad_value: - printk(" Bad IP value."); - break; - } - - if (i == 0) - printk("(%02x) ", c); - else - printk("%02x ", c); - } - printk("\n"); - } -} - -void arch_enable_nmi(void) -{ - unsigned long flags; - - local_save_flags(flags); - flags |= (1 << 30); /* NMI M flag is at bit 30 */ - local_irq_restore(flags); -} - -extern void (*nmi_handler)(struct pt_regs *); -void handle_nmi(struct pt_regs *regs) -{ -#ifdef CONFIG_ETRAXFS - reg_intr_vect_r_nmi r; -#endif - - if (nmi_handler) - nmi_handler(regs); - -#ifdef CONFIG_ETRAXFS - /* Wait until nmi is no longer active. */ - do { - r = REG_RD(intr_vect, regi_irq, r_nmi); - } while (r.ext == regk_intr_vect_on); -#endif -} - - -#ifdef CONFIG_BUG -extern void die_if_kernel(const char *str, struct pt_regs *regs, long err); - -/* Copy of the regs at BUG() time. */ -struct pt_regs BUG_regs; - -void do_BUG(char *file, unsigned int line) -{ - printk("kernel BUG at %s:%d!\n", file, line); - die_if_kernel("Oops", &BUG_regs, 0); -} -EXPORT_SYMBOL(do_BUG); - -void fixup_BUG(struct pt_regs *regs) -{ - BUG_regs = *regs; - -#ifdef CONFIG_DEBUG_BUGVERBOSE - /* - * Fixup the BUG arguments through exception handlers. - */ - { - const struct exception_table_entry *fixup; - - /* - * ERP points at the "break 14" + 2, compensate for the 2 - * bytes. - */ - fixup = search_exception_tables(instruction_pointer(regs) - 2); - if (fixup) { - /* Adjust the instruction pointer in the stackframe. */ - instruction_pointer(regs) = fixup->fixup; - arch_fixup(regs); - } - } -#else - /* Dont try to lookup the filename + line, just dump regs. */ - do_BUG("unknown", 0); -#endif -} - -/* - * Break 14 handler. Save regs and jump into the fixup_BUG. - */ -__asm__ ( ".text\n\t" - ".global breakh_BUG\n\t" - "breakh_BUG:\n\t" - SAVE_ALL - KGDB_FIXUP - "move.d $sp, $r10\n\t" - "jsr fixup_BUG\n\t" - "nop\n\t" - "jump ret_from_intr\n\t" - "nop\n\t"); - - -#ifdef CONFIG_DEBUG_BUGVERBOSE -void -handle_BUG(struct pt_regs *regs) -{ -} -#endif -#endif diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile deleted file mode 100644 index e91cf02f625d..000000000000 --- a/arch/cris/arch-v32/lib/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# Makefile for Etrax-specific library files.. -# - -lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ - csumcpfruser.o delay.o strcmp.o - diff --git a/arch/cris/arch-v32/lib/checksum.S b/arch/cris/arch-v32/lib/checksum.S deleted file mode 100644 index f773d4d93609..000000000000 --- a/arch/cris/arch-v32/lib/checksum.S +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * A fast checksum routine using movem - * Copyright (c) 1998-2007 Axis Communications AB - * - * csum_partial(const unsigned char * buff, int len, unsigned int sum) - */ - - .globl csum_partial - .type csum_partial,@function -csum_partial: - - ;; r10 - src - ;; r11 - length - ;; r12 - checksum - - ;; Optimized for large packets - subq 10*4, $r11 - blt _word_loop - move.d $r11, $acr - - subq 9*4,$sp - clearf c - movem $r8,[$sp] - - ;; do a movem checksum - -_mloop: movem [$r10+],$r9 ; read 10 longwords - ;; Loop count without touching the c flag. - addoq -10*4, $acr, $acr - ;; perform dword checksumming on the 10 longwords - - addc $r0,$r12 - addc $r1,$r12 - addc $r2,$r12 - addc $r3,$r12 - addc $r4,$r12 - addc $r5,$r12 - addc $r6,$r12 - addc $r7,$r12 - addc $r8,$r12 - addc $r9,$r12 - - ;; test $acr without trashing carry. - move.d $acr, $acr - bpl _mloop - ;; r11 <= acr is not really needed in the mloop, just using the dslot - ;; to prepare for what is needed after mloop. - move.d $acr, $r11 - - ;; fold the last carry into r13 - addc 0, $r12 - movem [$sp+],$r8 ; restore regs - -_word_loop: - addq 10*4,$r11 ; compensate for last loop underflowing length - - moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9 - lsrq 16,$r9 - - move.d $r12,$r13 - lsrq 16,$r13 ; r13 = checksum >> 16 - and.d $r9,$r12 ; checksum = checksum & 0xffff - -_no_fold: - subq 2,$r11 - blt _no_words - add.d $r13,$r12 ; checksum += r13 - - ;; checksum the rest of the words -_wloop: subq 2,$r11 - bge _wloop - addu.w [$r10+],$r12 - -_no_words: - addq 2,$r11 - ;; see if we have one odd byte more - bne _do_byte - nop - ret - move.d $r12,$r10 - -_do_byte: - ;; copy and checksum the last byte - addu.b [$r10],$r12 - ret - move.d $r12,$r10 - - .size csum_partial, .-csum_partial diff --git a/arch/cris/arch-v32/lib/checksumcopy.S b/arch/cris/arch-v32/lib/checksumcopy.S deleted file mode 100644 index a76e586d4114..000000000000 --- a/arch/cris/arch-v32/lib/checksumcopy.S +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * A fast checksum+copy routine using movem - * Copyright (c) 1998-2007 Axis Communications AB - * - * Authors: Bjorn Wesen - * - * csum_partial_copy_nocheck(const char *src, char *dst, - * int len, unsigned int sum) - */ - - .globl csum_partial_copy_nocheck - .type csum_partial_copy_nocheck,@function -csum_partial_copy_nocheck: - - ;; r10 - src - ;; r11 - dst - ;; r12 - length - ;; r13 - checksum - - ;; Optimized for large packets - subq 10*4, $r12 - blt _word_loop - move.d $r12, $acr - - subq 9*4,$sp - clearf c - movem $r8,[$sp] - - ;; do a movem copy and checksum -1: ;; A failing userspace access (the read) will have this as PC. -_mloop: movem [$r10+],$r9 ; read 10 longwords - addoq -10*4, $acr, $acr ; loop counter in latency cycle - movem $r9,[$r11+] ; write 10 longwords - - ;; perform dword checksumming on the 10 longwords - addc $r0,$r13 - addc $r1,$r13 - addc $r2,$r13 - addc $r3,$r13 - addc $r4,$r13 - addc $r5,$r13 - addc $r6,$r13 - addc $r7,$r13 - addc $r8,$r13 - addc $r9,$r13 - - ;; test $acr, without trashing carry. - move.d $acr, $acr - bpl _mloop - ;; r12 <= acr is needed after mloop and in the exception handlers. - move.d $acr, $r12 - - ;; fold the last carry into r13 - addc 0, $r13 - movem [$sp+],$r8 ; restore regs - -_word_loop: - addq 10*4,$r12 ; compensate for last loop underflowing length - - ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below - ;; r9 can be used as temporary. - move.d $r13,$r9 - lsrq 16,$r9 ; r0 = checksum >> 16 - and.d 0xffff,$r13 ; checksum = checksum & 0xffff - - subq 2, $r12 - blt _no_words - add.d $r9,$r13 ; checksum += r0 - - ;; copy and checksum the rest of the words -2: ;; A failing userspace access for the read below will have this as PC. -_wloop: move.w [$r10+],$r9 - addu.w $r9,$r13 - subq 2,$r12 - bge _wloop - move.w $r9,[$r11+] - -_no_words: - addq 2,$r12 - bne _do_byte - nop - ret - move.d $r13,$r10 - -_do_byte: - ;; copy and checksum the last byte -3: ;; A failing userspace access for the read below will have this as PC. - move.b [$r10],$r9 - addu.b $r9,$r13 - move.b $r9,[$r11] - ret - move.d $r13,$r10 - - .size csum_partial_copy_nocheck, . - csum_partial_copy_nocheck diff --git a/arch/cris/arch-v32/lib/csumcpfruser.S b/arch/cris/arch-v32/lib/csumcpfruser.S deleted file mode 100644 index 093cd757fcfa..000000000000 --- a/arch/cris/arch-v32/lib/csumcpfruser.S +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into - * csum_partial_copy_from_user by adding exception records. - * - * Copyright (C) 2001, 2003 Axis Communications AB. - * - * Author: Hans-Peter Nilsson. - */ - -#include - -/* Same function body, but a different name. If we just added exception - records to _csum_partial_copy_nocheck and made it generic, we wouldn't - know a user fault from a kernel fault and we would have overhead in - each kernel caller for the error-pointer argument. - - unsigned int csum_partial_copy_from_user - (const char *src, char *dst, int len, unsigned int sum, int *errptr); - - Note that the errptr argument is only set if we encounter an error. - It is conveniently located on the stack, so the normal function body - does not have to handle it. */ - -#define csum_partial_copy_nocheck csum_partial_copy_from_user - -/* There are local labels numbered 1, 2 and 3 present to mark the - different from-user accesses. */ -#include "checksumcopy.S" - - .section .fixup,"ax" - -;; Here from the movem loop; restore stack. -4: - movem [$sp+],$r8 -;; r12 is already decremented. Add back chunk_size-2. - addq 40-2,$r12 - -;; Here from the word loop; r12 is off by 2; add it back. -5: - addq 2,$r12 - -;; Here from a failing single byte. -6: - -;; Signal in *errptr that we had a failing access. - move.d [$sp],$acr - moveq -EFAULT,$r9 - subq 4,$sp - move.d $r9,[$acr] - -;; Clear the rest of the destination area using memset. Preserve the -;; checksum for the readable bytes. - move.d $r13,[$sp] - subq 4,$sp - move.d $r11,$r10 - move $srp,[$sp] - jsr memset - clear.d $r11 - - move [$sp+],$srp - ret - move.d [$sp+],$r10 - - .previous - .section __ex_table,"a" - .dword 1b,4b - .dword 2b,5b - .dword 3b,6b - .previous diff --git a/arch/cris/arch-v32/lib/delay.c b/arch/cris/arch-v32/lib/delay.c deleted file mode 100644 index db06a94ef646..000000000000 --- a/arch/cris/arch-v32/lib/delay.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Precise Delay Loops for ETRAX FS - * - * Copyright (C) 2006 Axis Communications AB. - * - */ - -#include -#include -#include -#include -#include -#include - -/* - * On ETRAX FS, we can check the free-running read-only 100MHz timer - * getting 32-bit 10ns precision, theoretically good for 42.94967295 - * seconds. Unsigned arithmetic and careful expression handles - * wrapping. - */ - -void cris_delay10ns(u32 n10ns) -{ - u32 t0 = REG_RD(timer, regi_timer0, r_time); - while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns) - ; -} -EXPORT_SYMBOL(cris_delay10ns); diff --git a/arch/cris/arch-v32/lib/memset.c b/arch/cris/arch-v32/lib/memset.c deleted file mode 100644 index c94ea9b3ec29..000000000000 --- a/arch/cris/arch-v32/lib/memset.c +++ /dev/null @@ -1,259 +0,0 @@ -/* A memset for CRIS. - Copyright (C) 1999-2005 Axis Communications. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - 2. Neither the name of Axis Communications nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS - ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS - COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* FIXME: This file should really only be used for reference, as the - result is somewhat depending on gcc generating what we expect rather - than what we describe. An assembly file should be used instead. */ - -/* Note the multiple occurrence of the expression "12*4", including the - asm. It is hard to get it into the asm in a good way. Thus better to - expose the problem everywhere: no macro. */ - -/* Assuming one cycle per dword written or read (ok, not really true; the - world is not ideal), and one cycle per instruction, then 43+3*(n/48-1) - <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full - 48-byte block to set. */ - -#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48) - -/* No name ambiguities in this file. */ -__asm__ (".syntax no_register_prefix"); - -void *memset(void *pdst, int c, unsigned int plen) -{ - /* Now we want the parameters in special registers. Make sure the - compiler does something usable with this. */ - - register char *return_dst __asm__ ("r10") = pdst; - register int n __asm__ ("r12") = plen; - register int lc __asm__ ("r11") = c; - - /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get - penalized here compared to the generic implementation. */ - - /* This is fragile performancewise at best. Check with newer GCC - releases, if they compile cascaded "x |= x << 8" to sane code. */ - __asm__("movu.b %0,r13 \n\ - lslq 8,r13 \n\ - move.b %0,r13 \n\ - move.d r13,%0 \n\ - lslq 16,r13 \n\ - or.d r13,%0" - : "=r" (lc) /* Inputs. */ - : "0" (lc) /* Outputs. */ - : "r13"); /* Trash. */ - - { - register char *dst __asm__ ("r13") = pdst; - - if (((unsigned long) pdst & 3) != 0 - /* Oops! n = 0 must be a valid call, regardless of alignment. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - *dst = (char) lc; - n--; - dst++; - } - - if ((unsigned long) dst & 2) - { - *(short *) dst = lc; - n -= 2; - dst += 2; - } - } - - /* Decide which setting method to use. */ - if (n >= MEMSET_BY_BLOCK_THRESHOLD) - { - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-block sizes - suboptimal. */ - __asm__ volatile - ("\ - ;; GCC does promise correct register allocations, but let's \n\ - ;; make sure it keeps its promises. \n\ - .ifnc %0-%1-%4,$r13-$r12-$r11 \n\ - .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ - .endif \n\ - \n\ - ;; Save the registers we'll clobber in the movem process \n\ - ;; on the stack. Don't mention them to gcc, it will only be \n\ - ;; upset. \n\ - subq 11*4,sp \n\ - movem r10,[sp] \n\ - \n\ - move.d r11,r0 \n\ - move.d r11,r1 \n\ - move.d r11,r2 \n\ - move.d r11,r3 \n\ - move.d r11,r4 \n\ - move.d r11,r5 \n\ - move.d r11,r6 \n\ - move.d r11,r7 \n\ - move.d r11,r8 \n\ - move.d r11,r9 \n\ - move.d r11,r10 \n\ - \n\ - ;; Now we've got this: \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 12*4,r12 \n\ -0: \n\ -" -#ifdef __arch_common_v10_v32 - /* Cater to branch offset difference between v32 and v10. We - assume the branch below has an 8-bit offset. */ -" setf\n" -#endif -" subq 12*4,r12 \n\ - bge 0b \n\ - movem r11,[r13+] \n\ - \n\ - ;; Compensate for last loop underflowing n. \n\ - addq 12*4,r12 \n\ - \n\ - ;; Restore registers from stack. \n\ - movem [sp+],r10" - - /* Outputs. */ - : "=r" (dst), "=r" (n) - - /* Inputs. */ - : "0" (dst), "1" (n), "r" (lc)); - } - - /* An ad-hoc unroll, used for 4*12-1..16 bytes. */ - while (n >= 16) - { - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - n -= 16; - } - - switch (n) - { - case 0: - break; - - case 1: - *dst = (char) lc; - break; - - case 2: - *(short *) dst = (short) lc; - break; - - case 3: - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - - case 4: - *(long *) dst = lc; - break; - - case 5: - *(long *) dst = lc; dst += 4; - *dst = (char) lc; - break; - - case 6: - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; - break; - - case 7: - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - - case 8: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; - break; - - case 9: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *dst = (char) lc; - break; - - case 10: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; - break; - - case 11: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - - case 12: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; - break; - - case 13: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *dst = (char) lc; - break; - - case 14: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; - break; - - case 15: - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(long *) dst = lc; dst += 4; - *(short *) dst = (short) lc; dst += 2; - *dst = (char) lc; - break; - } - } - - return return_dst; -} diff --git a/arch/cris/arch-v32/lib/strcmp.S b/arch/cris/arch-v32/lib/strcmp.S deleted file mode 100644 index 8f7a1ee62591..000000000000 --- a/arch/cris/arch-v32/lib/strcmp.S +++ /dev/null @@ -1,21 +0,0 @@ -; strcmp.S -- CRISv32 version. -; Copyright (C) 2008 AXIS Communications AB -; Written by Edgar E. Iglesias -; -; This source code is licensed under the GNU General Public License, -; Version 2. See the file COPYING for more details. - - .global strcmp - .type strcmp,@function -strcmp: -1: - move.b [$r10+], $r12 - seq $r13 - sub.b [$r11+], $r12 - or.b $r12, $r13 - beq 1b - nop - - ret - movs.b $r12, $r10 - .size strcmp, . - strcmp diff --git a/arch/cris/arch-v32/lib/string.c b/arch/cris/arch-v32/lib/string.c deleted file mode 100644 index c7bd6ebdc93c..000000000000 --- a/arch/cris/arch-v32/lib/string.c +++ /dev/null @@ -1,236 +0,0 @@ -/* A memcpy for CRIS. - Copyright (C) 1994-2005 Axis Communications. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - 1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - 2. Neither the name of Axis Communications nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS - ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS - COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* FIXME: This file should really only be used for reference, as the - result is somewhat depending on gcc generating what we expect rather - than what we describe. An assembly file should be used instead. */ - -#include - -/* Break even between movem and move16 is really at 38.7 * 2, but - modulo 44, so up to the next multiple of 44, we use ordinary code. */ -#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2) - -/* No name ambiguities in this file. */ -__asm__ (".syntax no_register_prefix"); - -void * -memcpy(void *pdst, const void *psrc, size_t pn) -{ - /* Now we want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - If gcc was allright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register void *return_dst __asm__ ("r10") = pdst; - register unsigned char *dst __asm__ ("r13") = pdst; - register unsigned const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - - /* When src is aligned but not dst, this makes a few extra needless - cycles. I believe it would take as many to check that the - re-alignment was unnecessary. */ - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes; so we - don't have to check further for overflows. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - n--; - *dst = *src; - src++; - dst++; - } - - if ((unsigned long) dst & 2) - { - n -= 2; - *(short *) dst = *(short *) src; - src += 2; - dst += 2; - } - } - - /* Decide which copying method to use. */ - if (n >= MEMCPY_BY_BLOCK_THRESHOLD) - { - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile - ("\ - ;; GCC does promise correct register allocations, but let's \n\ - ;; make sure it keeps its promises. \n\ - .ifnc %0-%1-%2,$r13-$r11-$r12 \n\ - .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,sp \n\ - movem r10,[sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop. \n\ - subq 44,r12 \n\ -0: \n\ -" -#ifdef __arch_common_v10_v32 - /* Cater to branch offset difference between v32 and v10. We - assume the branch below has an 8-bit offset. */ -" setf\n" -#endif -" movem [r11+],r10 \n\ - subq 44,r12 \n\ - bge 0b \n\ - movem r10,[r13+] \n\ - \n\ - ;; Compensate for last loop underflowing n. \n\ - addq 44,r12 \n\ - \n\ - ;; Restore registers from stack. \n\ - movem [sp+],r10" - - /* Outputs. */ - : "=r" (dst), "=r" (src), "=r" (n) - - /* Inputs. */ - : "0" (dst), "1" (src), "2" (n)); - } - - while (n >= 16) - { - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - - n -= 16; - } - - switch (n) - { - case 0: - break; - - case 1: - *dst = *src; - break; - - case 2: - *(short *) dst = *(short *) src; - break; - - case 3: - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - - case 4: - *(long *) dst = *(long *) src; - break; - - case 5: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *dst = *src; - break; - - case 6: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; - break; - - case 7: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - - case 8: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; - break; - - case 9: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *dst = *src; - break; - - case 10: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; - break; - - case 11: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - - case 12: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; - break; - - case 13: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *dst = *src; - break; - - case 14: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; - break; - - case 15: - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(long *) dst = *(long *) src; dst += 4; src += 4; - *(short *) dst = *(short *) src; dst += 2; src += 2; - *dst = *src; - break; - } - - return return_dst; -} diff --git a/arch/cris/arch-v32/lib/usercopy.c b/arch/cris/arch-v32/lib/usercopy.c deleted file mode 100644 index 04e78b6ffa22..000000000000 --- a/arch/cris/arch-v32/lib/usercopy.c +++ /dev/null @@ -1,458 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * User address space access functions. - * The non-inlined parts of asm-cris/uaccess.h are here. - * - * Copyright (C) 2000, 2003 Axis Communications AB. - * - * Written by Hans-Peter Nilsson. - * Pieces used from memcpy, originally by Kenny Ranerup long time ago. - */ - -#include - -/* Asm:s have been tweaked (within the domain of correctness) to give - satisfactory results for "gcc version 3.2.1 Axis release R53/1.53-v32". - - Check regularly... - - Note that for CRISv32, the PC saved at a bus-fault is the address - *at* the faulting instruction, with a special case for instructions - in delay slots: then it's the address of the branch. Note also that - in contrast to v10, a postincrement in the instruction is *not* - performed at a bus-fault; the register is seen having the original - value in fault handlers. */ - - -/* Copy to userspace. This is based on the memcpy used for - kernel-to-kernel copying; see "string.c". */ - -unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was alright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - - /* When src is aligned but not dst, this makes a few extra needless - cycles. I believe it would take as many to check that the - re-alignment was unnecessary. */ - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes; so we - don't have to check further for overflows. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - __asm_copy_to_user_1 (dst, src, retn); - n--; - } - - if ((unsigned long) dst & 2) - { - __asm_copy_to_user_2 (dst, src, retn); - n -= 2; - } - } - - /* Movem is dirt cheap. The overheap is low enough to always use the - minimum possible block size as the threshold. */ - if (n >= 44) - { - /* For large copies we use 'movem'. */ - - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile ("\ - ;; Check that the register asm declaration got right. \n\ - ;; The GCC manual explicitly says TRT will happen. \n\ - .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ -0: \n\ - movem [$r11+],$r10 \n\ - subq 44,$r12 \n\ -1: bge 0b \n\ - movem $r10,[$r13+] \n\ -3: \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -2: \n\ - .section .fixup,\"ax\" \n\ -4: \n\ -; When failing on any of the 1..44 bytes in a chunk, we adjust back the \n\ -; source pointer and just drop through to the by-16 and by-4 loops to \n\ -; get the correct number of failing bytes. This necessarily means a \n\ -; few extra exceptions, but invalid user pointers shouldn't happen in \n\ -; time-critical code anyway. \n\ - jump 3b \n\ - subq 44,$r11 \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 1b,4b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); - - } - - while (n >= 16) - { - __asm_copy_to_user_16 (dst, src, retn); - n -= 16; - } - - /* Having a separate by-four loops cuts down on cache footprint. - FIXME: Test with and without; increasing switch to be 0..15. */ - while (n >= 4) - { - __asm_copy_to_user_4 (dst, src, retn); - n -= 4; - } - - switch (n) - { - case 0: - break; - case 1: - __asm_copy_to_user_1 (dst, src, retn); - break; - case 2: - __asm_copy_to_user_2 (dst, src, retn); - break; - case 3: - __asm_copy_to_user_3 (dst, src, retn); - break; - } - - return retn; -} -EXPORT_SYMBOL(__copy_user); - -/* Copy from user to kernel. The return-value is the number of bytes that were - inaccessible. */ -unsigned long __copy_user_in(void *pdst, const void __user *psrc, - unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was alright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pdst; - register const char *src __asm__ ("r11") = psrc; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - /* The best reason to align src is that we then know that a read-fault - was for aligned bytes; there's no 1..3 remaining good bytes to - pickle. */ - if (((unsigned long) src & 3) != 0) - { - if (((unsigned long) src & 1) && n != 0) - { - __asm_copy_from_user_1 (dst, src, retn); - n--; - if (retn != 0) - goto exception; - } - - if (((unsigned long) src & 2) && n >= 2) - { - __asm_copy_from_user_2 (dst, src, retn); - n -= 2; - if (retn != 0) - goto exception; - } - - } - - /* Movem is dirt cheap. The overheap is low enough to always use the - minimum possible block size as the threshold. */ - if (n >= 44) - { - /* It is not optimal to tell the compiler about clobbering any - registers; that will move the saving/restoring of those registers - to the function prologue/epilogue, and make non-movem sizes - suboptimal. */ - __asm__ volatile ("\ - .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll use in the movem process \n\ - ;; on the stack. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - ;; Now we've got this: \n\ - ;; r11 - src \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 44,$r12 \n\ -0: \n\ - movem [$r11+],$r10 \n\ - \n\ - subq 44,$r12 \n\ - bge 0b \n\ - movem $r10,[$r13+] \n\ - \n\ -4: \n\ - addq 44,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ - .section .fixup,\"ax\" \n\ - \n\ -;; Do not jump back into the loop if we fail. For some uses, we get a \n\ -;; page fault somewhere on the line. Without checking for page limits, \n\ -;; we don't know where, but we need to copy accurately and keep an \n\ -;; accurate count; not just clear the whole line. To do that, we fall \n\ -;; down in the code below, proceeding with smaller amounts. It should \n\ -;; be kept in mind that we have to cater to code like what at one time \n\ -;; was in fs/super.c: \n\ -;; i = size - copy_from_user((void *)page, data, size); \n\ -;; which would cause repeated faults while clearing the remainder of \n\ -;; the SIZE bytes at PAGE after the first fault. \n\ -;; A caveat here is that we must not fall through from a failing page \n\ -;; to a valid page. \n\ - \n\ -3: \n\ - jump 4b ;; Fall through, pretending the fault didn't happen. \n\ - nop \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 0b,3b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn)); - } - - /* Either we directly start copying here, using dword copying in a loop, - or we copy as much as possible with 'movem' and then the last block - (<44 bytes) is copied here. This will work since 'movem' will have - updated src, dst and n. (Except with failing src.) - - Since we want to keep src accurate, we can't use - __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and - retn, but not src (by design; it's value is ignored elsewhere). */ - - while (n >= 4) - { - __asm_copy_from_user_4 (dst, src, retn); - n -= 4; - - if (retn) - goto exception; - } - - /* If we get here, there were no memory read faults. */ - switch (n) - { - /* These copies are at least "naturally aligned" (so we don't have - to check each byte), due to the src alignment code before the - movem loop. The *_3 case *will* get the correct count for retn. */ - case 0: - /* This case deliberately left in (if you have doubts check the - generated assembly code). */ - break; - case 1: - __asm_copy_from_user_1 (dst, src, retn); - break; - case 2: - __asm_copy_from_user_2 (dst, src, retn); - break; - case 3: - __asm_copy_from_user_3 (dst, src, retn); - break; - } - - /* If we get here, retn correctly reflects the number of failing - bytes. */ - return retn; - -exception: - return retn + n; -} -EXPORT_SYMBOL(__copy_user_in); - -/* Zero userspace. */ -unsigned long __do_clear_user(void __user *pto, unsigned long pn) -{ - /* We want the parameters put in special registers. - Make sure the compiler is able to make something useful of this. - As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop). - - FIXME: Comment for old gcc version. Check. - If gcc was alright, it really would need no temporaries, and no - stack space to save stuff on. */ - - register char *dst __asm__ ("r13") = pto; - register int n __asm__ ("r12") = pn; - register int retn __asm__ ("r10") = 0; - - - if (((unsigned long) dst & 3) != 0 - /* Don't align if we wouldn't copy more than a few bytes. */ - && n >= 3) - { - if ((unsigned long) dst & 1) - { - __asm_clear_1 (dst, retn); - n--; - } - - if ((unsigned long) dst & 2) - { - __asm_clear_2 (dst, retn); - n -= 2; - } - } - - /* Decide which copying method to use. - FIXME: This number is from the "ordinary" kernel memset. */ - if (n >= 48) - { - /* For large clears we use 'movem' */ - - /* It is not optimal to tell the compiler about clobbering any - call-saved registers; that will move the saving/restoring of - those registers to the function prologue/epilogue, and make - non-movem sizes suboptimal. - - This method is not foolproof; it assumes that the "asm reg" - declarations at the beginning of the function really are used - here (beware: they may be moved to temporary registers). - This way, we do not have to save/move the registers around into - temporaries; we can safely use them straight away. - - If you want to check that the allocation was right; then - check the equalities in the first comment. It should say - something like "r13=r13, r11=r11, r12=r12". */ - __asm__ volatile ("\ - .ifnc %0%1%2,$r13$r12$r10 \n\ - .err \n\ - .endif \n\ - \n\ - ;; Save the registers we'll clobber in the movem process \n\ - ;; on the stack. Don't mention them to gcc, it will only be \n\ - ;; upset. \n\ - subq 11*4,$sp \n\ - movem $r10,[$sp] \n\ - \n\ - clear.d $r0 \n\ - clear.d $r1 \n\ - clear.d $r2 \n\ - clear.d $r3 \n\ - clear.d $r4 \n\ - clear.d $r5 \n\ - clear.d $r6 \n\ - clear.d $r7 \n\ - clear.d $r8 \n\ - clear.d $r9 \n\ - clear.d $r10 \n\ - clear.d $r11 \n\ - \n\ - ;; Now we've got this: \n\ - ;; r13 - dst \n\ - ;; r12 - n \n\ - \n\ - ;; Update n for the first loop \n\ - subq 12*4,$r12 \n\ -0: \n\ - subq 12*4,$r12 \n\ -1: \n\ - bge 0b \n\ - movem $r11,[$r13+] \n\ - \n\ - addq 12*4,$r12 ;; compensate for last loop underflowing n \n\ - \n\ - ;; Restore registers from stack \n\ - movem [$sp+],$r10 \n\ -2: \n\ - .section .fixup,\"ax\" \n\ -3: \n\ - movem [$sp],$r10 \n\ - addq 12*4,$r10 \n\ - addq 12*4,$r13 \n\ - movem $r10,[$sp] \n\ - jump 0b \n\ - clear.d $r10 \n\ - \n\ - .previous \n\ - .section __ex_table,\"a\" \n\ - .dword 1b,3b \n\ - .previous" - - /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn) - /* Inputs */ : "0" (dst), "1" (n), "2" (retn) - /* Clobber */ : "r11"); - } - - while (n >= 16) - { - __asm_clear_16 (dst, retn); - n -= 16; - } - - /* Having a separate by-four loops cuts down on cache footprint. - FIXME: Test with and without; increasing switch to be 0..15. */ - while (n >= 4) - { - __asm_clear_4 (dst, retn); - n -= 4; - } - - switch (n) - { - case 0: - break; - case 1: - __asm_clear_1 (dst, retn); - break; - case 2: - __asm_clear_2 (dst, retn); - break; - case 3: - __asm_clear_3 (dst, retn); - break; - } - - return retn; -} -EXPORT_SYMBOL(__do_clear_user); diff --git a/arch/cris/arch-v32/mach-a3/Kconfig b/arch/cris/arch-v32/mach-a3/Kconfig deleted file mode 100644 index 7b63755544dd..000000000000 --- a/arch/cris/arch-v32/mach-a3/Kconfig +++ /dev/null @@ -1,111 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if CRIS_MACH_ARTPEC3 - -menu "Artpec-3 options" - depends on CRIS_MACH_ARTPEC3 - -config ETRAX_DRAM_VIRTUAL_BASE - hex - default "c0000000" - -config ETRAX_L2CACHE - bool - default y - -config ETRAX_SERIAL_PORTS - int - default 5 - -config ETRAX_DDR2_MRS - hex "DDR2 MRS" - default "0" - -config ETRAX_DDR2_TIMING - hex "DDR2 SDRAM timing" - default "0" - help - SDRAM timing parameters. - -config ETRAX_DDR2_CONFIG - hex "DDR2 config" - default "0" - -config ETRAX_DDR2_LATENCY - hex "DDR2 latency" - default "0" - -config ETRAX_PIO_CE0_CFG - hex "PIO CE0 configuration" - default "0" - -config ETRAX_PIO_CE1_CFG - hex "PIO CE1 configuration" - default "0" - -config ETRAX_PIO_CE2_CFG - hex "PIO CE2 configuration" - default "0" - -config ETRAX_DEF_GIO_PA_OE - hex "GIO_PA_OE" - default "00000000" - help - Configures the direction of general port A bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PA_OUT - hex "GIO_PA_OUT" - default "00000000" - help - Configures the initial data for the general port A bits. Most - products should use 00 here. - -config ETRAX_DEF_GIO_PB_OE - hex "GIO_PB_OE" - default "000000000" - help - Configures the direction of general port B bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PB_OUT - hex "GIO_PB_OUT" - default "000000000" - help - Configures the initial data for the general port B bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PC_OE - hex "GIO_PC_OE" - default "00000" - help - Configures the direction of general port C bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PC_OUT - hex "GIO_PC_OUT" - default "00000" - help - Configures the initial data for the general port C bits. Most - products should use 00000 here. - -endmenu - -endif diff --git a/arch/cris/arch-v32/mach-a3/Makefile b/arch/cris/arch-v32/mach-a3/Makefile deleted file mode 100644 index 0cc6eebacbed..000000000000 --- a/arch/cris/arch-v32/mach-a3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := dma.o pinmux.o arbiter.o - -clean: - diff --git a/arch/cris/arch-v32/mach-a3/arbiter.c b/arch/cris/arch-v32/mach-a3/arbiter.c deleted file mode 100644 index 076182cc65a3..000000000000 --- a/arch/cris/arch-v32/mach-a3/arbiter.c +++ /dev/null @@ -1,635 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Memory arbiter functions. Allocates bandwidth through the - * arbiter and sets up arbiter breakpoints. - * - * The algorithm first assigns slots to the clients that has specified - * bandwidth (e.g. ethernet) and then the remaining slots are divided - * on all the active clients. - * - * Copyright (c) 2004-2007 Axis Communications AB. - * - * The artpec-3 has two arbiters. The memory hierarchy looks like this: - * - * - * CPU DMAs - * | | - * | | - * -------------- ------------------ - * | foo arbiter|----| Internal memory| - * -------------- ------------------ - * | - * -------------- - * | L2 cache | - * -------------- - * | - * h264 etc | - * | | - * | | - * -------------- - * | bar arbiter| - * -------------- - * | - * --------- - * | SDRAM | - * --------- - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define D(x) - -struct crisv32_watch_entry { - unsigned long instance; - watch_callback *cb; - unsigned long start; - unsigned long end; - int used; -}; - -#define NUMBER_OF_BP 4 -#define SDRAM_BANDWIDTH 400000000 -#define INTMEM_BANDWIDTH 400000000 -#define NBR_OF_SLOTS 64 -#define NBR_OF_REGIONS 2 -#define NBR_OF_CLIENTS 15 -#define ARBITERS 2 -#define UNASSIGNED 100 - -struct arbiter { - unsigned long instance; - int nbr_regions; - int nbr_clients; - int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS]; - int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS]; -}; - -static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] = -{ - { - {regi_marb_foo_bp0}, - {regi_marb_foo_bp1}, - {regi_marb_foo_bp2}, - {regi_marb_foo_bp3} - }, - { - {regi_marb_bar_bp0}, - {regi_marb_bar_bp1}, - {regi_marb_bar_bp2}, - {regi_marb_bar_bp3} - } -}; - -struct arbiter arbiters[ARBITERS] = -{ - { /* L2 cache arbiter */ - .instance = regi_marb_foo, - .nbr_regions = 2, - .nbr_clients = 15 - }, - { /* DDR2 arbiter */ - .instance = regi_marb_bar, - .nbr_regions = 1, - .nbr_clients = 9 - } -}; - -static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH}; - -DEFINE_SPINLOCK(arbiter_lock); - -static irqreturn_t -crisv32_foo_arbiter_irq(int irq, void *dev_id); -static irqreturn_t -crisv32_bar_arbiter_irq(int irq, void *dev_id); - -/* - * "I'm the arbiter, I know the score. - * From square one I'll be watching all 64." - * (memory arbiter slots, that is) - * - * Or in other words: - * Program the memory arbiter slots for "region" according to what's - * in requested_slots[] and active_clients[], while minimizing - * latency. A caller may pass a non-zero positive amount for - * "unused_slots", which must then be the unallocated, remaining - * number of slots, free to hand out to any client. - */ - -static void crisv32_arbiter_config(int arbiter, int region, int unused_slots) -{ - int slot; - int client; - int interval = 0; - - /* - * This vector corresponds to the hardware arbiter slots (see - * the hardware documentation for semantics). We initialize - * each slot with a suitable sentinel value outside the valid - * range {0 .. NBR_OF_CLIENTS - 1} and replace them with - * client indexes. Then it's fed to the hardware. - */ - s8 val[NBR_OF_SLOTS]; - - for (slot = 0; slot < NBR_OF_SLOTS; slot++) - val[slot] = -1; - - for (client = 0; client < arbiters[arbiter].nbr_clients; client++) { - int pos; - /* Allocate the requested non-zero number of slots, but - * also give clients with zero-requests one slot each - * while stocks last. We do the latter here, in client - * order. This makes sure zero-request clients are the - * first to get to any spare slots, else those slots - * could, when bandwidth is allocated close to the limit, - * all be allocated to low-index non-zero-request clients - * in the default-fill loop below. Another positive but - * secondary effect is a somewhat better spread of the - * zero-bandwidth clients in the vector, avoiding some of - * the latency that could otherwise be caused by the - * partitioning of non-zero-bandwidth clients at low - * indexes and zero-bandwidth clients at high - * indexes. (Note that this spreading can only affect the - * unallocated bandwidth.) All the above only matters for - * memory-intensive situations, of course. - */ - if (!arbiters[arbiter].requested_slots[region][client]) { - /* - * Skip inactive clients. Also skip zero-slot - * allocations in this pass when there are no known - * free slots. - */ - if (!arbiters[arbiter].active_clients[region][client] || - unused_slots <= 0) - continue; - - unused_slots--; - - /* Only allocate one slot for this client. */ - interval = NBR_OF_SLOTS; - } else - interval = NBR_OF_SLOTS / - arbiters[arbiter].requested_slots[region][client]; - - pos = 0; - while (pos < NBR_OF_SLOTS) { - if (val[pos] >= 0) - pos++; - else { - val[pos] = client; - pos += interval; - } - } - } - - client = 0; - for (slot = 0; slot < NBR_OF_SLOTS; slot++) { - /* - * Allocate remaining slots in round-robin - * client-number order for active clients. For this - * pass, we ignore requested bandwidth and previous - * allocations. - */ - if (val[slot] < 0) { - int first = client; - while (!arbiters[arbiter].active_clients[region][client]) { - client = (client + 1) % - arbiters[arbiter].nbr_clients; - if (client == first) - break; - } - val[slot] = client; - client = (client + 1) % arbiters[arbiter].nbr_clients; - } - if (arbiter == 0) { - if (region == EXT_REGION) - REG_WR_INT_VECT(marb_foo, regi_marb_foo, - rw_l2_slots, slot, val[slot]); - else if (region == INT_REGION) - REG_WR_INT_VECT(marb_foo, regi_marb_foo, - rw_intm_slots, slot, val[slot]); - } else { - REG_WR_INT_VECT(marb_bar, regi_marb_bar, - rw_ddr2_slots, slot, val[slot]); - } - } -} - -extern char _stext[], _etext[]; - -static void crisv32_arbiter_init(void) -{ - static int initialized; - - if (initialized) - return; - - initialized = 1; - - /* - * CPU caches are always set to active, but with zero - * bandwidth allocated. It should be ok to allocate zero - * bandwidth for the caches, because DMA for other channels - * will supposedly finish, once their programmed amount is - * done, and then the caches will get access according to the - * "fixed scheme" for unclaimed slots. Though, if for some - * use-case somewhere, there's a maximum CPU latency for - * e.g. some interrupt, we have to start allocating specific - * bandwidth for the CPU caches too. - */ - arbiters[0].active_clients[EXT_REGION][11] = 1; - arbiters[0].active_clients[EXT_REGION][12] = 1; - crisv32_arbiter_config(0, EXT_REGION, 0); - crisv32_arbiter_config(0, INT_REGION, 0); - crisv32_arbiter_config(1, EXT_REGION, 0); - - if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq, - 0, "arbiter", NULL)) - printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); - - if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq, - 0, "arbiter", NULL)) - printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); - -#ifndef CONFIG_ETRAX_KGDB - /* Global watch for writes to kernel text segment. */ - crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext, - MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients), - arbiter_all_write, NULL); -#endif - - /* Set up max burst sizes by default */ - REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3); - REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3); -} - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth) -{ - int i; - int total_assigned = 0; - int total_clients = 0; - int req; - int arbiter = 0; - - crisv32_arbiter_init(); - - if (client & 0xffff0000) { - arbiter = 1; - client >>= 16; - } - - for (i = 0; i < arbiters[arbiter].nbr_clients; i++) { - total_assigned += arbiters[arbiter].requested_slots[region][i]; - total_clients += arbiters[arbiter].active_clients[region][i]; - } - - /* Avoid division by 0 for 0-bandwidth requests. */ - req = bandwidth == 0 - ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth); - - /* - * We make sure that there are enough slots only for non-zero - * requests. Requesting 0 bandwidth *may* allocate slots, - * though if all bandwidth is allocated, such a client won't - * get any and will have to rely on getting memory access - * according to the fixed scheme that's the default when one - * of the slot-allocated clients doesn't claim their slot. - */ - if (total_assigned + req > NBR_OF_SLOTS) - return -ENOMEM; - - arbiters[arbiter].active_clients[region][client] = 1; - arbiters[arbiter].requested_slots[region][client] = req; - crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned); - - /* Propagate allocation from foo to bar */ - if (arbiter == 0) - crisv32_arbiter_allocate_bandwidth(8 << 16, - EXT_REGION, bandwidth); - return 0; -} - -/* - * Main entry for bandwidth deallocation. - * - * Strictly speaking, for a somewhat constant set of clients where - * each client gets a constant bandwidth and is just enabled or - * disabled (somewhat dynamically), no action is necessary here to - * avoid starvation for non-zero-allocation clients, as the allocated - * slots will just be unused. However, handing out those unused slots - * to active clients avoids needless latency if the "fixed scheme" - * would give unclaimed slots to an eager low-index client. - */ - -void crisv32_arbiter_deallocate_bandwidth(int client, int region) -{ - int i; - int total_assigned = 0; - int arbiter = 0; - - if (client & 0xffff0000) - arbiter = 1; - - arbiters[arbiter].requested_slots[region][client] = 0; - arbiters[arbiter].active_clients[region][client] = 0; - - for (i = 0; i < arbiters[arbiter].nbr_clients; i++) - total_assigned += arbiters[arbiter].requested_slots[region][i]; - - crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned); -} - -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback *cb) -{ - int i; - int arbiter; - int used[2]; - int ret = 0; - - crisv32_arbiter_init(); - - if (start > 0x80000000) { - printk(KERN_ERR "Arbiter: %lX doesn't look like a " - "physical address", start); - return -EFAULT; - } - - spin_lock(&arbiter_lock); - - if (clients & 0xffff) - used[0] = 1; - if (clients & 0xffff0000) - used[1] = 1; - - for (arbiter = 0; arbiter < ARBITERS; arbiter++) { - if (!used[arbiter]) - continue; - - for (i = 0; i < NUMBER_OF_BP; i++) { - if (!watches[arbiter][i].used) { - unsigned intr_mask; - if (arbiter) - intr_mask = REG_RD_INT(marb_bar, - regi_marb_bar, rw_intr_mask); - else - intr_mask = REG_RD_INT(marb_foo, - regi_marb_foo, rw_intr_mask); - - watches[arbiter][i].used = 1; - watches[arbiter][i].start = start; - watches[arbiter][i].end = start + size; - watches[arbiter][i].cb = cb; - - ret |= (i + 1) << (arbiter + 8); - if (arbiter) { - REG_WR_INT(marb_bar_bp, - watches[arbiter][i].instance, - rw_first_addr, - watches[arbiter][i].start); - REG_WR_INT(marb_bar_bp, - watches[arbiter][i].instance, - rw_last_addr, - watches[arbiter][i].end); - REG_WR_INT(marb_bar_bp, - watches[arbiter][i].instance, - rw_op, accesses); - REG_WR_INT(marb_bar_bp, - watches[arbiter][i].instance, - rw_clients, - clients & 0xffff); - } else { - REG_WR_INT(marb_foo_bp, - watches[arbiter][i].instance, - rw_first_addr, - watches[arbiter][i].start); - REG_WR_INT(marb_foo_bp, - watches[arbiter][i].instance, - rw_last_addr, - watches[arbiter][i].end); - REG_WR_INT(marb_foo_bp, - watches[arbiter][i].instance, - rw_op, accesses); - REG_WR_INT(marb_foo_bp, - watches[arbiter][i].instance, - rw_clients, clients >> 16); - } - - if (i == 0) - intr_mask |= 1; - else if (i == 1) - intr_mask |= 2; - else if (i == 2) - intr_mask |= 4; - else if (i == 3) - intr_mask |= 8; - - if (arbiter) - REG_WR_INT(marb_bar, regi_marb_bar, - rw_intr_mask, intr_mask); - else - REG_WR_INT(marb_foo, regi_marb_foo, - rw_intr_mask, intr_mask); - - spin_unlock(&arbiter_lock); - - break; - } - } - } - spin_unlock(&arbiter_lock); - if (ret) - return ret; - else - return -ENOMEM; -} - -int crisv32_arbiter_unwatch(int id) -{ - int arbiter; - int intr_mask; - - crisv32_arbiter_init(); - - spin_lock(&arbiter_lock); - - for (arbiter = 0; arbiter < ARBITERS; arbiter++) { - int id2; - - if (arbiter) - intr_mask = REG_RD_INT(marb_bar, regi_marb_bar, - rw_intr_mask); - else - intr_mask = REG_RD_INT(marb_foo, regi_marb_foo, - rw_intr_mask); - - id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8); - if (id2 == 0) - continue; - id2--; - if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) { - spin_unlock(&arbiter_lock); - return -EINVAL; - } - - memset(&watches[arbiter][id2], 0, - sizeof(struct crisv32_watch_entry)); - - if (id2 == 0) - intr_mask &= ~1; - else if (id2 == 1) - intr_mask &= ~2; - else if (id2 == 2) - intr_mask &= ~4; - else if (id2 == 3) - intr_mask &= ~8; - - if (arbiter) - REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask, - intr_mask); - else - REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask, - intr_mask); - } - - spin_unlock(&arbiter_lock); - return 0; -} - -extern void show_registers(struct pt_regs *regs); - - -static irqreturn_t -crisv32_foo_arbiter_irq(int irq, void *dev_id) -{ - reg_marb_foo_r_masked_intr masked_intr = - REG_RD(marb_foo, regi_marb_foo, r_masked_intr); - reg_marb_foo_bp_r_brk_clients r_clients; - reg_marb_foo_bp_r_brk_addr r_addr; - reg_marb_foo_bp_r_brk_op r_op; - reg_marb_foo_bp_r_brk_first_client r_first; - reg_marb_foo_bp_r_brk_size r_size; - reg_marb_foo_bp_rw_ack ack = {0}; - reg_marb_foo_rw_ack_intr ack_intr = { - .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1 - }; - struct crisv32_watch_entry *watch; - unsigned arbiter = (unsigned)dev_id; - - masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr); - - if (masked_intr.bp0) - watch = &watches[arbiter][0]; - else if (masked_intr.bp1) - watch = &watches[arbiter][1]; - else if (masked_intr.bp2) - watch = &watches[arbiter][2]; - else if (masked_intr.bp3) - watch = &watches[arbiter][3]; - else - return IRQ_NONE; - - /* Retrieve all useful information and print it. */ - r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients); - r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr); - r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op); - r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client); - r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size); - - printk(KERN_DEBUG "Arbiter IRQ\n"); - printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n", - REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients), - REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr), - REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op), - REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first), - REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size)); - - REG_WR(marb_foo_bp, watch->instance, rw_ack, ack); - REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr); - - printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()); - - if (watch->cb) - watch->cb(); - - return IRQ_HANDLED; -} - -static irqreturn_t -crisv32_bar_arbiter_irq(int irq, void *dev_id) -{ - reg_marb_bar_r_masked_intr masked_intr = - REG_RD(marb_bar, regi_marb_bar, r_masked_intr); - reg_marb_bar_bp_r_brk_clients r_clients; - reg_marb_bar_bp_r_brk_addr r_addr; - reg_marb_bar_bp_r_brk_op r_op; - reg_marb_bar_bp_r_brk_first_client r_first; - reg_marb_bar_bp_r_brk_size r_size; - reg_marb_bar_bp_rw_ack ack = {0}; - reg_marb_bar_rw_ack_intr ack_intr = { - .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1 - }; - struct crisv32_watch_entry *watch; - unsigned arbiter = (unsigned)dev_id; - - masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr); - - if (masked_intr.bp0) - watch = &watches[arbiter][0]; - else if (masked_intr.bp1) - watch = &watches[arbiter][1]; - else if (masked_intr.bp2) - watch = &watches[arbiter][2]; - else if (masked_intr.bp3) - watch = &watches[arbiter][3]; - else - return IRQ_NONE; - - /* Retrieve all useful information and print it. */ - r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients); - r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr); - r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op); - r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client); - r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size); - - printk(KERN_DEBUG "Arbiter IRQ\n"); - printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n", - REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients), - REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr), - REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op), - REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first), - REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size)); - - REG_WR(marb_bar_bp, watch->instance, rw_ack, ack); - REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr); - - printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp); - - if (watch->cb) - watch->cb(); - - return IRQ_HANDLED; -} - diff --git a/arch/cris/arch-v32/mach-a3/dma.c b/arch/cris/arch-v32/mach-a3/dma.c deleted file mode 100644 index 3f4e923b2527..000000000000 --- a/arch/cris/arch-v32/mach-a3/dma.c +++ /dev/null @@ -1,184 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Wrapper for DMA channel allocator that starts clocks etc */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static char used_dma_channels[MAX_DMA_CHANNELS]; -static const char *used_dma_channels_users[MAX_DMA_CHANNELS]; - -static DEFINE_SPINLOCK(dma_lock); - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned int bandwidth, enum dma_owner owner) -{ - unsigned long flags; - reg_clkgen_rw_clk_ctrl clk_ctrl; - reg_strmux_rw_cfg strmux_cfg; - - if (crisv32_arbiter_allocate_bandwidth(dmanr, - options & DMA_INT_MEM ? INT_REGION : EXT_REGION, - bandwidth)) - return -ENOMEM; - - spin_lock_irqsave(&dma_lock, flags); - - if (used_dma_channels[dmanr]) { - spin_unlock_irqrestore(&dma_lock, flags); - if (options & DMA_VERBOSE_ON_ERROR) - printk(KERN_ERR "Failed to request DMA %i for %s, " - "already allocated by %s\n", - dmanr, - device_id, - used_dma_channels_users[dmanr]); - - if (options & DMA_PANIC_ON_ERROR) - panic("request_dma error!"); - return -EBUSY; - } - clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); - strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); - - switch (dmanr) { - case 0: - case 1: - clk_ctrl.dma0_1_eth = 1; - break; - case 2: - case 3: - clk_ctrl.dma2_3_strcop = 1; - break; - case 4: - case 5: - clk_ctrl.dma4_5_iop = 1; - break; - case 6: - case 7: - clk_ctrl.sser_ser_dma6_7 = 1; - break; - case 9: - case 11: - clk_ctrl.dma9_11 = 1; - break; -#if MAX_DMA_CHANNELS-1 != 11 -#error Check dma.c -#endif - default: - spin_unlock_irqrestore(&dma_lock, flags); - if (options & DMA_VERBOSE_ON_ERROR) - printk(KERN_ERR "Failed to request DMA %i for %s, " - "only 0-%i valid)\n", - dmanr, device_id, MAX_DMA_CHANNELS-1); - - if (options & DMA_PANIC_ON_ERROR) - panic("request_dma error!"); - return -EINVAL; - } - - switch (owner) { - case dma_eth: - if (dmanr == 0) - strmux_cfg.dma0 = regk_strmux_eth; - else if (dmanr == 1) - strmux_cfg.dma1 = regk_strmux_eth; - else - panic("Invalid DMA channel for eth\n"); - break; - case dma_ser0: - if (dmanr == 0) - strmux_cfg.dma0 = regk_strmux_ser0; - else if (dmanr == 1) - strmux_cfg.dma1 = regk_strmux_ser0; - else - panic("Invalid DMA channel for ser0\n"); - break; - case dma_ser3: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ser3; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ser3; - else - panic("Invalid DMA channel for ser3\n"); - break; - case dma_strp: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_strcop; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_strcop; - else - panic("Invalid DMA channel for strp\n"); - break; - case dma_ser1: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_ser1; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_ser1; - else - panic("Invalid DMA channel for ser1\n"); - break; - case dma_iop: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_iop; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_iop; - else - panic("Invalid DMA channel for iop\n"); - break; - case dma_ser2: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_ser2; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_ser2; - else - panic("Invalid DMA channel for ser2\n"); - break; - case dma_sser: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_sser; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_sser; - else - panic("Invalid DMA channel for sser\n"); - break; - case dma_ser4: - if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_ser4; - else - panic("Invalid DMA channel for ser4\n"); - break; - case dma_jpeg: - if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_jpeg; - else - panic("Invalid DMA channel for JPEG\n"); - break; - case dma_h264: - if (dmanr == 11) - strmux_cfg.dma11 = regk_strmux_h264; - else - panic("Invalid DMA channel for H264\n"); - break; - } - - used_dma_channels[dmanr] = 1; - used_dma_channels_users[dmanr] = device_id; - REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); - REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); - spin_unlock_irqrestore(&dma_lock, flags); - return 0; -} - -void crisv32_free_dma(unsigned int dmanr) -{ - spin_lock(&dma_lock); - used_dma_channels[dmanr] = 0; - spin_unlock(&dma_lock); -} diff --git a/arch/cris/arch-v32/mach-a3/dram_init.S b/arch/cris/arch-v32/mach-a3/dram_init.S deleted file mode 100644 index 733c3564ad79..000000000000 --- a/arch/cris/arch-v32/mach-a3/dram_init.S +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * DDR SDRAM initialization - alter with care - * This file is intended to be included from other assembler files - * - * Note: This file may not modify r8 or r9 because they are used to - * carry information from the decompressor to the kernel - * - * Copyright (C) 2005-2007 Axis Communications AB - * - * Authors: Mikael Starvik - */ - -/* Just to be certain the config file is included, we include it here - * explicitly instead of depending on it being included in the file that - * uses this code. - */ - -#include -#include - - ;; WARNING! The registers r8 and r9 are used as parameters carrying - ;; information from the decompressor (if the kernel was compressed). - ;; They should not be used in the code below. - - ;; Refer to ddr2 MDS for initialization sequence - - ; 2. Wait 200us - move.d 10000, $r2 -1: bne 1b - subq 1, $r2 - - ; Start clock - move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0 - move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1 - move.d $r1, [$r0] - - ; 2. Wait 200us - move.d 10000, $r2 -1: bne 1b - subq 1, $r2 - - ; Reset phy and start calibration - move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0 - move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \ - REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1 - move.d $r1, [$r0] - move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1 - move.d $r1, [$r0] - - ; 2. Wait 200us - move.d 10000, $r2 -1: bne 1b - subq 1, $r2 - - ; Issue commands - move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0 - move.d sdram_commands_start, $r2 -command_loop: - movu.b [$r2+], $r1 - movu.w [$r2+], $r3 -do_cmd: - lslq 16, $r1 - or.d $r3, $r1 - move.d $r1, [$r0] - ; 2. Wait 200us - move.d 10000, $r4 -1: bne 1b - subq 1, $r4 - cmp.d sdram_commands_end, $r2 - blo command_loop - nop - - ; Set timing - move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0 - move.d CONFIG_ETRAX_DDR2_TIMING, $r1 - move.d $r1, [$r0] - - ; Set latency - move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0 - move.d CONFIG_ETRAX_DDR2_LATENCY, $r1 - move.d $r1, [$r0] - - ; Set configuration - move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0 - move.d CONFIG_ETRAX_DDR2_CONFIG, $r1 - move.d $r1, [$r0] - - ba after_sdram_commands - nop - -sdram_commands_start: - .byte regk_ddr2_deselect - .word 0 - .byte regk_ddr2_pre - .word regk_ddr2_pre_all - .byte regk_ddr2_emrs2 - .word 0 - .byte regk_ddr2_emrs3 - .word 0 - .byte regk_ddr2_emrs - .word regk_ddr2_dll_en - .byte regk_ddr2_mrs - .word regk_ddr2_dll_rst - .byte regk_ddr2_pre - .word regk_ddr2_pre_all - .byte regk_ddr2_ref - .word 0 - .byte regk_ddr2_ref - .word 0 - .byte regk_ddr2_mrs - .word CONFIG_ETRAX_DDR2_MRS & 0xffff - .byte regk_ddr2_emrs - .word regk_ddr2_ocd_default | regk_ddr2_dll_en - .byte regk_ddr2_emrs - .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16) -sdram_commands_end: - .align 1 -after_sdram_commands: diff --git a/arch/cris/arch-v32/mach-a3/hw_settings.S b/arch/cris/arch-v32/mach-a3/hw_settings.S deleted file mode 100644 index 7c325cc59e1f..000000000000 --- a/arch/cris/arch-v32/mach-a3/hw_settings.S +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This table is used by some tools to extract hardware parameters. - * The table should be included in the kernel and the decompressor. - * Don't forget to update the tools if you change this table. - * - * Copyright (C) 2001-2007 Axis Communications AB - * - * Authors: Mikael Starvik - */ - -#include -#include -#include - - .ascii "HW_PARAM_MAGIC" ; Magic number - .dword 0xc0004000 ; Kernel start address - - ; Debug port -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - .dword 0 -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) - .dword 1 -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) - .dword 2 -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) - .dword 3 -#else - .dword 4 ; No debug -#endif - - ; Register values - .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg) - .dword CONFIG_ETRAX_DDR2_CONFIG - .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency) - .dword CONFIG_ETRAX_DDR2_LATENCY - .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing) - .dword CONFIG_ETRAX_DDR2_TIMING - .dword CONFIG_ETRAX_DDR2_MRS - - .dword REG_ADDR(gio, regi_gio, rw_pa_dout) - .dword CONFIG_ETRAX_DEF_GIO_PA_OUT - .dword REG_ADDR(gio, regi_gio, rw_pa_oe) - .dword CONFIG_ETRAX_DEF_GIO_PA_OE - .dword REG_ADDR(gio, regi_gio, rw_pb_dout) - .dword CONFIG_ETRAX_DEF_GIO_PB_OUT - .dword REG_ADDR(gio, regi_gio, rw_pb_oe) - .dword CONFIG_ETRAX_DEF_GIO_PB_OE - .dword REG_ADDR(gio, regi_gio, rw_pc_dout) - .dword CONFIG_ETRAX_DEF_GIO_PC_OUT - .dword REG_ADDR(gio, regi_gio, rw_pc_oe) - .dword CONFIG_ETRAX_DEF_GIO_PC_OE - - .dword 0 ; No more register values diff --git a/arch/cris/arch-v32/mach-a3/pinmux.c b/arch/cris/arch-v32/mach-a3/pinmux.c deleted file mode 100644 index 4875bf7aa53f..000000000000 --- a/arch/cris/arch-v32/mach-a3/pinmux.c +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Allocator for I/O pins. All pins are allocated to GPIO at bootup. - * Unassigned pins and GPIO pins can be allocated to a fixed interface - * or the I/O processor instead. - * - * Copyright (c) 2005-2007 Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG - -#define PINS 80 -#define PORT_PINS 32 -#define PORTS 3 - -static char pins[PINS]; -static DEFINE_SPINLOCK(pinmux_lock); - -static void crisv32_pinmux_set(int port); - -int -crisv32_pinmux_init(void) -{ - static int initialized; - - if (!initialized) { - initialized = 1; - REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); - crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio); - crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio); - crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio); - } - - return 0; -} - -int -crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode) -{ - int i; - unsigned long flags; - - crisv32_pinmux_init(); - - if (port >= PORTS) - return -EINVAL; - - spin_lock_irqsave(&pinmux_lock, flags); - - for (i = first_pin; i <= last_pin; i++) { - if ((pins[port * PORT_PINS + i] != pinmux_none) && - (pins[port * PORT_PINS + i] != pinmux_gpio) && - (pins[port * PORT_PINS + i] != mode)) { - spin_unlock_irqrestore(&pinmux_lock, flags); -#ifdef DEBUG - panic("Pinmux alloc failed!\n"); -#endif - return -EPERM; - } - } - - for (i = first_pin; i <= last_pin; i++) - pins[port * PORT_PINS + i] = mode; - - crisv32_pinmux_set(port); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return 0; -} - -int -crisv32_pinmux_alloc_fixed(enum fixed_function function) -{ - int ret = -EINVAL; - char saved[sizeof pins]; - unsigned long flags; - reg_pinmux_rw_hwprot hwprot; - reg_clkgen_rw_clk_ctrl clk_ctrl; - - spin_lock_irqsave(&pinmux_lock, flags); - - /* Save internal data for recovery */ - memcpy(saved, pins, sizeof pins); - - crisv32_pinmux_init(); /* must be done before we read rw_hwprot */ - - hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); - clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); - - switch (function) { - case pinmux_eth: - clk_ctrl.eth = regk_clkgen_yes; - clk_ctrl.dma0_1_eth = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed); - hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes; - break; - case pinmux_geth: - ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed); - hwprot.geth = regk_pinmux_yes; - break; - case pinmux_tg_cmos: - clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed); - hwprot.tg_clk = regk_pinmux_yes; - break; - case pinmux_tg_ccd: - clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed); - hwprot.tg = hwprot.tg_clk = regk_pinmux_yes; - break; - case pinmux_vout: - clk_ctrl.strdma0_2_video = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed); - hwprot.vout = hwprot.vout_sync = regk_pinmux_yes; - break; - case pinmux_ser1: - clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed); - hwprot.ser1 = regk_pinmux_yes; - break; - case pinmux_ser2: - clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed); - hwprot.ser2 = regk_pinmux_yes; - break; - case pinmux_ser3: - clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed); - hwprot.ser3 = regk_pinmux_yes; - break; - case pinmux_ser4: - clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed); - hwprot.ser4 = regk_pinmux_yes; - break; - case pinmux_sser: - clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; - ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed); - hwprot.sser = regk_pinmux_yes; - break; - case pinmux_pio: - hwprot.pio = regk_pinmux_yes; - ret = 0; - break; - case pinmux_pwm0: - ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed); - hwprot.pwm0 = regk_pinmux_yes; - break; - case pinmux_pwm1: - ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed); - hwprot.pwm1 = regk_pinmux_yes; - break; - case pinmux_pwm2: - ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed); - hwprot.pwm2 = regk_pinmux_yes; - break; - case pinmux_i2c0: - ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed); - hwprot.i2c0 = regk_pinmux_yes; - break; - case pinmux_i2c1: - ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); - hwprot.i2c1 = regk_pinmux_yes; - break; - case pinmux_i2c1_3wire: - ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed); - hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes; - break; - case pinmux_i2c1_sda1: - ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed); - hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes; - break; - case pinmux_i2c1_sda2: - ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed); - hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes; - break; - case pinmux_i2c1_sda3: - ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed); - ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed); - hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes; - break; - default: - ret = -EINVAL; - break; - } - - if (!ret) { - REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); - REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); - } else - memcpy(pins, saved, sizeof pins); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return ret; -} - -void -crisv32_pinmux_set(int port) -{ - int i; - int gpio_val = 0; - int iop_val = 0; - int pin = port * PORT_PINS; - - for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) { - if (pins[pin] == pinmux_gpio) - gpio_val |= (1 << i); - else if (pins[pin] == pinmux_iop) - iop_val |= (1 << i); - } - - REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port, - gpio_val); - REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port, - iop_val); - -#ifdef DEBUG - crisv32_pinmux_dump(); -#endif -} - -int -crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) -{ - int i; - unsigned long flags; - - crisv32_pinmux_init(); - - if (port > PORTS || port < 0) - return -EINVAL; - - spin_lock_irqsave(&pinmux_lock, flags); - - for (i = first_pin; i <= last_pin; i++) - pins[port * PORT_PINS + i] = pinmux_none; - - crisv32_pinmux_set(port); - spin_unlock_irqrestore(&pinmux_lock, flags); - - return 0; -} - -int -crisv32_pinmux_dealloc_fixed(enum fixed_function function) -{ - int ret = -EINVAL; - char saved[sizeof pins]; - unsigned long flags; - reg_pinmux_rw_hwprot hwprot; - - spin_lock_irqsave(&pinmux_lock, flags); - - /* Save internal data for recovery */ - memcpy(saved, pins, sizeof pins); - - crisv32_pinmux_init(); /* must be done before we read rw_hwprot */ - - hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); - - switch (function) { - case pinmux_eth: - ret = crisv32_pinmux_dealloc(PORT_B, 8, 23); - ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25); - ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7); - hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no; - break; - case pinmux_tg_cmos: - ret = crisv32_pinmux_dealloc(PORT_B, 27, 29); - hwprot.tg_clk = regk_pinmux_no; - break; - case pinmux_tg_ccd: - ret = crisv32_pinmux_dealloc(PORT_B, 27, 31); - ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15); - hwprot.tg = hwprot.tg_clk = regk_pinmux_no; - break; - case pinmux_vout: - ret = crisv32_pinmux_dealloc(PORT_A, 8, 18); - hwprot.vout = hwprot.vout_sync = regk_pinmux_no; - break; - case pinmux_ser1: - ret = crisv32_pinmux_dealloc(PORT_A, 24, 25); - hwprot.ser1 = regk_pinmux_no; - break; - case pinmux_ser2: - ret = crisv32_pinmux_dealloc(PORT_A, 26, 27); - hwprot.ser2 = regk_pinmux_no; - break; - case pinmux_ser3: - ret = crisv32_pinmux_dealloc(PORT_A, 28, 29); - hwprot.ser3 = regk_pinmux_no; - break; - case pinmux_ser4: - ret = crisv32_pinmux_dealloc(PORT_A, 30, 31); - hwprot.ser4 = regk_pinmux_no; - break; - case pinmux_sser: - ret = crisv32_pinmux_dealloc(PORT_A, 19, 23); - hwprot.sser = regk_pinmux_no; - break; - case pinmux_pwm0: - ret = crisv32_pinmux_dealloc(PORT_A, 30, 30); - hwprot.pwm0 = regk_pinmux_no; - break; - case pinmux_pwm1: - ret = crisv32_pinmux_dealloc(PORT_A, 31, 31); - hwprot.pwm1 = regk_pinmux_no; - break; - case pinmux_pwm2: - ret = crisv32_pinmux_dealloc(PORT_B, 26, 26); - hwprot.pwm2 = regk_pinmux_no; - break; - case pinmux_i2c0: - ret = crisv32_pinmux_dealloc(PORT_A, 0, 1); - hwprot.i2c0 = regk_pinmux_no; - break; - case pinmux_i2c1: - ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); - hwprot.i2c1 = regk_pinmux_no; - break; - case pinmux_i2c1_3wire: - ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); - ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7); - hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no; - break; - case pinmux_i2c1_sda1: - ret = crisv32_pinmux_dealloc(PORT_A, 2, 4); - hwprot.i2c1_sda1 = regk_pinmux_no; - break; - case pinmux_i2c1_sda2: - ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); - ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5); - hwprot.i2c1_sda2 = regk_pinmux_no; - break; - case pinmux_i2c1_sda3: - ret = crisv32_pinmux_dealloc(PORT_A, 2, 3); - ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6); - hwprot.i2c1_sda3 = regk_pinmux_no; - break; - default: - ret = -EINVAL; - break; - } - - if (!ret) - REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); - else - memcpy(pins, saved, sizeof pins); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return ret; -} - -void -crisv32_pinmux_dump(void) -{ - int i, j; - int pin = 0; - - crisv32_pinmux_init(); - - for (i = 0; i < PORTS; i++) { - pin++; - printk(KERN_DEBUG "Port %c\n", 'A'+i); - for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++) - printk(KERN_DEBUG - " Pin %d = %d\n", j, pins[i * PORT_PINS + j]); - } -} - -__initcall(crisv32_pinmux_init); diff --git a/arch/cris/arch-v32/mach-fs/Kconfig b/arch/cris/arch-v32/mach-fs/Kconfig deleted file mode 100644 index 743ba3bcbaec..000000000000 --- a/arch/cris/arch-v32/mach-fs/Kconfig +++ /dev/null @@ -1,198 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if ETRAXFS - -menu "ETRAX FS options" - depends on ETRAXFS - -config ETRAX_DRAM_VIRTUAL_BASE - hex - depends on ETRAX_ARCH_V32 - default "c0000000" - -config ETRAX_SERIAL_PORTS - int - default 4 - -config ETRAX_MEM_GRP1_CONFIG - hex "MEM_GRP1_CONFIG" - depends on ETRAX_ARCH_V32 - default "4044a" - help - Waitstates for flash. The default value is suitable for the - standard flashes used in axis products (120 ns). - -config ETRAX_MEM_GRP2_CONFIG - hex "MEM_GRP2_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for SRAM. 0 is a good choice for most Axis products. - -config ETRAX_MEM_GRP3_CONFIG - hex "MEM_GRP3_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for CSP0-3. 0 is a good choice for most Axis products. - It may need to be changed if external devices such as extra - register-mapped LEDs are used. - -config ETRAX_MEM_GRP4_CONFIG - hex "MEM_GRP4_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - Waitstates for CSP4-6. 0 is a good choice for most Axis products. - -config ETRAX_SDRAM_GRP0_CONFIG - hex "SDRAM_GRP0_CONFIG" - depends on ETRAX_ARCH_V32 - default "336" - help - SDRAM configuration for group 0. The value depends on the - hardware configuration. The default value is suitable - for 32 MB organized as two 16 bits chips (e.g. Axis - part number 18550) connected as one 32 bit device (i.e. in - the same group). - -config ETRAX_SDRAM_GRP1_CONFIG - hex "SDRAM_GRP1_CONFIG" - depends on ETRAX_ARCH_V32 - default "0" - help - SDRAM configuration for group 1. The default value is 0 - because group 1 is not used in the default configuration, - described in the help for SDRAM_GRP0_CONFIG. - -config ETRAX_SDRAM_TIMING - hex "SDRAM_TIMING" - depends on ETRAX_ARCH_V32 - default "104a" - help - SDRAM timing parameters. The default value is ok for - most hardwares but large SDRAMs may require a faster - refresh (a.k.a 8K refresh). The default value implies - 100MHz clock and SDR mode. - -config ETRAX_SDRAM_COMMAND - hex "SDRAM_COMMAND" - depends on ETRAX_ARCH_V32 - default "0" - help - SDRAM command. Should be 0 unless you really know what - you are doing (may be != 0 for unusual address line - mappings such as in a MCM).. - -config ETRAX_DEF_GIO_PA_OE - hex "GIO_PA_OE" - depends on ETRAX_ARCH_V32 - default "1c" - help - Configures the direction of general port A bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PA_OUT - hex "GIO_PA_OUT" - depends on ETRAX_ARCH_V32 - default "00" - help - Configures the initial data for the general port A bits. Most - products should use 00 here. - -config ETRAX_DEF_GIO_PB_OE - hex "GIO_PB_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port B bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PB_OUT - hex "GIO_PB_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port B bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PC_OE - hex "GIO_PC_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port C bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PC_OUT - hex "GIO_PC_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port C bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PD_OE - hex "GIO_PD_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port D bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PD_OUT - hex "GIO_PD_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port D bits. Most - products should use 00000 here. - -config ETRAX_DEF_GIO_PE_OE - hex "GIO_PE_OE" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the direction of general port E bits. 1 is out, 0 is in. - This is often totally different depending on the product used. - There are some guidelines though - if you know that only LED's are - connected to port PA, then they are usually connected to bits 2-4 - and you can therefore use 1c. On other boards which don't have the - LED's at the general ports, these bits are used for all kinds of - stuff. If you don't know what to use, it is always safe to put all - as inputs, although floating inputs isn't good. - -config ETRAX_DEF_GIO_PE_OUT - hex "GIO_PE_OUT" - depends on ETRAX_ARCH_V32 - default "00000" - help - Configures the initial data for the general port E bits. Most - products should use 00000 here. - -endmenu - -endif diff --git a/arch/cris/arch-v32/mach-fs/Makefile b/arch/cris/arch-v32/mach-fs/Makefile deleted file mode 100644 index 0cc6eebacbed..000000000000 --- a/arch/cris/arch-v32/mach-fs/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-y := dma.o pinmux.o arbiter.o - -clean: - diff --git a/arch/cris/arch-v32/mach-fs/arbiter.c b/arch/cris/arch-v32/mach-fs/arbiter.c deleted file mode 100644 index c4750d97e46c..000000000000 --- a/arch/cris/arch-v32/mach-fs/arbiter.c +++ /dev/null @@ -1,405 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Memory arbiter functions. Allocates bandwidth through the - * arbiter and sets up arbiter breakpoints. - * - * The algorithm first assigns slots to the clients that has specified - * bandwidth (e.g. ethernet) and then the remaining slots are divided - * on all the active clients. - * - * Copyright (c) 2004-2007 Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct crisv32_watch_entry { - unsigned long instance; - watch_callback *cb; - unsigned long start; - unsigned long end; - int used; -}; - -#define NUMBER_OF_BP 4 -#define NBR_OF_CLIENTS 14 -#define NBR_OF_SLOTS 64 -#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */ -#define INTMEM_BANDWIDTH 400000000 -#define NBR_OF_REGIONS 2 - -static struct crisv32_watch_entry watches[NUMBER_OF_BP] = { - {regi_marb_bp0}, - {regi_marb_bp1}, - {regi_marb_bp2}, - {regi_marb_bp3} -}; - -static u8 requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS]; -static u8 active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS]; -static int max_bandwidth[NBR_OF_REGIONS] = - { SDRAM_BANDWIDTH, INTMEM_BANDWIDTH }; - -DEFINE_SPINLOCK(arbiter_lock); - -static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id); - -/* - * "I'm the arbiter, I know the score. - * From square one I'll be watching all 64." - * (memory arbiter slots, that is) - * - * Or in other words: - * Program the memory arbiter slots for "region" according to what's - * in requested_slots[] and active_clients[], while minimizing - * latency. A caller may pass a non-zero positive amount for - * "unused_slots", which must then be the unallocated, remaining - * number of slots, free to hand out to any client. - */ - -static void crisv32_arbiter_config(int region, int unused_slots) -{ - int slot; - int client; - int interval = 0; - - /* - * This vector corresponds to the hardware arbiter slots (see - * the hardware documentation for semantics). We initialize - * each slot with a suitable sentinel value outside the valid - * range {0 .. NBR_OF_CLIENTS - 1} and replace them with - * client indexes. Then it's fed to the hardware. - */ - s8 val[NBR_OF_SLOTS]; - - for (slot = 0; slot < NBR_OF_SLOTS; slot++) - val[slot] = -1; - - for (client = 0; client < NBR_OF_CLIENTS; client++) { - int pos; - /* Allocate the requested non-zero number of slots, but - * also give clients with zero-requests one slot each - * while stocks last. We do the latter here, in client - * order. This makes sure zero-request clients are the - * first to get to any spare slots, else those slots - * could, when bandwidth is allocated close to the limit, - * all be allocated to low-index non-zero-request clients - * in the default-fill loop below. Another positive but - * secondary effect is a somewhat better spread of the - * zero-bandwidth clients in the vector, avoiding some of - * the latency that could otherwise be caused by the - * partitioning of non-zero-bandwidth clients at low - * indexes and zero-bandwidth clients at high - * indexes. (Note that this spreading can only affect the - * unallocated bandwidth.) All the above only matters for - * memory-intensive situations, of course. - */ - if (!requested_slots[region][client]) { - /* - * Skip inactive clients. Also skip zero-slot - * allocations in this pass when there are no known - * free slots. - */ - if (!active_clients[region][client] - || unused_slots <= 0) - continue; - - unused_slots--; - - /* Only allocate one slot for this client. */ - interval = NBR_OF_SLOTS; - } else - interval = - NBR_OF_SLOTS / requested_slots[region][client]; - - pos = 0; - while (pos < NBR_OF_SLOTS) { - if (val[pos] >= 0) - pos++; - else { - val[pos] = client; - pos += interval; - } - } - } - - client = 0; - for (slot = 0; slot < NBR_OF_SLOTS; slot++) { - /* - * Allocate remaining slots in round-robin - * client-number order for active clients. For this - * pass, we ignore requested bandwidth and previous - * allocations. - */ - if (val[slot] < 0) { - int first = client; - while (!active_clients[region][client]) { - client = (client + 1) % NBR_OF_CLIENTS; - if (client == first) - break; - } - val[slot] = client; - client = (client + 1) % NBR_OF_CLIENTS; - } - if (region == EXT_REGION) - REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, - val[slot]); - else if (region == INT_REGION) - REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, - val[slot]); - } -} - -extern char _stext[], _etext[]; - -static void crisv32_arbiter_init(void) -{ - static int initialized; - - if (initialized) - return; - - initialized = 1; - - /* - * CPU caches are always set to active, but with zero - * bandwidth allocated. It should be ok to allocate zero - * bandwidth for the caches, because DMA for other channels - * will supposedly finish, once their programmed amount is - * done, and then the caches will get access according to the - * "fixed scheme" for unclaimed slots. Though, if for some - * use-case somewhere, there's a maximum CPU latency for - * e.g. some interrupt, we have to start allocating specific - * bandwidth for the CPU caches too. - */ - active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1; - crisv32_arbiter_config(EXT_REGION, 0); - crisv32_arbiter_config(INT_REGION, 0); - - if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, 0, - "arbiter", NULL)) - printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); - -#ifndef CONFIG_ETRAX_KGDB - /* Global watch for writes to kernel text segment. */ - crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext, - arbiter_all_clients, arbiter_all_write, NULL); -#endif -} - -/* Main entry for bandwidth allocation. */ - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth) -{ - int i; - int total_assigned = 0; - int total_clients = 0; - int req; - - crisv32_arbiter_init(); - - for (i = 0; i < NBR_OF_CLIENTS; i++) { - total_assigned += requested_slots[region][i]; - total_clients += active_clients[region][i]; - } - - /* Avoid division by 0 for 0-bandwidth requests. */ - req = bandwidth == 0 - ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth); - - /* - * We make sure that there are enough slots only for non-zero - * requests. Requesting 0 bandwidth *may* allocate slots, - * though if all bandwidth is allocated, such a client won't - * get any and will have to rely on getting memory access - * according to the fixed scheme that's the default when one - * of the slot-allocated clients doesn't claim their slot. - */ - if (total_assigned + req > NBR_OF_SLOTS) - return -ENOMEM; - - active_clients[region][client] = 1; - requested_slots[region][client] = req; - crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned); - - return 0; -} - -/* - * Main entry for bandwidth deallocation. - * - * Strictly speaking, for a somewhat constant set of clients where - * each client gets a constant bandwidth and is just enabled or - * disabled (somewhat dynamically), no action is necessary here to - * avoid starvation for non-zero-allocation clients, as the allocated - * slots will just be unused. However, handing out those unused slots - * to active clients avoids needless latency if the "fixed scheme" - * would give unclaimed slots to an eager low-index client. - */ - -void crisv32_arbiter_deallocate_bandwidth(int client, int region) -{ - int i; - int total_assigned = 0; - - requested_slots[region][client] = 0; - active_clients[region][client] = 0; - - for (i = 0; i < NBR_OF_CLIENTS; i++) - total_assigned += requested_slots[region][i]; - - crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned); -} - -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback *cb) -{ - int i; - - crisv32_arbiter_init(); - - if (start > 0x80000000) { - printk(KERN_ERR "Arbiter: %lX doesn't look like a " - "physical address", start); - return -EFAULT; - } - - spin_lock(&arbiter_lock); - - for (i = 0; i < NUMBER_OF_BP; i++) { - if (!watches[i].used) { - reg_marb_rw_intr_mask intr_mask = - REG_RD(marb, regi_marb, rw_intr_mask); - - watches[i].used = 1; - watches[i].start = start; - watches[i].end = start + size; - watches[i].cb = cb; - - REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, - watches[i].start); - REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, - watches[i].end); - REG_WR_INT(marb_bp, watches[i].instance, rw_op, - accesses); - REG_WR_INT(marb_bp, watches[i].instance, rw_clients, - clients); - - if (i == 0) - intr_mask.bp0 = regk_marb_yes; - else if (i == 1) - intr_mask.bp1 = regk_marb_yes; - else if (i == 2) - intr_mask.bp2 = regk_marb_yes; - else if (i == 3) - intr_mask.bp3 = regk_marb_yes; - - REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); - spin_unlock(&arbiter_lock); - - return i; - } - } - spin_unlock(&arbiter_lock); - return -ENOMEM; -} - -int crisv32_arbiter_unwatch(int id) -{ - reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask); - - crisv32_arbiter_init(); - - spin_lock(&arbiter_lock); - - if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) { - spin_unlock(&arbiter_lock); - return -EINVAL; - } - - memset(&watches[id], 0, sizeof(struct crisv32_watch_entry)); - - if (id == 0) - intr_mask.bp0 = regk_marb_no; - else if (id == 1) - intr_mask.bp1 = regk_marb_no; - else if (id == 2) - intr_mask.bp2 = regk_marb_no; - else if (id == 3) - intr_mask.bp3 = regk_marb_no; - - REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); - - spin_unlock(&arbiter_lock); - return 0; -} - -extern void show_registers(struct pt_regs *regs); - -static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id) -{ - reg_marb_r_masked_intr masked_intr = - REG_RD(marb, regi_marb, r_masked_intr); - reg_marb_bp_r_brk_clients r_clients; - reg_marb_bp_r_brk_addr r_addr; - reg_marb_bp_r_brk_op r_op; - reg_marb_bp_r_brk_first_client r_first; - reg_marb_bp_r_brk_size r_size; - reg_marb_bp_rw_ack ack = { 0 }; - reg_marb_rw_ack_intr ack_intr = { - .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1 - }; - struct crisv32_watch_entry *watch; - - if (masked_intr.bp0) { - watch = &watches[0]; - ack_intr.bp0 = regk_marb_yes; - } else if (masked_intr.bp1) { - watch = &watches[1]; - ack_intr.bp1 = regk_marb_yes; - } else if (masked_intr.bp2) { - watch = &watches[2]; - ack_intr.bp2 = regk_marb_yes; - } else if (masked_intr.bp3) { - watch = &watches[3]; - ack_intr.bp3 = regk_marb_yes; - } else { - return IRQ_NONE; - } - - /* Retrieve all useful information and print it. */ - r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients); - r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr); - r_op = REG_RD(marb_bp, watch->instance, r_brk_op); - r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client); - r_size = REG_RD(marb_bp, watch->instance, r_brk_size); - - printk(KERN_INFO "Arbiter IRQ\n"); - printk(KERN_INFO "Clients %X addr %X op %X first %X size %X\n", - REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first), - REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size)); - - REG_WR(marb_bp, watch->instance, rw_ack, ack); - REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); - - printk(KERN_INFO "IRQ occurred at %lX\n", get_irq_regs()->erp); - - if (watch->cb) - watch->cb(); - - return IRQ_HANDLED; -} diff --git a/arch/cris/arch-v32/mach-fs/dma.c b/arch/cris/arch-v32/mach-fs/dma.c deleted file mode 100644 index c0347a4f8c65..000000000000 --- a/arch/cris/arch-v32/mach-fs/dma.c +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Wrapper for DMA channel allocator that starts clocks etc */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static char used_dma_channels[MAX_DMA_CHANNELS]; -static const char *used_dma_channels_users[MAX_DMA_CHANNELS]; - -static DEFINE_SPINLOCK(dma_lock); - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned int bandwidth, - enum dma_owner owner) -{ - unsigned long flags; - reg_config_rw_clk_ctrl clk_ctrl; - reg_strmux_rw_cfg strmux_cfg; - - if (crisv32_arbiter_allocate_bandwidth(dmanr, - options & DMA_INT_MEM ? - INT_REGION : EXT_REGION, - bandwidth)) - return -ENOMEM; - - spin_lock_irqsave(&dma_lock, flags); - - if (used_dma_channels[dmanr]) { - spin_unlock_irqrestore(&dma_lock, flags); - if (options & DMA_VERBOSE_ON_ERROR) { - printk(KERN_ERR "Failed to request DMA %i for %s, " - "already allocated by %s\n", - dmanr, - device_id, - used_dma_channels_users[dmanr]); - } - if (options & DMA_PANIC_ON_ERROR) - panic("request_dma error!"); - return -EBUSY; - } - clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl); - strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg); - - switch (dmanr) { - case 0: - case 1: - clk_ctrl.dma01_eth0 = 1; - break; - case 2: - case 3: - clk_ctrl.dma23 = 1; - break; - case 4: - case 5: - clk_ctrl.dma45 = 1; - break; - case 6: - case 7: - clk_ctrl.dma67 = 1; - break; - case 8: - case 9: - clk_ctrl.dma89_strcop = 1; - break; -#if MAX_DMA_CHANNELS-1 != 9 -#error Check dma.c -#endif - default: - spin_unlock_irqrestore(&dma_lock, flags); - if (options & DMA_VERBOSE_ON_ERROR) { - printk(KERN_ERR "Failed to request DMA %i for %s, " - "only 0-%i valid)\n", - dmanr, device_id, MAX_DMA_CHANNELS - 1); - } - - if (options & DMA_PANIC_ON_ERROR) - panic("request_dma error!"); - return -EINVAL; - } - - switch (owner) { - case dma_eth0: - if (dmanr == 0) - strmux_cfg.dma0 = regk_strmux_eth0; - else if (dmanr == 1) - strmux_cfg.dma1 = regk_strmux_eth0; - else - panic("Invalid DMA channel for eth0\n"); - break; - case dma_eth1: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_eth1; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_eth1; - else - panic("Invalid DMA channel for eth1\n"); - break; - case dma_iop0: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_iop0; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_iop0; - else - panic("Invalid DMA channel for iop0\n"); - break; - case dma_iop1: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_iop1; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_iop1; - else - panic("Invalid DMA channel for iop1\n"); - break; - case dma_ser0: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_ser0; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_ser0; - else - panic("Invalid DMA channel for ser0\n"); - break; - case dma_ser1: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_ser1; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_ser1; - else - panic("Invalid DMA channel for ser1\n"); - break; - case dma_ser2: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ser2; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ser2; - else - panic("Invalid DMA channel for ser2\n"); - break; - case dma_ser3: - if (dmanr == 8) - strmux_cfg.dma8 = regk_strmux_ser3; - else if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_ser3; - else - panic("Invalid DMA channel for ser3\n"); - break; - case dma_sser0: - if (dmanr == 4) - strmux_cfg.dma4 = regk_strmux_sser0; - else if (dmanr == 5) - strmux_cfg.dma5 = regk_strmux_sser0; - else - panic("Invalid DMA channel for sser0\n"); - break; - case dma_sser1: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_sser1; - else if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_sser1; - else - panic("Invalid DMA channel for sser1\n"); - break; - case dma_ata: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ata; - else if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ata; - else - panic("Invalid DMA channel for ata\n"); - break; - case dma_strp: - if (dmanr == 8) - strmux_cfg.dma8 = regk_strmux_strcop; - else if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_strcop; - else - panic("Invalid DMA channel for strp\n"); - break; - case dma_ext0: - if (dmanr == 6) - strmux_cfg.dma6 = regk_strmux_ext0; - else - panic("Invalid DMA channel for ext0\n"); - break; - case dma_ext1: - if (dmanr == 7) - strmux_cfg.dma7 = regk_strmux_ext1; - else - panic("Invalid DMA channel for ext1\n"); - break; - case dma_ext2: - if (dmanr == 2) - strmux_cfg.dma2 = regk_strmux_ext2; - else if (dmanr == 8) - strmux_cfg.dma8 = regk_strmux_ext2; - else - panic("Invalid DMA channel for ext2\n"); - break; - case dma_ext3: - if (dmanr == 3) - strmux_cfg.dma3 = regk_strmux_ext3; - else if (dmanr == 9) - strmux_cfg.dma9 = regk_strmux_ext2; - else - panic("Invalid DMA channel for ext2\n"); - break; - } - - used_dma_channels[dmanr] = 1; - used_dma_channels_users[dmanr] = device_id; - REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); - REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); - spin_unlock_irqrestore(&dma_lock, flags); - return 0; -} - -void crisv32_free_dma(unsigned int dmanr) -{ - spin_lock(&dma_lock); - used_dma_channels[dmanr] = 0; - spin_unlock(&dma_lock); -} diff --git a/arch/cris/arch-v32/mach-fs/dram_init.S b/arch/cris/arch-v32/mach-fs/dram_init.S deleted file mode 100644 index e1a01fa4c272..000000000000 --- a/arch/cris/arch-v32/mach-fs/dram_init.S +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * DRAM/SDRAM initialization - alter with care - * This file is intended to be included from other assembler files - * - * Note: This file may not modify r8 or r9 because they are used to - * carry information from the decompressor to the kernel - * - * Copyright (C) 2000-2007 Axis Communications AB - * - * Authors: Mikael Starvik - */ - -/* Just to be certain the config file is included, we include it here - * explicitly instead of depending on it being included in the file that - * uses this code. - */ - -#include -#include - - ;; WARNING! The registers r8 and r9 are used as parameters carrying - ;; information from the decompressor (if the kernel was compressed). - ;; They should not be used in the code below. - - ; Refer to BIF MDS for a description of SDRAM initialization - - ; Bank configuration - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0 - move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0 - move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - - ; Calculate value of mrs_data - ; CAS latency = 2 && bus_width = 32 => 0x40 - ; CAS latency = 3 && bus_width = 32 => 0x60 - ; CAS latency = 2 && bus_width = 16 => 0x20 - ; CAS latency = 3 && bus_width = 16 => 0x30 - - ; Check if value is already supplied in kernel config - move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2 - bne _set_timing - nop - - move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2 - move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 - and.d 0x07, $r1 ; Get CAS latency - cmpq 2, $r1 ; CL = 2 ? - beq _bw_check - nop - move.d 0x60, $r4 - -_bw_check: - ; Assume that group 0 width is equal to group 1. This assumption - ; is wrong for a group 1 only hardware (such as the grand old - ; StorPoint+). - move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1 - and.d 0x200, $r1 ; DRAM width is bit 9 - beq _set_timing - lslq 2, $r4 ; mrs_data starts at bit 2 - lsrq 1, $r4 ; 16 bits. Shift down value. - - ; Set timing parameters (refresh off to avoid Guinness TR 83) -_set_timing: - move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 - and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1 - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0 - move.d $r1, [$r0] - - ; Issue NOP command - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5 - moveq regk_bif_core_nop, $r1 - move.d $r1, [$r5] - - ; Wait 200us - move.d 10000, $r2 -1: bne 1b - subq 1, $r2 - - ; Issue initialization command sequence - lapc _sdram_commands_start, $r2 - lapc _sdram_commands_end, $r3 -1: clear.d $r6 - move.b [$r2+], $r6 ; Load command - or.d $r4, $r6 ; Add calculated mrs - move.d $r6, [$r5] ; Write rw_sdram_cmd - ; Wait 80 ns between each command - move.d 4000, $r7 -2: bne 2b - subq 1, $r7 - cmp.d $r2, $r3 ; Last command? - bne 1b - nop - - ; Start refresh - move.d CONFIG_ETRAX_SDRAM_TIMING, $r1 - move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0 - move.d $r1, [$r0] - - ; Initialization finished - ba _sdram_commands_end - nop - -_sdram_commands_start: - .byte regk_bif_core_pre ; Precharge - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_ref ; refresh - .byte regk_bif_core_mrs ; mrs -_sdram_commands_end: diff --git a/arch/cris/arch-v32/mach-fs/hw_settings.S b/arch/cris/arch-v32/mach-fs/hw_settings.S deleted file mode 100644 index 7fbadcc48c0c..000000000000 --- a/arch/cris/arch-v32/mach-fs/hw_settings.S +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This table is used by some tools to extract hardware parameters. - * The table should be included in the kernel and the decompressor. - * Don't forget to update the tools if you change this table. - * - * Copyright (C) 2001-2007 Axis Communications AB - * - * Authors: Mikael Starvik - */ - -#include -#include -#include - - .ascii "HW_PARAM_MAGIC" ; Magic number - .dword 0xc0004000 ; Kernel start address - - ; Debug port -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - .dword 0 -#elif defined(CONFIG_ETRAX_DEBUG_PORT1) - .dword 1 -#elif defined(CONFIG_ETRAX_DEBUG_PORT2) - .dword 2 -#elif defined(CONFIG_ETRAX_DEBUG_PORT3) - .dword 3 -#else - .dword 4 ; No debug -#endif - - ; Register values - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg) - .dword CONFIG_ETRAX_MEM_GRP1_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg) - .dword CONFIG_ETRAX_MEM_GRP2_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg) - .dword CONFIG_ETRAX_MEM_GRP3_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg) - .dword CONFIG_ETRAX_MEM_GRP4_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0) - .dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1) - .dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing) - .dword CONFIG_ETRAX_SDRAM_TIMING - .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd) - .dword CONFIG_ETRAX_SDRAM_COMMAND - - .dword REG_ADDR(gio, regi_gio, rw_pa_dout) - .dword CONFIG_ETRAX_DEF_GIO_PA_OUT - .dword REG_ADDR(gio, regi_gio, rw_pa_oe) - .dword CONFIG_ETRAX_DEF_GIO_PA_OE - .dword REG_ADDR(gio, regi_gio, rw_pb_dout) - .dword CONFIG_ETRAX_DEF_GIO_PB_OUT - .dword REG_ADDR(gio, regi_gio, rw_pb_oe) - .dword CONFIG_ETRAX_DEF_GIO_PB_OE - .dword REG_ADDR(gio, regi_gio, rw_pc_dout) - .dword CONFIG_ETRAX_DEF_GIO_PC_OUT - .dword REG_ADDR(gio, regi_gio, rw_pc_oe) - .dword CONFIG_ETRAX_DEF_GIO_PC_OE - .dword REG_ADDR(gio, regi_gio, rw_pd_dout) - .dword CONFIG_ETRAX_DEF_GIO_PD_OUT - .dword REG_ADDR(gio, regi_gio, rw_pd_oe) - .dword CONFIG_ETRAX_DEF_GIO_PD_OE - .dword REG_ADDR(gio, regi_gio, rw_pe_dout) - .dword CONFIG_ETRAX_DEF_GIO_PE_OUT - .dword REG_ADDR(gio, regi_gio, rw_pe_oe) - .dword CONFIG_ETRAX_DEF_GIO_PE_OE - - .dword 0 ; No more register values diff --git a/arch/cris/arch-v32/mach-fs/pinmux.c b/arch/cris/arch-v32/mach-fs/pinmux.c deleted file mode 100644 index a0b2f101003a..000000000000 --- a/arch/cris/arch-v32/mach-fs/pinmux.c +++ /dev/null @@ -1,328 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Allocator for I/O pins. All pins are allocated to GPIO at bootup. - * Unassigned pins and GPIO pins can be allocated to a fixed interface - * or the I/O processor instead. - * - * Copyright (c) 2004-2007 Axis Communications AB. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#undef DEBUG - -#define PORT_PINS 18 -#define PORTS 4 - -static char pins[PORTS][PORT_PINS]; -static DEFINE_SPINLOCK(pinmux_lock); - -static void crisv32_pinmux_set(int port); - -static int __crisv32_pinmux_alloc(int port, int first_pin, int last_pin, - enum pin_mode mode) -{ - int i; - - for (i = first_pin; i <= last_pin; i++) { - if ((pins[port][i] != pinmux_none) - && (pins[port][i] != pinmux_gpio) - && (pins[port][i] != mode)) { -#ifdef DEBUG - panic("Pinmux alloc failed!\n"); -#endif - return -EPERM; - } - } - - for (i = first_pin; i <= last_pin; i++) - pins[port][i] = mode; - - crisv32_pinmux_set(port); - - return 0; -} - -static int crisv32_pinmux_init(void) -{ - static int initialized; - - if (!initialized) { - reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa); - initialized = 1; - REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0); - pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 = - pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes; - REG_WR(pinmux, regi_pinmux, rw_pa, pa); - __crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio); - __crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio); - __crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio); - __crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio); - } - - return 0; -} - -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, - enum pin_mode mode) -{ - unsigned long flags; - int ret; - - crisv32_pinmux_init(); - - if (port > PORTS || port < 0) - return -EINVAL; - - spin_lock_irqsave(&pinmux_lock, flags); - - ret = __crisv32_pinmux_alloc(port, first_pin, last_pin, mode); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return ret; -} - -int crisv32_pinmux_alloc_fixed(enum fixed_function function) -{ - int ret = -EINVAL; - char saved[sizeof pins]; - unsigned long flags; - reg_pinmux_rw_hwprot hwprot; - - spin_lock_irqsave(&pinmux_lock, flags); - - /* Save internal data for recovery */ - memcpy(saved, pins, sizeof pins); - - crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */ - - hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); - - switch (function) { - case pinmux_ser1: - ret = __crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed); - hwprot.ser1 = regk_pinmux_yes; - break; - case pinmux_ser2: - ret = __crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed); - hwprot.ser2 = regk_pinmux_yes; - break; - case pinmux_ser3: - ret = __crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed); - hwprot.ser3 = regk_pinmux_yes; - break; - case pinmux_sser0: - ret = __crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed); - ret |= __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); - hwprot.sser0 = regk_pinmux_yes; - break; - case pinmux_sser1: - ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); - hwprot.sser1 = regk_pinmux_yes; - break; - case pinmux_ata0: - ret = __crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed); - ret |= __crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed); - hwprot.ata0 = regk_pinmux_yes; - break; - case pinmux_ata1: - ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed); - ret |= __crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed); - hwprot.ata1 = regk_pinmux_yes; - break; - case pinmux_ata2: - ret = __crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed); - ret |= __crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed); - hwprot.ata2 = regk_pinmux_yes; - break; - case pinmux_ata3: - ret = __crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed); - ret |= __crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed); - hwprot.ata2 = regk_pinmux_yes; - break; - case pinmux_ata: - ret = __crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed); - ret |= __crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed); - hwprot.ata = regk_pinmux_yes; - break; - case pinmux_eth1: - ret = __crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed); - hwprot.eth1 = regk_pinmux_yes; - hwprot.eth1_mgm = regk_pinmux_yes; - break; - case pinmux_timer: - ret = __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed); - hwprot.timer = regk_pinmux_yes; - spin_unlock_irqrestore(&pinmux_lock, flags); - return ret; - } - - if (!ret) - REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); - else - memcpy(pins, saved, sizeof pins); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return ret; -} - -void crisv32_pinmux_set(int port) -{ - int i; - int gpio_val = 0; - int iop_val = 0; - - for (i = 0; i < PORT_PINS; i++) { - if (pins[port][i] == pinmux_gpio) - gpio_val |= (1 << i); - else if (pins[port][i] == pinmux_iop) - iop_val |= (1 << i); - } - - REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port, - gpio_val); - REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port, - iop_val); - -#ifdef DEBUG - crisv32_pinmux_dump(); -#endif -} - -static int __crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) -{ - int i; - - for (i = first_pin; i <= last_pin; i++) - pins[port][i] = pinmux_none; - - crisv32_pinmux_set(port); - return 0; -} - -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin) -{ - unsigned long flags; - - crisv32_pinmux_init(); - - if (port > PORTS || port < 0) - return -EINVAL; - - spin_lock_irqsave(&pinmux_lock, flags); - __crisv32_pinmux_dealloc(port, first_pin, last_pin); - spin_unlock_irqrestore(&pinmux_lock, flags); - - return 0; -} - -int crisv32_pinmux_dealloc_fixed(enum fixed_function function) -{ - int ret = -EINVAL; - char saved[sizeof pins]; - unsigned long flags; - reg_pinmux_rw_hwprot hwprot; - - spin_lock_irqsave(&pinmux_lock, flags); - - /* Save internal data for recovery */ - memcpy(saved, pins, sizeof pins); - - crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */ - - hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); - - switch (function) { - case pinmux_ser1: - ret = __crisv32_pinmux_dealloc(PORT_C, 4, 7); - hwprot.ser1 = regk_pinmux_no; - break; - case pinmux_ser2: - ret = __crisv32_pinmux_dealloc(PORT_C, 8, 11); - hwprot.ser2 = regk_pinmux_no; - break; - case pinmux_ser3: - ret = __crisv32_pinmux_dealloc(PORT_C, 12, 15); - hwprot.ser3 = regk_pinmux_no; - break; - case pinmux_sser0: - ret = __crisv32_pinmux_dealloc(PORT_C, 0, 3); - ret |= __crisv32_pinmux_dealloc(PORT_C, 16, 16); - hwprot.sser0 = regk_pinmux_no; - break; - case pinmux_sser1: - ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4); - hwprot.sser1 = regk_pinmux_no; - break; - case pinmux_ata0: - ret = __crisv32_pinmux_dealloc(PORT_D, 5, 7); - ret |= __crisv32_pinmux_dealloc(PORT_D, 15, 17); - hwprot.ata0 = regk_pinmux_no; - break; - case pinmux_ata1: - ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4); - ret |= __crisv32_pinmux_dealloc(PORT_E, 17, 17); - hwprot.ata1 = regk_pinmux_no; - break; - case pinmux_ata2: - ret = __crisv32_pinmux_dealloc(PORT_C, 11, 15); - ret |= __crisv32_pinmux_dealloc(PORT_E, 3, 3); - hwprot.ata2 = regk_pinmux_no; - break; - case pinmux_ata3: - ret = __crisv32_pinmux_dealloc(PORT_C, 8, 10); - ret |= __crisv32_pinmux_dealloc(PORT_C, 0, 2); - hwprot.ata2 = regk_pinmux_no; - break; - case pinmux_ata: - ret = __crisv32_pinmux_dealloc(PORT_B, 0, 15); - ret |= __crisv32_pinmux_dealloc(PORT_D, 8, 15); - hwprot.ata = regk_pinmux_no; - break; - case pinmux_eth1: - ret = __crisv32_pinmux_dealloc(PORT_E, 0, 17); - hwprot.eth1 = regk_pinmux_no; - hwprot.eth1_mgm = regk_pinmux_no; - break; - case pinmux_timer: - ret = __crisv32_pinmux_dealloc(PORT_C, 16, 16); - hwprot.timer = regk_pinmux_no; - spin_unlock_irqrestore(&pinmux_lock, flags); - return ret; - } - - if (!ret) - REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); - else - memcpy(pins, saved, sizeof pins); - - spin_unlock_irqrestore(&pinmux_lock, flags); - - return ret; -} - -#ifdef DEBUG -static void crisv32_pinmux_dump(void) -{ - int i, j; - - crisv32_pinmux_init(); - - for (i = 0; i < PORTS; i++) { - printk(KERN_DEBUG "Port %c\n", 'B' + i); - for (j = 0; j < PORT_PINS; j++) - printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]); - } -} -#endif -__initcall(crisv32_pinmux_init); diff --git a/arch/cris/arch-v32/mm/Makefile b/arch/cris/arch-v32/mm/Makefile deleted file mode 100644 index 0b801f2964ac..000000000000 --- a/arch/cris/arch-v32/mm/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# Makefile for the Linux/cris parts of the memory manager. - -obj-y += mmu.o init.o tlb.o intmem.o -obj-$(CONFIG_ETRAX_L2CACHE) += l2cache.o diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c deleted file mode 100644 index 784876afa001..000000000000 --- a/arch/cris/arch-v32/mm/init.c +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Set up paging and the MMU. - * - * Copyright (C) 2000-2003, Axis Communications AB. - * - * Authors: Bjorn Wesen - * Tobias Anderberg , CRISv32 port. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern void tlb_init(void); - -/* - * The kernel is already mapped with linear mapping at kseg_c so there's no - * need to map it with a page table. However, head.S also temporarily mapped it - * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various - * other paging stuff. - */ -void __init cris_mmu_init(void) -{ - unsigned long mmu_config; - unsigned long mmu_kbase_hi; - unsigned long mmu_kbase_lo; - unsigned short mmu_page_id; - - /* - * Make sure the current pgd table points to something sane, even if it - * is most probably not used until the next switch_mm. - */ - per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; - - /* Initialise the TLB. Function found in tlb.c. */ - tlb_init(); - - /* - * Enable exceptions and initialize the kernel segments. - * See head.S for differences between ARTPEC-3 and ETRAX FS. - */ - mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) | - REG_STATE(mmu, rw_mm_cfg, acc, on) | - REG_STATE(mmu, rw_mm_cfg, ex, on) | - REG_STATE(mmu, rw_mm_cfg, inv, on) | -#ifdef CONFIG_CRIS_MACH_ARTPEC3 - REG_STATE(mmu, rw_mm_cfg, seg_f, page) | - REG_STATE(mmu, rw_mm_cfg, seg_e, page) | - REG_STATE(mmu, rw_mm_cfg, seg_d, linear) | -#else - REG_STATE(mmu, rw_mm_cfg, seg_f, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_e, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_d, page) | -#endif - REG_STATE(mmu, rw_mm_cfg, seg_c, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_b, linear) | - REG_STATE(mmu, rw_mm_cfg, seg_a, page) | - REG_STATE(mmu, rw_mm_cfg, seg_9, page) | - REG_STATE(mmu, rw_mm_cfg, seg_8, page) | - REG_STATE(mmu, rw_mm_cfg, seg_7, page) | - REG_STATE(mmu, rw_mm_cfg, seg_6, page) | - REG_STATE(mmu, rw_mm_cfg, seg_5, page) | - REG_STATE(mmu, rw_mm_cfg, seg_4, page) | - REG_STATE(mmu, rw_mm_cfg, seg_3, page) | - REG_STATE(mmu, rw_mm_cfg, seg_2, page) | - REG_STATE(mmu, rw_mm_cfg, seg_1, page) | - REG_STATE(mmu, rw_mm_cfg, seg_0, page)); - - /* See head.S for differences between ARTPEC-3 and ETRAX FS. */ - mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) | -#ifdef CONFIG_CRIS_MACH_ARTPEC3 - REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) | -#else - REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) | -#endif - REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0)); - - mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) | - REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0)); - - mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0); - - /* Update the instruction MMU. */ - SUPP_BANK_SEL(BANK_IM); - SUPP_REG_WR(RW_MM_CFG, mmu_config); - SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi); - SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo); - SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id); - - /* Update the data MMU. */ - SUPP_BANK_SEL(BANK_DM); - SUPP_REG_WR(RW_MM_CFG, mmu_config); - SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi); - SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo); - SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id); - - SPEC_REG_WR(SPEC_REG_PID, 0); - - /* - * The MMU has been enabled ever since head.S but just to make it - * totally obvious enable it here as well. - */ - SUPP_BANK_SEL(BANK_GC); - SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */ -} - -void __init paging_init(void) -{ - int i; - unsigned long zones_size[MAX_NR_ZONES]; - - printk("Setting up paging and the MMU.\n"); - - /* Clear out the init_mm.pgd that will contain the kernel's mappings. */ - for(i = 0; i < PTRS_PER_PGD; i++) - swapper_pg_dir[i] = __pgd(0); - - cris_mmu_init(); - - /* - * Initialize the bad page table and bad page to point to a couple of - * allocated pages. - */ - empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); - memset((void *) empty_zero_page, 0, PAGE_SIZE); - - /* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */ - zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT; - - for (i = 1; i < MAX_NR_ZONES; i++) - zones_size[i] = 0; - - /* - * Use free_area_init_node instead of free_area_init, because it is - * designed for systems where the DRAM starts at an address - * substantially higher than 0, like us (we start at PAGE_OFFSET). This - * saves space in the mem_map page array. - */ - free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); - - mem_map = contig_page_data.node_mem_map; -} diff --git a/arch/cris/arch-v32/mm/intmem.c b/arch/cris/arch-v32/mm/intmem.c deleted file mode 100644 index 928b94d1d320..000000000000 --- a/arch/cris/arch-v32/mm/intmem.c +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Simple allocator for internal RAM in ETRAX FS - * - * Copyright (c) 2004 Axis Communications AB. - */ - -#include -#include -#include -#include - -#define STATUS_FREE 0 -#define STATUS_ALLOCATED 1 - -#ifdef CONFIG_ETRAX_L2CACHE -#define RESERVED_SIZE 66*1024 -#else -#define RESERVED_SIZE 0 -#endif - -struct intmem_allocation { - struct list_head entry; - unsigned int size; - unsigned offset; - char status; -}; - - -static struct list_head intmem_allocations; -static void* intmem_virtual; - -static void crisv32_intmem_init(void) -{ - static int initiated = 0; - if (!initiated) { - struct intmem_allocation* alloc; - alloc = kmalloc(sizeof *alloc, GFP_KERNEL); - INIT_LIST_HEAD(&intmem_allocations); - intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE, - MEM_INTMEM_SIZE - RESERVED_SIZE); - initiated = 1; - alloc->size = MEM_INTMEM_SIZE - RESERVED_SIZE; - alloc->offset = 0; - alloc->status = STATUS_FREE; - list_add_tail(&alloc->entry, &intmem_allocations); - } -} - -void* crisv32_intmem_alloc(unsigned size, unsigned align) -{ - struct intmem_allocation* allocation; - struct intmem_allocation* tmp; - void* ret = NULL; - - preempt_disable(); - crisv32_intmem_init(); - - list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { - int alignment = allocation->offset % align; - alignment = alignment ? align - alignment : alignment; - - if (allocation->status == STATUS_FREE && - allocation->size >= size + alignment) { - if (allocation->size > size + alignment) { - struct intmem_allocation* alloc; - alloc = kmalloc(sizeof *alloc, GFP_ATOMIC); - alloc->status = STATUS_FREE; - alloc->size = allocation->size - size - - alignment; - alloc->offset = allocation->offset + size + - alignment; - list_add(&alloc->entry, &allocation->entry); - - if (alignment) { - struct intmem_allocation *tmp; - tmp = kmalloc(sizeof *tmp, GFP_ATOMIC); - tmp->offset = allocation->offset; - tmp->size = alignment; - tmp->status = STATUS_FREE; - allocation->offset += alignment; - list_add_tail(&tmp->entry, - &allocation->entry); - } - } - allocation->status = STATUS_ALLOCATED; - allocation->size = size; - ret = (void*)((int)intmem_virtual + allocation->offset); - } - } - preempt_enable(); - return ret; -} - -void crisv32_intmem_free(void* addr) -{ - struct intmem_allocation* allocation; - struct intmem_allocation* tmp; - - if (addr == NULL) - return; - - preempt_disable(); - crisv32_intmem_init(); - - list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) { - if (allocation->offset == (int)(addr - intmem_virtual)) { - struct intmem_allocation *prev = - list_entry(allocation->entry.prev, - struct intmem_allocation, entry); - struct intmem_allocation *next = - list_entry(allocation->entry.next, - struct intmem_allocation, entry); - - allocation->status = STATUS_FREE; - /* Join with prev and/or next if also free */ - if ((&prev->entry != &intmem_allocations) && - (prev->status == STATUS_FREE)) { - prev->size += allocation->size; - list_del(&allocation->entry); - kfree(allocation); - allocation = prev; - } - if ((&next->entry != &intmem_allocations) && - (next->status == STATUS_FREE)) { - allocation->size += next->size; - list_del(&next->entry); - kfree(next); - } - preempt_enable(); - return; - } - } - preempt_enable(); -} - -void* crisv32_intmem_phys_to_virt(unsigned long addr) -{ - return (void *)(addr - (MEM_INTMEM_START + RESERVED_SIZE) + - (unsigned long)intmem_virtual); -} - -unsigned long crisv32_intmem_virt_to_phys(void* addr) -{ - return (unsigned long)((unsigned long )addr - - (unsigned long)intmem_virtual + MEM_INTMEM_START + - RESERVED_SIZE); -} - -static int __init crisv32_intmem_setup(void) -{ - crisv32_intmem_init(); - - return 0; -} -device_initcall(crisv32_intmem_setup); - diff --git a/arch/cris/arch-v32/mm/l2cache.c b/arch/cris/arch-v32/mm/l2cache.c deleted file mode 100644 index 4fef321d5606..000000000000 --- a/arch/cris/arch-v32/mm/l2cache.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include - -#define L2CACHE_SIZE 64 - -int __init l2cache_init(void) -{ - reg_l2cache_rw_ctrl ctrl = {0}; - reg_l2cache_rw_cfg cfg = {.en = regk_l2cache_yes}; - - ctrl.csize = L2CACHE_SIZE; - ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0); - REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl); - - /* Flush the tag memory */ - memset((void *)(MEM_INTMEM_START | MEM_NON_CACHEABLE), 0, 2*1024); - - /* Enable the cache */ - REG_WR(l2cache, regi_l2cache, rw_cfg, cfg); - - return 0; -} - diff --git a/arch/cris/arch-v32/mm/mmu.S b/arch/cris/arch-v32/mm/mmu.S deleted file mode 100644 index f24965703f6d..000000000000 --- a/arch/cris/arch-v32/mm/mmu.S +++ /dev/null @@ -1,211 +0,0 @@ -; SPDX-License-Identifier: GPL-2.0 -; WARNING : The refill handler has been modified, see below !!! - -/* - * Copyright (C) 2003 Axis Communications AB - * - * Authors: Mikael Starvik (starvik@axis.com) - * - * Code for the fault low-level handling routines. - * - */ - -#include -#include - -; Save all register. Must save in same order as struct pt_regs. -.macro SAVE_ALL - subq 12, $sp - move $erp, [$sp] - subq 4, $sp - move $srp, [$sp] - subq 4, $sp - move $ccs, [$sp] - subq 4, $sp - move $spc, [$sp] - subq 4, $sp - move $mof, [$sp] - subq 4, $sp - move $srs, [$sp] - subq 4, $sp - move.d $acr, [$sp] - subq 14*4, $sp - movem $r13, [$sp] - subq 4, $sp - move.d $r10, [$sp] -.endm - -; Bus fault handler. Extracts relevant information and calls mm subsystem -; to handle the fault. -.macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex - .globl \handler - .type \handler,"function" -\handler: - SAVE_ALL - move \mmu, $srs ; Select MMU support register bank - move.d $sp, $r11 ; regs - moveq 1, $r12 ; protection fault - moveq \we, $r13 ; write exception? - orq \ex << 1, $r13 ; execute? - move $s3, $r10 ; rw_mm_cause - and.d ~8191, $r10 ; Get faulting page start address - - jsr do_page_fault - nop - ba ret_from_intr - nop - .size \handler, . - \handler -.endm - -; Refill handler. Three cases may occur: -; 1. PMD and PTE exists in mm subsystem but not in TLB -; 2. PMD exists but not PTE -; 3. PMD doesn't exist -; The code below handles case 1 and calls the mm subsystem for case 2 and 3. -; Do not touch this code without very good reasons and extensive testing. -; Note that the code is optimized to minimize stalls (makes the code harder -; to read). -; -; WARNING !!! -; Modified by Mikael Asker 060725: added a workaround for strange TLB -; behavior. If the same PTE is present in more than one set, the TLB -; doesn't recognize it and we get stuck in a loop of refill exceptions. -; The workaround detects such loops and exits them by flushing -; the TLB contents. The problem and workaround were verified -; in VCS by Mikael Starvik. -; -; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each -; PMD holds 16 MB of virtual memory. -; Bits 0-12 : Offset within a page -; Bits 13-23 : PTE offset within a PMD -; Bits 24-31 : PMD offset within the PGD - -.macro MMU_REFILL_HANDLER handler, mmu - .data -1: .dword 0 ; refill_count - ; == 0 <=> last_refill_cause is invalid -2: .dword 0 ; last_refill_cause - .text - .globl \handler - .type \handler, "function" -\handler: - subq 4, $sp -; (The pipeline stalls for one cycle; $sp used as address in the next cycle.) - move $srs, [$sp] - subq 4, $sp - move \mmu, $srs ; Select MMU support register bank - move.d $acr, [$sp] - subq 12, $sp - move.d 1b, $acr ; Point to refill_count - movem $r2, [$sp] - - test.d [$acr] ; refill_count == 0 ? - beq 5f ; yes, last_refill_cause is invalid - move.d $acr, $r1 - - ; last_refill_cause is valid, investigate cause - addq 4, $r1 ; Point to last_refill_cause - move $s3, $r0 ; Get rw_mm_cause - move.d [$r1], $r2 ; Get last_refill_cause - cmp.d $r0, $r2 ; rw_mm_cause == last_refill_cause ? - beq 6f ; yes, increment count - moveq 1, $r2 - - ; rw_mm_cause != last_refill_cause - move.d $r2, [$acr] ; refill_count = 1 - move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause - -3: ; Probably not in a loop, continue normal processing - move.d current_pgd, $acr ; PGD - ; Look up PMD in PGD - lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31) - move.d [$acr], $acr ; PGD for the current process - addi $r0.d, $acr, $acr - move $s3, $r0 ; rw_mm_cause - move.d [$acr], $acr ; Get PMD - beq 8f - ; Look up PTE in PMD - lsrq PAGE_SHIFT, $r0 - and.w PAGE_MASK, $acr ; Remove PMD flags - and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23) - addi $r0.d, $acr, $acr - move.d [$acr], $acr ; Get PTE - beq 9f - movem [$sp], $r2 ; Restore r0-r2 in delay slot - addq 12, $sp - ; Store in TLB - move $acr, $s5 -4: ; Return - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - rete - rfe - -5: ; last_refill_cause is invalid - moveq 1, $r2 - addq 4, $r1 ; Point to last_refill_cause - move.d $r2, [$acr] ; refill_count = 1 - move $s3, $r0 ; Get rw_mm_cause - ba 3b ; Continue normal processing - move.d $r0,[$r1] ; last_refill_cause = rw_mm_cause - -6: ; rw_mm_cause == last_refill_cause - move.d [$acr], $r2 ; Get refill_count - cmpq 4, $r2 ; refill_count > 4 ? - bhi 7f ; yes - addq 1, $r2 ; refill_count++ - ba 3b ; Continue normal processing - move.d $r2, [$acr] - -7: ; refill_count > 4, error - move.d $acr, $r0 ; Save pointer to refill_count - clear.d [$r0] ; refill_count = 0 - - ;; rewind the short stack - movem [$sp], $r2 ; Restore r0-r2 - addq 12, $sp - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - ;; Keep it simple (slow), save all the regs. - SAVE_ALL - jsr __flush_tlb_all - nop - ba ret_from_intr ; Return - nop - -8: ; PMD missing, let the mm subsystem fix it up. - movem [$sp], $r2 ; Restore r0-r2 -9: ; PTE missing, let the mm subsystem fix it up. - addq 12, $sp - move.d [$sp+], $acr - move [$sp], $srs - addq 4, $sp - SAVE_ALL - move \mmu, $srs - move.d $sp, $r11 ; regs - clear.d $r12 ; Not a protection fault - move.w PAGE_MASK, $acr - move $s3, $r10 ; rw_mm_cause - btstq 9, $r10 ; Check if write access - smi $r13 - and.w PAGE_MASK, $r10 ; Get VPN (virtual address) - jsr do_page_fault - and.w $acr, $r10 - ; Return - ba ret_from_intr - nop - .size \handler, . - \handler -.endm - - ; This is the MMU bus fault handlers. - -MMU_REFILL_HANDLER i_mmu_refill, 1 -MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0 -MMU_BUS_FAULT_HANDLER i_mmu_access, 1, 0, 0 -MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1 -MMU_REFILL_HANDLER d_mmu_refill, 2 -MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0 -MMU_BUS_FAULT_HANDLER d_mmu_access, 2, 0, 0 -MMU_BUS_FAULT_HANDLER d_mmu_write, 2, 1, 0 diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c deleted file mode 100644 index 9e4b5ab4971d..000000000000 --- a/arch/cris/arch-v32/mm/tlb.c +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Low level TLB handling. - * - * Copyright (C) 2000-2003, Axis Communications AB. - * - * Authors: Bjorn Wesen - * Tobias Anderberg , CRISv32 port. - */ -#include - -#include -#include -#include -#include - -#define UPDATE_TLB_SEL_IDX(val) \ -do { \ - unsigned long tlb_sel; \ - \ - tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \ - SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \ -} while(0) - -#define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \ -do { \ - SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \ - SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \ -} while(0) - -/* - * The TLB can host up to 256 different mm contexts at the same time. The running - * context is found in the PID register. Each TLB entry contains a page_id that - * has to match the PID register to give a hit. page_id_map keeps track of which - * mm's is assigned to which page_id's, making sure it's known when to - * invalidate TLB entries. - * - * The last page_id is never running, it is used as an invalid page_id so that - * it's possible to make TLB entries that will nerver match. - * - * Note; the flushes needs to be atomic otherwise an interrupt hander that uses - * vmalloc'ed memory might cause a TLB load in the middle of a flush. - */ - -/* Flush all TLB entries. */ -void -__flush_tlb_all(void) -{ - int i; - int mmu; - unsigned long flags; - unsigned long mmu_tlb_hi; - unsigned long mmu_tlb_sel; - - /* - * Mask with 0xf so similar TLB entries aren't written in the same 4-way - * entry group. - */ - local_irq_save(flags); - - for (mmu = 1; mmu <= 2; mmu++) { - SUPP_BANK_SEL(mmu); /* Select the MMU */ - for (i = 0; i < NUM_TLB_ENTRIES; i++) { - /* Store invalid entry */ - mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i); - - mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID) - | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf)); - - SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel); - SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi); - SUPP_REG_WR(RW_MM_TLB_LO, 0); - } - } - - local_irq_restore(flags); -} - -/* Flush an entire user address space. */ -void -__flush_tlb_mm(struct mm_struct *mm) -{ - int i; - int mmu; - unsigned long flags; - unsigned long page_id; - unsigned long tlb_hi; - unsigned long mmu_tlb_hi; - - page_id = mm->context.page_id; - - if (page_id == NO_CONTEXT) - return; - - /* Mark the TLB entries that match the page_id as invalid. */ - local_irq_save(flags); - - for (mmu = 1; mmu <= 2; mmu++) { - SUPP_BANK_SEL(mmu); - for (i = 0; i < NUM_TLB_ENTRIES; i++) { - UPDATE_TLB_SEL_IDX(i); - - /* Get the page_id */ - SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); - - /* Check if the page_id match. */ - if ((tlb_hi & 0xff) == page_id) { - mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, - INVALID_PAGEID) - | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, - i & 0xf)); - - UPDATE_TLB_HILO(mmu_tlb_hi, 0); - } - } - } - - local_irq_restore(flags); -} - -/* Invalidate a single page. */ -void -__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) -{ - int i; - int mmu; - unsigned long page_id; - unsigned long flags; - unsigned long tlb_hi; - unsigned long mmu_tlb_hi; - - page_id = vma->vm_mm->context.page_id; - - if (page_id == NO_CONTEXT) - return; - - addr &= PAGE_MASK; - - /* - * Invalidate those TLB entries that match both the mm context and the - * requested virtual address. - */ - local_irq_save(flags); - - for (mmu = 1; mmu <= 2; mmu++) { - SUPP_BANK_SEL(mmu); - for (i = 0; i < NUM_TLB_ENTRIES; i++) { - UPDATE_TLB_SEL_IDX(i); - SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi); - - /* Check if page_id and address matches */ - if (((tlb_hi & 0xff) == page_id) && - ((tlb_hi & PAGE_MASK) == addr)) { - mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid, - INVALID_PAGEID) | addr; - - UPDATE_TLB_HILO(mmu_tlb_hi, 0); - } - } - } - - local_irq_restore(flags); -} - -/* - * Initialize the context related info for a new mm_struct - * instance. - */ - -int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - mm->context.page_id = NO_CONTEXT; - return 0; -} - -static DEFINE_SPINLOCK(mmu_context_lock); - -/* Called in schedule() just before actually doing the switch_to. */ -void -switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - if (prev != next) { - int cpu = smp_processor_id(); - - /* Make sure there is a MMU context. */ - spin_lock(&mmu_context_lock); - get_mmu_context(next); - cpumask_set_cpu(cpu, mm_cpumask(next)); - spin_unlock(&mmu_context_lock); - - /* - * Remember the pgd for the fault handlers. Keep a separate - * copy of it because current and active_mm might be invalid - * at points where * there's still a need to derefer the pgd. - */ - per_cpu(current_pgd, cpu) = next->pgd; - - /* Switch context in the MMU. */ - if (tsk && task_thread_info(tsk)) { - SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | - task_thread_info(tsk)->tls); - } else { - SPEC_REG_WR(SPEC_REG_PID, next->context.page_id); - } - } -} - diff --git a/arch/cris/arch-v32/output_arch.ld b/arch/cris/arch-v32/output_arch.ld deleted file mode 100644 index d60a57db0ec2..000000000000 --- a/arch/cris/arch-v32/output_arch.ld +++ /dev/null @@ -1,2 +0,0 @@ -/* At the time of this writing, there's no equivalent ld option. */ -OUTPUT_ARCH (crisv32) diff --git a/arch/cris/boot/.gitignore b/arch/cris/boot/.gitignore deleted file mode 100644 index 171a0853caf8..000000000000 --- a/arch/cris/boot/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -Image -zImage diff --git a/arch/cris/boot/Makefile b/arch/cris/boot/Makefile deleted file mode 100644 index 859d275f862b..000000000000 --- a/arch/cris/boot/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/cris/boot/Makefile -# - -objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment -objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id - -OBJCOPYFLAGS = -O binary $(objcopyflags-y) - - -subdir- := compressed rescue -targets := Image - -$(obj)/Image: vmlinux FORCE - $(call if_changed,objcopy) - @echo ' Kernel: $@ is ready' - -$(obj)/compressed/vmlinux: $(obj)/Image FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed $@ - $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin - -$(obj)/zImage: $(obj)/compressed/vmlinux - @cp $< $@ - @echo ' Kernel: $@ is ready' diff --git a/arch/cris/boot/compressed/Makefile b/arch/cris/boot/compressed/Makefile deleted file mode 100644 index e149c3467c93..000000000000 --- a/arch/cris/boot/compressed/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# arch/cris/boot/compressed/Makefile -# - -# asflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/mach \ -# -I$(srctree)/include/asm/arch -# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -O2 -I$(srctree)/include/asm/mach -# -I$(srctree)/include/asm/arch - -arch-$(CONFIG_ETRAX_ARCH_V10) = v10 -arch-$(CONFIG_ETRAX_ARCH_V32) = v32 - -ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds - -OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o -OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o -OBJECTS= $(OBJECTS-y) $(obj)/misc.o -OBJCOPYFLAGS = -O binary --remove-section=.bss - -quiet_cmd_image = BUILD $@ -cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ - -targets := vmlinux piggy.gz decompress.o decompress.bin - -$(obj)/decompress.o: $(OBJECTS) FORCE - $(call if_changed,ld) - -$(obj)/decompress.bin: $(obj)/decompress.o FORCE - $(call if_changed,objcopy) - -$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE - $(call if_changed,image) - -$(obj)/piggy.gz: $(obj)/../Image FORCE - $(call if_changed,gzip) diff --git a/arch/cris/boot/compressed/README b/arch/cris/boot/compressed/README deleted file mode 100644 index 182c5d75784b..000000000000 --- a/arch/cris/boot/compressed/README +++ /dev/null @@ -1,24 +0,0 @@ -Creation of the self-extracting compressed kernel image (vmlinuz) ------------------------------------------------------------------ - -This can be slightly confusing because it's a process with many steps. - -The kernel object built by the arch/etrax100/Makefile, vmlinux, is split -by that makefile into text and data binary files, vmlinux.text and -vmlinux.data. - -Those files together with a ROM filesystem can be catted together and -burned into a flash or executed directly at the DRAM origin. - -They can also be catted together and compressed with gzip, which is what -happens in this makefile. Together they make up piggy.img. - -The decompressor is built into the file decompress.o. It is turned into -the binary file decompress.bin, which is catted together with piggy.img -into the file vmlinuz. It can be executed in an arbitrary place in flash. - -Be careful - it assumes some things about free locations in DRAM. It -assumes the DRAM starts at 0x40000000 and that it is at least 8 MB, -so it puts its code at 0x40700000, and initial stack at 0x40800000. - --Bjorn diff --git a/arch/cris/boot/compressed/decompress_v10.lds b/arch/cris/boot/compressed/decompress_v10.lds deleted file mode 100644 index d8326779dda2..000000000000 --- a/arch/cris/boot/compressed/decompress_v10.lds +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* OUTPUT_FORMAT(elf32-us-cris) */ -OUTPUT_FORMAT(elf32-cris) - -MEMORY - { - dram : ORIGIN = 0x40700000, - LENGTH = 0x00100000 - } - -SECTIONS -{ - .text : - { - _stext = . ; - *(.text) - *(.rodata) - *(.rodata.*) - _etext = . ; - } > dram - .data : - { - *(.data) - _edata = . ; - } > dram - .bss : - { - *(.bss) - _end = ALIGN( 0x10 ) ; - } > dram -} diff --git a/arch/cris/boot/compressed/decompress_v32.lds b/arch/cris/boot/compressed/decompress_v32.lds deleted file mode 100644 index 91d311c243ed..000000000000 --- a/arch/cris/boot/compressed/decompress_v32.lds +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/*#OUTPUT_FORMAT(elf32-us-cris) */ -OUTPUT_ARCH (crisv32) - -MEMORY - { - dram : ORIGIN = 0x40700000, - LENGTH = 0x00100000 - } - -SECTIONS -{ - .text : - { - _stext = . ; - *(.text) - *(.rodata) - *(.rodata.*) - _etext = . ; - } > dram - .data : - { - *(.data) - _edata = . ; - } > dram - .bss : - { - *(.bss) - _end = ALIGN( 0x10 ) ; - } > dram -} diff --git a/arch/cris/boot/compressed/head_v10.S b/arch/cris/boot/compressed/head_v10.S deleted file mode 100644 index 08198d8cd37f..000000000000 --- a/arch/cris/boot/compressed/head_v10.S +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/cris/boot/compressed/head.S - * - * Copyright (C) 1999, 2001 Axis Communications AB - * - * Code that sets up the DRAM registers, calls the - * decompressor to unpack the piggybacked kernel, and jumps. - * - */ - -#define ASSEMBLER_MACROS_ONLY -#include - -#define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 - - ;; Exported symbols - - .globl input_data - - - .text - - nop - di - -;; We need to initialze DRAM registers before we start using the DRAM - - cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? - beq dram_init_finished - nop - -#include "../../arch-v10/lib/dram_init.S" - -dram_init_finished: - - ;; Initiate the PA and PB ports - - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0 - move.b $r0, [R_PORT_PA_DATA] - - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0 - move.b $r0, [R_PORT_PA_DIR] - - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0 - move.b $r0, [R_PORT_PB_DATA] - - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0 - move.b $r0, [R_PORT_PB_DIR] - - ;; Setup the stack to a suitably high address. - ;; We assume 8 MB is the minimum DRAM in an eLinux - ;; product and put the sp at the top for now. - - move.d 0x40800000, $sp - - ;; Figure out where the compressed piggyback image is - ;; in the flash (since we wont try to copy it to DRAM - ;; before unpacking). It is at _edata, but in flash. - ;; Use (_edata - basse) as offset to the current PC. - -basse: move.d $pc, $r5 - and.d 0x7fffffff, $r5 ; strip any non-cache bit - subq 2, $r5 ; compensate for the move.d $pc instr - move.d $r5, $r0 ; save for later - flash address of 'basse' - add.d _edata, $r5 - sub.d basse, $r5 ; $r5 = flash address of '_edata' - - ;; Copy text+data to DRAM - - move.d basse, $r1 ; destination - move.d _edata, $r2 ; end destination -1: move.w [$r0+], $r3 - move.w $r3, [$r1+] - cmp.d $r2, $r1 - bcs 1b - nop - - move.d $r5, [input_data] ; for the decompressor - - - ;; Clear the decompressors BSS (between _edata and _end) - - moveq 0, $r0 - move.d _edata, $r1 - move.d _end, $r2 -1: move.w $r0, [$r1+] - cmp.d $r2, $r1 - bcs 1b - nop - - ;; Save command line magic and address. - move.d _cmd_line_magic, $r12 - move.d $r10, [$r12] - move.d _cmd_line_addr, $r12 - move.d $r11, [$r12] - - ;; Do the decompression and save compressed size in inptr - - jsr decompress_kernel - - ;; Put start address of root partition in $r9 so the kernel can use it - ;; when mounting from flash - - move.d [input_data], $r9 ; flash address of compressed kernel - add.d [inptr], $r9 ; size of compressed kernel - - ;; Restore command line magic and address. - move.d _cmd_line_magic, $r10 - move.d [$r10], $r10 - move.d _cmd_line_addr, $r11 - move.d [$r11], $r11 - - ;; Enter the decompressed kernel - move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized - jump 0x40004000 ; kernel is linked to this address - - .data - -input_data: - .dword 0 ; used by the decompressor -_cmd_line_magic: - .dword 0 -_cmd_line_addr: - .dword 0 -#include "../../arch-v10/lib/hw_settings.S" diff --git a/arch/cris/boot/compressed/head_v32.S b/arch/cris/boot/compressed/head_v32.S deleted file mode 100644 index a997947d31e3..000000000000 --- a/arch/cris/boot/compressed/head_v32.S +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Code that sets up the DRAM registers, calls the - * decompressor to unpack the piggybacked kernel, and jumps. - * - * Copyright (C) 1999 - 2006, Axis Communications AB - */ - -#define ASSEMBLER_MACROS_ONLY -#include -#include - -#define RAM_INIT_MAGIC 0x56902387 -#define COMMAND_LINE_MAGIC 0x87109563 - - ;; Exported symbols - - .globl input_data - - .text -start: - di - - ;; Start clocks for used blocks. - START_CLOCKS - - ;; Initialize the DRAM registers. - cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized? - beq dram_init_finished - nop - -#if defined CONFIG_ETRAXFS -#include "../../arch-v32/mach-fs/dram_init.S" -#elif defined CONFIG_CRIS_MACH_ARTPEC3 -#include "../../arch-v32/mach-a3/dram_init.S" -#else -#error Only ETRAXFS and ARTPEC-3 supported! -#endif - -dram_init_finished: - - GIO_INIT - ;; Setup the stack to a suitably high address. - ;; We assume 8 MB is the minimum DRAM and put - ;; the SP at the top for now. - - move.d 0x40800000, $sp - - ;; Figure out where the compressed piggyback image is. - ;; It is either in [NOR] flash (we don't want to copy it - ;; to DRAM before unpacking), or copied to DRAM - ;; by the [NAND] flash boot loader. - ;; The piggyback image is at _edata, but relative to where the - ;; image is actually located in memory, not where it is linked - ;; (the decompressor is linked at 0x40700000+ and runs there). - ;; Use (_edata - herami) as offset to the current PC. - -hereami: - lapcq ., $r5 ; get PC - and.d 0x7fffffff, $r5 ; strip any non-cache bit - move.d $r5, $r0 ; source address of 'herami' - add.d _edata, $r5 - sub.d hereami, $r5 ; r5 = flash address of '_edata' - move.d hereami, $r1 ; destination - - ;; Copy text+data to DRAM - - move.d _edata, $r2 ; end destination -1: move.w [$r0+], $r3 ; from herami+ source - move.w $r3, [$r1+] ; to hereami+ destination (linked address) - cmp.d $r2, $r1 ; finish when destination == _edata - bcs 1b - nop - move.d input_data, $r0 ; for the decompressor - move.d $r5, [$r0] ; for the decompressor - - ;; Clear the decompressors BSS (between _edata and _end) - - moveq 0, $r0 - move.d _edata, $r1 - move.d _end, $r2 -1: move.w $r0, [$r1+] - cmp.d $r2, $r1 - bcs 1b - nop - - ;; Save command line magic and address. - move.d _cmd_line_magic, $r0 - move.d $r10, [$r0] - move.d _cmd_line_addr, $r0 - move.d $r11, [$r0] - - ;; Save boot source indicator - move.d _boot_source, $r0 - move.d $r12, [$r0] - - ;; Do the decompression and save compressed size in _inptr - - jsr decompress_kernel - nop - - ;; Restore boot source indicator - move.d _boot_source, $r12 - move.d [$r12], $r12 - - ;; Restore command line magic and address. - move.d _cmd_line_magic, $r10 - move.d [$r10], $r10 - move.d _cmd_line_addr, $r11 - move.d [$r11], $r11 - - ;; Put start address of root partition in r9 so the kernel can use it - ;; when mounting from flash - move.d input_data, $r0 - move.d [$r0], $r9 ; flash address of compressed kernel - move.d inptr, $r0 - add.d [$r0], $r9 ; size of compressed kernel - cmp.d 0x40000000, $r9 ; image in DRAM ? - blo enter_kernel ; no, must be [NOR] flash, jump - nop ; delay slot - and.d 0x001fffff, $r9 ; assume compressed kernel was < 2M - -enter_kernel: - ;; Enter the decompressed kernel - move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized - jump 0x40004000 ; kernel is linked to this address - nop - - .data - -input_data: - .dword 0 ; used by the decompressor -_cmd_line_magic: - .dword 0 -_cmd_line_addr: - .dword 0 -_boot_source: - .dword 0 - -#if defined CONFIG_ETRAXFS -#include "../../arch-v32/mach-fs/hw_settings.S" -#elif defined CONFIG_CRIS_MACH_ARTPEC3 -#include "../../arch-v32/mach-a3/hw_settings.S" -#else -#error Only ETRAXFS and ARTPEC-3 supported! -#endif diff --git a/arch/cris/boot/compressed/misc.c b/arch/cris/boot/compressed/misc.c deleted file mode 100644 index 1ad464a117b8..000000000000 --- a/arch/cris/boot/compressed/misc.c +++ /dev/null @@ -1,377 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * misc.c - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * puts by Nick Holloway 1993, better puts by Martin Mares 1995 - * adaptation for Linux/CRIS Axis Communications AB, 1999 - * - */ - -/* where the piggybacked kernel image expects itself to live. - * it is the same address we use when we network load an uncompressed - * image into DRAM, and it is the address the kernel is linked to live - * at by vmlinux.lds.S - */ - -#define KERNEL_LOAD_ADR 0x40004000 - -#include - -#ifdef CONFIG_ETRAX_ARCH_V32 -#include -#include -#include -#include -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -#include -#endif -#else -#include -#endif - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -void *memset(void *s, int c, size_t n); -void *memcpy(void *__dest, __const void *__src, size_t __n); - -#define memzero(s, n) memset((s), 0, (n)) - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, */ - /* and a power of two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* Sliding window buffer */ - -unsigned inptr = 0; /* index of next byte to be processed in inbuf - * After decompression it will contain the - * compressed size, and head.S will read it. - */ - -static unsigned outcnt = 0; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -#define get_byte() (inbuf[inptr++]) - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond, msg) do { \ - if (!(cond)) \ - error(msg); \ - } while (0) -# define Trace(x) fprintf x -# define Tracev(x) do { \ - if (verbose) \ - fprintf x; \ - } while (0) -# define Tracevv(x) do { \ - if (verbose > 1) \ - fprintf x; \ - } while (0) -# define Tracec(c, x) do { \ - if (verbose && (c)) \ - fprintf x; \ - } while (0) -# define Tracecv(c, x) do { \ - if (verbose > 1 && (c)) \ - fprintf x; \ - } while (0) -#else -# define Assert(cond, msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c, x) -# define Tracecv(c, x) -#endif - -static void flush_window(void); -static void error(char *m); -static void aputs(const char *s); - -extern char *input_data; /* lives in head.S */ - -static long bytes_out; -static uch *output_data; -static unsigned long output_ptr; - -/* the "heap" is put directly after the BSS ends, at end */ - -extern int _end; -static long free_mem_ptr = (long)&_end; -static long free_mem_end_ptr; - -#include "../../../../../lib/inflate.c" - -/* decompressor info and error messages to serial console */ - -#ifdef CONFIG_ETRAX_ARCH_V32 -static inline void serout(const char *s, reg_scope_instances regi_ser) -{ - reg_ser_rs_stat_din rs; - reg_ser_rw_dout dout = {.data = *s}; - - do { - rs = REG_RD(ser, regi_ser, rs_stat_din); - } - while (!rs.tr_rdy);/* Wait for transceiver. */ - - REG_WR(ser, regi_ser, rw_dout, dout); -} -#define SEROUT(S, N) \ - do { \ - serout(S, regi_ser ## N); \ - s++; \ - } while (0) -#else -#define SEROUT(S, N) do { \ - while (!(*R_SERIAL ## N ## _STATUS & (1 << 5))) \ - ; \ - *R_SERIAL ## N ## _TR_DATA = *s++; \ - } while (0) -#endif - -static void aputs(const char *s) -{ -#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL - while (*s) { -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - SEROUT(s, 0); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - SEROUT(s, 1); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - SEROUT(s, 2); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - SEROUT(s, 3); -#endif - } -#endif /* CONFIG_ETRAX_DEBUG_PORT_NULL */ -} - -void *memset(void *s, int c, size_t n) -{ - int i; - char *ss = (char*)s; - - for (i=0;i> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -} - -static void error(char *x) -{ - aputs("\n\n"); - aputs(x); - aputs("\n\n -- System halted\n"); - - while(1); /* Halt */ -} - -void setup_normal_output_buffer(void) -{ - output_data = (char *)KERNEL_LOAD_ADR; -} - -#ifdef CONFIG_ETRAX_ARCH_V32 -static inline void serial_setup(reg_scope_instances regi_ser) -{ - reg_ser_rw_xoff xoff; - reg_ser_rw_tr_ctrl tr_ctrl; - reg_ser_rw_rec_ctrl rec_ctrl; - reg_ser_rw_tr_baud_div tr_baud; - reg_ser_rw_rec_baud_div rec_baud; - - /* Turn off XOFF. */ - xoff = REG_RD(ser, regi_ser, rw_xoff); - - xoff.chr = 0; - xoff.automatic = regk_ser_no; - - REG_WR(ser, regi_ser, rw_xoff, xoff); - - /* Set baudrate and stopbits. */ - tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); - rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); - tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div); - rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div); - - tr_ctrl.stop_bits = 1; /* 2 stop bits. */ - tr_ctrl.en = 1; /* enable transmitter */ - rec_ctrl.en = 1; /* enabler receiver */ - - /* - * The baudrate setup used to be a bit fishy, but now transmitter and - * receiver are both set to the intended baud rate, 115200. - * The magic value is 29.493 MHz. - */ - tr_ctrl.base_freq = regk_ser_f29_493; - rec_ctrl.base_freq = regk_ser_f29_493; - tr_baud.div = (29493000 / 8) / 115200; - rec_baud.div = (29493000 / 8) / 115200; - - REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); - REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); - REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); - REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); -} -#endif - -void decompress_kernel(void) -{ - char revision; - char compile_rev; - -#ifdef CONFIG_ETRAX_ARCH_V32 - /* Need at least a CRISv32 to run. */ - compile_rev = 32; -#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \ - defined(CONFIG_ETRAX_DEBUG_PORT2) || \ - defined(CONFIG_ETRAX_DEBUG_PORT3) - reg_pinmux_rw_hwprot hwprot; - -#ifdef CONFIG_CRIS_MACH_ARTPEC3 - reg_clkgen_rw_clk_ctrl clk_ctrl; - - /* Enable corresponding clock region when serial 1..3 selected */ - - clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl); - clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes; - REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); -#endif - - /* pinmux setup for ports 1..3 */ - hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot); -#endif - - -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - serial_setup(regi_ser0); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - hwprot.ser1 = regk_pinmux_yes; - serial_setup(regi_ser1); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - hwprot.ser2 = regk_pinmux_yes; - serial_setup(regi_ser2); -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - hwprot.ser3 = regk_pinmux_yes; - serial_setup(regi_ser3); -#endif -#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \ - defined(CONFIG_ETRAX_DEBUG_PORT2) || \ - defined(CONFIG_ETRAX_DEBUG_PORT3) - REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); -#endif - - /* input_data is set in head.S */ - inbuf = input_data; -#else /* CRISv10 */ - /* Need at least a crisv10 to run. */ - compile_rev = 10; - - /* input_data is set in head.S */ - inbuf = input_data; - -#ifdef CONFIG_ETRAX_DEBUG_PORT0 - *R_SERIAL0_XOFF = 0; - *R_SERIAL0_BAUD = 0x99; - *R_SERIAL0_TR_CTRL = 0x40; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT1 - *R_SERIAL1_XOFF = 0; - *R_SERIAL1_BAUD = 0x99; - *R_SERIAL1_TR_CTRL = 0x40; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT2 - *R_GEN_CONFIG = 0x08; - *R_SERIAL2_XOFF = 0; - *R_SERIAL2_BAUD = 0x99; - *R_SERIAL2_TR_CTRL = 0x40; -#endif -#ifdef CONFIG_ETRAX_DEBUG_PORT3 - *R_GEN_CONFIG = 0x100; - *R_SERIAL3_XOFF = 0; - *R_SERIAL3_BAUD = 0x99; - *R_SERIAL3_TR_CTRL = 0x40; -#endif -#endif - - setup_normal_output_buffer(); - - makecrc(); - - __asm__ volatile ("move $vr,%0" : "=rm" (revision)); - if (revision < compile_rev) { -#ifdef CONFIG_ETRAX_ARCH_V32 - aputs("You need at least ETRAX FS to run Linux 2.6/crisv32\n"); -#else - aputs("You need an ETRAX 100LX to run linux 2.6/crisv10\n"); -#endif - while(1); - } - - aputs("Uncompressing Linux...\n"); - gunzip(); - aputs("Done. Now booting the kernel\n"); -} diff --git a/arch/cris/boot/dts/Makefile b/arch/cris/boot/dts/Makefile deleted file mode 100644 index 118fe990a173..000000000000 --- a/arch/cris/boot/dts/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o -ifneq ($(CONFIG_BUILTIN_DTB),"") -obj-$(CONFIG_OF) += $(BUILTIN_DTB) -endif diff --git a/arch/cris/boot/dts/artpec3.dtsi b/arch/cris/boot/dts/artpec3.dtsi deleted file mode 100644 index f857300f4edd..000000000000 --- a/arch/cris/boot/dts/artpec3.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - model = "axis,crisv32"; - reg = <0>; - }; - }; - - soc { - compatible = "simple-bus"; - model = "artpec3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - intc: interrupt-controller { - compatible = "axis,crisv32-intc"; - reg = <0xb002a000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gio: gpio@b0020000 { - compatible = "axis,artpec3-gio"; - reg = <0xb0020000 0x1000>; - interrupts = <61>; - gpio-controller; - #gpio-cells = <3>; - }; - - serial@b003e000 { - compatible = "axis,etraxfs-uart"; - reg = <0xb003e000 0x1000>; - interrupts = <64>; - status = "disabled"; - }; - }; -}; diff --git a/arch/cris/boot/dts/dev88.dts b/arch/cris/boot/dts/dev88.dts deleted file mode 100644 index 415270ea5309..000000000000 --- a/arch/cris/boot/dts/dev88.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include - -/include/ "etraxfs.dtsi" - -/ { - model = "Axis 88 Developer Board"; - compatible = "axis,dev88"; - - aliases { - serial0 = &uart0; - }; - - soc { - uart0: serial@b00260000 { - status = "okay"; - }; - }; - - spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - gpio-sck = <&gio 1 0 0xd>; - gpio-miso = <&gio 4 0 0xd>; - gpio-mosi = <&gio 0 0 0xd>; - cs-gpios = <&gio 3 0 0xd>; - num-chipselects = <1>; - - temp-sensor@0 { - compatible = "ti,lm70"; - reg = <0>; - - spi-max-frequency = <100000>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - gpios = <&gio 5 0 0xd>, <&gio 6 0 0xd>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - leds { - compatible = "gpio-leds"; - - network { - label = "network"; - gpios = <&gio 2 GPIO_ACTIVE_LOW 0xa>; - }; - - status { - label = "status"; - gpios = <&gio 3 GPIO_ACTIVE_LOW 0xa>; - linux,default-trigger = "heartbeat"; - }; - }; -}; diff --git a/arch/cris/boot/dts/etraxfs.dtsi b/arch/cris/boot/dts/etraxfs.dtsi deleted file mode 100644 index 4513edf72545..000000000000 --- a/arch/cris/boot/dts/etraxfs.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - model = "axis,crisv32"; - reg = <0>; - }; - }; - - soc { - compatible = "simple-bus"; - model = "etraxfs"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - intc: interrupt-controller { - compatible = "axis,crisv32-intc"; - reg = <0xb001c000 0x1000>; - interrupt-controller; - #interrupt-cells = <1>; - }; - - gio: gpio@b001a000 { - compatible = "axis,etraxfs-gio"; - reg = <0xb001a000 0x1000>; - interrupts = <50>; - gpio-controller; - #gpio-cells = <3>; - }; - - serial@b00260000 { - compatible = "axis,etraxfs-uart"; - reg = <0xb0026000 0x1000>; - interrupts = <68>; - status = "disabled"; - }; - }; -}; diff --git a/arch/cris/boot/dts/p1343.dts b/arch/cris/boot/dts/p1343.dts deleted file mode 100644 index 6030561d4574..000000000000 --- a/arch/cris/boot/dts/p1343.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include - -/include/ "artpec3.dtsi" - -/ { - model = "Axis P1343 Network Camera"; - compatible = "axis,p1343"; - - aliases { - serial0 = &uart0; - }; - - soc { - uart0: serial@b003e000 { - status = "okay"; - }; - }; - - i2c { - compatible = "i2c-gpio"; - gpios = <&gio 3 0 0xa>, <&gio 2 0 0xa>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - }; - - leds { - compatible = "gpio-leds"; - - status_green { - label = "status:green"; - gpios = <&gio 0 GPIO_ACTIVE_LOW 0xc>; - linux,default-trigger = "heartbeat"; - }; - - status_red { - label = "status:red"; - gpios = <&gio 1 GPIO_ACTIVE_LOW 0xc>; - }; - - network_green { - label = "network:green"; - gpios = <&gio 2 GPIO_ACTIVE_LOW 0xc>; - }; - - network_red { - label = "network:red"; - gpios = <&gio 3 GPIO_ACTIVE_LOW 0xc>; - }; - - power_red { - label = "power:red"; - gpios = <&gio 4 GPIO_ACTIVE_LOW 0xc>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - activity-button@0 { - label = "Activity Button"; - linux,code = ; - gpios = <&gio 13 GPIO_ACTIVE_LOW 0xd>; - }; - }; -}; diff --git a/arch/cris/boot/rescue/Makefile b/arch/cris/boot/rescue/Makefile deleted file mode 100644 index f73ac4c83b96..000000000000 --- a/arch/cris/boot/rescue/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for rescue (bootstrap) code -# - -# CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE) -# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/arch/mach/ \ -# -I$(srctree)/include/asm/arch -# asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch -# LD = gcc-cris -mlinux -march=v32 -nostdlib - -ifdef CONFIG_ETRAX_AXISFLASHMAP - -arch-$(CONFIG_ETRAX_ARCH_V10) = v10 -arch-$(CONFIG_ETRAX_ARCH_V32) = v32 - -ldflags-y += -T $(srctree)/$(src)/rescue_$(arch-y).lds -OBJCOPYFLAGS = -O binary --remove-section=.bss -obj-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o -obj-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o -OBJECTS := $(obj-y) - -targets := rescue.o rescue.bin - -$(obj)/rescue.o: $(OBJECTS) FORCE - $(call if_changed,ld) - -$(obj)/rescue.bin: $(obj)/rescue.o FORCE - $(call if_changed,objcopy) - cp -p $(obj)/rescue.bin $(objtree) - -else -$(obj)/rescue.bin: - -endif - -$(obj)/testrescue.bin: $(obj)/testrescue.o - $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/testrescue.o tr.bin -# Pad it to 784 bytes - dd if=/dev/zero of=tmp2423 bs=1 count=784 - cat tr.bin tmp2423 >testrescue_tmp.bin - dd if=testrescue_tmp.bin of=$(obj)/testrescue.bin bs=1 count=784 - rm tr.bin tmp2423 testrescue_tmp.bin - - -$(obj)/kimagerescue.bin: $(obj)/kimagerescue.o - $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/kimagerescue.o ktr.bin -# Pad it to 784 bytes, that's what the rescue loader expects - dd if=/dev/zero of=tmp2423 bs=1 count=784 - cat ktr.bin tmp2423 >kimagerescue_tmp.bin - dd if=kimagerescue_tmp.bin of=$(obj)/kimagerescue.bin bs=1 count=784 - rm ktr.bin tmp2423 kimagerescue_tmp.bin - diff --git a/arch/cris/boot/rescue/head_v10.S b/arch/cris/boot/rescue/head_v10.S deleted file mode 100644 index 11eedb1bf31a..000000000000 --- a/arch/cris/boot/rescue/head_v10.S +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Rescue code, made to reside at the beginning of the - * flash-memory. when it starts, it checks a partition - * table at the first sector after the rescue sector. - * the partition table was generated by the product builder - * script and contains offsets, lengths, types and checksums - * for each partition that this code should check. - * - * If any of the checksums fail, we assume the flash is so - * corrupt that we can't use it to boot into the ftp flash - * loader, and instead we initialize the serial port to - * receive a flash-loader and new flash image. we dont include - * any flash code here, but just accept a certain amount of - * bytes from the serial port and jump into it. the downloaded - * code is put in the cache. - * - * The partitiontable is designed so that it is transparent to - * code execution - it has a relative branch opcode in the - * beginning that jumps over it. each entry contains extra - * data so we can add stuff later. - * - * Partition table format: - * - * Code transparency: - * - * 2 bytes [opcode 'nop'] - * 2 bytes [opcode 'di'] - * 4 bytes [opcode 'ba ', 8-bit or 16-bit version] - * 2 bytes [opcode 'nop', delay slot] - * - * Table validation (at +10): - * - * 2 bytes [magic/version word for partitiontable - 0xef, 0xbe] - * 2 bytes [length of all entries plus the end marker] - * 4 bytes [checksum for the partitiontable itself] - * - * Entries, each with the following format, last has offset -1: - * - * 4 bytes [offset in bytes, from start of flash] - * 4 bytes [length in bytes of partition] - * 4 bytes [checksum, simple longword sum] - * 2 bytes [partition type] - * 2 bytes [flags, only bit 0 used, ro/rw = 1/0] - * 16 bytes [reserved for future use] - * - * End marker - * - * 4 bytes [-1] - * - * 10 bytes [0, padding] - * - * Bit 0 in flags signifies RW or RO. The rescue code only bothers - * to check the checksum for RO partitions, since the others will - * change their data without updating the checksums. A 1 in bit 0 - * means RO, 0 means RW. That way, it is possible to set a partition - * in RO mode initially, and later mark it as RW, since you can always - * write 0's to the flash. - * - * During the wait for serial input, the status LED will flash so the - * user knows something went wrong. - * - * Copyright (C) 1999-2007 Axis Communications AB - */ - -#ifdef CONFIG_ETRAX_AXISFLASHMAP - -#define ASSEMBLER_MACROS_ONLY -#include - - ;; The partitiontable is looked for at the first sector after the boot - ;; sector. Sector size is 65536 bytes in all flashes we use. - -#define PTABLE_START CONFIG_ETRAX_PTABLE_SECTOR -#define PTABLE_MAGIC 0xbeef - - ;; The normal Etrax100 on-chip boot ROM does serial boot at 0x380000f0. - ;; That is not where we put our downloaded serial boot-code. - ;; The length is enough for downloading code that loads the rest - ;; of itself (after having setup the DRAM etc). - ;; It is the same length as the on-chip ROM loads, so the same - ;; host loader can be used to load a rescued product as well as - ;; one booted through the Etrax serial boot code. - -#define CODE_START 0x40000000 -#define CODE_LENGTH 784 - -#ifdef CONFIG_ETRAX_RESCUE_SER0 -#define SERXOFF R_SERIAL0_XOFF -#define SERBAUD R_SERIAL0_BAUD -#define SERRECC R_SERIAL0_REC_CTRL -#define SERRDAT R_SERIAL0_REC_DATA -#define SERSTAT R_SERIAL0_STATUS -#endif -#ifdef CONFIG_ETRAX_RESCUE_SER1 -#define SERXOFF R_SERIAL1_XOFF -#define SERBAUD R_SERIAL1_BAUD -#define SERRECC R_SERIAL1_REC_CTRL -#define SERRDAT R_SERIAL1_REC_DATA -#define SERSTAT R_SERIAL1_STATUS -#endif -#ifdef CONFIG_ETRAX_RESCUE_SER2 -#define SERXOFF R_SERIAL2_XOFF -#define SERBAUD R_SERIAL2_BAUD -#define SERRECC R_SERIAL2_REC_CTRL -#define SERRDAT R_SERIAL2_REC_DATA -#define SERSTAT R_SERIAL2_STATUS -#endif -#ifdef CONFIG_ETRAX_RESCUE_SER3 -#define SERXOFF R_SERIAL3_XOFF -#define SERBAUD R_SERIAL3_BAUD -#define SERRECC R_SERIAL3_REC_CTRL -#define SERRDAT R_SERIAL3_REC_DATA -#define SERSTAT R_SERIAL3_STATUS -#endif - -#define NOP_DI 0xf025050f -#define RAM_INIT_MAGIC 0x56902387 - - .text - - ;; This is the entry point of the rescue code - ;; 0x80000000 if loaded in flash (as it should be) - ;; Since etrax actually starts at address 2 when booting from flash, we - ;; put a nop (2 bytes) here first so we dont accidentally skip the di - - nop - di - - jump in_cache ; enter cached area instead -in_cache: - - - ;; First put a jump test to give a possibility of upgrading the - ;; rescue code without erasing/reflashing the sector. - ;; We put a longword of -1 here and if it is not -1, we jump using - ;; the value as jump target. Since we can always change 1's to 0's - ;; without erasing the sector, it is possible to add new - ;; code after this and altering the jumptarget in an upgrade. - -jtcd: move.d [jumptarget], $r0 - cmp.d 0xffffffff, $r0 - beq no_newjump - nop - - jump [$r0] - -jumptarget: - .dword 0xffffffff ; can be overwritten later to insert new code - -no_newjump: -#ifdef CONFIG_ETRAX_ETHERNET - ;; Start MII clock to make sure it is running when tranceiver is reset - move.d 0x3, $r0 ; enable = on, phy = mii_clk - move.d $r0, [R_NETWORK_GEN_CONFIG] -#endif - - ;; We need to setup the bus registers before we start using the DRAM -#include "../../../arch-v10/lib/dram_init.S" - - ;; we now should go through the checksum-table and check the listed - ;; partitions for errors. - - move.d PTABLE_START, $r3 - move.d [$r3], $r0 - cmp.d NOP_DI, $r0 ; make sure the nop/di is there... - bne do_rescue - nop - - ;; skip the code transparency block (10 bytes). - - addq 10, $r3 - - ;; check for correct magic - - move.w [$r3+], $r0 - cmp.w PTABLE_MAGIC, $r0 - bne do_rescue ; didn't recognize - trig rescue - nop - - ;; check for correct ptable checksum - - movu.w [$r3+], $r2 ; ptable length - move.d $r2, $r8 ; save for later, length of total ptable - addq 28, $r8 ; account for the rest - move.d [$r3+], $r4 ; ptable checksum - move.d $r3, $r1 - jsr checksum ; r1 source, r2 length, returns in r0 - - cmp.d $r0, $r4 - bne do_rescue ; didn't match - trig rescue - nop - - ;; ptable is ok. validate each entry. - - moveq -1, $r7 - -ploop: move.d [$r3+], $r1 ; partition offset (from ptable start) - bne notfirst ; check if it is the partition containing ptable - nop ; yes.. - move.d $r8, $r1 ; for its checksum check, skip the ptable - move.d [$r3+], $r2 ; partition length - sub.d $r8, $r2 ; minus the ptable length - ba bosse - nop -notfirst: - cmp.d -1, $r1 ; the end of the ptable ? - beq flash_ok ; if so, the flash is validated - move.d [$r3+], $r2 ; partition length -bosse: move.d [$r3+], $r5 ; checksum - move.d [$r3+], $r4 ; type and flags - addq 16, $r3 ; skip the reserved bytes - btstq 16, $r4 ; check ro flag - bpl ploop ; rw partition, skip validation - nop - btstq 17, $r4 ; check bootable flag - bpl 1f - nop - move.d $r1, $r7 ; remember boot partition offset -1: - add.d PTABLE_START, $r1 - - jsr checksum ; checksum the partition - - cmp.d $r0, $r5 - beq ploop ; checksums matched, go to next entry - nop - - ;; otherwise fall through to the rescue code. - -do_rescue: - ;; setup port PA and PB default initial directions and data - ;; (so we can flash LEDs, and so that DTR and others are set) - - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0 - move.b $r0, [R_PORT_PA_DIR] - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0 - move.b $r0, [R_PORT_PA_DATA] - - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0 - move.b $r0, [R_PORT_PB_DIR] - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0 - move.b $r0, [R_PORT_PB_DATA] - - ;; setup the serial port at 115200 baud - - moveq 0, $r0 - move.d $r0, [SERXOFF] - - move.b 0x99, $r0 - move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive - - move.b 0x40, $r0 ; rec enable - move.b $r0, [SERRECC] - - moveq 0, $r1 ; "timer" to clock out a LED red flash - move.d CODE_START, $r3 ; destination counter - movu.w CODE_LENGTH, $r4; length - -wait_ser: - addq 1, $r1 -#ifndef CONFIG_ETRAX_NO_LEDS -#ifdef CONFIG_ETRAX_PA_LEDS - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2 -#endif -#ifdef CONFIG_ETRAX_PB_LEDS - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2 -#endif - move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0 - btstq 16, $r1 - bpl 1f - nop - or.d $r0, $r2 ; set bit - ba 2f - nop -1: not $r0 ; clear bit - and.d $r0, $r2 -2: -#ifdef CONFIG_ETRAX_PA_LEDS - move.b $r2, [R_PORT_PA_DATA] -#endif -#ifdef CONFIG_ETRAX_PB_LEDS - move.b $r2, [R_PORT_PB_DATA] -#endif -#endif - - ;; check if we got something on the serial port - - move.b [SERSTAT], $r0 - btstq 0, $r0 ; data_avail - bpl wait_ser - nop - - ;; got something - copy the byte and loop - - move.b [SERRDAT], $r0 - move.b $r0, [$r3+] - - subq 1, $r4 ; decrease length - bne wait_ser - nop - - ;; jump into downloaded code - - move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is - ; initialized - jump CODE_START - -flash_ok: - ;; check r7, which contains either -1 or the partition to boot from - - cmp.d -1, $r7 - bne 1f - nop - move.d PTABLE_START, $r7; otherwise use the ptable start -1: - move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is - ; initialized - jump $r7 ; boot! - - - ;; Helper subroutines - - ;; Will checksum by simple addition - ;; r1 - source - ;; r2 - length in bytes - ;; result will be in r0 -checksum: - moveq 0, $r0 - moveq CONFIG_ETRAX_FLASH1_SIZE, $r6 - - ;; If the first physical flash memory is exceeded wrap to the - ;; second one - btstq 26, $r1 ; Are we addressing first flash? - bpl 1f - nop - clear.d $r6 - -1: test.d $r6 ; 0 = no wrapping - beq 2f - nop - lslq 20, $r6 ; Convert MB to bytes - sub.d $r1, $r6 - -2: addu.b [$r1+], $r0 - subq 1, $r6 ; Flash memory left - beq 3f - subq 1, $r2 ; Length left - bne 2b - nop - ret - nop - -3: move.d MEM_CSE1_START, $r1 ; wrap to second flash - ba 2b - nop - -#endif diff --git a/arch/cris/boot/rescue/head_v32.S b/arch/cris/boot/rescue/head_v32.S deleted file mode 100644 index 9eb04abaa0c0..000000000000 --- a/arch/cris/boot/rescue/head_v32.S +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Just get started by jumping to CONFIG_ETRAX_PTABLE_SECTOR to start - * kernel decompressor. - * - * In practice, this only works for NOR flash (or some convoluted RAM boot) - * and hence is not really useful for Artpec-3, so it's Etrax FS / NOR only. - * - */ - -#include - -#ifdef CONFIG_ETRAX_AXISFLASHMAP - -;; Code - - .text -start: - - ;; Start clocks for used blocks. - START_CLOCKS - - move.d CONFIG_ETRAX_PTABLE_SECTOR, $r10 - jump $r10 ; Jump to decompressor - nop - -#endif diff --git a/arch/cris/boot/rescue/kimagerescue.S b/arch/cris/boot/rescue/kimagerescue.S deleted file mode 100644 index 3306098dee15..000000000000 --- a/arch/cris/boot/rescue/kimagerescue.S +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Rescue code to be prepended on a kimage and copied to the - * rescue serial port. - * This is called from the rescue code, it will copy received data to - * 4004000 and after a timeout jump to it. - */ - -#define ASSEMBLER_MACROS_ONLY -#include - -#define CODE_START 0x40004000 -#define CODE_LENGTH 784 -#define TIMEOUT_VALUE 1000 - - -#ifdef CONFIG_ETRAX_RESCUE_SER0 -#define SERXOFF R_SERIAL0_XOFF -#define SERBAUD R_SERIAL0_BAUD -#define SERRECC R_SERIAL0_REC_CTRL -#define SERRDAT R_SERIAL0_REC_DATA -#define SERSTAT R_SERIAL0_STATUS -#endif -#ifdef CONFIG_ETRAX_RESCUE_SER1 -#define SERXOFF R_SERIAL1_XOFF -#define SERBAUD R_SERIAL1_BAUD -#define SERRECC R_SERIAL1_REC_CTRL -#define SERRDAT R_SERIAL1_REC_DATA -#define SERSTAT R_SERIAL1_STATUS -#endif -#ifdef CONFIG_ETRAX_RESCUE_SER2 -#define SERXOFF R_SERIAL2_XOFF -#define SERBAUD R_SERIAL2_BAUD -#define SERRECC R_SERIAL2_REC_CTRL -#define SERRDAT R_SERIAL2_REC_DATA -#define SERSTAT R_SERIAL2_STATUS -#endif -#ifdef CONFIG_ETRAX_RESCUE_SER3 -#define SERXOFF R_SERIAL3_XOFF -#define SERBAUD R_SERIAL3_BAUD -#define SERRECC R_SERIAL3_REC_CTRL -#define SERRDAT R_SERIAL3_REC_DATA -#define SERSTAT R_SERIAL3_STATUS -#endif - - .text - ;; This is the entry point of the rescue code - ;; 0x80000000 if loaded in flash (as it should be) - ;; since etrax actually starts at address 2 when booting from flash, we - ;; put a nop (2 bytes) here first so we dont accidentally skip the di - - nop - di - ;; setup port PA and PB default initial directions and data - ;; (so we can flash LEDs, and so that DTR and others are set) - - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0 - move.b $r0, [R_PORT_PA_DIR] - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0 - move.b $r0, [R_PORT_PA_DATA] - - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0 - move.b $r0, [R_PORT_PB_DIR] - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0 - move.b $r0, [R_PORT_PB_DATA] - - ;; We need to setup the bus registers before we start using the DRAM -#include "../../lib/dram_init.S" - - ;; Setup the stack to a suitably high address. - ;; We assume 8 MB is the minimum DRAM in an eLinux - ;; product and put the sp at the top for now. - - move.d 0x40800000, $sp - - ;; setup the serial port at 115200 baud - - moveq 0, $r0 - move.d $r0, [SERXOFF] - - move.b 0x99, $r0 - move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit - ; and receive - - move.b 0x40, $r0 ; rec enable - move.b $r0, [SERRECC] - - - moveq 0, $r1 ; "timer" to clock out a LED red flash - move.d CODE_START, $r3 ; destination counter - move.d CODE_LENGTH, $r4 ; length - move.d TIMEOUT_VALUE, $r5 ; "timeout" until jump - -wait_ser: - addq 1, $r1 - subq 1, $r5 ; decrease timeout - beq jump_start ; timed out - nop -#ifndef CONFIG_ETRAX_NO_LEDS -#ifdef CONFIG_ETRAX_PA_LEDS - move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2 -#endif -#ifdef CONFIG_ETRAX_PB_LEDS - move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2 -#endif - move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0 - btstq 16, $r1 - bpl 1f - nop - or.d $r0, $r2 ; set bit - ba 2f - nop -1: not $r0 ; clear bit - and.d $r0, $r2 -2: -#ifdef CONFIG_ETRAX_PA_LEDS - move.b $r2, [R_PORT_PA_DATA] -#endif -#ifdef CONFIG_ETRAX_PB_LEDS - move.b $r2, [R_PORT_PB_DATA] -#endif -#endif - - ;; check if we got something on the serial port - - move.b [SERSTAT], $r0 - btstq 0, $r0 ; data_avail - bpl wait_ser - nop - - ;; got something - copy the byte and loop - - move.b [SERRDAT], $r0 - move.b $r0, [$r3+] - move.d TIMEOUT_VALUE, $r5 ; reset "timeout" - subq 1, $r4 ; decrease length - bne wait_ser - nop -jump_start: - ;; jump into downloaded code - - jump CODE_START diff --git a/arch/cris/boot/rescue/rescue_v10.lds b/arch/cris/boot/rescue/rescue_v10.lds deleted file mode 100644 index e58a53f91728..000000000000 --- a/arch/cris/boot/rescue/rescue_v10.lds +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -MEMORY - { - flash : ORIGIN = 0x00000000, - LENGTH = 0x00100000 - } - -SECTIONS -{ - .text : - { - stext = . ; - *(.text) - etext = . ; - } > flash - .data : - { - *(.data) - edata = . ; - } > flash -} diff --git a/arch/cris/boot/rescue/rescue_v32.lds b/arch/cris/boot/rescue/rescue_v32.lds deleted file mode 100644 index f1542183f263..000000000000 --- a/arch/cris/boot/rescue/rescue_v32.lds +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/*#OUTPUT_FORMAT(elf32-us-cris) */ -OUTPUT_ARCH (crisv32) -/* Now that NAND support has been stripped, this file could be simplified, - * but it doesn't do any harm on the other hand so why bother. */ - -MEMORY - { - bootblk : ORIGIN = 0x38000000, - LENGTH = 0x00004000 - intmem : ORIGIN = 0x38004000, - LENGTH = 0x00005000 - } - -SECTIONS -{ - .text : - { - _stext = . ; - *(.text) - *(.init.text) - *(.rodata) - *(.rodata.*) - _etext = . ; - } > bootblk - .data : - { - *(.data) - _edata = . ; - } > bootblk - .bss : - { - _bss = . ; - *(.bss) - _end = ALIGN( 0x10 ) ; - } > intmem - - /* Get rid of stuff from EXPORT_SYMBOL(foo). */ - /DISCARD/ : - { - *(__ksymtab_strings) - *(__ksymtab) - } -} diff --git a/arch/cris/boot/rescue/testrescue.S b/arch/cris/boot/rescue/testrescue.S deleted file mode 100644 index 06f78a0b0622..000000000000 --- a/arch/cris/boot/rescue/testrescue.S +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Simple testcode to download by the rescue block. - * Just lights some LEDs to show it was downloaded correctly. - * - * Copyright (C) 1999 Axis Communications AB - */ - -#define ASSEMBLER_MACROS_ONLY -#include - - .text - - nop - nop - moveq -1, $r2 - move.b $r2, [R_PORT_PA_DIR] - moveq 0, $r2 - move.b $r2, [R_PORT_PA_DATA] - -endless: - nop - ba endless - nop - diff --git a/arch/cris/boot/tools/build.c b/arch/cris/boot/tools/build.c deleted file mode 100644 index 3ae485049779..000000000000 --- a/arch/cris/boot/tools/build.c +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/tools/build.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - */ - -/* - * This file builds a disk-image from three different files: - * - * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest - * - setup: 8086 machine code, sets up system parm - * - system: 80386 code for actual system - * - * It does some checking that all files are of the correct type, and - * just writes the result to stdout, removing headers and padding to - * the right amount. It also writes some system data to stderr. - */ - -/* - * Changes by tytso to allow root device specification - * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996 - * Cross compiling fixes by Gertjan van Wingerde, July 1996 - */ - -#include /* fprintf */ -#include -#include /* contains exit */ -#include /* unistd.h needs this */ -#include -#include -#include /* contains read/write */ -#include -#include - -#define MINIX_HEADER 32 - -#define N_MAGIC_OFFSET 1024 -#ifndef __BFD__ -static int GCC_HEADER = sizeof(struct exec); -#endif - -#ifdef __BIG_KERNEL__ -#define SYS_SIZE 0xffff -#else -#define SYS_SIZE DEF_SYSSIZE -#endif - -#define DEFAULT_MAJOR_ROOT 0 -#define DEFAULT_MINOR_ROOT 0 - -/* max nr of sectors of setup: don't change unless you also change - * bootsect etc */ -#define SETUP_SECTS 4 - -#define STRINGIFY(x) #x - -typedef union { - int i; - long l; - short s[2]; - char b[4]; -} conv; - -long intel_long(long l) -{ - conv t; - - t.b[0] = l & 0xff; l >>= 8; - t.b[1] = l & 0xff; l >>= 8; - t.b[2] = l & 0xff; l >>= 8; - t.b[3] = l & 0xff; l >>= 8; - return t.l; -} - -int intel_int(int i) -{ - conv t; - - t.b[0] = i & 0xff; i >>= 8; - t.b[1] = i & 0xff; i >>= 8; - t.b[2] = i & 0xff; i >>= 8; - t.b[3] = i & 0xff; i >>= 8; - return t.i; -} - -short intel_short(short l) -{ - conv t; - - t.b[0] = l & 0xff; l >>= 8; - t.b[1] = l & 0xff; l >>= 8; - return t.s[0]; -} - -void die(const char * str) -{ - fprintf(stderr,"%s\n",str); - exit(1); -} - -void usage(void) -{ - die("Usage: build bootsect setup system [rootdev] [> image]"); -} - -int main(int argc, char ** argv) -{ - int i,c,id,sz,tmp_int; - unsigned long sys_size, tmp_long; - char buf[1024]; -#ifndef __BFD__ - struct exec *ex = (struct exec *)buf; -#endif - char major_root, minor_root; - struct stat sb; - unsigned char setup_sectors; - - if ((argc < 4) || (argc > 5)) - usage(); - if (argc > 4) { - if (!strcmp(argv[4], "CURRENT")) { - if (stat("/", &sb)) { - perror("/"); - die("Couldn't stat /"); - } - major_root = major(sb.st_dev); - minor_root = minor(sb.st_dev); - } else if (strcmp(argv[4], "FLOPPY")) { - if (stat(argv[4], &sb)) { - perror(argv[4]); - die("Couldn't stat root device."); - } - major_root = major(sb.st_rdev); - minor_root = minor(sb.st_rdev); - } else { - major_root = 0; - minor_root = 0; - } - } else { - major_root = DEFAULT_MAJOR_ROOT; - minor_root = DEFAULT_MINOR_ROOT; - } - fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root); - for (i=0;i0 ; i+=c ) -#ifdef __BIG_KERNEL__ - { - if (!i) { - /* Working with memcpy because of alignment constraints - on Sparc - Gertjan */ - memcpy(&tmp_long, &buf[2], sizeof(long)); - if (tmp_long != intel_long(0x53726448) ) - die("Wrong magic in loader header of 'setup'"); - memcpy(&tmp_int, &buf[6], sizeof(int)); - if (tmp_int < intel_int(0x200)) - die("Wrong version of loader header of 'setup'"); - buf[0x11] = 1; /* LOADED_HIGH */ - tmp_long = intel_long(0x100000); - memcpy(&buf[0x14], &tmp_long, sizeof(long)); /* code32_start */ - } -#endif - if (write(1,buf,c)!=c) - die("Write call failed"); -#ifdef __BIG_KERNEL__ - } -#endif - if (c != 0) - die("read-error on 'setup'"); - close (id); - setup_sectors = (unsigned char)((i + 511) / 512); - /* for compatibility with LILO */ - if (setup_sectors < SETUP_SECTS) - setup_sectors = SETUP_SECTS; - fprintf(stderr,"Setup is %d bytes.\n",i); - for (c=0 ; c sizeof(buf)) - c = sizeof(buf); - if (write(1,buf,c) != c) - die("Write call failed"); - i += c; - } - - if ((id=open(argv[3],O_RDONLY,0))<0) - die("Unable to open 'system'"); -#ifndef __BFD__ - if (read(id,buf,GCC_HEADER) != GCC_HEADER) - die("Unable to read header of 'system'"); - if (N_MAGIC(*ex) == ZMAGIC) { - GCC_HEADER = N_MAGIC_OFFSET; - lseek(id, GCC_HEADER, SEEK_SET); - } else if (N_MAGIC(*ex) != QMAGIC) - die("Non-GCC header of 'system'"); - fprintf(stderr,"System is %d kB (%d kB code, %d kB data and %d kB bss)\n", - (ex->a_text+ex->a_data+ex->a_bss)/1024, - ex->a_text /1024, - ex->a_data /1024, - ex->a_bss /1024); - sz = N_SYMOFF(*ex) - GCC_HEADER + 4; -#else - if (fstat (id, &sb)) { - perror ("fstat"); - die ("Unable to stat 'system'"); - } - sz = sb.st_size; - fprintf (stderr, "System is %d kB\n", sz/1024); -#endif - sys_size = (sz + 15) / 16; - if (sys_size > SYS_SIZE) - die("System is too big"); - while (sz > 0) { - int l, n; - - l = sz; - if (l > sizeof(buf)) - l = sizeof(buf); - if ((n=read(id, buf, l)) != l) { - if (n == -1) - perror(argv[1]); - else - fprintf(stderr, "Unexpected EOF\n"); - die("Can't read 'system'"); - } - if (write(1, buf, l) != l) - die("Write failed"); - sz -= l; - } - close(id); - if (lseek(1, 497, 0) == 497) { - if (write(1, &setup_sectors, 1) != 1) - die("Write of setup sectors failed"); - } - if (lseek(1,500,0) == 500) { - buf[0] = (sys_size & 0xff); - buf[1] = ((sys_size >> 8) & 0xff); - if (write(1, buf, 2) != 2) - die("Write failed"); - } - return(0); -} diff --git a/arch/cris/configs/artpec_3_defconfig b/arch/cris/configs/artpec_3_defconfig deleted file mode 100644 index d31851f29db8..000000000000 --- a/arch/cris/configs/artpec_3_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_HOTPLUG is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" -CONFIG_ETRAX_FAST_TIMER=y -CONFIG_CRIS_MACH_ARTPEC3=y -CONFIG_ETRAX_DRAM_SIZE=32 -CONFIG_ETRAX_FLASH1_SIZE=4 -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_ETRAX_ETHERNET=y -CONFIG_ETRAX_AXISFLASHMAP=y -CONFIG_MTD_RAM=y -CONFIG_MTD_MTDRAM=y -CONFIG_MTDRAM_TOTAL_SIZE=0 -CONFIG_MTDRAM_ERASE_SIZE=64 -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_INPUT is not set -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ETRAX_GPIO=y diff --git a/arch/cris/configs/dev88_defconfig b/arch/cris/configs/dev88_defconfig deleted file mode 100644 index beff4ee6edb3..000000000000 --- a/arch/cris/configs/dev88_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_BUILTIN_DTB="dev88" -# CONFIG_SWAP is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ETRAX_FAST_TIMER=y -CONFIG_ETRAXFS=y -CONFIG_ETRAX_DRAM_SIZE=32 -CONFIG_ETRAX_FLASH1_SIZE=4 -CONFIG_ETRAX_MEM_GRP1_CONFIG=0x40688 -CONFIG_ETRAX_MEM_GRP3_CONFIG=0x3 -CONFIG_ETRAX_MEM_GRP4_CONFIG=0x10040 -CONFIG_ETRAX_SDRAM_GRP0_CONFIG=0x958 -CONFIG_ETRAX_SDRAM_TIMING=0x824a -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_ETRAX_ETHERNET=y -CONFIG_ETRAX_AXISFLASHMAP=y -CONFIG_DEVTMPFS=y -CONFIG_MTD_RAM=y -CONFIG_MTDRAM_TOTAL_SIZE=0 -CONFIG_MTDRAM_ERASE_SIZE=64 -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_INPUT is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -CONFIG_SERIAL_ETRAXFS=y -CONFIG_SERIAL_ETRAXFS_CONSOLE=y -CONFIG_GPIO_ETRAXFS=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y diff --git a/arch/cris/configs/etrax-100lx_defconfig b/arch/cris/configs/etrax-100lx_defconfig deleted file mode 100644 index cbbcefeaa8fc..000000000000 --- a/arch/cris/configs/etrax-100lx_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_ETRAX_LED1R=2 -CONFIG_ETRAX_LED2G=2 -CONFIG_ETRAX_LED2R=2 -CONFIG_ETRAX_DEF_R_PORT_PA_DIR=1d -CONFIG_ETRAX_DEF_R_PORT_PA_DATA=f0 -CONFIG_ETRAX_DEF_R_PORT_PB_DIR=1e -CONFIG_ETRAX_DEF_R_PORT_PB_DATA=f3 -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IPV6 is not set -CONFIG_ETRAX_ETHERNET=y -CONFIG_ETRAX_SERIAL=y -CONFIG_ETRAX_SERIAL_PORT0=y -CONFIG_ETRAX_SERIAL_PORT1=y -CONFIG_ETRAX_I2C=y -CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C=y -CONFIG_ETRAX_GPIO=y -CONFIG_ETRAX_AXISFLASHMAP=y -CONFIG_NETDEVICES=y -CONFIG_CRAMFS=y diff --git a/arch/cris/configs/etrax-100lx_v2_defconfig b/arch/cris/configs/etrax-100lx_v2_defconfig deleted file mode 100644 index d90ac95c1e44..000000000000 --- a/arch/cris/configs/etrax-100lx_v2_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_HOTPLUG is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" -CONFIG_ETRAX_FAST_TIMER=y -CONFIG_ETRAX100LX_V2=y -CONFIG_ETRAX_DRAM_SIZE=32 -CONFIG_ETRAX_FLASH1_SIZE=4 -CONFIG_ETRAX_DEBUG_PORT_NULL=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_ETRAX_ETHERNET=y -CONFIG_ETRAX_SERIAL=y -CONFIG_ETRAX_AXISFLASHMAP=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_RAM=y -CONFIG_MTD_MTDRAM=y -CONFIG_MTDRAM_TOTAL_SIZE=0 -CONFIG_MTDRAM_ERASE_SIZE=64 -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_INPUT is not set -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y diff --git a/arch/cris/configs/etraxfs_defconfig b/arch/cris/configs/etraxfs_defconfig deleted file mode 100644 index f714e9dfef9b..000000000000 --- a/arch/cris/configs/etraxfs_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_EXPERIMENTAL=y -# CONFIG_SWAP is not set -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_HOTPLUG is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc" -CONFIG_ETRAX_FAST_TIMER=y -CONFIG_ETRAXFS=y -CONFIG_ETRAX_DRAM_SIZE=32 -CONFIG_ETRAX_FLASH1_SIZE=4 -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_ETRAX_ETHERNET=y -CONFIG_ETRAX_AXISFLASHMAP=y -CONFIG_MTD_RAM=y -CONFIG_MTD_MTDRAM=y -CONFIG_MTDRAM_TOTAL_SIZE=0 -CONFIG_MTDRAM_ERASE_SIZE=64 -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -# CONFIG_INPUT is not set -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ETRAX_GPIO=y diff --git a/arch/cris/include/arch-v10/arch/bitops.h b/arch/cris/include/arch-v10/arch/bitops.h deleted file mode 100644 index c18f81858899..000000000000 --- a/arch/cris/include/arch-v10/arch/bitops.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* asm/arch/bitops.h for Linux/CRISv10 */ - -#ifndef _CRIS_ARCH_BITOPS_H -#define _CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions, wrapping the - * syntactically awkward asms. The asms compute the number of leading - * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped - * number. They differ in that the first function also inverts all bits - * in the input. - */ -static inline unsigned long cris_swapnwbrlz(unsigned long w) -{ - /* Let's just say we return the result in the same register as the - input. Saying we clobber the input but can return the result - in another register: - ! __asm__ ("swapnwbr %2\n\tlz %2,%0" - ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w)); - confuses gcc (core.c, gcc from cris-dist-1.14). */ - - unsigned long res; - __asm__ ("swapnwbr %0 \n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - return res; -} - -static inline unsigned long cris_swapwbrlz(unsigned long w) -{ - unsigned res; - __asm__ ("swapwbr %0 \n\t" - "lz %0,%0" - : "=r" (res) - : "0" (w)); - return res; -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/** - * __ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline unsigned long __ffs(unsigned long word) -{ - return cris_swapnwbrlz(~word); -} - -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -static inline unsigned long kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h deleted file mode 100644 index 06da9d49152a..000000000000 --- a/arch/cris/include/arch-v10/arch/bug.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRISv10_ARCH_BUG_H -#define __ASM_CRISv10_ARCH_BUG_H - -#include - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -/* The BUG() macro is used for marking obviously incorrect code paths. - * It will cause a message with the file name and line number to be printed, - * and then cause an oops. The message is actually printed by handle_BUG() - * in arch/cris/kernel/traps.c, and the reason we use this method of storing - * the file name and line number is that we do not want to affect the registers - * by calling printk() before causing the oops. - */ - -#define BUG_PREFIX 0x0D7F -#define BUG_MAGIC 0x00001234 - -struct bug_frame { - unsigned short prefix; - unsigned int magic; - unsigned short clear; - unsigned short movu; - unsigned short line; - unsigned short jump; - unsigned char *filename; -}; - -#if 0 -/* Unfortunately this version of the macro does not work due to a problem - * with the compiler (aka a bug) when compiling with -O2, which sometimes - * erroneously causes the second input to be stored in a register... - */ -#define BUG() \ - __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ - "movu.w %0,$r0\n\t" \ - "jump %1\n\t" \ - : : "i" (__LINE__), "i" (__FILE__)) -#else -/* This version will have to do for now, until the compiler is fixed. - * The drawbacks of this version are that the file name will appear multiple - * times in the .rodata section, and that __LINE__ and __FILE__ can probably - * not be used like this with newer versions of gcc. - */ -#define BUG() \ -do { \ - __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\ - "movu.w " __stringify(__LINE__) ",$r0\n\t"\ - "jump 0f\n\t" \ - ".section .rodata\n" \ - "0:\t.string \"" __FILE__ "\"\n\t" \ - ".previous"); \ - unreachable(); \ -} while (0) -#endif - -#else - -/* This just causes an oops. */ -#define BUG() \ -do { \ - barrier_before_unreachable(); \ - __builtin_trap(); \ -} while (0) - -#endif - -#define HAVE_ARCH_BUG -#endif - -#include - -#endif diff --git a/arch/cris/include/arch-v10/arch/cache.h b/arch/cris/include/arch-v10/arch/cache.h deleted file mode 100644 index d4049bcab3c5..000000000000 --- a/arch/cris/include/arch-v10/arch/cache.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_CACHE_H -#define _ASM_ARCH_CACHE_H - -/* Etrax 100LX have 32-byte cache-lines. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 - -#endif /* _ASM_ARCH_CACHE_H */ diff --git a/arch/cris/include/arch-v10/arch/checksum.h b/arch/cris/include/arch-v10/arch/checksum.h deleted file mode 100644 index eb186be4fb32..000000000000 --- a/arch/cris/include/arch-v10/arch/checksum.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_CHECKSUM_H -#define _CRIS_ARCH_CHECKSUM_H - -/* Checksum some values used in TCP/UDP headers. - * - * The gain by doing this in asm is that C will not generate carry-additions - * for the 32-bit components of the checksum, so otherwise we would have had - * to split all of those into 16-bit components, then add. - */ - -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len, - __u8 proto, __wsum sum) -{ - __wsum res; - __asm__ ("add.d %2, %0\n\t" - "ax\n\t" - "add.d %3, %0\n\t" - "ax\n\t" - "add.d %4, %0\n\t" - "ax\n\t" - "addq 0, %0\n" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8)); - - return res; -} - -#endif diff --git a/arch/cris/include/arch-v10/arch/delay.h b/arch/cris/include/arch-v10/arch/delay.h deleted file mode 100644 index a57d2cc0baf7..000000000000 --- a/arch/cris/include/arch-v10/arch/delay.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_DELAY_H -#define _CRIS_ARCH_DELAY_H - -static inline void __delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0,$r9\n\t" - "beq 2f\n\t" - "subq 1,$r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1,$r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* defined(_CRIS_ARCH_DELAY_H) */ - - - diff --git a/arch/cris/include/arch-v10/arch/dma.h b/arch/cris/include/arch-v10/arch/dma.h deleted file mode 100644 index ea794a32cf5e..000000000000 --- a/arch/cris/include/arch-v10/arch/dma.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Defines for using and allocating dma channels. */ - -#ifndef _ASM_ARCH_DMA_H -#define _ASM_ARCH_DMA_H - -#define MAX_DMA_CHANNELS 10 - -/* dma0 and dma1 used for network (ethernet) */ -#define NETWORK_TX_DMA_NBR 0 -#define NETWORK_RX_DMA_NBR 1 - -/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */ -#define PAR0_TX_DMA_NBR 2 -#define PAR0_RX_DMA_NBR 3 -#define SCSI0_TX_DMA_NBR 2 -#define SCSI0_RX_DMA_NBR 3 -#define SER2_TX_DMA_NBR 2 -#define SER2_RX_DMA_NBR 3 -#define ATA_TX_DMA_NBR 2 -#define ATA_RX_DMA_NBR 3 - -/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ -#define PAR1_TX_DMA_NBR 4 -#define PAR1_RX_DMA_NBR 5 -#define SCSI1_TX_DMA_NBR 4 -#define SCSI1_RX_DMA_NBR 5 -#define SER3_TX_DMA_NBR 4 -#define SER3_RX_DMA_NBR 5 -#define EXTDMA0_TX_DMA_NBR 4 -#define EXTDMA0_RX_DMA_NBR 5 - -/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */ -#define SER0_TX_DMA_NBR 6 -#define SER0_RX_DMA_NBR 7 -#define EXTDMA1_TX_DMA_NBR 6 -#define EXTDMA1_RX_DMA_NBR 7 -#define MEM2MEM_TX_DMA_NBR 6 -#define MEM2MEM_RX_DMA_NBR 7 - -/* dma8 and dma9 shared by ser1 and usb */ -#define SER1_TX_DMA_NBR 8 -#define SER1_RX_DMA_NBR 9 -#define USB_TX_DMA_NBR 8 -#define USB_RX_DMA_NBR 9 - -#endif - -enum dma_owner -{ - dma_eth, - dma_ser0, - dma_ser1, /* Async and sync */ - dma_ser2, - dma_ser3, /* Async and sync */ - dma_ata, - dma_par0, - dma_par1, - dma_ext0, - dma_ext1, - dma_int6, - dma_int7, - dma_usb, - dma_scsi0, - dma_scsi1 -}; - -/* Masks used by cris_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR (1<<0) -#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR) - -int cris_request_dma(unsigned int dmanr, const char * device_id, - unsigned options, enum dma_owner owner); - -void cris_free_dma(unsigned int dmanr, const char * device_id); diff --git a/arch/cris/include/arch-v10/arch/io.h b/arch/cris/include/arch-v10/arch/io.h deleted file mode 100644 index bae5f77cfabc..000000000000 --- a/arch/cris/include/arch-v10/arch/io.h +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_CRIS_IO_H -#define _ASM_ARCH_CRIS_IO_H - -/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */ - -extern unsigned long gen_config_ii_shadow; -extern unsigned long port_g_data_shadow; -extern unsigned char port_pa_dir_shadow; -extern unsigned char port_pa_data_shadow; -extern unsigned char port_pb_i2c_shadow; -extern unsigned char port_pb_config_shadow; -extern unsigned char port_pb_dir_shadow; -extern unsigned char port_pb_data_shadow; -extern unsigned long r_timer_ctrl_shadow; - -extern unsigned long port_cse1_shadow; -extern unsigned long port_csp0_shadow; -extern unsigned long port_csp4_shadow; - -extern volatile unsigned long *port_cse1_addr; -extern volatile unsigned long *port_csp0_addr; -extern volatile unsigned long *port_csp4_addr; - -/* macro for setting regs through a shadow - - * r = register name (like R_PORT_PA_DATA) - * s = shadow name (like port_pa_data_shadow) - * b = bit number - * v = value (0 or 1) - */ - -#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b)) - -/* The LED's on various Etrax-based products are set differently. */ - -#if defined(CONFIG_ETRAX_NO_LEDS) -#undef CONFIG_ETRAX_PA_LEDS -#undef CONFIG_ETRAX_PB_LEDS -#undef CONFIG_ETRAX_CSP0_LEDS -#define CRIS_LED_NETWORK_SET_G(x) -#define CRIS_LED_NETWORK_SET_R(x) -#define CRIS_LED_ACTIVE_SET_G(x) -#define CRIS_LED_ACTIVE_SET_R(x) -#define CRIS_LED_DISK_WRITE(x) -#define CRIS_LED_DISK_READ(x) -#endif - -#if !defined(CONFIG_ETRAX_CSP0_LEDS) -#define CRIS_LED_BIT_SET(x) -#define CRIS_LED_BIT_CLR(x) -#endif - -#define CRIS_LED_OFF 0x00 -#define CRIS_LED_GREEN 0x01 -#define CRIS_LED_RED 0x02 -#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED) - -#if defined(CONFIG_ETRAX_NO_LEDS) -#define CRIS_LED_NETWORK_SET(x) -#else -#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R -#define CRIS_LED_NETWORK_SET(x) \ - do { \ - CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ - } while (0) -#else -#define CRIS_LED_NETWORK_SET(x) \ - do { \ - CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#endif -#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - } while (0) -#else -#define CRIS_LED_ACTIVE_SET(x) \ - do { \ - CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \ - CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \ - } while (0) -#endif -#endif - -#ifdef CONFIG_ETRAX_PA_LEDS -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \ - CONFIG_ETRAX_LED3G, !(x)) -#endif - -#ifdef CONFIG_ETRAX_PB_LEDS -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \ - CONFIG_ETRAX_LED3G, !(x)) -#endif - -#ifdef CONFIG_ETRAX_CSP0_LEDS -#define CONFIGURABLE_LEDS\ - ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\ - (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\ - (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\ - (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\ - (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\ - (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\ - (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\ - (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\ - (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\ - (1 << CONFIG_ETRAX_LED12R )) - -#define CRIS_LED_NETWORK_SET_G(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x)) -#define CRIS_LED_NETWORK_SET_R(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x)) -#define CRIS_LED_ACTIVE_SET_G(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x)) -#define CRIS_LED_ACTIVE_SET_R(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x)) -#define CRIS_LED_DISK_WRITE(x) \ - do{\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\ - }while(0) -#define CRIS_LED_DISK_READ(x) \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x)) -#define CRIS_LED_BIT_SET(x)\ - do{\ - if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\ - }while(0) -#define CRIS_LED_BIT_CLR(x)\ - do{\ - if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\ - }while(0) -#endif - -# -#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN -#define SOFT_SHUTDOWN() \ - REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1) -#else -#define SOFT_SHUTDOWN() -#endif - -#endif diff --git a/arch/cris/include/arch-v10/arch/io_interface_mux.h b/arch/cris/include/arch-v10/arch/io_interface_mux.h deleted file mode 100644 index 2d5617e67ab0..000000000000 --- a/arch/cris/include/arch-v10/arch/io_interface_mux.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* IO interface mux allocator for ETRAX100LX. - * Copyright 2004, Axis Communications AB - * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $ - */ - - -#ifndef _IO_INTERFACE_MUX_H -#define _IO_INTERFACE_MUX_H - - -/* C.f. ETRAX100LX Designer's Reference 20.9 */ - -/* The order in enum must match the order of interfaces[] in - * io_interface_mux.c */ -enum cris_io_interface { - /* Begin Non-multiplexed interfaces */ - if_eth = 0, - if_serial_0, - /* End Non-multiplexed interfaces */ - if_serial_1, - if_serial_2, - if_serial_3, - if_sync_serial_1, - if_sync_serial_3, - if_shared_ram, - if_shared_ram_w, - if_par_0, - if_par_1, - if_par_w, - if_scsi8_0, - if_scsi8_1, - if_scsi_w, - if_ata, - if_csp, - if_i2c, - if_usb_1, - if_usb_2, - /* GPIO pins */ - if_gpio_grp_a, - if_gpio_grp_b, - if_gpio_grp_c, - if_gpio_grp_d, - if_gpio_grp_e, - if_gpio_grp_f, - if_max_interfaces, - if_unclaimed -}; - -int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id); - -void cris_free_io_interface(enum cris_io_interface ioif); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_allocate_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -/* port can be 'a', 'b' or 'g' */ -int cris_io_interface_free_pins(const enum cris_io_interface ioif, - const char port, - const unsigned start_bit, - const unsigned stop_bit); - -int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available, - const unsigned int gpio_out_available, - const unsigned char pa_available, - const unsigned char pb_available)); - -#endif /* _IO_INTERFACE_MUX_H */ diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h deleted file mode 100644 index c4e8a78e33d1..000000000000 --- a/arch/cris/include/arch-v10/arch/irq.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Interrupt handling assembler and defines for Linux/CRISv10 - */ - -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include - -#define NR_IRQS 32 - -/* The first vector number used for IRQs in v10 is really 0x20 */ -/* but all the code and constants are offseted to make 0 the first */ -#define FIRST_IRQ 0 - -#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */ -#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */ -#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */ -#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */ -/* mio, ata, par0, scsi0 on 4 */ -/* par1, scsi1 on 5 */ -#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */ - -#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */ -#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */ -/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */ -#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0) -#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1) - -/* dma0-9 is irq 16..25 */ -/* 16,17: network */ -#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0) -#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1) -#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR -#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR - -/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */ -#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2) -#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3) -#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR -#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR - -/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */ -#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4) -#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5) -#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR -#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR - -/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */ -#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6) -#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7) -#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR -#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR -#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR -#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR - -/* 24,25: dma8 and dma9 shared by ser1 and usb */ -#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8) -#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9) -#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR -#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR -#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR -#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR - -/* usb: controller at irq 31 + uses DMA8 and DMA9 */ -#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb) - -/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */ - -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; -void set_int_vector(int n, irqvectptr addr); -void set_break_vector(int n, irqvectptr addr); - -#define __STR(x) #x -#define STR(x) __STR(x) - -/* SAVE_ALL saves registers so they match pt_regs */ - -#define SAVE_ALL \ - "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \ - "push $srp\n\t" /* push subroutine return pointer */ \ - "push $dccr\n\t" /* push condition codes */ \ - "push $mof\n\t" /* push multiply overflow reg */ \ - "di\n\t" /* need to disable irq's at this point */\ - "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \ - "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \ - "push $r10\n\t" /* push orig_r10 */ \ - "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */ - -/* BLOCK_IRQ and UNBLOCK_IRQ do the same as - * crisv10_mask_irq and crisv10_unmask_irq */ - -#define BLOCK_IRQ(mask,nr) \ - "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000d8]\n\t" - -#define UNBLOCK_IRQ(mask) \ - "move.d " #mask ",$r0\n\t" \ - "move.d $r0,[0xb00000dc]\n\t" - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) -#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr) -#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr) - - /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls - * do_IRQ (with irq disabled still). after that it unblocks and jumps to - * ret_from_intr (entry.S) - * - * The reason the IRQ is blocked is to allow an sti() before the handler which - * will acknowledge the interrupt is run. - */ - -#define BUILD_IRQ(nr,mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \ - "moveq "#nr",$r10\n\t" \ - "move.d $sp,$r11\n\t" \ - "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ - UNBLOCK_IRQ(mask) \ - "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); - -/* This is subtle. The timer interrupt is crucial and it should not be disabled for - * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would - * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK. - * If the softirq's take too much time to run, the timer irq won't run and the - * watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq - * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed - * it here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt runs - * with interrupts disabled, and therefore there will not be an sti() before the - * timer irq handler is run to acknowledge the interrupt. - */ - -#define BUILD_TIMER_IRQ(nr,mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - "moveq "#nr",$r10\n\t" \ - "move.d $sp,$r11\n\t" \ - "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \ - "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \ - "jump ret_from_intr\n\t"); - -#endif diff --git a/arch/cris/include/arch-v10/arch/irqflags.h b/arch/cris/include/arch-v10/arch/irqflags.h deleted file mode 100644 index 9959b0a8a58c..000000000000 --- a/arch/cris/include/arch-v10/arch/irqflags.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H -#define __ASM_CRIS_ARCH_IRQFLAGS_H - -#include - -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory"); - return flags; -} - -static inline void arch_local_irq_disable(void) -{ - asm volatile("di" : : : "memory"); -} - -static inline void arch_local_irq_enable(void) -{ - asm volatile("ei" : : : "memory"); -} - -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags = arch_local_save_flags(); - arch_local_irq_disable(); - return flags; -} - -static inline void arch_local_irq_restore(unsigned long flags) -{ - asm volatile("move %0,$ccr" : : "rm" (flags) : "memory"); -} - -static inline bool arch_irqs_disabled_flags(unsigned long flags) -{ - return !(flags & (1 << 5)); -} - -static inline bool arch_irqs_disabled(void) -{ - return arch_irqs_disabled_flags(arch_local_save_flags()); -} - -#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */ diff --git a/arch/cris/include/arch-v10/arch/memmap.h b/arch/cris/include/arch-v10/arch/memmap.h deleted file mode 100644 index b6b171f48b29..000000000000 --- a/arch/cris/include/arch-v10/arch/memmap.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/arch/cris/include/arch-v10/arch/mmu.h b/arch/cris/include/arch-v10/arch/mmu.h deleted file mode 100644 index 74c53048be79..000000000000 --- a/arch/cris/include/arch-v10/arch/mmu.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * CRIS MMU constants and PTE layout - */ - -#ifndef _CRIS_ARCH_MMU_H -#define _CRIS_ARCH_MMU_H - -/* type used in struct mm to couple an MMU context to an active mm */ - -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* kernel memory segments */ - -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* CRIS PTE bits (see R_TLB_LO in the register description) - * - * Bit: 31 30-13 12-------4 3 2 1 0 - * _______________________________________________________ - * | cache |pfn | reserved | global | valid | kernel | we | - * |_______|____|__________|________|_______|________|_____| - * - * (pfn = physical frame number) - */ - -/* Real HW-based PTE bits. We use some synonym names so that - * things become less confusing in combination with the SW-based - * bits further below. - * - */ - -#define _PAGE_WE (1<<0) /* page is write-enabled */ -#define _PAGE_SILENT_WRITE (1<<0) /* synonym */ -#define _PAGE_KERNEL (1<<1) /* page is kernel only */ -#define _PAGE_VALID (1<<2) /* page is valid */ -#define _PAGE_SILENT_READ (1<<2) /* synonym */ -#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */ -#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */ - -/* Bits the HW doesn't care about but the kernel uses them in SW */ - -#define _PAGE_PRESENT (1<<4) /* page present in memory */ -#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */ -#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */ -#define _PAGE_READ (1<<7) /* read-enabled */ -#define _PAGE_WRITE (1<<8) /* write-enabled */ - -/* Define some higher level generic page attributes. */ - -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* - * CRIS can't do page protection for execute, and considers read the same. - * Also, write permissions imply read permissions. This is the closest we can - * get.. - */ - -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED - -#endif diff --git a/arch/cris/include/arch-v10/arch/offset.h b/arch/cris/include/arch-v10/arch/offset.h deleted file mode 100644 index 6f0f2b4a163f..000000000000 --- a/arch/cris/include/arch-v10/arch/offset.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 8 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 12 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 16 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 20 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 24 /* offsetof(struct pt_regs, r9) */ -#define PT_mof 64 /* offsetof(struct pt_regs, mof) */ -#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */ -#define PT_srp 72 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */ - -#define TASK_pid 141 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/arch/cris/include/arch-v10/arch/page.h b/arch/cris/include/arch-v10/arch/page.h deleted file mode 100644 index a4bbff64868c..000000000000 --- a/arch/cris/include/arch-v10/arch/page.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_PAGE_H -#define _CRIS_ARCH_PAGE_H - - -#ifdef __KERNEL__ - -/* This handles the memory map.. */ -#ifdef CONFIG_CRIS_LOW_MAP -#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */ -#else -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */ -#endif - -/* macros to convert between really physical and virtual addresses - * by stripping a selected bit, we can convert between KSEG_x and - * 0x40000000 where the DRAM really resides - */ - -#ifdef CONFIG_CRIS_LOW_MAP -/* we have DRAM virtually at 0x6 */ -#define __pa(x) ((unsigned long)(x) & 0xdfffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x20000000)) -#else -/* we have DRAM virtually at 0xc */ -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) -#endif - -#endif -#endif diff --git a/arch/cris/include/arch-v10/arch/pgtable.h b/arch/cris/include/arch-v10/arch/pgtable.h deleted file mode 100644 index a61532d06acb..000000000000 --- a/arch/cris/include/arch-v10/arch/pgtable.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_PGTABLE_H -#define _CRIS_ARCH_PGTABLE_H - -/* - * Kernels own virtual memory area. - */ - -#ifdef CONFIG_CRIS_LOW_MAP -#define VMALLOC_START KSEG_7 -#define VMALLOC_END KSEG_8 -#else -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#endif - -#endif - diff --git a/arch/cris/include/arch-v10/arch/processor.h b/arch/cris/include/arch-v10/arch/processor.h deleted file mode 100644 index b2df646bc1eb..000000000000 --- a/arch/cris/include/arch-v10/arch/processor.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_ARCH_PROCESSOR_H -#define __ASM_CRIS_ARCH_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; }) - -/* CRIS has no problems with write protection */ -#define wp_works_ok 1 - -/* CRIS thread_struct. this really has nothing to do with the processor itself, since - * CRIS does not do any hardware task-switching, but it's here for legacy reasons. - * The thread_struct here is used when task-switching using _resume defined in entry.S. - * The offsets here are hardcoded into _resume - if you change this struct, you need to - * change them as well!!! -*/ - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned long dccr; /* saved flag register */ -}; - -/* - * User space process size. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ - -#ifdef CONFIG_CRIS_LOW_MAP -#define TASK_SIZE (0x50000000UL) /* 1.25 GB */ -#else -#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */ -#endif - -#define INIT_THREAD { \ - 0, 0, 0x20 } /* ccr = int enable, nothing else */ - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)task_pt_regs(tsk); \ - if (regs > PAGE_SIZE && \ - virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->irp; \ - eip; \ -}) - -/* give the thread a program location - * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8) - * switch user-stackpointer - */ - -#define start_thread(regs, ip, usp) do { \ - regs->irp = ip; \ - regs->dccr |= 1 << U_DCCR_BITNR; \ - wrusp(usp); \ -} while(0) - -/* Called when handling a kernel bus fault fixup. - * - * After a fixup we do not want to return by restoring the CPU-state - * anymore, so switch frame-types (see ptrace.h) - */ -#define arch_fixup(regs) \ - regs->frametype = CRIS_FRAME_NORMAL; - -#endif diff --git a/arch/cris/include/arch-v10/arch/swab.h b/arch/cris/include/arch-v10/arch/swab.h deleted file mode 100644 index 8cc27dfb9d3a..000000000000 --- a/arch/cris/include/arch-v10/arch/swab.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_SWAB_H -#define _CRIS_ARCH_SWAB_H - -#include -#include - -#define __SWAB_64_THRU_32__ - -/* we just define these two (as we can do the swap in a single - * asm instruction in CRIS) and the arch-independent files will put - * them together into ntohl etc. - */ - -static inline __attribute_const__ __u32 __arch_swab32(__u32 x) -{ - __asm__ ("swapwb %0" : "=r" (x) : "0" (x)); - - return(x); -} -#define __arch_swab32 __arch_swab32 - -static inline __attribute_const__ __u16 __arch_swab16(__u16 x) -{ - __asm__ ("swapb %0" : "=r" (x) : "0" (x)); - - return(x); -} -#define __arch_swab16 __arch_swab16 - -#endif diff --git a/arch/cris/include/arch-v10/arch/system.h b/arch/cris/include/arch-v10/arch/system.h deleted file mode 100644 index 4c63f728122b..000000000000 --- a/arch/cris/include/arch-v10/arch/system.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_ARCH_SYSTEM_H -#define __ASM_CRIS_ARCH_SYSTEM_H - - -/* read the CPU version register */ - -static inline unsigned long rdvr(void) { - unsigned char vr; - __asm__ volatile ("move $vr,%0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "cris" - -/* read/write the user-mode stackpointer */ - -static inline unsigned long rdusp(void) { - unsigned long usp; - __asm__ __volatile__("move $usp,%0" : "=rm" (usp)); - return usp; -} - -#define wrusp(usp) \ - __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp)) - -/* read the current stackpointer */ - -static inline unsigned long rdsp(void) { - unsigned long sp; - __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp)); - return sp; -} - -static inline unsigned long _get_base(char * addr) -{ - return 0; -} - -#endif diff --git a/arch/cris/include/arch-v10/arch/thread_info.h b/arch/cris/include/arch-v10/arch/thread_info.h deleted file mode 100644 index 0ef1223998c1..000000000000 --- a/arch/cris/include/arch-v10/arch/thread_info.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_THREAD_INFO_H -#define _ASM_ARCH_THREAD_INFO_H - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif diff --git a/arch/cris/include/arch-v10/arch/timex.h b/arch/cris/include/arch-v10/arch/timex.h deleted file mode 100644 index 9c9583e5aed6..000000000000 --- a/arch/cris/include/arch-v10/arch/timex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Use prescale timer at 25000 Hz instead of the baudrate timer at - * 19200 to get rid of the 64ppm to fast timer (and we get better - * resolution within a jiffie as well. - */ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */ -/* If you change anything here you must check time.c as well... */ -#define PRESCALE_FREQ 25000000 -#define PRESCALE_VALUE 1000 -#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */ -/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_CLKSEL flexible -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - - -#define GET_JIFFIES_USEC() \ - ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV ) - -unsigned long get_ns_in_jiffie(void); - -static inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie()/1000; -} - -#endif diff --git a/arch/cris/include/arch-v10/arch/tlb.h b/arch/cris/include/arch-v10/arch/tlb.h deleted file mode 100644 index 9f039d83f21b..000000000000 --- a/arch/cris/include/arch-v10/arch/tlb.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* The TLB can host up to 64 different mm contexts at the same time. - * The last page_id is never running - it is used as an invalid page_id - * so we can make TLB entries that will never match. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 64 -#define INVALID_PAGEID 63 -#define NO_CONTEXT -1 - -#endif diff --git a/arch/cris/include/arch-v10/arch/uaccess.h b/arch/cris/include/arch-v10/arch/uaccess.h deleted file mode 100644 index 8d033c534f1f..000000000000 --- a/arch/cris/include/arch-v10/arch/uaccess.h +++ /dev/null @@ -1,651 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Authors: Bjorn Wesen (bjornw@axis.com) - * Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *after* the faulting - * instruction. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - " "op" %1,[%2]\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) \ - __asm__ __volatile__( \ - " move.d %M1,[%2]\n" \ - "2: move.d %H1,[%2+4]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - " "op" [%2],%1\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " moveq 0,%1\n" \ - " jump 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) \ - __asm__ __volatile__( \ - " move.d [%2],%M1\n" \ - "2: move.d [%2+4],%H1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " moveq 0,%1\n" \ - " jump 4b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -static inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3 - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - " move.b [%2+],$r9\n" - "1: beq 2f\n" - " move.b $r9,[%1+]\n" - - " subq 1,%0\n" - " bne 1b\n" - " move.b [%2+],$r9\n" - - "2: sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - - /* There's one address for a fault at the first move, and - two possible PC values for a fault at the second move, - being a delay-slot filler. However, the branch-target - for the second move is the same as the first address. - Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 1b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=r" (dst), "=r" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "r9"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address *after* the insn. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " jump 1b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=r" (to), "=r" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "r9", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "2: move.b $r9,[%0+]\n", \ - "3: addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "2: move.w $r9,[%0+]\n" COPY, \ - "3: addq 2,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "4: move.b $r9,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "2: move.d $r9,[%0+]\n" COPY, \ - "3: addq 4,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "4: move.b $r9,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "4: move.w $r9,[%0+]\n" COPY, \ - "5: addq 2,%2\n" \ - FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "6: move.b $r9,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "4: move.d $r9,[%0+]\n" COPY, \ - "5: addq 4,%2\n" \ - FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "6: move.b $r9,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "6: move.w $r9,[%0+]\n" COPY, \ - "7: addq 2,%2\n" \ - FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "8: move.b $r9,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "6: move.d $r9,[%0+]\n" COPY, \ - "7: addq 4,%2\n" \ - FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "8: move.b $r9,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - "8: move.w $r9,[%0+]\n" COPY, \ - "9: addq 2,%2\n" \ - FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - "10: move.b $r9,[%0+]\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "8: move.d $r9,[%0+]\n" COPY, \ - "9: addq 4,%2\n" \ - FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "10: move.d $r9,[%0+]\n" COPY, \ - "11: addq 4,%2\n" \ - FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - "12: move.d $r9,[%0+]\n" COPY, \ - "13: addq 4,%2\n" \ - FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n2:\n", \ - "3: addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n2:\n" COPY, \ - "3: addq 2,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n4:\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n2:\n" COPY, \ - "3: addq 4,%2\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n4:\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n4:\n" COPY, \ - "5: addq 2,%2\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n6:\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n4:\n" COPY, \ - "5: addq 4,%2\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n6:\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n6:\n" COPY, \ - "7: addq 2,%2\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n8:\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n6:\n" COPY, \ - "7: addq 4,%2\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n8:\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.w [%1+],$r9\n" \ - " move.w $r9,[%0+]\n8:\n" COPY, \ - "9: addq 2,%2\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$r9\n" \ - " move.b $r9,[%0+]\n10:\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n8:\n" COPY, \ - "9: addq 4,%2\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n10:\n" COPY, \ - "11: addq 4,%2\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - " move.d [%1+],$r9\n" \ - " move.d $r9,[%0+]\n12:\n" COPY, \ - "13: addq 4,%2\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " jump 1b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=r" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - " clear.b [%0+]\n2:\n", \ - "3: addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - " clear.w [%0+]\n2:\n", \ - "3: addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - " clear.w [%0+]\n" \ - "2: clear.b [%0+]\n3:\n", \ - "4: addq 2,%1\n" \ - "5: addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - " clear.d [%0+]\n2:\n" CLEAR, \ - "3: addq 4,%1\n" FIXUP, \ - " .dword 2b,3b\n" TENTRY) - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - " clear.d [%0+]\n4:\n" CLEAR, \ - "5: addq 4,%1\n" FIXUP, \ - " .dword 4b,5b\n" TENTRY) - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - " clear.d [%0+]\n6:\n" CLEAR, \ - "7: addq 4,%1\n" FIXUP, \ - " .dword 6b,7b\n" TENTRY) - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - " clear.d [%0+]\n8:\n" CLEAR, \ - "9: addq 4,%1\n" FIXUP, \ - " .dword 8b,9b\n" TENTRY) - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - " clear.d [%0+]\n10:\n" CLEAR, \ - "11: addq 4,%1\n" FIXUP, \ - " .dword 10b,11b\n" TENTRY) - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - " clear.d [%0+]\n12:\n" CLEAR, \ - "13: addq 4,%1\n" FIXUP, \ - " .dword 12b,13b\n" TENTRY) - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -static inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$r9\n" - "0:\n" - " ble 1f\n" - " subq 1,$r9\n" - - " test.b [%0+]\n" - " bne 0b\n" - " test.d $r9\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $r9,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: clear.d %0\n" - " jump 2b\n" - - /* There's one address for a fault at the first move, and - two possible PC values for a fault at the second move, - being a delay-slot filler. However, the branch-target - for the second move is the same as the first address. - Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 0b,3b\n" - " .dword 1b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "r9"); - - return res; -} - -#endif diff --git a/arch/cris/include/arch-v10/arch/unistd.h b/arch/cris/include/arch-v10/arch/unistd.h deleted file mode 100644 index 03cd0b8652f4..000000000000 --- a/arch/cris/include/arch-v10/arch/unistd.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "move %6,$mof\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "g" (arg5)); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "move %6,$mof\n\tmove %7,$srp\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\ - : "srp"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/arch/cris/include/arch-v32/arch/bitops.h b/arch/cris/include/arch-v32/arch/bitops.h deleted file mode 100644 index 7df94798f063..000000000000 --- a/arch/cris/include/arch-v32/arch/bitops.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_BITOPS_H -#define _ASM_CRIS_ARCH_BITOPS_H - -/* - * Helper functions for the core of the ff[sz] functions. They compute the - * number of leading zeroes of a bits-in-byte, byte-in-word and - * word-in-dword-swapped number. They differ in that the first function also - * inverts all bits in the input. - */ - -static inline unsigned long -cris_swapnwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapnwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -static inline unsigned long -cris_swapwbrlz(unsigned long w) -{ - unsigned long res; - - __asm__ __volatile__ ("swapwbr %0\n\t" - "lz %0,%0" - : "=r" (res) : "0" (w)); - - return res; -} - -/* - * Find First Zero in word. Undefined if no zero exist, so the caller should - * check against ~0 first. - */ -static inline unsigned long -ffz(unsigned long w) -{ - return cris_swapnwbrlz(w); -} - -/* - * Find First Set bit in word. Undefined if no 1 exist, so the caller - * should check against 0 first. - */ -static inline unsigned long -__ffs(unsigned long w) -{ - return cris_swapnwbrlz(~w); -} - -/* - * Find First Bit that is set. - */ -static inline unsigned long -kernel_ffs(unsigned long w) -{ - return w ? cris_swapwbrlz (w) + 1 : 0; -} - -#endif /* _ASM_CRIS_ARCH_BITOPS_H */ diff --git a/arch/cris/include/arch-v32/arch/bug.h b/arch/cris/include/arch-v32/arch/bug.h deleted file mode 100644 index 982c6b08fdf1..000000000000 --- a/arch/cris/include/arch-v32/arch/bug.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRISv32_ARCH_BUG_H -#define __ASM_CRISv32_ARCH_BUG_H - -#include - -#ifdef CONFIG_BUG -#ifdef CONFIG_DEBUG_BUGVERBOSE -/* - * The penalty for the in-band code path will be the size of break 14. - * All other stuff is done out-of-band with exception handlers. - */ -#define BUG() \ -do { \ - __asm__ __volatile__ ("0: break 14\n\t" \ - ".section .fixup,\"ax\"\n" \ - "1:\n\t" \ - "move.d %0, $r10\n\t" \ - "move.d %1, $r11\n\t" \ - "jump do_BUG\n\t" \ - "nop\n\t" \ - ".previous\n\t" \ - ".section __ex_table,\"a\"\n\t" \ - ".dword 0b, 1b\n\t" \ - ".previous\n\t" \ - : : "ri" (__FILE__), "i" (__LINE__)); \ - unreachable(); \ -} while (0) -#else -#define BUG() \ -do { \ - __asm__ __volatile__ ("break 14\n\t"); \ - unreachable(); \ -} while (0) -#endif - -#define HAVE_ARCH_BUG -#endif - -#include -#endif diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h deleted file mode 100644 index f61f3088c45b..000000000000 --- a/arch/cris/include/arch-v32/arch/cache.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_CACHE_H -#define _ASM_CRIS_ARCH_CACHE_H - -#include - -/* A cache-line is 32 bytes. */ -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 - -#define __read_mostly __attribute__((__section__(".data..read_mostly"))) - -void flush_dma_list(dma_descr_data *descr); -void flush_dma_descr(dma_descr_data *descr, int flush_buf); - -#define flush_dma_context(c) \ - flush_dma_list(phys_to_virt((c)->saved_data)); - -void cris_flush_cache_range(void *buf, unsigned long len); -void cris_flush_cache(void); - -#endif /* _ASM_CRIS_ARCH_CACHE_H */ diff --git a/arch/cris/include/arch-v32/arch/checksum.h b/arch/cris/include/arch-v32/arch/checksum.h deleted file mode 100644 index fea1341ef244..000000000000 --- a/arch/cris/include/arch-v32/arch/checksum.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_CHECKSUM_H -#define _ASM_CRIS_ARCH_CHECKSUM_H - -/* - * Check values used in TCP/UDP headers. - * - * The gain of doing this in assembler instead of C, is that C doesn't - * generate carry-additions for the 32-bit components of the - * checksum. Which means it would be necessary to split all those into - * 16-bit components and then add. - */ -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, - __u32 len, __u8 proto, __wsum sum) -{ - __wsum res; - - __asm__ __volatile__ ("add.d %2, %0\n\t" - "addc %3, %0\n\t" - "addc %4, %0\n\t" - "addc 0, %0\n\t" - : "=r" (res) - : "0" (sum), "r" (daddr), "r" (saddr), \ - "r" ((len + proto) << 8)); - - return res; -} - -#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */ diff --git a/arch/cris/include/arch-v32/arch/cryptocop.h b/arch/cris/include/arch-v32/arch/cryptocop.h deleted file mode 100644 index f2f8eda1ffb1..000000000000 --- a/arch/cris/include/arch-v32/arch/cryptocop.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * The device /dev/cryptocop is accessible using this driver using - * CRYPTOCOP_MAJOR (254) and minor number 0. - */ -#ifndef CRYPTOCOP_H -#define CRYPTOCOP_H - -#include - - -/********** The API to use from inside the kernel. ************/ - -#include - -typedef enum { - cryptocop_alg_csum = 0, - cryptocop_alg_mem2mem, - cryptocop_alg_md5, - cryptocop_alg_sha1, - cryptocop_alg_des, - cryptocop_alg_3des, - cryptocop_alg_aes, - cryptocop_no_alg, -} cryptocop_algorithm; - -typedef u8 cryptocop_tfrm_id; - - -struct cryptocop_operation; - -typedef void (cryptocop_callback)(struct cryptocop_operation*, void*); - -struct cryptocop_transform_init { - cryptocop_algorithm alg; - /* Keydata for ciphers. */ - unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH]; - unsigned int keylen; - cryptocop_cipher_mode cipher_mode; - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */ - - cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */ - struct cryptocop_transform_init *next; -}; - - -typedef enum { - cryptocop_source_dma = 0, - cryptocop_source_des, - cryptocop_source_3des, - cryptocop_source_aes, - cryptocop_source_md5, - cryptocop_source_sha1, - cryptocop_source_csum, - cryptocop_source_none, -} cryptocop_source; - - -struct cryptocop_desc_cfg { - cryptocop_tfrm_id tid; - cryptocop_source src; - unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */ - struct cryptocop_desc_cfg *next; -}; - -struct cryptocop_desc { - size_t length; - struct cryptocop_desc_cfg *cfg; - struct cryptocop_desc *next; -}; - - -/* Flags for cryptocop_tfrm_cfg */ -#define CRYPTOCOP_NO_FLAG (0x00) -#define CRYPTOCOP_ENCRYPT (0x01) -#define CRYPTOCOP_DECRYPT (0x02) -#define CRYPTOCOP_EXPLICIT_IV (0x04) - -struct cryptocop_tfrm_cfg { - cryptocop_tfrm_id tid; - - unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */ - - /* CBC initialisation vector for ciphers. */ - u8 iv[CRYPTOCOP_MAX_IV_LENGTH]; - - /* The position in output where to write the transform output. The order - in which the driver writes the output is unspecified, hence if several - transforms write on the same positions in the output the result is - unspecified. */ - size_t inject_ix; - - struct cryptocop_tfrm_cfg *next; -}; - - - -struct cryptocop_dma_list_operation{ - /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in - struct cryptocop_operation must be set for the driver to use them. outlist, - out_data_buf, inlist and in_data_buf must all be physical addresses since they will - be loaded to DMA . */ - dma_descr_data *outlist; /* Out from memory to the co-processor. */ - char *out_data_buf; - dma_descr_data *inlist; /* In from the co-processor to memory. */ - char *in_data_buf; - - cryptocop_3des_mode tdes_mode; - cryptocop_csum_type csum_mode; -}; - - -struct cryptocop_tfrm_operation{ - /* Operation configuration, if not 'use_dmalists' is set. */ - struct cryptocop_tfrm_cfg *tfrm_cfg; - struct cryptocop_desc *desc; - - struct iovec *indata; - size_t incount; - size_t inlen; /* Total inlength. */ - - struct iovec *outdata; - size_t outcount; - size_t outlen; /* Total outlength. */ -}; - - -struct cryptocop_operation { - cryptocop_callback *cb; - void *cb_data; - - cryptocop_session_id sid; - - /* The status of the operation when returned to consumer. */ - int operation_status; /* 0, -EAGAIN */ - - /* Flags */ - unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */ - unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */ - unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */ - - union{ - struct cryptocop_dma_list_operation list_op; - struct cryptocop_tfrm_operation tfrm_op; - }; -}; - - -int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag); -int cryptocop_free_session(cryptocop_session_id sid); - -int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); - -int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); - -#endif /* CRYPTOCOP_H */ diff --git a/arch/cris/include/arch-v32/arch/delay.h b/arch/cris/include/arch-v32/arch/delay.h deleted file mode 100644 index 94307c1fbb1c..000000000000 --- a/arch/cris/include/arch-v32/arch/delay.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_DELAY_H -#define _ASM_CRIS_ARCH_DELAY_H - -extern void cris_delay10ns(u32 n10ns); -#define udelay(u) cris_delay10ns((u)*100) -#define ndelay(n) cris_delay10ns(((n)+9)/10) - -/* - * Not used anymore for udelay or ndelay. Referenced by - * e.g. init/calibrate.c. All other references are likely bugs; - * should be replaced by mdelay, udelay or ndelay. - */ - -static inline void -__delay(int loops) -{ - __asm__ __volatile__ ( - "move.d %0, $r9\n\t" - "beq 2f\n\t" - "subq 1, $r9\n\t" - "1:\n\t" - "bne 1b\n\t" - "subq 1, $r9\n" - "2:" - : : "g" (loops) : "r9"); -} - -#endif /* _ASM_CRIS_ARCH_DELAY_H */ diff --git a/arch/cris/include/arch-v32/arch/dma.h b/arch/cris/include/arch-v32/arch/dma.h deleted file mode 100644 index 6f92f4f23f28..000000000000 --- a/arch/cris/include/arch-v32/arch/dma.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/arch-v32/arch/hwregs/Makefile b/arch/cris/include/arch-v32/arch/hwregs/Makefile deleted file mode 100644 index bb5ffa7ff9f4..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/Makefile +++ /dev/null @@ -1,187 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The official place for these files is at: -RELEASE ?= r1_alfa5 -OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -# which is updated on each new release. -INCL_ASMFILES = -INCL_FILES = ata_defs.h -INCL_FILES += bif_core_defs.h -INCL_ASMFILES += bif_core_defs_asm.h -INCL_FILES += bif_slave_defs.h -#INCL_FILES += bif_slave_ext_defs.h -INCL_FILES += config_defs.h -INCL_ASMFILES += config_defs_asm.h -INCL_FILES += cpu_vect.h -#INCL_FILES += cris_defs.h -#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h -INCL_FILES += dma.h -INCL_FILES += dma_defs.h -INCL_FILES += eth_defs.h -INCL_FILES += extmem_defs.h -INCL_FILES += gio_defs.h -INCL_ASMFILES += gio_defs_asm.h -INCL_FILES += intr_vect.h -INCL_FILES += intr_vect_defs.h -INCL_ASMFILES += intr_vect_defs_asm.h -INCL_FILES += marb_bp_defs.h -INCL_FILES += marb_defs.h -INCL_ASMFILES += mmu_defs_asm.h -#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h -#INCL_FILES += par_defs.h # No useful content -INCL_FILES += pinmux_defs.h -INCL_FILES += reg_map.h -INCL_ASMFILES += reg_map_asm.h -INCL_FILES += reg_rdwr.h -INCL_FILES += ser_defs.h -#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h -INCL_FILES += sser_defs.h -INCL_FILES += strcop_defs.h -#INCL_FILES += strcop.h # Where is this? -INCL_FILES += strmux_defs.h -#INCL_FILES += supp_reg.h # Handcrafted instead -INCL_FILES += timer_defs.h - -REGDESC = -REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r -REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r -#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r -REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r -REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r -REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r -REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r -REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r -REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r -REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r -#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r -REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r -REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r -REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r -REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r -REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r -#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - - -BASEDIR = /n/asic/design -DESIGNDIR = /n/asic/projects/guinness/design -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -# Disable implicit rule that may generate deleted files from RCS/ directory. -%.r: - -%.h: - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(INCL_FILES) $(INCL_ASMFILES) - -ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r - $(RDES2C) $< -config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) $< -config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r - $(RDES2C) -asm $< -# Can't generate cpu_vect.h yet -#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ???? -# $(RDES2INTR) $< -cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r - $(RDES2C) $< -$(BASEDIR)/core/dma/sw/dma.h: -dma.h: $(BASEDIR)/core/dma/sw/dma.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r - $(RDES2C) $< -extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r - $(RDES2C) $< -gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r - $(RDES2C) $< -intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) $< -intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r - $(RDES2C) -asm $< -# Can't generate intr_vect.h yet -#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r -# $(RDES2INTR) $< -intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r - $(RDES2C) -asm $< -par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r - $(RDES2C) $< - -# From /n/asic/projects/guinness/design/ -reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 $^ -reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap - $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^ - -reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r - $(RDES2C) $< -strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r - $(RDES2C) $< -strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r - $(RDES2C) $< -timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r - $(RDES2C) $< -usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r - $(RDES2C) $< - -## copy - Copy files from official location -copy: - @for HFILE in $(INCL_FILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(INCL_ASMFILES); do \ - echo " $$HFILE"; \ - cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done -## ls_official - List official location -ls_official: - (cd $(OFFICIAL_INCDIR); ls -l *.h ) - -## diff_official - Diff current directory with official location -diff_official: - diff . $(OFFICIAL_INCDIR) - -## doc - Generate .axw files from register description. -doc: $(REGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming ir .r files. -%.axw: axw - @for RDES in $(REGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(INCL_FILES) *.axw - diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h deleted file mode 100644 index 6886ba3c2d53..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h +++ /dev/null @@ -1,223 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ata_defs_asm_h -#define __ata_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ctrl0, scope ata, type rw */ -#define reg_ata_rw_ctrl0___pio_hold___lsb 0 -#define reg_ata_rw_ctrl0___pio_hold___width 6 -#define reg_ata_rw_ctrl0___pio_strb___lsb 6 -#define reg_ata_rw_ctrl0___pio_strb___width 6 -#define reg_ata_rw_ctrl0___pio_setup___lsb 12 -#define reg_ata_rw_ctrl0___pio_setup___width 6 -#define reg_ata_rw_ctrl0___dma_hold___lsb 18 -#define reg_ata_rw_ctrl0___dma_hold___width 6 -#define reg_ata_rw_ctrl0___dma_strb___lsb 24 -#define reg_ata_rw_ctrl0___dma_strb___width 6 -#define reg_ata_rw_ctrl0___rst___lsb 30 -#define reg_ata_rw_ctrl0___rst___width 1 -#define reg_ata_rw_ctrl0___rst___bit 30 -#define reg_ata_rw_ctrl0___en___lsb 31 -#define reg_ata_rw_ctrl0___en___width 1 -#define reg_ata_rw_ctrl0___en___bit 31 -#define reg_ata_rw_ctrl0_offset 12 - -/* Register rw_ctrl1, scope ata, type rw */ -#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0 -#define reg_ata_rw_ctrl1___udma_tcyc___width 4 -#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4 -#define reg_ata_rw_ctrl1___udma_tdvs___width 4 -#define reg_ata_rw_ctrl1_offset 16 - -/* Register rw_ctrl2, scope ata, type rw */ -#define reg_ata_rw_ctrl2___data___lsb 0 -#define reg_ata_rw_ctrl2___data___width 16 -#define reg_ata_rw_ctrl2___dma_size___lsb 19 -#define reg_ata_rw_ctrl2___dma_size___width 1 -#define reg_ata_rw_ctrl2___dma_size___bit 19 -#define reg_ata_rw_ctrl2___multi___lsb 20 -#define reg_ata_rw_ctrl2___multi___width 1 -#define reg_ata_rw_ctrl2___multi___bit 20 -#define reg_ata_rw_ctrl2___hsh___lsb 21 -#define reg_ata_rw_ctrl2___hsh___width 2 -#define reg_ata_rw_ctrl2___trf_mode___lsb 23 -#define reg_ata_rw_ctrl2___trf_mode___width 1 -#define reg_ata_rw_ctrl2___trf_mode___bit 23 -#define reg_ata_rw_ctrl2___rw___lsb 24 -#define reg_ata_rw_ctrl2___rw___width 1 -#define reg_ata_rw_ctrl2___rw___bit 24 -#define reg_ata_rw_ctrl2___addr___lsb 25 -#define reg_ata_rw_ctrl2___addr___width 3 -#define reg_ata_rw_ctrl2___cs0___lsb 28 -#define reg_ata_rw_ctrl2___cs0___width 1 -#define reg_ata_rw_ctrl2___cs0___bit 28 -#define reg_ata_rw_ctrl2___cs1___lsb 29 -#define reg_ata_rw_ctrl2___cs1___width 1 -#define reg_ata_rw_ctrl2___cs1___bit 29 -#define reg_ata_rw_ctrl2___sel___lsb 30 -#define reg_ata_rw_ctrl2___sel___width 2 -#define reg_ata_rw_ctrl2_offset 0 - -/* Register rs_stat_data, scope ata, type rs */ -#define reg_ata_rs_stat_data___data___lsb 0 -#define reg_ata_rs_stat_data___data___width 16 -#define reg_ata_rs_stat_data___dav___lsb 16 -#define reg_ata_rs_stat_data___dav___width 1 -#define reg_ata_rs_stat_data___dav___bit 16 -#define reg_ata_rs_stat_data___busy___lsb 17 -#define reg_ata_rs_stat_data___busy___width 1 -#define reg_ata_rs_stat_data___busy___bit 17 -#define reg_ata_rs_stat_data_offset 4 - -/* Register r_stat_data, scope ata, type r */ -#define reg_ata_r_stat_data___data___lsb 0 -#define reg_ata_r_stat_data___data___width 16 -#define reg_ata_r_stat_data___dav___lsb 16 -#define reg_ata_r_stat_data___dav___width 1 -#define reg_ata_r_stat_data___dav___bit 16 -#define reg_ata_r_stat_data___busy___lsb 17 -#define reg_ata_r_stat_data___busy___width 1 -#define reg_ata_r_stat_data___busy___bit 17 -#define reg_ata_r_stat_data_offset 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -#define reg_ata_rw_trf_cnt___cnt___lsb 0 -#define reg_ata_rw_trf_cnt___cnt___width 17 -#define reg_ata_rw_trf_cnt_offset 20 - -/* Register r_stat_misc, scope ata, type r */ -#define reg_ata_r_stat_misc___crc___lsb 0 -#define reg_ata_r_stat_misc___crc___width 16 -#define reg_ata_r_stat_misc_offset 24 - -/* Register rw_intr_mask, scope ata, type rw */ -#define reg_ata_rw_intr_mask___bus0___lsb 0 -#define reg_ata_rw_intr_mask___bus0___width 1 -#define reg_ata_rw_intr_mask___bus0___bit 0 -#define reg_ata_rw_intr_mask___bus1___lsb 1 -#define reg_ata_rw_intr_mask___bus1___width 1 -#define reg_ata_rw_intr_mask___bus1___bit 1 -#define reg_ata_rw_intr_mask___bus2___lsb 2 -#define reg_ata_rw_intr_mask___bus2___width 1 -#define reg_ata_rw_intr_mask___bus2___bit 2 -#define reg_ata_rw_intr_mask___bus3___lsb 3 -#define reg_ata_rw_intr_mask___bus3___width 1 -#define reg_ata_rw_intr_mask___bus3___bit 3 -#define reg_ata_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope ata, type rw */ -#define reg_ata_rw_ack_intr___bus0___lsb 0 -#define reg_ata_rw_ack_intr___bus0___width 1 -#define reg_ata_rw_ack_intr___bus0___bit 0 -#define reg_ata_rw_ack_intr___bus1___lsb 1 -#define reg_ata_rw_ack_intr___bus1___width 1 -#define reg_ata_rw_ack_intr___bus1___bit 1 -#define reg_ata_rw_ack_intr___bus2___lsb 2 -#define reg_ata_rw_ack_intr___bus2___width 1 -#define reg_ata_rw_ack_intr___bus2___bit 2 -#define reg_ata_rw_ack_intr___bus3___lsb 3 -#define reg_ata_rw_ack_intr___bus3___width 1 -#define reg_ata_rw_ack_intr___bus3___bit 3 -#define reg_ata_rw_ack_intr_offset 32 - -/* Register r_intr, scope ata, type r */ -#define reg_ata_r_intr___bus0___lsb 0 -#define reg_ata_r_intr___bus0___width 1 -#define reg_ata_r_intr___bus0___bit 0 -#define reg_ata_r_intr___bus1___lsb 1 -#define reg_ata_r_intr___bus1___width 1 -#define reg_ata_r_intr___bus1___bit 1 -#define reg_ata_r_intr___bus2___lsb 2 -#define reg_ata_r_intr___bus2___width 1 -#define reg_ata_r_intr___bus2___bit 2 -#define reg_ata_r_intr___bus3___lsb 3 -#define reg_ata_r_intr___bus3___width 1 -#define reg_ata_r_intr___bus3___bit 3 -#define reg_ata_r_intr_offset 36 - -/* Register r_masked_intr, scope ata, type r */ -#define reg_ata_r_masked_intr___bus0___lsb 0 -#define reg_ata_r_masked_intr___bus0___width 1 -#define reg_ata_r_masked_intr___bus0___bit 0 -#define reg_ata_r_masked_intr___bus1___lsb 1 -#define reg_ata_r_masked_intr___bus1___width 1 -#define reg_ata_r_masked_intr___bus1___bit 1 -#define reg_ata_r_masked_intr___bus2___lsb 2 -#define reg_ata_r_masked_intr___bus2___width 1 -#define reg_ata_r_masked_intr___bus2___bit 2 -#define reg_ata_r_masked_intr___bus3___lsb 3 -#define reg_ata_r_masked_intr___bus3___width 1 -#define reg_ata_r_masked_intr___bus3___bit 3 -#define reg_ata_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_ata_active 0x00000001 -#define regk_ata_byte 0x00000001 -#define regk_ata_data 0x00000001 -#define regk_ata_dma 0x00000001 -#define regk_ata_inactive 0x00000000 -#define regk_ata_no 0x00000000 -#define regk_ata_nodata 0x00000000 -#define regk_ata_pio 0x00000000 -#define regk_ata_rd 0x00000001 -#define regk_ata_reg 0x00000000 -#define regk_ata_rw_ctrl0_default 0x00000000 -#define regk_ata_rw_ctrl2_default 0x00000000 -#define regk_ata_rw_intr_mask_default 0x00000000 -#define regk_ata_udma 0x00000002 -#define regk_ata_word 0x00000000 -#define regk_ata_wr 0x00000000 -#define regk_ata_yes 0x00000001 -#endif /* __ata_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index 1d75d8c31cc0..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,320 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h deleted file mode 100644 index a07447fa75f8..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h +++ /dev/null @@ -1,496 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_dma_defs_asm_h -#define __bif_dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch0_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch0_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch0_ctrl_offset 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch0_addr___addr___width 32 -#define reg_bif_dma_rw_ch0_addr_offset 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_start___run___lsb 0 -#define reg_bif_dma_rw_ch0_start___run___width 1 -#define reg_bif_dma_rw_ch0_start___run___bit 0 -#define reg_bif_dma_rw_ch0_start_offset 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch0_cnt_offset 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch0_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch0_stat___cnt___width 16 -#define reg_bif_dma_r_ch0_stat___run___lsb 31 -#define reg_bif_dma_r_ch0_stat___run___width 1 -#define reg_bif_dma_r_ch0_stat___run___bit 31 -#define reg_bif_dma_r_ch0_stat_offset 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch1_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch1_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch1_ctrl_offset 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch1_addr___addr___width 32 -#define reg_bif_dma_rw_ch1_addr_offset 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_start___run___lsb 0 -#define reg_bif_dma_rw_ch1_start___run___width 1 -#define reg_bif_dma_rw_ch1_start___run___bit 0 -#define reg_bif_dma_rw_ch1_start_offset 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch1_cnt_offset 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch1_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch1_stat___cnt___width 16 -#define reg_bif_dma_r_ch1_stat___run___lsb 31 -#define reg_bif_dma_r_ch1_stat___run___width 1 -#define reg_bif_dma_r_ch1_stat___run___bit 31 -#define reg_bif_dma_r_ch1_stat_offset 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch2_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch2_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1 -#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4 -#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1 -#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19 -#define reg_bif_dma_rw_ch2_ctrl_offset 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch2_addr___addr___width 32 -#define reg_bif_dma_rw_ch2_addr_offset 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_start___run___lsb 0 -#define reg_bif_dma_rw_ch2_start___run___width 1 -#define reg_bif_dma_rw_ch2_start___run___bit 0 -#define reg_bif_dma_rw_ch2_start_offset 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch2_cnt_offset 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch2_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch2_stat___cnt___width 16 -#define reg_bif_dma_r_ch2_stat___run___lsb 31 -#define reg_bif_dma_r_ch2_stat___run___width 1 -#define reg_bif_dma_r_ch2_stat___run___bit 31 -#define reg_bif_dma_r_ch2_stat_offset 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0 -#define reg_bif_dma_rw_ch3_ctrl___bw___width 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1 -#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2 -#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3 -#define reg_bif_dma_rw_ch3_ctrl___cont___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1 -#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4 -#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5 -#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1 -#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6 -#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9 -#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14 -#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16 -#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1 -#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18 -#define reg_bif_dma_rw_ch3_ctrl_offset 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_addr___addr___lsb 0 -#define reg_bif_dma_rw_ch3_addr___addr___width 32 -#define reg_bif_dma_rw_ch3_addr_offset 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_start___run___lsb 0 -#define reg_bif_dma_rw_ch3_start___run___width 1 -#define reg_bif_dma_rw_ch3_start___run___bit 0 -#define reg_bif_dma_rw_ch3_start_offset 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0 -#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16 -#define reg_bif_dma_rw_ch3_cnt_offset 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_ch3_stat___cnt___lsb 0 -#define reg_bif_dma_r_ch3_stat___cnt___width 16 -#define reg_bif_dma_r_ch3_stat___run___lsb 31 -#define reg_bif_dma_r_ch3_stat___run___width 1 -#define reg_bif_dma_r_ch3_stat___run___bit 31 -#define reg_bif_dma_r_ch3_stat_offset 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0 -#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0 -#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2 -#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2 -#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3 -#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1 -#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3 -#define reg_bif_dma_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0 -#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0 -#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2 -#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2 -#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3 -#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1 -#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3 -#define reg_bif_dma_rw_ack_intr_offset 132 - -/* Register r_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_intr___ext_dma0___width 1 -#define reg_bif_dma_r_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_intr___ext_dma1___width 1 -#define reg_bif_dma_r_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_intr___ext_dma2___width 1 -#define reg_bif_dma_r_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_intr___ext_dma3___width 1 -#define reg_bif_dma_r_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_intr_offset 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0 -#define reg_bif_dma_r_masked_intr___ext_dma0___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0 -#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2 -#define reg_bif_dma_r_masked_intr___ext_dma2___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2 -#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3 -#define reg_bif_dma_r_masked_intr___ext_dma3___width 1 -#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3 -#define reg_bif_dma_r_masked_intr_offset 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin0_cfg_offset 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin1_cfg_offset 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin2_cfg_offset 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin3_cfg_offset 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin4_cfg_offset 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin5_cfg_offset 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin6_cfg_offset 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0 -#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2 -#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5 -#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7 -#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3 -#define reg_bif_dma_rw_pin7_cfg_offset 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -#define reg_bif_dma_r_pin_stat___pin0___lsb 0 -#define reg_bif_dma_r_pin_stat___pin0___width 1 -#define reg_bif_dma_r_pin_stat___pin0___bit 0 -#define reg_bif_dma_r_pin_stat___pin1___lsb 1 -#define reg_bif_dma_r_pin_stat___pin1___width 1 -#define reg_bif_dma_r_pin_stat___pin1___bit 1 -#define reg_bif_dma_r_pin_stat___pin2___lsb 2 -#define reg_bif_dma_r_pin_stat___pin2___width 1 -#define reg_bif_dma_r_pin_stat___pin2___bit 2 -#define reg_bif_dma_r_pin_stat___pin3___lsb 3 -#define reg_bif_dma_r_pin_stat___pin3___width 1 -#define reg_bif_dma_r_pin_stat___pin3___bit 3 -#define reg_bif_dma_r_pin_stat___pin4___lsb 4 -#define reg_bif_dma_r_pin_stat___pin4___width 1 -#define reg_bif_dma_r_pin_stat___pin4___bit 4 -#define reg_bif_dma_r_pin_stat___pin5___lsb 5 -#define reg_bif_dma_r_pin_stat___pin5___width 1 -#define reg_bif_dma_r_pin_stat___pin5___bit 5 -#define reg_bif_dma_r_pin_stat___pin6___lsb 6 -#define reg_bif_dma_r_pin_stat___pin6___width 1 -#define reg_bif_dma_r_pin_stat___pin6___bit 6 -#define reg_bif_dma_r_pin_stat___pin7___lsb 7 -#define reg_bif_dma_r_pin_stat___pin7___width 1 -#define reg_bif_dma_r_pin_stat___pin7___bit 7 -#define reg_bif_dma_r_pin_stat_offset 192 - - -/* Constants */ -#define regk_bif_dma_as_master 0x00000001 -#define regk_bif_dma_as_slave 0x00000001 -#define regk_bif_dma_burst1 0x00000000 -#define regk_bif_dma_burst8 0x00000001 -#define regk_bif_dma_bw16 0x00000001 -#define regk_bif_dma_bw32 0x00000002 -#define regk_bif_dma_bw8 0x00000000 -#define regk_bif_dma_dack 0x00000006 -#define regk_bif_dma_dack_inv 0x00000007 -#define regk_bif_dma_force 0x00000001 -#define regk_bif_dma_hi 0x00000003 -#define regk_bif_dma_inv 0x00000003 -#define regk_bif_dma_lo 0x00000002 -#define regk_bif_dma_master 0x00000001 -#define regk_bif_dma_no 0x00000000 -#define regk_bif_dma_norm 0x00000002 -#define regk_bif_dma_off 0x00000000 -#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch0_start_default 0x00000000 -#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch1_start_default 0x00000000 -#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch2_start_default 0x00000000 -#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000 -#define regk_bif_dma_rw_ch3_start_default 0x00000000 -#define regk_bif_dma_rw_intr_mask_default 0x00000000 -#define regk_bif_dma_rw_pin0_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin1_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin2_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin3_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin4_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin5_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin6_cfg_default 0x00000000 -#define regk_bif_dma_rw_pin7_cfg_default 0x00000000 -#define regk_bif_dma_slave 0x00000002 -#define regk_bif_dma_sreq 0x00000006 -#define regk_bif_dma_sreq_inv 0x00000007 -#define regk_bif_dma_tc 0x00000004 -#define regk_bif_dma_tc_inv 0x00000005 -#define regk_bif_dma_yes 0x00000001 -#endif /* __bif_dma_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h deleted file mode 100644 index 55697fec603e..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_slave_defs_asm_h -#define __bif_slave_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0 -#define reg_bif_slave_rw_slave_cfg___slave_id___width 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1 -#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1 -#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4 -#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5 -#define reg_bif_slave_rw_slave_cfg___loopback___width 1 -#define reg_bif_slave_rw_slave_cfg___loopback___bit 5 -#define reg_bif_slave_rw_slave_cfg___dis___lsb 6 -#define reg_bif_slave_rw_slave_cfg___dis___width 1 -#define reg_bif_slave_rw_slave_cfg___dis___bit 6 -#define reg_bif_slave_rw_slave_cfg_offset 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0 -#define reg_bif_slave_r_slave_mode___ch0_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0 -#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2 -#define reg_bif_slave_r_slave_mode___ch2_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2 -#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3 -#define reg_bif_slave_r_slave_mode___ch3_mode___width 1 -#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3 -#define reg_bif_slave_r_slave_mode_offset 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch0_cfg_offset 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch1_cfg_offset 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch2_cfg_offset 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0 -#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2 -#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1 -#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3 -#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4 -#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2 -#define reg_bif_slave_rw_ch3_cfg_offset 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0 -#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1 -#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0 -#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1 -#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4 -#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3 -#define reg_bif_slave_rw_arb_cfg___release___lsb 7 -#define reg_bif_slave_rw_arb_cfg___release___width 2 -#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9 -#define reg_bif_slave_rw_arb_cfg___acquire___width 1 -#define reg_bif_slave_rw_arb_cfg___acquire___bit 9 -#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10 -#define reg_bif_slave_rw_arb_cfg___settle_time___width 2 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1 -#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12 -#define reg_bif_slave_rw_arb_cfg_offset 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -#define reg_bif_slave_r_arb_stat___init_mode___lsb 0 -#define reg_bif_slave_r_arb_stat___init_mode___width 1 -#define reg_bif_slave_r_arb_stat___init_mode___bit 0 -#define reg_bif_slave_r_arb_stat___mode___lsb 1 -#define reg_bif_slave_r_arb_stat___mode___width 1 -#define reg_bif_slave_r_arb_stat___mode___bit 1 -#define reg_bif_slave_r_arb_stat___brin___lsb 2 -#define reg_bif_slave_r_arb_stat___brin___width 1 -#define reg_bif_slave_r_arb_stat___brin___bit 2 -#define reg_bif_slave_r_arb_stat___brout___lsb 3 -#define reg_bif_slave_r_arb_stat___brout___width 1 -#define reg_bif_slave_r_arb_stat___brout___bit 3 -#define reg_bif_slave_r_arb_stat___bg___lsb 4 -#define reg_bif_slave_r_arb_stat___bg___width 1 -#define reg_bif_slave_r_arb_stat___bg___bit 4 -#define reg_bif_slave_r_arb_stat_offset 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0 -#define reg_bif_slave_rw_intr_mask___bus_release___width 1 -#define reg_bif_slave_rw_intr_mask___bus_release___bit 0 -#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1 -#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1 -#define reg_bif_slave_rw_intr_mask_offset 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0 -#define reg_bif_slave_rw_ack_intr___bus_release___width 1 -#define reg_bif_slave_rw_ack_intr___bus_release___bit 0 -#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1 -#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1 -#define reg_bif_slave_rw_ack_intr_offset 68 - -/* Register r_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_intr___bus_release___lsb 0 -#define reg_bif_slave_r_intr___bus_release___width 1 -#define reg_bif_slave_r_intr___bus_release___bit 0 -#define reg_bif_slave_r_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_intr___bus_acquire___width 1 -#define reg_bif_slave_r_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_intr_offset 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -#define reg_bif_slave_r_masked_intr___bus_release___lsb 0 -#define reg_bif_slave_r_masked_intr___bus_release___width 1 -#define reg_bif_slave_r_masked_intr___bus_release___bit 0 -#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___width 1 -#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1 -#define reg_bif_slave_r_masked_intr_offset 76 - - -/* Constants */ -#define regk_bif_slave_active_hi 0x00000003 -#define regk_bif_slave_active_lo 0x00000002 -#define regk_bif_slave_addr 0x00000000 -#define regk_bif_slave_always 0x00000001 -#define regk_bif_slave_at_idle 0x00000002 -#define regk_bif_slave_burst_end 0x00000003 -#define regk_bif_slave_dma 0x00000001 -#define regk_bif_slave_hi 0x00000003 -#define regk_bif_slave_inv 0x00000001 -#define regk_bif_slave_lo 0x00000002 -#define regk_bif_slave_local 0x00000001 -#define regk_bif_slave_master 0x00000000 -#define regk_bif_slave_mode_reg 0x00000001 -#define regk_bif_slave_no 0x00000000 -#define regk_bif_slave_norm 0x00000000 -#define regk_bif_slave_on_access 0x00000000 -#define regk_bif_slave_rw_arb_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch0_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch1_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch2_cfg_default 0x00000000 -#define regk_bif_slave_rw_ch3_cfg_default 0x00000000 -#define regk_bif_slave_rw_intr_mask_default 0x00000000 -#define regk_bif_slave_rw_slave_cfg_default 0x00000000 -#define regk_bif_slave_shared 0x00000000 -#define regk_bif_slave_slave 0x00000001 -#define regk_bif_slave_t0ns 0x00000003 -#define regk_bif_slave_t10ns 0x00000002 -#define regk_bif_slave_t20ns 0x00000003 -#define regk_bif_slave_t30ns 0x00000002 -#define regk_bif_slave_t40ns 0x00000001 -#define regk_bif_slave_t50ns 0x00000000 -#define regk_bif_slave_yes 0x00000001 -#define regk_bif_slave_z 0x00000004 -#endif /* __bif_slave_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h deleted file mode 100644 index 6455b4897bcc..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h deleted file mode 100644 index 8370aee8a14a..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h +++ /dev/null @@ -1,41 +0,0 @@ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h deleted file mode 100644 index bd048296d2f8..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __cris_defs_asm_h -#define __cris_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/crisp/doc/cris.r - * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp - * last modfied: Mon Apr 11 16:06:39 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r - * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gc_cfg, scope cris, type rw */ -#define reg_cris_rw_gc_cfg___ic___lsb 0 -#define reg_cris_rw_gc_cfg___ic___width 1 -#define reg_cris_rw_gc_cfg___ic___bit 0 -#define reg_cris_rw_gc_cfg___dc___lsb 1 -#define reg_cris_rw_gc_cfg___dc___width 1 -#define reg_cris_rw_gc_cfg___dc___bit 1 -#define reg_cris_rw_gc_cfg___im___lsb 2 -#define reg_cris_rw_gc_cfg___im___width 1 -#define reg_cris_rw_gc_cfg___im___bit 2 -#define reg_cris_rw_gc_cfg___dm___lsb 3 -#define reg_cris_rw_gc_cfg___dm___width 1 -#define reg_cris_rw_gc_cfg___dm___bit 3 -#define reg_cris_rw_gc_cfg___gb___lsb 4 -#define reg_cris_rw_gc_cfg___gb___width 1 -#define reg_cris_rw_gc_cfg___gb___bit 4 -#define reg_cris_rw_gc_cfg___gk___lsb 5 -#define reg_cris_rw_gc_cfg___gk___width 1 -#define reg_cris_rw_gc_cfg___gk___bit 5 -#define reg_cris_rw_gc_cfg___gp___lsb 6 -#define reg_cris_rw_gc_cfg___gp___width 1 -#define reg_cris_rw_gc_cfg___gp___bit 6 -#define reg_cris_rw_gc_cfg_offset 0 - -/* Register rw_gc_ccs, scope cris, type rw */ -#define reg_cris_rw_gc_ccs_offset 4 - -/* Register rw_gc_srs, scope cris, type rw */ -#define reg_cris_rw_gc_srs___srs___lsb 0 -#define reg_cris_rw_gc_srs___srs___width 8 -#define reg_cris_rw_gc_srs_offset 8 - -/* Register rw_gc_nrp, scope cris, type rw */ -#define reg_cris_rw_gc_nrp_offset 12 - -/* Register rw_gc_exs, scope cris, type rw */ -#define reg_cris_rw_gc_exs_offset 16 - -/* Register rw_gc_eda, scope cris, type rw */ -#define reg_cris_rw_gc_eda_offset 20 - -/* Register rw_gc_r0, scope cris, type rw */ -#define reg_cris_rw_gc_r0_offset 32 - -/* Register rw_gc_r1, scope cris, type rw */ -#define reg_cris_rw_gc_r1_offset 36 - -/* Register rw_gc_r2, scope cris, type rw */ -#define reg_cris_rw_gc_r2_offset 40 - -/* Register rw_gc_r3, scope cris, type rw */ -#define reg_cris_rw_gc_r3_offset 44 - - -/* Constants */ -#define regk_cris_no 0x00000000 -#define regk_cris_rw_gc_cfg_default 0x00000000 -#define regk_cris_yes 0x00000001 -#endif /* __cris_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h deleted file mode 100644 index 429fe0d4ffe4..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_EDA 5 -#define RW_GC_R0 8 -#define RW_GC_R1 9 -#define RW_GC_R2 10 -#define RW_GC_R3 11 diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h deleted file mode 100644 index fec451d2a3db..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __dma_defs_asm_h -#define __dma_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope dma, type rw */ -#define reg_dma_rw_data_offset 0 - -/* Register rw_data_next, scope dma, type rw */ -#define reg_dma_rw_data_next_offset 4 - -/* Register rw_data_buf, scope dma, type rw */ -#define reg_dma_rw_data_buf_offset 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -#define reg_dma_rw_data_ctrl___eol___lsb 0 -#define reg_dma_rw_data_ctrl___eol___width 1 -#define reg_dma_rw_data_ctrl___eol___bit 0 -#define reg_dma_rw_data_ctrl___out_eop___lsb 3 -#define reg_dma_rw_data_ctrl___out_eop___width 1 -#define reg_dma_rw_data_ctrl___out_eop___bit 3 -#define reg_dma_rw_data_ctrl___intr___lsb 4 -#define reg_dma_rw_data_ctrl___intr___width 1 -#define reg_dma_rw_data_ctrl___intr___bit 4 -#define reg_dma_rw_data_ctrl___wait___lsb 5 -#define reg_dma_rw_data_ctrl___wait___width 1 -#define reg_dma_rw_data_ctrl___wait___bit 5 -#define reg_dma_rw_data_ctrl_offset 12 - -/* Register rw_data_stat, scope dma, type rw */ -#define reg_dma_rw_data_stat___in_eop___lsb 3 -#define reg_dma_rw_data_stat___in_eop___width 1 -#define reg_dma_rw_data_stat___in_eop___bit 3 -#define reg_dma_rw_data_stat_offset 16 - -/* Register rw_data_md, scope dma, type rw */ -#define reg_dma_rw_data_md___md___lsb 0 -#define reg_dma_rw_data_md___md___width 16 -#define reg_dma_rw_data_md_offset 20 - -/* Register rw_data_md_s, scope dma, type rw */ -#define reg_dma_rw_data_md_s___md_s___lsb 0 -#define reg_dma_rw_data_md_s___md_s___width 16 -#define reg_dma_rw_data_md_s_offset 24 - -/* Register rw_data_after, scope dma, type rw */ -#define reg_dma_rw_data_after_offset 28 - -/* Register rw_ctxt, scope dma, type rw */ -#define reg_dma_rw_ctxt_offset 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -#define reg_dma_rw_ctxt_next_offset 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -#define reg_dma_rw_ctxt_ctrl___eol___lsb 0 -#define reg_dma_rw_ctxt_ctrl___eol___width 1 -#define reg_dma_rw_ctxt_ctrl___eol___bit 0 -#define reg_dma_rw_ctxt_ctrl___intr___lsb 4 -#define reg_dma_rw_ctxt_ctrl___intr___width 1 -#define reg_dma_rw_ctxt_ctrl___intr___bit 4 -#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6 -#define reg_dma_rw_ctxt_ctrl___store_mode___width 1 -#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6 -#define reg_dma_rw_ctxt_ctrl___en___lsb 7 -#define reg_dma_rw_ctxt_ctrl___en___width 1 -#define reg_dma_rw_ctxt_ctrl___en___bit 7 -#define reg_dma_rw_ctxt_ctrl_offset 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -#define reg_dma_rw_ctxt_stat___dis___lsb 7 -#define reg_dma_rw_ctxt_stat___dis___width 1 -#define reg_dma_rw_ctxt_stat___dis___bit 7 -#define reg_dma_rw_ctxt_stat_offset 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0___md0___lsb 0 -#define reg_dma_rw_ctxt_md0___md0___width 16 -#define reg_dma_rw_ctxt_md0_offset 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0 -#define reg_dma_rw_ctxt_md0_s___md0_s___width 16 -#define reg_dma_rw_ctxt_md0_s_offset 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_offset 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md1_s_offset 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_offset 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md2_s_offset 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_offset 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md3_s_offset 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_offset 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -#define reg_dma_rw_ctxt_md4_s_offset 84 - -/* Register rw_saved_data, scope dma, type rw */ -#define reg_dma_rw_saved_data_offset 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -#define reg_dma_rw_saved_data_buf_offset 92 - -/* Register rw_group, scope dma, type rw */ -#define reg_dma_rw_group_offset 96 - -/* Register rw_group_next, scope dma, type rw */ -#define reg_dma_rw_group_next_offset 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -#define reg_dma_rw_group_ctrl___eol___lsb 0 -#define reg_dma_rw_group_ctrl___eol___width 1 -#define reg_dma_rw_group_ctrl___eol___bit 0 -#define reg_dma_rw_group_ctrl___tol___lsb 1 -#define reg_dma_rw_group_ctrl___tol___width 1 -#define reg_dma_rw_group_ctrl___tol___bit 1 -#define reg_dma_rw_group_ctrl___bol___lsb 2 -#define reg_dma_rw_group_ctrl___bol___width 1 -#define reg_dma_rw_group_ctrl___bol___bit 2 -#define reg_dma_rw_group_ctrl___intr___lsb 4 -#define reg_dma_rw_group_ctrl___intr___width 1 -#define reg_dma_rw_group_ctrl___intr___bit 4 -#define reg_dma_rw_group_ctrl___en___lsb 7 -#define reg_dma_rw_group_ctrl___en___width 1 -#define reg_dma_rw_group_ctrl___en___bit 7 -#define reg_dma_rw_group_ctrl_offset 104 - -/* Register rw_group_stat, scope dma, type rw */ -#define reg_dma_rw_group_stat___dis___lsb 7 -#define reg_dma_rw_group_stat___dis___width 1 -#define reg_dma_rw_group_stat___dis___bit 7 -#define reg_dma_rw_group_stat_offset 108 - -/* Register rw_group_md, scope dma, type rw */ -#define reg_dma_rw_group_md___md___lsb 0 -#define reg_dma_rw_group_md___md___width 16 -#define reg_dma_rw_group_md_offset 112 - -/* Register rw_group_md_s, scope dma, type rw */ -#define reg_dma_rw_group_md_s___md_s___lsb 0 -#define reg_dma_rw_group_md_s___md_s___width 16 -#define reg_dma_rw_group_md_s_offset 116 - -/* Register rw_group_up, scope dma, type rw */ -#define reg_dma_rw_group_up_offset 120 - -/* Register rw_group_down, scope dma, type rw */ -#define reg_dma_rw_group_down_offset 124 - -/* Register rw_cmd, scope dma, type rw */ -#define reg_dma_rw_cmd___cont_data___lsb 0 -#define reg_dma_rw_cmd___cont_data___width 1 -#define reg_dma_rw_cmd___cont_data___bit 0 -#define reg_dma_rw_cmd_offset 128 - -/* Register rw_cfg, scope dma, type rw */ -#define reg_dma_rw_cfg___en___lsb 0 -#define reg_dma_rw_cfg___en___width 1 -#define reg_dma_rw_cfg___en___bit 0 -#define reg_dma_rw_cfg___stop___lsb 1 -#define reg_dma_rw_cfg___stop___width 1 -#define reg_dma_rw_cfg___stop___bit 1 -#define reg_dma_rw_cfg_offset 132 - -/* Register rw_stat, scope dma, type rw */ -#define reg_dma_rw_stat___mode___lsb 0 -#define reg_dma_rw_stat___mode___width 5 -#define reg_dma_rw_stat___list_state___lsb 5 -#define reg_dma_rw_stat___list_state___width 3 -#define reg_dma_rw_stat___stream_cmd_src___lsb 8 -#define reg_dma_rw_stat___stream_cmd_src___width 8 -#define reg_dma_rw_stat___buf___lsb 24 -#define reg_dma_rw_stat___buf___width 8 -#define reg_dma_rw_stat_offset 136 - -/* Register rw_intr_mask, scope dma, type rw */ -#define reg_dma_rw_intr_mask___group___lsb 0 -#define reg_dma_rw_intr_mask___group___width 1 -#define reg_dma_rw_intr_mask___group___bit 0 -#define reg_dma_rw_intr_mask___ctxt___lsb 1 -#define reg_dma_rw_intr_mask___ctxt___width 1 -#define reg_dma_rw_intr_mask___ctxt___bit 1 -#define reg_dma_rw_intr_mask___data___lsb 2 -#define reg_dma_rw_intr_mask___data___width 1 -#define reg_dma_rw_intr_mask___data___bit 2 -#define reg_dma_rw_intr_mask___in_eop___lsb 3 -#define reg_dma_rw_intr_mask___in_eop___width 1 -#define reg_dma_rw_intr_mask___in_eop___bit 3 -#define reg_dma_rw_intr_mask___stream_cmd___lsb 4 -#define reg_dma_rw_intr_mask___stream_cmd___width 1 -#define reg_dma_rw_intr_mask___stream_cmd___bit 4 -#define reg_dma_rw_intr_mask_offset 140 - -/* Register rw_ack_intr, scope dma, type rw */ -#define reg_dma_rw_ack_intr___group___lsb 0 -#define reg_dma_rw_ack_intr___group___width 1 -#define reg_dma_rw_ack_intr___group___bit 0 -#define reg_dma_rw_ack_intr___ctxt___lsb 1 -#define reg_dma_rw_ack_intr___ctxt___width 1 -#define reg_dma_rw_ack_intr___ctxt___bit 1 -#define reg_dma_rw_ack_intr___data___lsb 2 -#define reg_dma_rw_ack_intr___data___width 1 -#define reg_dma_rw_ack_intr___data___bit 2 -#define reg_dma_rw_ack_intr___in_eop___lsb 3 -#define reg_dma_rw_ack_intr___in_eop___width 1 -#define reg_dma_rw_ack_intr___in_eop___bit 3 -#define reg_dma_rw_ack_intr___stream_cmd___lsb 4 -#define reg_dma_rw_ack_intr___stream_cmd___width 1 -#define reg_dma_rw_ack_intr___stream_cmd___bit 4 -#define reg_dma_rw_ack_intr_offset 144 - -/* Register r_intr, scope dma, type r */ -#define reg_dma_r_intr___group___lsb 0 -#define reg_dma_r_intr___group___width 1 -#define reg_dma_r_intr___group___bit 0 -#define reg_dma_r_intr___ctxt___lsb 1 -#define reg_dma_r_intr___ctxt___width 1 -#define reg_dma_r_intr___ctxt___bit 1 -#define reg_dma_r_intr___data___lsb 2 -#define reg_dma_r_intr___data___width 1 -#define reg_dma_r_intr___data___bit 2 -#define reg_dma_r_intr___in_eop___lsb 3 -#define reg_dma_r_intr___in_eop___width 1 -#define reg_dma_r_intr___in_eop___bit 3 -#define reg_dma_r_intr___stream_cmd___lsb 4 -#define reg_dma_r_intr___stream_cmd___width 1 -#define reg_dma_r_intr___stream_cmd___bit 4 -#define reg_dma_r_intr_offset 148 - -/* Register r_masked_intr, scope dma, type r */ -#define reg_dma_r_masked_intr___group___lsb 0 -#define reg_dma_r_masked_intr___group___width 1 -#define reg_dma_r_masked_intr___group___bit 0 -#define reg_dma_r_masked_intr___ctxt___lsb 1 -#define reg_dma_r_masked_intr___ctxt___width 1 -#define reg_dma_r_masked_intr___ctxt___bit 1 -#define reg_dma_r_masked_intr___data___lsb 2 -#define reg_dma_r_masked_intr___data___width 1 -#define reg_dma_r_masked_intr___data___bit 2 -#define reg_dma_r_masked_intr___in_eop___lsb 3 -#define reg_dma_r_masked_intr___in_eop___width 1 -#define reg_dma_r_masked_intr___in_eop___bit 3 -#define reg_dma_r_masked_intr___stream_cmd___lsb 4 -#define reg_dma_r_masked_intr___stream_cmd___width 1 -#define reg_dma_r_masked_intr___stream_cmd___bit 4 -#define reg_dma_r_masked_intr_offset 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -#define reg_dma_rw_stream_cmd___cmd___lsb 0 -#define reg_dma_rw_stream_cmd___cmd___width 10 -#define reg_dma_rw_stream_cmd___n___lsb 16 -#define reg_dma_rw_stream_cmd___n___width 8 -#define reg_dma_rw_stream_cmd___busy___lsb 31 -#define reg_dma_rw_stream_cmd___busy___width 1 -#define reg_dma_rw_stream_cmd___busy___bit 31 -#define reg_dma_rw_stream_cmd_offset 156 - - -/* Constants */ -#define regk_dma_ack_pkt 0x00000100 -#define regk_dma_anytime 0x00000001 -#define regk_dma_array 0x00000008 -#define regk_dma_burst 0x00000020 -#define regk_dma_client 0x00000002 -#define regk_dma_copy_next 0x00000010 -#define regk_dma_copy_up 0x00000020 -#define regk_dma_data_at_eol 0x00000001 -#define regk_dma_dis_c 0x00000010 -#define regk_dma_dis_g 0x00000020 -#define regk_dma_idle 0x00000001 -#define regk_dma_intern 0x00000004 -#define regk_dma_load_c 0x00000200 -#define regk_dma_load_c_n 0x00000280 -#define regk_dma_load_c_next 0x00000240 -#define regk_dma_load_d 0x00000140 -#define regk_dma_load_g 0x00000300 -#define regk_dma_load_g_down 0x000003c0 -#define regk_dma_load_g_next 0x00000340 -#define regk_dma_load_g_up 0x00000380 -#define regk_dma_next_en 0x00000010 -#define regk_dma_next_pkt 0x00000010 -#define regk_dma_no 0x00000000 -#define regk_dma_only_at_wait 0x00000000 -#define regk_dma_restore 0x00000020 -#define regk_dma_rst 0x00000001 -#define regk_dma_running 0x00000004 -#define regk_dma_rw_cfg_default 0x00000000 -#define regk_dma_rw_cmd_default 0x00000000 -#define regk_dma_rw_intr_mask_default 0x00000000 -#define regk_dma_rw_stat_default 0x00000101 -#define regk_dma_rw_stream_cmd_default 0x00000000 -#define regk_dma_save_down 0x00000020 -#define regk_dma_save_up 0x00000020 -#define regk_dma_set_reg 0x00000050 -#define regk_dma_set_w_size1 0x00000190 -#define regk_dma_set_w_size2 0x000001a0 -#define regk_dma_set_w_size4 0x000001c0 -#define regk_dma_stopped 0x00000002 -#define regk_dma_store_c 0x00000002 -#define regk_dma_store_descr 0x00000000 -#define regk_dma_store_g 0x00000004 -#define regk_dma_store_md 0x00000001 -#define regk_dma_sw 0x00000008 -#define regk_dma_update_down 0x00000020 -#define regk_dma_yes 0x00000001 -#endif /* __dma_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h deleted file mode 100644 index 97fe523d4d72..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h +++ /dev/null @@ -1,499 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __eth_defs_asm_h -#define __eth_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/eth/rtl/eth_regs.r - * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp - * last modfied: Mon Apr 11 16:07:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r - * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_ma0_lo, scope eth, type rw */ -#define reg_eth_rw_ma0_lo___addr___lsb 0 -#define reg_eth_rw_ma0_lo___addr___width 32 -#define reg_eth_rw_ma0_lo_offset 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -#define reg_eth_rw_ma0_hi___addr___lsb 0 -#define reg_eth_rw_ma0_hi___addr___width 16 -#define reg_eth_rw_ma0_hi_offset 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -#define reg_eth_rw_ma1_lo___addr___lsb 0 -#define reg_eth_rw_ma1_lo___addr___width 32 -#define reg_eth_rw_ma1_lo_offset 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -#define reg_eth_rw_ma1_hi___addr___lsb 0 -#define reg_eth_rw_ma1_hi___addr___width 16 -#define reg_eth_rw_ma1_hi_offset 12 - -/* Register rw_ga_lo, scope eth, type rw */ -#define reg_eth_rw_ga_lo___table___lsb 0 -#define reg_eth_rw_ga_lo___table___width 32 -#define reg_eth_rw_ga_lo_offset 16 - -/* Register rw_ga_hi, scope eth, type rw */ -#define reg_eth_rw_ga_hi___table___lsb 0 -#define reg_eth_rw_ga_hi___table___width 32 -#define reg_eth_rw_ga_hi_offset 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -#define reg_eth_rw_gen_ctrl___en___lsb 0 -#define reg_eth_rw_gen_ctrl___en___width 1 -#define reg_eth_rw_gen_ctrl___en___bit 0 -#define reg_eth_rw_gen_ctrl___phy___lsb 1 -#define reg_eth_rw_gen_ctrl___phy___width 2 -#define reg_eth_rw_gen_ctrl___protocol___lsb 3 -#define reg_eth_rw_gen_ctrl___protocol___width 1 -#define reg_eth_rw_gen_ctrl___protocol___bit 3 -#define reg_eth_rw_gen_ctrl___loopback___lsb 4 -#define reg_eth_rw_gen_ctrl___loopback___width 1 -#define reg_eth_rw_gen_ctrl___loopback___bit 4 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1 -#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5 -#define reg_eth_rw_gen_ctrl_offset 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -#define reg_eth_rw_rec_ctrl___ma0___lsb 0 -#define reg_eth_rw_rec_ctrl___ma0___width 1 -#define reg_eth_rw_rec_ctrl___ma0___bit 0 -#define reg_eth_rw_rec_ctrl___ma1___lsb 1 -#define reg_eth_rw_rec_ctrl___ma1___width 1 -#define reg_eth_rw_rec_ctrl___ma1___bit 1 -#define reg_eth_rw_rec_ctrl___individual___lsb 2 -#define reg_eth_rw_rec_ctrl___individual___width 1 -#define reg_eth_rw_rec_ctrl___individual___bit 2 -#define reg_eth_rw_rec_ctrl___broadcast___lsb 3 -#define reg_eth_rw_rec_ctrl___broadcast___width 1 -#define reg_eth_rw_rec_ctrl___broadcast___bit 3 -#define reg_eth_rw_rec_ctrl___undersize___lsb 4 -#define reg_eth_rw_rec_ctrl___undersize___width 1 -#define reg_eth_rw_rec_ctrl___undersize___bit 4 -#define reg_eth_rw_rec_ctrl___oversize___lsb 5 -#define reg_eth_rw_rec_ctrl___oversize___width 1 -#define reg_eth_rw_rec_ctrl___oversize___bit 5 -#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6 -#define reg_eth_rw_rec_ctrl___bad_crc___width 1 -#define reg_eth_rw_rec_ctrl___bad_crc___bit 6 -#define reg_eth_rw_rec_ctrl___duplex___lsb 7 -#define reg_eth_rw_rec_ctrl___duplex___width 1 -#define reg_eth_rw_rec_ctrl___duplex___bit 7 -#define reg_eth_rw_rec_ctrl___max_size___lsb 8 -#define reg_eth_rw_rec_ctrl___max_size___width 1 -#define reg_eth_rw_rec_ctrl___max_size___bit 8 -#define reg_eth_rw_rec_ctrl_offset 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -#define reg_eth_rw_tr_ctrl___crc___lsb 0 -#define reg_eth_rw_tr_ctrl___crc___width 1 -#define reg_eth_rw_tr_ctrl___crc___bit 0 -#define reg_eth_rw_tr_ctrl___pad___lsb 1 -#define reg_eth_rw_tr_ctrl___pad___width 1 -#define reg_eth_rw_tr_ctrl___pad___bit 1 -#define reg_eth_rw_tr_ctrl___retry___lsb 2 -#define reg_eth_rw_tr_ctrl___retry___width 1 -#define reg_eth_rw_tr_ctrl___retry___bit 2 -#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3 -#define reg_eth_rw_tr_ctrl___ignore_col___width 1 -#define reg_eth_rw_tr_ctrl___ignore_col___bit 3 -#define reg_eth_rw_tr_ctrl___cancel___lsb 4 -#define reg_eth_rw_tr_ctrl___cancel___width 1 -#define reg_eth_rw_tr_ctrl___cancel___bit 4 -#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5 -#define reg_eth_rw_tr_ctrl___hsh_delay___width 1 -#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5 -#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6 -#define reg_eth_rw_tr_ctrl___ignore_crs___width 1 -#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6 -#define reg_eth_rw_tr_ctrl_offset 32 - -/* Register rw_clr_err, scope eth, type rw */ -#define reg_eth_rw_clr_err___clr___lsb 0 -#define reg_eth_rw_clr_err___clr___width 1 -#define reg_eth_rw_clr_err___clr___bit 0 -#define reg_eth_rw_clr_err_offset 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -#define reg_eth_rw_mgm_ctrl___mdio___lsb 0 -#define reg_eth_rw_mgm_ctrl___mdio___width 1 -#define reg_eth_rw_mgm_ctrl___mdio___bit 0 -#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1 -#define reg_eth_rw_mgm_ctrl___mdoe___width 1 -#define reg_eth_rw_mgm_ctrl___mdoe___bit 1 -#define reg_eth_rw_mgm_ctrl___mdc___lsb 2 -#define reg_eth_rw_mgm_ctrl___mdc___width 1 -#define reg_eth_rw_mgm_ctrl___mdc___bit 2 -#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3 -#define reg_eth_rw_mgm_ctrl___phyclk___width 1 -#define reg_eth_rw_mgm_ctrl___phyclk___bit 3 -#define reg_eth_rw_mgm_ctrl___txdata___lsb 4 -#define reg_eth_rw_mgm_ctrl___txdata___width 4 -#define reg_eth_rw_mgm_ctrl___txen___lsb 8 -#define reg_eth_rw_mgm_ctrl___txen___width 1 -#define reg_eth_rw_mgm_ctrl___txen___bit 8 -#define reg_eth_rw_mgm_ctrl_offset 40 - -/* Register r_stat, scope eth, type r */ -#define reg_eth_r_stat___mdio___lsb 0 -#define reg_eth_r_stat___mdio___width 1 -#define reg_eth_r_stat___mdio___bit 0 -#define reg_eth_r_stat___exc_col___lsb 1 -#define reg_eth_r_stat___exc_col___width 1 -#define reg_eth_r_stat___exc_col___bit 1 -#define reg_eth_r_stat___urun___lsb 2 -#define reg_eth_r_stat___urun___width 1 -#define reg_eth_r_stat___urun___bit 2 -#define reg_eth_r_stat___phyclk___lsb 3 -#define reg_eth_r_stat___phyclk___width 1 -#define reg_eth_r_stat___phyclk___bit 3 -#define reg_eth_r_stat___txdata___lsb 4 -#define reg_eth_r_stat___txdata___width 4 -#define reg_eth_r_stat___txen___lsb 8 -#define reg_eth_r_stat___txen___width 1 -#define reg_eth_r_stat___txen___bit 8 -#define reg_eth_r_stat___col___lsb 9 -#define reg_eth_r_stat___col___width 1 -#define reg_eth_r_stat___col___bit 9 -#define reg_eth_r_stat___crs___lsb 10 -#define reg_eth_r_stat___crs___width 1 -#define reg_eth_r_stat___crs___bit 10 -#define reg_eth_r_stat___txclk___lsb 11 -#define reg_eth_r_stat___txclk___width 1 -#define reg_eth_r_stat___txclk___bit 11 -#define reg_eth_r_stat___rxdata___lsb 12 -#define reg_eth_r_stat___rxdata___width 4 -#define reg_eth_r_stat___rxer___lsb 16 -#define reg_eth_r_stat___rxer___width 1 -#define reg_eth_r_stat___rxer___bit 16 -#define reg_eth_r_stat___rxdv___lsb 17 -#define reg_eth_r_stat___rxdv___width 1 -#define reg_eth_r_stat___rxdv___bit 17 -#define reg_eth_r_stat___rxclk___lsb 18 -#define reg_eth_r_stat___rxclk___width 1 -#define reg_eth_r_stat___rxclk___bit 18 -#define reg_eth_r_stat_offset 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -#define reg_eth_rs_rec_cnt___crc_err___lsb 0 -#define reg_eth_rs_rec_cnt___crc_err___width 8 -#define reg_eth_rs_rec_cnt___align_err___lsb 8 -#define reg_eth_rs_rec_cnt___align_err___width 8 -#define reg_eth_rs_rec_cnt___oversize___lsb 16 -#define reg_eth_rs_rec_cnt___oversize___width 8 -#define reg_eth_rs_rec_cnt___congestion___lsb 24 -#define reg_eth_rs_rec_cnt___congestion___width 8 -#define reg_eth_rs_rec_cnt_offset 48 - -/* Register r_rec_cnt, scope eth, type r */ -#define reg_eth_r_rec_cnt___crc_err___lsb 0 -#define reg_eth_r_rec_cnt___crc_err___width 8 -#define reg_eth_r_rec_cnt___align_err___lsb 8 -#define reg_eth_r_rec_cnt___align_err___width 8 -#define reg_eth_r_rec_cnt___oversize___lsb 16 -#define reg_eth_r_rec_cnt___oversize___width 8 -#define reg_eth_r_rec_cnt___congestion___lsb 24 -#define reg_eth_r_rec_cnt___congestion___width 8 -#define reg_eth_r_rec_cnt_offset 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -#define reg_eth_rs_tr_cnt___single_col___lsb 0 -#define reg_eth_rs_tr_cnt___single_col___width 8 -#define reg_eth_rs_tr_cnt___mult_col___lsb 8 -#define reg_eth_rs_tr_cnt___mult_col___width 8 -#define reg_eth_rs_tr_cnt___late_col___lsb 16 -#define reg_eth_rs_tr_cnt___late_col___width 8 -#define reg_eth_rs_tr_cnt___deferred___lsb 24 -#define reg_eth_rs_tr_cnt___deferred___width 8 -#define reg_eth_rs_tr_cnt_offset 56 - -/* Register r_tr_cnt, scope eth, type r */ -#define reg_eth_r_tr_cnt___single_col___lsb 0 -#define reg_eth_r_tr_cnt___single_col___width 8 -#define reg_eth_r_tr_cnt___mult_col___lsb 8 -#define reg_eth_r_tr_cnt___mult_col___width 8 -#define reg_eth_r_tr_cnt___late_col___lsb 16 -#define reg_eth_r_tr_cnt___late_col___width 8 -#define reg_eth_r_tr_cnt___deferred___lsb 24 -#define reg_eth_r_tr_cnt___deferred___width 8 -#define reg_eth_r_tr_cnt_offset 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_rs_phy_cnt___carrier_loss___width 8 -#define reg_eth_rs_phy_cnt___sqe_err___lsb 8 -#define reg_eth_rs_phy_cnt___sqe_err___width 8 -#define reg_eth_rs_phy_cnt_offset 64 - -/* Register r_phy_cnt, scope eth, type r */ -#define reg_eth_r_phy_cnt___carrier_loss___lsb 0 -#define reg_eth_r_phy_cnt___carrier_loss___width 8 -#define reg_eth_r_phy_cnt___sqe_err___lsb 8 -#define reg_eth_r_phy_cnt___sqe_err___width 8 -#define reg_eth_r_phy_cnt_offset 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0 -#define reg_eth_rw_test_ctrl___snmp_inc___width 1 -#define reg_eth_rw_test_ctrl___snmp_inc___bit 0 -#define reg_eth_rw_test_ctrl___snmp___lsb 1 -#define reg_eth_rw_test_ctrl___snmp___width 1 -#define reg_eth_rw_test_ctrl___snmp___bit 1 -#define reg_eth_rw_test_ctrl___backoff___lsb 2 -#define reg_eth_rw_test_ctrl___backoff___width 1 -#define reg_eth_rw_test_ctrl___backoff___bit 2 -#define reg_eth_rw_test_ctrl_offset 72 - -/* Register rw_intr_mask, scope eth, type rw */ -#define reg_eth_rw_intr_mask___crc___lsb 0 -#define reg_eth_rw_intr_mask___crc___width 1 -#define reg_eth_rw_intr_mask___crc___bit 0 -#define reg_eth_rw_intr_mask___align___lsb 1 -#define reg_eth_rw_intr_mask___align___width 1 -#define reg_eth_rw_intr_mask___align___bit 1 -#define reg_eth_rw_intr_mask___oversize___lsb 2 -#define reg_eth_rw_intr_mask___oversize___width 1 -#define reg_eth_rw_intr_mask___oversize___bit 2 -#define reg_eth_rw_intr_mask___congestion___lsb 3 -#define reg_eth_rw_intr_mask___congestion___width 1 -#define reg_eth_rw_intr_mask___congestion___bit 3 -#define reg_eth_rw_intr_mask___single_col___lsb 4 -#define reg_eth_rw_intr_mask___single_col___width 1 -#define reg_eth_rw_intr_mask___single_col___bit 4 -#define reg_eth_rw_intr_mask___mult_col___lsb 5 -#define reg_eth_rw_intr_mask___mult_col___width 1 -#define reg_eth_rw_intr_mask___mult_col___bit 5 -#define reg_eth_rw_intr_mask___late_col___lsb 6 -#define reg_eth_rw_intr_mask___late_col___width 1 -#define reg_eth_rw_intr_mask___late_col___bit 6 -#define reg_eth_rw_intr_mask___deferred___lsb 7 -#define reg_eth_rw_intr_mask___deferred___width 1 -#define reg_eth_rw_intr_mask___deferred___bit 7 -#define reg_eth_rw_intr_mask___carrier_loss___lsb 8 -#define reg_eth_rw_intr_mask___carrier_loss___width 1 -#define reg_eth_rw_intr_mask___carrier_loss___bit 8 -#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9 -#define reg_eth_rw_intr_mask___sqe_test_err___width 1 -#define reg_eth_rw_intr_mask___sqe_test_err___bit 9 -#define reg_eth_rw_intr_mask___orun___lsb 10 -#define reg_eth_rw_intr_mask___orun___width 1 -#define reg_eth_rw_intr_mask___orun___bit 10 -#define reg_eth_rw_intr_mask___urun___lsb 11 -#define reg_eth_rw_intr_mask___urun___width 1 -#define reg_eth_rw_intr_mask___urun___bit 11 -#define reg_eth_rw_intr_mask___excessive_col___lsb 12 -#define reg_eth_rw_intr_mask___excessive_col___width 1 -#define reg_eth_rw_intr_mask___excessive_col___bit 12 -#define reg_eth_rw_intr_mask___mdio___lsb 13 -#define reg_eth_rw_intr_mask___mdio___width 1 -#define reg_eth_rw_intr_mask___mdio___bit 13 -#define reg_eth_rw_intr_mask_offset 76 - -/* Register rw_ack_intr, scope eth, type rw */ -#define reg_eth_rw_ack_intr___crc___lsb 0 -#define reg_eth_rw_ack_intr___crc___width 1 -#define reg_eth_rw_ack_intr___crc___bit 0 -#define reg_eth_rw_ack_intr___align___lsb 1 -#define reg_eth_rw_ack_intr___align___width 1 -#define reg_eth_rw_ack_intr___align___bit 1 -#define reg_eth_rw_ack_intr___oversize___lsb 2 -#define reg_eth_rw_ack_intr___oversize___width 1 -#define reg_eth_rw_ack_intr___oversize___bit 2 -#define reg_eth_rw_ack_intr___congestion___lsb 3 -#define reg_eth_rw_ack_intr___congestion___width 1 -#define reg_eth_rw_ack_intr___congestion___bit 3 -#define reg_eth_rw_ack_intr___single_col___lsb 4 -#define reg_eth_rw_ack_intr___single_col___width 1 -#define reg_eth_rw_ack_intr___single_col___bit 4 -#define reg_eth_rw_ack_intr___mult_col___lsb 5 -#define reg_eth_rw_ack_intr___mult_col___width 1 -#define reg_eth_rw_ack_intr___mult_col___bit 5 -#define reg_eth_rw_ack_intr___late_col___lsb 6 -#define reg_eth_rw_ack_intr___late_col___width 1 -#define reg_eth_rw_ack_intr___late_col___bit 6 -#define reg_eth_rw_ack_intr___deferred___lsb 7 -#define reg_eth_rw_ack_intr___deferred___width 1 -#define reg_eth_rw_ack_intr___deferred___bit 7 -#define reg_eth_rw_ack_intr___carrier_loss___lsb 8 -#define reg_eth_rw_ack_intr___carrier_loss___width 1 -#define reg_eth_rw_ack_intr___carrier_loss___bit 8 -#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9 -#define reg_eth_rw_ack_intr___sqe_test_err___width 1 -#define reg_eth_rw_ack_intr___sqe_test_err___bit 9 -#define reg_eth_rw_ack_intr___orun___lsb 10 -#define reg_eth_rw_ack_intr___orun___width 1 -#define reg_eth_rw_ack_intr___orun___bit 10 -#define reg_eth_rw_ack_intr___urun___lsb 11 -#define reg_eth_rw_ack_intr___urun___width 1 -#define reg_eth_rw_ack_intr___urun___bit 11 -#define reg_eth_rw_ack_intr___excessive_col___lsb 12 -#define reg_eth_rw_ack_intr___excessive_col___width 1 -#define reg_eth_rw_ack_intr___excessive_col___bit 12 -#define reg_eth_rw_ack_intr___mdio___lsb 13 -#define reg_eth_rw_ack_intr___mdio___width 1 -#define reg_eth_rw_ack_intr___mdio___bit 13 -#define reg_eth_rw_ack_intr_offset 80 - -/* Register r_intr, scope eth, type r */ -#define reg_eth_r_intr___crc___lsb 0 -#define reg_eth_r_intr___crc___width 1 -#define reg_eth_r_intr___crc___bit 0 -#define reg_eth_r_intr___align___lsb 1 -#define reg_eth_r_intr___align___width 1 -#define reg_eth_r_intr___align___bit 1 -#define reg_eth_r_intr___oversize___lsb 2 -#define reg_eth_r_intr___oversize___width 1 -#define reg_eth_r_intr___oversize___bit 2 -#define reg_eth_r_intr___congestion___lsb 3 -#define reg_eth_r_intr___congestion___width 1 -#define reg_eth_r_intr___congestion___bit 3 -#define reg_eth_r_intr___single_col___lsb 4 -#define reg_eth_r_intr___single_col___width 1 -#define reg_eth_r_intr___single_col___bit 4 -#define reg_eth_r_intr___mult_col___lsb 5 -#define reg_eth_r_intr___mult_col___width 1 -#define reg_eth_r_intr___mult_col___bit 5 -#define reg_eth_r_intr___late_col___lsb 6 -#define reg_eth_r_intr___late_col___width 1 -#define reg_eth_r_intr___late_col___bit 6 -#define reg_eth_r_intr___deferred___lsb 7 -#define reg_eth_r_intr___deferred___width 1 -#define reg_eth_r_intr___deferred___bit 7 -#define reg_eth_r_intr___carrier_loss___lsb 8 -#define reg_eth_r_intr___carrier_loss___width 1 -#define reg_eth_r_intr___carrier_loss___bit 8 -#define reg_eth_r_intr___sqe_test_err___lsb 9 -#define reg_eth_r_intr___sqe_test_err___width 1 -#define reg_eth_r_intr___sqe_test_err___bit 9 -#define reg_eth_r_intr___orun___lsb 10 -#define reg_eth_r_intr___orun___width 1 -#define reg_eth_r_intr___orun___bit 10 -#define reg_eth_r_intr___urun___lsb 11 -#define reg_eth_r_intr___urun___width 1 -#define reg_eth_r_intr___urun___bit 11 -#define reg_eth_r_intr___excessive_col___lsb 12 -#define reg_eth_r_intr___excessive_col___width 1 -#define reg_eth_r_intr___excessive_col___bit 12 -#define reg_eth_r_intr___mdio___lsb 13 -#define reg_eth_r_intr___mdio___width 1 -#define reg_eth_r_intr___mdio___bit 13 -#define reg_eth_r_intr_offset 84 - -/* Register r_masked_intr, scope eth, type r */ -#define reg_eth_r_masked_intr___crc___lsb 0 -#define reg_eth_r_masked_intr___crc___width 1 -#define reg_eth_r_masked_intr___crc___bit 0 -#define reg_eth_r_masked_intr___align___lsb 1 -#define reg_eth_r_masked_intr___align___width 1 -#define reg_eth_r_masked_intr___align___bit 1 -#define reg_eth_r_masked_intr___oversize___lsb 2 -#define reg_eth_r_masked_intr___oversize___width 1 -#define reg_eth_r_masked_intr___oversize___bit 2 -#define reg_eth_r_masked_intr___congestion___lsb 3 -#define reg_eth_r_masked_intr___congestion___width 1 -#define reg_eth_r_masked_intr___congestion___bit 3 -#define reg_eth_r_masked_intr___single_col___lsb 4 -#define reg_eth_r_masked_intr___single_col___width 1 -#define reg_eth_r_masked_intr___single_col___bit 4 -#define reg_eth_r_masked_intr___mult_col___lsb 5 -#define reg_eth_r_masked_intr___mult_col___width 1 -#define reg_eth_r_masked_intr___mult_col___bit 5 -#define reg_eth_r_masked_intr___late_col___lsb 6 -#define reg_eth_r_masked_intr___late_col___width 1 -#define reg_eth_r_masked_intr___late_col___bit 6 -#define reg_eth_r_masked_intr___deferred___lsb 7 -#define reg_eth_r_masked_intr___deferred___width 1 -#define reg_eth_r_masked_intr___deferred___bit 7 -#define reg_eth_r_masked_intr___carrier_loss___lsb 8 -#define reg_eth_r_masked_intr___carrier_loss___width 1 -#define reg_eth_r_masked_intr___carrier_loss___bit 8 -#define reg_eth_r_masked_intr___sqe_test_err___lsb 9 -#define reg_eth_r_masked_intr___sqe_test_err___width 1 -#define reg_eth_r_masked_intr___sqe_test_err___bit 9 -#define reg_eth_r_masked_intr___orun___lsb 10 -#define reg_eth_r_masked_intr___orun___width 1 -#define reg_eth_r_masked_intr___orun___bit 10 -#define reg_eth_r_masked_intr___urun___lsb 11 -#define reg_eth_r_masked_intr___urun___width 1 -#define reg_eth_r_masked_intr___urun___bit 11 -#define reg_eth_r_masked_intr___excessive_col___lsb 12 -#define reg_eth_r_masked_intr___excessive_col___width 1 -#define reg_eth_r_masked_intr___excessive_col___bit 12 -#define reg_eth_r_masked_intr___mdio___lsb 13 -#define reg_eth_r_masked_intr___mdio___width 1 -#define reg_eth_r_masked_intr___mdio___bit 13 -#define reg_eth_r_masked_intr_offset 88 - - -/* Constants */ -#define regk_eth_discard 0x00000000 -#define regk_eth_ether 0x00000000 -#define regk_eth_full 0x00000001 -#define regk_eth_half 0x00000000 -#define regk_eth_hsh 0x00000001 -#define regk_eth_mii 0x00000001 -#define regk_eth_mii_clk 0x00000000 -#define regk_eth_mii_rec 0x00000002 -#define regk_eth_no 0x00000000 -#define regk_eth_rec 0x00000001 -#define regk_eth_rw_ga_hi_default 0x00000000 -#define regk_eth_rw_ga_lo_default 0x00000000 -#define regk_eth_rw_gen_ctrl_default 0x00000000 -#define regk_eth_rw_intr_mask_default 0x00000000 -#define regk_eth_rw_ma0_hi_default 0x00000000 -#define regk_eth_rw_ma0_lo_default 0x00000000 -#define regk_eth_rw_ma1_hi_default 0x00000000 -#define regk_eth_rw_ma1_lo_default 0x00000000 -#define regk_eth_rw_mgm_ctrl_default 0x00000000 -#define regk_eth_rw_test_ctrl_default 0x00000000 -#define regk_eth_size1518 0x00000000 -#define regk_eth_size1522 0x00000001 -#define regk_eth_yes 0x00000001 -#endif /* __eth_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 41bc2f83795c..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h deleted file mode 100644 index e371052fa1bc..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e - -#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h deleted file mode 100644 index 8d0c788b286b..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h +++ /dev/null @@ -1,356 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __intr_vect_defs_asm_h -#define __intr_vect_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mask, scope intr_vect, type rw */ -#define reg_intr_vect_rw_mask___memarb___lsb 0 -#define reg_intr_vect_rw_mask___memarb___width 1 -#define reg_intr_vect_rw_mask___memarb___bit 0 -#define reg_intr_vect_rw_mask___gen_io___lsb 1 -#define reg_intr_vect_rw_mask___gen_io___width 1 -#define reg_intr_vect_rw_mask___gen_io___bit 1 -#define reg_intr_vect_rw_mask___iop0___lsb 2 -#define reg_intr_vect_rw_mask___iop0___width 1 -#define reg_intr_vect_rw_mask___iop0___bit 2 -#define reg_intr_vect_rw_mask___iop1___lsb 3 -#define reg_intr_vect_rw_mask___iop1___width 1 -#define reg_intr_vect_rw_mask___iop1___bit 3 -#define reg_intr_vect_rw_mask___iop2___lsb 4 -#define reg_intr_vect_rw_mask___iop2___width 1 -#define reg_intr_vect_rw_mask___iop2___bit 4 -#define reg_intr_vect_rw_mask___iop3___lsb 5 -#define reg_intr_vect_rw_mask___iop3___width 1 -#define reg_intr_vect_rw_mask___iop3___bit 5 -#define reg_intr_vect_rw_mask___dma0___lsb 6 -#define reg_intr_vect_rw_mask___dma0___width 1 -#define reg_intr_vect_rw_mask___dma0___bit 6 -#define reg_intr_vect_rw_mask___dma1___lsb 7 -#define reg_intr_vect_rw_mask___dma1___width 1 -#define reg_intr_vect_rw_mask___dma1___bit 7 -#define reg_intr_vect_rw_mask___dma2___lsb 8 -#define reg_intr_vect_rw_mask___dma2___width 1 -#define reg_intr_vect_rw_mask___dma2___bit 8 -#define reg_intr_vect_rw_mask___dma3___lsb 9 -#define reg_intr_vect_rw_mask___dma3___width 1 -#define reg_intr_vect_rw_mask___dma3___bit 9 -#define reg_intr_vect_rw_mask___dma4___lsb 10 -#define reg_intr_vect_rw_mask___dma4___width 1 -#define reg_intr_vect_rw_mask___dma4___bit 10 -#define reg_intr_vect_rw_mask___dma5___lsb 11 -#define reg_intr_vect_rw_mask___dma5___width 1 -#define reg_intr_vect_rw_mask___dma5___bit 11 -#define reg_intr_vect_rw_mask___dma6___lsb 12 -#define reg_intr_vect_rw_mask___dma6___width 1 -#define reg_intr_vect_rw_mask___dma6___bit 12 -#define reg_intr_vect_rw_mask___dma7___lsb 13 -#define reg_intr_vect_rw_mask___dma7___width 1 -#define reg_intr_vect_rw_mask___dma7___bit 13 -#define reg_intr_vect_rw_mask___dma8___lsb 14 -#define reg_intr_vect_rw_mask___dma8___width 1 -#define reg_intr_vect_rw_mask___dma8___bit 14 -#define reg_intr_vect_rw_mask___dma9___lsb 15 -#define reg_intr_vect_rw_mask___dma9___width 1 -#define reg_intr_vect_rw_mask___dma9___bit 15 -#define reg_intr_vect_rw_mask___ata___lsb 16 -#define reg_intr_vect_rw_mask___ata___width 1 -#define reg_intr_vect_rw_mask___ata___bit 16 -#define reg_intr_vect_rw_mask___sser0___lsb 17 -#define reg_intr_vect_rw_mask___sser0___width 1 -#define reg_intr_vect_rw_mask___sser0___bit 17 -#define reg_intr_vect_rw_mask___sser1___lsb 18 -#define reg_intr_vect_rw_mask___sser1___width 1 -#define reg_intr_vect_rw_mask___sser1___bit 18 -#define reg_intr_vect_rw_mask___ser0___lsb 19 -#define reg_intr_vect_rw_mask___ser0___width 1 -#define reg_intr_vect_rw_mask___ser0___bit 19 -#define reg_intr_vect_rw_mask___ser1___lsb 20 -#define reg_intr_vect_rw_mask___ser1___width 1 -#define reg_intr_vect_rw_mask___ser1___bit 20 -#define reg_intr_vect_rw_mask___ser2___lsb 21 -#define reg_intr_vect_rw_mask___ser2___width 1 -#define reg_intr_vect_rw_mask___ser2___bit 21 -#define reg_intr_vect_rw_mask___ser3___lsb 22 -#define reg_intr_vect_rw_mask___ser3___width 1 -#define reg_intr_vect_rw_mask___ser3___bit 22 -#define reg_intr_vect_rw_mask___p21___lsb 23 -#define reg_intr_vect_rw_mask___p21___width 1 -#define reg_intr_vect_rw_mask___p21___bit 23 -#define reg_intr_vect_rw_mask___eth0___lsb 24 -#define reg_intr_vect_rw_mask___eth0___width 1 -#define reg_intr_vect_rw_mask___eth0___bit 24 -#define reg_intr_vect_rw_mask___eth1___lsb 25 -#define reg_intr_vect_rw_mask___eth1___width 1 -#define reg_intr_vect_rw_mask___eth1___bit 25 -#define reg_intr_vect_rw_mask___timer___lsb 26 -#define reg_intr_vect_rw_mask___timer___width 1 -#define reg_intr_vect_rw_mask___timer___bit 26 -#define reg_intr_vect_rw_mask___bif_arb___lsb 27 -#define reg_intr_vect_rw_mask___bif_arb___width 1 -#define reg_intr_vect_rw_mask___bif_arb___bit 27 -#define reg_intr_vect_rw_mask___bif_dma___lsb 28 -#define reg_intr_vect_rw_mask___bif_dma___width 1 -#define reg_intr_vect_rw_mask___bif_dma___bit 28 -#define reg_intr_vect_rw_mask___ext___lsb 29 -#define reg_intr_vect_rw_mask___ext___width 1 -#define reg_intr_vect_rw_mask___ext___bit 29 -#define reg_intr_vect_rw_mask_offset 0 - -/* Register r_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_vect___memarb___lsb 0 -#define reg_intr_vect_r_vect___memarb___width 1 -#define reg_intr_vect_r_vect___memarb___bit 0 -#define reg_intr_vect_r_vect___gen_io___lsb 1 -#define reg_intr_vect_r_vect___gen_io___width 1 -#define reg_intr_vect_r_vect___gen_io___bit 1 -#define reg_intr_vect_r_vect___iop0___lsb 2 -#define reg_intr_vect_r_vect___iop0___width 1 -#define reg_intr_vect_r_vect___iop0___bit 2 -#define reg_intr_vect_r_vect___iop1___lsb 3 -#define reg_intr_vect_r_vect___iop1___width 1 -#define reg_intr_vect_r_vect___iop1___bit 3 -#define reg_intr_vect_r_vect___iop2___lsb 4 -#define reg_intr_vect_r_vect___iop2___width 1 -#define reg_intr_vect_r_vect___iop2___bit 4 -#define reg_intr_vect_r_vect___iop3___lsb 5 -#define reg_intr_vect_r_vect___iop3___width 1 -#define reg_intr_vect_r_vect___iop3___bit 5 -#define reg_intr_vect_r_vect___dma0___lsb 6 -#define reg_intr_vect_r_vect___dma0___width 1 -#define reg_intr_vect_r_vect___dma0___bit 6 -#define reg_intr_vect_r_vect___dma1___lsb 7 -#define reg_intr_vect_r_vect___dma1___width 1 -#define reg_intr_vect_r_vect___dma1___bit 7 -#define reg_intr_vect_r_vect___dma2___lsb 8 -#define reg_intr_vect_r_vect___dma2___width 1 -#define reg_intr_vect_r_vect___dma2___bit 8 -#define reg_intr_vect_r_vect___dma3___lsb 9 -#define reg_intr_vect_r_vect___dma3___width 1 -#define reg_intr_vect_r_vect___dma3___bit 9 -#define reg_intr_vect_r_vect___dma4___lsb 10 -#define reg_intr_vect_r_vect___dma4___width 1 -#define reg_intr_vect_r_vect___dma4___bit 10 -#define reg_intr_vect_r_vect___dma5___lsb 11 -#define reg_intr_vect_r_vect___dma5___width 1 -#define reg_intr_vect_r_vect___dma5___bit 11 -#define reg_intr_vect_r_vect___dma6___lsb 12 -#define reg_intr_vect_r_vect___dma6___width 1 -#define reg_intr_vect_r_vect___dma6___bit 12 -#define reg_intr_vect_r_vect___dma7___lsb 13 -#define reg_intr_vect_r_vect___dma7___width 1 -#define reg_intr_vect_r_vect___dma7___bit 13 -#define reg_intr_vect_r_vect___dma8___lsb 14 -#define reg_intr_vect_r_vect___dma8___width 1 -#define reg_intr_vect_r_vect___dma8___bit 14 -#define reg_intr_vect_r_vect___dma9___lsb 15 -#define reg_intr_vect_r_vect___dma9___width 1 -#define reg_intr_vect_r_vect___dma9___bit 15 -#define reg_intr_vect_r_vect___ata___lsb 16 -#define reg_intr_vect_r_vect___ata___width 1 -#define reg_intr_vect_r_vect___ata___bit 16 -#define reg_intr_vect_r_vect___sser0___lsb 17 -#define reg_intr_vect_r_vect___sser0___width 1 -#define reg_intr_vect_r_vect___sser0___bit 17 -#define reg_intr_vect_r_vect___sser1___lsb 18 -#define reg_intr_vect_r_vect___sser1___width 1 -#define reg_intr_vect_r_vect___sser1___bit 18 -#define reg_intr_vect_r_vect___ser0___lsb 19 -#define reg_intr_vect_r_vect___ser0___width 1 -#define reg_intr_vect_r_vect___ser0___bit 19 -#define reg_intr_vect_r_vect___ser1___lsb 20 -#define reg_intr_vect_r_vect___ser1___width 1 -#define reg_intr_vect_r_vect___ser1___bit 20 -#define reg_intr_vect_r_vect___ser2___lsb 21 -#define reg_intr_vect_r_vect___ser2___width 1 -#define reg_intr_vect_r_vect___ser2___bit 21 -#define reg_intr_vect_r_vect___ser3___lsb 22 -#define reg_intr_vect_r_vect___ser3___width 1 -#define reg_intr_vect_r_vect___ser3___bit 22 -#define reg_intr_vect_r_vect___p21___lsb 23 -#define reg_intr_vect_r_vect___p21___width 1 -#define reg_intr_vect_r_vect___p21___bit 23 -#define reg_intr_vect_r_vect___eth0___lsb 24 -#define reg_intr_vect_r_vect___eth0___width 1 -#define reg_intr_vect_r_vect___eth0___bit 24 -#define reg_intr_vect_r_vect___eth1___lsb 25 -#define reg_intr_vect_r_vect___eth1___width 1 -#define reg_intr_vect_r_vect___eth1___bit 25 -#define reg_intr_vect_r_vect___timer___lsb 26 -#define reg_intr_vect_r_vect___timer___width 1 -#define reg_intr_vect_r_vect___timer___bit 26 -#define reg_intr_vect_r_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_vect___bif_arb___width 1 -#define reg_intr_vect_r_vect___bif_arb___bit 27 -#define reg_intr_vect_r_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_vect___bif_dma___width 1 -#define reg_intr_vect_r_vect___bif_dma___bit 28 -#define reg_intr_vect_r_vect___ext___lsb 29 -#define reg_intr_vect_r_vect___ext___width 1 -#define reg_intr_vect_r_vect___ext___bit 29 -#define reg_intr_vect_r_vect_offset 4 - -/* Register r_masked_vect, scope intr_vect, type r */ -#define reg_intr_vect_r_masked_vect___memarb___lsb 0 -#define reg_intr_vect_r_masked_vect___memarb___width 1 -#define reg_intr_vect_r_masked_vect___memarb___bit 0 -#define reg_intr_vect_r_masked_vect___gen_io___lsb 1 -#define reg_intr_vect_r_masked_vect___gen_io___width 1 -#define reg_intr_vect_r_masked_vect___gen_io___bit 1 -#define reg_intr_vect_r_masked_vect___iop0___lsb 2 -#define reg_intr_vect_r_masked_vect___iop0___width 1 -#define reg_intr_vect_r_masked_vect___iop0___bit 2 -#define reg_intr_vect_r_masked_vect___iop1___lsb 3 -#define reg_intr_vect_r_masked_vect___iop1___width 1 -#define reg_intr_vect_r_masked_vect___iop1___bit 3 -#define reg_intr_vect_r_masked_vect___iop2___lsb 4 -#define reg_intr_vect_r_masked_vect___iop2___width 1 -#define reg_intr_vect_r_masked_vect___iop2___bit 4 -#define reg_intr_vect_r_masked_vect___iop3___lsb 5 -#define reg_intr_vect_r_masked_vect___iop3___width 1 -#define reg_intr_vect_r_masked_vect___iop3___bit 5 -#define reg_intr_vect_r_masked_vect___dma0___lsb 6 -#define reg_intr_vect_r_masked_vect___dma0___width 1 -#define reg_intr_vect_r_masked_vect___dma0___bit 6 -#define reg_intr_vect_r_masked_vect___dma1___lsb 7 -#define reg_intr_vect_r_masked_vect___dma1___width 1 -#define reg_intr_vect_r_masked_vect___dma1___bit 7 -#define reg_intr_vect_r_masked_vect___dma2___lsb 8 -#define reg_intr_vect_r_masked_vect___dma2___width 1 -#define reg_intr_vect_r_masked_vect___dma2___bit 8 -#define reg_intr_vect_r_masked_vect___dma3___lsb 9 -#define reg_intr_vect_r_masked_vect___dma3___width 1 -#define reg_intr_vect_r_masked_vect___dma3___bit 9 -#define reg_intr_vect_r_masked_vect___dma4___lsb 10 -#define reg_intr_vect_r_masked_vect___dma4___width 1 -#define reg_intr_vect_r_masked_vect___dma4___bit 10 -#define reg_intr_vect_r_masked_vect___dma5___lsb 11 -#define reg_intr_vect_r_masked_vect___dma5___width 1 -#define reg_intr_vect_r_masked_vect___dma5___bit 11 -#define reg_intr_vect_r_masked_vect___dma6___lsb 12 -#define reg_intr_vect_r_masked_vect___dma6___width 1 -#define reg_intr_vect_r_masked_vect___dma6___bit 12 -#define reg_intr_vect_r_masked_vect___dma7___lsb 13 -#define reg_intr_vect_r_masked_vect___dma7___width 1 -#define reg_intr_vect_r_masked_vect___dma7___bit 13 -#define reg_intr_vect_r_masked_vect___dma8___lsb 14 -#define reg_intr_vect_r_masked_vect___dma8___width 1 -#define reg_intr_vect_r_masked_vect___dma8___bit 14 -#define reg_intr_vect_r_masked_vect___dma9___lsb 15 -#define reg_intr_vect_r_masked_vect___dma9___width 1 -#define reg_intr_vect_r_masked_vect___dma9___bit 15 -#define reg_intr_vect_r_masked_vect___ata___lsb 16 -#define reg_intr_vect_r_masked_vect___ata___width 1 -#define reg_intr_vect_r_masked_vect___ata___bit 16 -#define reg_intr_vect_r_masked_vect___sser0___lsb 17 -#define reg_intr_vect_r_masked_vect___sser0___width 1 -#define reg_intr_vect_r_masked_vect___sser0___bit 17 -#define reg_intr_vect_r_masked_vect___sser1___lsb 18 -#define reg_intr_vect_r_masked_vect___sser1___width 1 -#define reg_intr_vect_r_masked_vect___sser1___bit 18 -#define reg_intr_vect_r_masked_vect___ser0___lsb 19 -#define reg_intr_vect_r_masked_vect___ser0___width 1 -#define reg_intr_vect_r_masked_vect___ser0___bit 19 -#define reg_intr_vect_r_masked_vect___ser1___lsb 20 -#define reg_intr_vect_r_masked_vect___ser1___width 1 -#define reg_intr_vect_r_masked_vect___ser1___bit 20 -#define reg_intr_vect_r_masked_vect___ser2___lsb 21 -#define reg_intr_vect_r_masked_vect___ser2___width 1 -#define reg_intr_vect_r_masked_vect___ser2___bit 21 -#define reg_intr_vect_r_masked_vect___ser3___lsb 22 -#define reg_intr_vect_r_masked_vect___ser3___width 1 -#define reg_intr_vect_r_masked_vect___ser3___bit 22 -#define reg_intr_vect_r_masked_vect___p21___lsb 23 -#define reg_intr_vect_r_masked_vect___p21___width 1 -#define reg_intr_vect_r_masked_vect___p21___bit 23 -#define reg_intr_vect_r_masked_vect___eth0___lsb 24 -#define reg_intr_vect_r_masked_vect___eth0___width 1 -#define reg_intr_vect_r_masked_vect___eth0___bit 24 -#define reg_intr_vect_r_masked_vect___eth1___lsb 25 -#define reg_intr_vect_r_masked_vect___eth1___width 1 -#define reg_intr_vect_r_masked_vect___eth1___bit 25 -#define reg_intr_vect_r_masked_vect___timer___lsb 26 -#define reg_intr_vect_r_masked_vect___timer___width 1 -#define reg_intr_vect_r_masked_vect___timer___bit 26 -#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 -#define reg_intr_vect_r_masked_vect___bif_arb___width 1 -#define reg_intr_vect_r_masked_vect___bif_arb___bit 27 -#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 -#define reg_intr_vect_r_masked_vect___bif_dma___width 1 -#define reg_intr_vect_r_masked_vect___bif_dma___bit 28 -#define reg_intr_vect_r_masked_vect___ext___lsb 29 -#define reg_intr_vect_r_masked_vect___ext___width 1 -#define reg_intr_vect_r_masked_vect___ext___bit 29 -#define reg_intr_vect_r_masked_vect_offset 8 - -/* Register r_nmi, scope intr_vect, type r */ -#define reg_intr_vect_r_nmi___ext___lsb 0 -#define reg_intr_vect_r_nmi___ext___width 1 -#define reg_intr_vect_r_nmi___ext___bit 0 -#define reg_intr_vect_r_nmi___watchdog___lsb 1 -#define reg_intr_vect_r_nmi___watchdog___width 1 -#define reg_intr_vect_r_nmi___watchdog___bit 1 -#define reg_intr_vect_r_nmi_offset 12 - -/* Register r_guru, scope intr_vect, type r */ -#define reg_intr_vect_r_guru___jtag___lsb 0 -#define reg_intr_vect_r_guru___jtag___width 1 -#define reg_intr_vect_r_guru___jtag___bit 0 -#define reg_intr_vect_r_guru_offset 16 - - -/* Constants */ -#define regk_intr_vect_off 0x00000000 -#define regk_intr_vect_on 0x00000001 -#define regk_intr_vect_rw_mask_default 0x00000000 -#endif /* __intr_vect_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h deleted file mode 100644 index f624468346af..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __irq_nmi_defs_asm_h -#define __irq_nmi_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cmd, scope irq_nmi, type rw */ -#define reg_irq_nmi_rw_cmd___delay___lsb 0 -#define reg_irq_nmi_rw_cmd___delay___width 16 -#define reg_irq_nmi_rw_cmd___op___lsb 16 -#define reg_irq_nmi_rw_cmd___op___width 2 -#define reg_irq_nmi_rw_cmd_offset 0 - - -/* Constants */ -#define regk_irq_nmi_ack_irq 0x00000002 -#define regk_irq_nmi_ack_nmi 0x00000003 -#define regk_irq_nmi_irq 0x00000000 -#define regk_irq_nmi_nmi 0x00000001 -#endif /* __irq_nmi_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h deleted file mode 100644 index 6a5ce2141860..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h +++ /dev/null @@ -1,580 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_defs_asm_h -#define __marb_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -#define reg_marb_rw_int_slots___owner___lsb 0 -#define reg_marb_rw_int_slots___owner___width 4 -#define reg_marb_rw_int_slots_offset 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -#define reg_marb_rw_ext_slots___owner___lsb 0 -#define reg_marb_rw_ext_slots___owner___width 4 -#define reg_marb_rw_ext_slots_offset 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -#define reg_marb_rw_regs_slots___owner___lsb 0 -#define reg_marb_rw_regs_slots___owner___width 4 -#define reg_marb_rw_regs_slots_offset 512 - -/* Register rw_intr_mask, scope marb, type rw */ -#define reg_marb_rw_intr_mask___bp0___lsb 0 -#define reg_marb_rw_intr_mask___bp0___width 1 -#define reg_marb_rw_intr_mask___bp0___bit 0 -#define reg_marb_rw_intr_mask___bp1___lsb 1 -#define reg_marb_rw_intr_mask___bp1___width 1 -#define reg_marb_rw_intr_mask___bp1___bit 1 -#define reg_marb_rw_intr_mask___bp2___lsb 2 -#define reg_marb_rw_intr_mask___bp2___width 1 -#define reg_marb_rw_intr_mask___bp2___bit 2 -#define reg_marb_rw_intr_mask___bp3___lsb 3 -#define reg_marb_rw_intr_mask___bp3___width 1 -#define reg_marb_rw_intr_mask___bp3___bit 3 -#define reg_marb_rw_intr_mask_offset 528 - -/* Register rw_ack_intr, scope marb, type rw */ -#define reg_marb_rw_ack_intr___bp0___lsb 0 -#define reg_marb_rw_ack_intr___bp0___width 1 -#define reg_marb_rw_ack_intr___bp0___bit 0 -#define reg_marb_rw_ack_intr___bp1___lsb 1 -#define reg_marb_rw_ack_intr___bp1___width 1 -#define reg_marb_rw_ack_intr___bp1___bit 1 -#define reg_marb_rw_ack_intr___bp2___lsb 2 -#define reg_marb_rw_ack_intr___bp2___width 1 -#define reg_marb_rw_ack_intr___bp2___bit 2 -#define reg_marb_rw_ack_intr___bp3___lsb 3 -#define reg_marb_rw_ack_intr___bp3___width 1 -#define reg_marb_rw_ack_intr___bp3___bit 3 -#define reg_marb_rw_ack_intr_offset 532 - -/* Register r_intr, scope marb, type r */ -#define reg_marb_r_intr___bp0___lsb 0 -#define reg_marb_r_intr___bp0___width 1 -#define reg_marb_r_intr___bp0___bit 0 -#define reg_marb_r_intr___bp1___lsb 1 -#define reg_marb_r_intr___bp1___width 1 -#define reg_marb_r_intr___bp1___bit 1 -#define reg_marb_r_intr___bp2___lsb 2 -#define reg_marb_r_intr___bp2___width 1 -#define reg_marb_r_intr___bp2___bit 2 -#define reg_marb_r_intr___bp3___lsb 3 -#define reg_marb_r_intr___bp3___width 1 -#define reg_marb_r_intr___bp3___bit 3 -#define reg_marb_r_intr_offset 536 - -/* Register r_masked_intr, scope marb, type r */ -#define reg_marb_r_masked_intr___bp0___lsb 0 -#define reg_marb_r_masked_intr___bp0___width 1 -#define reg_marb_r_masked_intr___bp0___bit 0 -#define reg_marb_r_masked_intr___bp1___lsb 1 -#define reg_marb_r_masked_intr___bp1___width 1 -#define reg_marb_r_masked_intr___bp1___bit 1 -#define reg_marb_r_masked_intr___bp2___lsb 2 -#define reg_marb_r_masked_intr___bp2___width 1 -#define reg_marb_r_masked_intr___bp2___bit 2 -#define reg_marb_r_masked_intr___bp3___lsb 3 -#define reg_marb_r_masked_intr___bp3___width 1 -#define reg_marb_r_masked_intr___bp3___bit 3 -#define reg_marb_r_masked_intr_offset 540 - -/* Register rw_stop_mask, scope marb, type rw */ -#define reg_marb_rw_stop_mask___dma0___lsb 0 -#define reg_marb_rw_stop_mask___dma0___width 1 -#define reg_marb_rw_stop_mask___dma0___bit 0 -#define reg_marb_rw_stop_mask___dma1___lsb 1 -#define reg_marb_rw_stop_mask___dma1___width 1 -#define reg_marb_rw_stop_mask___dma1___bit 1 -#define reg_marb_rw_stop_mask___dma2___lsb 2 -#define reg_marb_rw_stop_mask___dma2___width 1 -#define reg_marb_rw_stop_mask___dma2___bit 2 -#define reg_marb_rw_stop_mask___dma3___lsb 3 -#define reg_marb_rw_stop_mask___dma3___width 1 -#define reg_marb_rw_stop_mask___dma3___bit 3 -#define reg_marb_rw_stop_mask___dma4___lsb 4 -#define reg_marb_rw_stop_mask___dma4___width 1 -#define reg_marb_rw_stop_mask___dma4___bit 4 -#define reg_marb_rw_stop_mask___dma5___lsb 5 -#define reg_marb_rw_stop_mask___dma5___width 1 -#define reg_marb_rw_stop_mask___dma5___bit 5 -#define reg_marb_rw_stop_mask___dma6___lsb 6 -#define reg_marb_rw_stop_mask___dma6___width 1 -#define reg_marb_rw_stop_mask___dma6___bit 6 -#define reg_marb_rw_stop_mask___dma7___lsb 7 -#define reg_marb_rw_stop_mask___dma7___width 1 -#define reg_marb_rw_stop_mask___dma7___bit 7 -#define reg_marb_rw_stop_mask___dma8___lsb 8 -#define reg_marb_rw_stop_mask___dma8___width 1 -#define reg_marb_rw_stop_mask___dma8___bit 8 -#define reg_marb_rw_stop_mask___dma9___lsb 9 -#define reg_marb_rw_stop_mask___dma9___width 1 -#define reg_marb_rw_stop_mask___dma9___bit 9 -#define reg_marb_rw_stop_mask___cpui___lsb 10 -#define reg_marb_rw_stop_mask___cpui___width 1 -#define reg_marb_rw_stop_mask___cpui___bit 10 -#define reg_marb_rw_stop_mask___cpud___lsb 11 -#define reg_marb_rw_stop_mask___cpud___width 1 -#define reg_marb_rw_stop_mask___cpud___bit 11 -#define reg_marb_rw_stop_mask___iop___lsb 12 -#define reg_marb_rw_stop_mask___iop___width 1 -#define reg_marb_rw_stop_mask___iop___bit 12 -#define reg_marb_rw_stop_mask___slave___lsb 13 -#define reg_marb_rw_stop_mask___slave___width 1 -#define reg_marb_rw_stop_mask___slave___bit 13 -#define reg_marb_rw_stop_mask_offset 544 - -/* Register r_stopped, scope marb, type r */ -#define reg_marb_r_stopped___dma0___lsb 0 -#define reg_marb_r_stopped___dma0___width 1 -#define reg_marb_r_stopped___dma0___bit 0 -#define reg_marb_r_stopped___dma1___lsb 1 -#define reg_marb_r_stopped___dma1___width 1 -#define reg_marb_r_stopped___dma1___bit 1 -#define reg_marb_r_stopped___dma2___lsb 2 -#define reg_marb_r_stopped___dma2___width 1 -#define reg_marb_r_stopped___dma2___bit 2 -#define reg_marb_r_stopped___dma3___lsb 3 -#define reg_marb_r_stopped___dma3___width 1 -#define reg_marb_r_stopped___dma3___bit 3 -#define reg_marb_r_stopped___dma4___lsb 4 -#define reg_marb_r_stopped___dma4___width 1 -#define reg_marb_r_stopped___dma4___bit 4 -#define reg_marb_r_stopped___dma5___lsb 5 -#define reg_marb_r_stopped___dma5___width 1 -#define reg_marb_r_stopped___dma5___bit 5 -#define reg_marb_r_stopped___dma6___lsb 6 -#define reg_marb_r_stopped___dma6___width 1 -#define reg_marb_r_stopped___dma6___bit 6 -#define reg_marb_r_stopped___dma7___lsb 7 -#define reg_marb_r_stopped___dma7___width 1 -#define reg_marb_r_stopped___dma7___bit 7 -#define reg_marb_r_stopped___dma8___lsb 8 -#define reg_marb_r_stopped___dma8___width 1 -#define reg_marb_r_stopped___dma8___bit 8 -#define reg_marb_r_stopped___dma9___lsb 9 -#define reg_marb_r_stopped___dma9___width 1 -#define reg_marb_r_stopped___dma9___bit 9 -#define reg_marb_r_stopped___cpui___lsb 10 -#define reg_marb_r_stopped___cpui___width 1 -#define reg_marb_r_stopped___cpui___bit 10 -#define reg_marb_r_stopped___cpud___lsb 11 -#define reg_marb_r_stopped___cpud___width 1 -#define reg_marb_r_stopped___cpud___bit 11 -#define reg_marb_r_stopped___iop___lsb 12 -#define reg_marb_r_stopped___iop___width 1 -#define reg_marb_r_stopped___iop___bit 12 -#define reg_marb_r_stopped___slave___lsb 13 -#define reg_marb_r_stopped___slave___width 1 -#define reg_marb_r_stopped___slave___bit 13 -#define reg_marb_r_stopped_offset 548 - -/* Register rw_no_snoop, scope marb, type rw */ -#define reg_marb_rw_no_snoop___dma0___lsb 0 -#define reg_marb_rw_no_snoop___dma0___width 1 -#define reg_marb_rw_no_snoop___dma0___bit 0 -#define reg_marb_rw_no_snoop___dma1___lsb 1 -#define reg_marb_rw_no_snoop___dma1___width 1 -#define reg_marb_rw_no_snoop___dma1___bit 1 -#define reg_marb_rw_no_snoop___dma2___lsb 2 -#define reg_marb_rw_no_snoop___dma2___width 1 -#define reg_marb_rw_no_snoop___dma2___bit 2 -#define reg_marb_rw_no_snoop___dma3___lsb 3 -#define reg_marb_rw_no_snoop___dma3___width 1 -#define reg_marb_rw_no_snoop___dma3___bit 3 -#define reg_marb_rw_no_snoop___dma4___lsb 4 -#define reg_marb_rw_no_snoop___dma4___width 1 -#define reg_marb_rw_no_snoop___dma4___bit 4 -#define reg_marb_rw_no_snoop___dma5___lsb 5 -#define reg_marb_rw_no_snoop___dma5___width 1 -#define reg_marb_rw_no_snoop___dma5___bit 5 -#define reg_marb_rw_no_snoop___dma6___lsb 6 -#define reg_marb_rw_no_snoop___dma6___width 1 -#define reg_marb_rw_no_snoop___dma6___bit 6 -#define reg_marb_rw_no_snoop___dma7___lsb 7 -#define reg_marb_rw_no_snoop___dma7___width 1 -#define reg_marb_rw_no_snoop___dma7___bit 7 -#define reg_marb_rw_no_snoop___dma8___lsb 8 -#define reg_marb_rw_no_snoop___dma8___width 1 -#define reg_marb_rw_no_snoop___dma8___bit 8 -#define reg_marb_rw_no_snoop___dma9___lsb 9 -#define reg_marb_rw_no_snoop___dma9___width 1 -#define reg_marb_rw_no_snoop___dma9___bit 9 -#define reg_marb_rw_no_snoop___cpui___lsb 10 -#define reg_marb_rw_no_snoop___cpui___width 1 -#define reg_marb_rw_no_snoop___cpui___bit 10 -#define reg_marb_rw_no_snoop___cpud___lsb 11 -#define reg_marb_rw_no_snoop___cpud___width 1 -#define reg_marb_rw_no_snoop___cpud___bit 11 -#define reg_marb_rw_no_snoop___iop___lsb 12 -#define reg_marb_rw_no_snoop___iop___width 1 -#define reg_marb_rw_no_snoop___iop___bit 12 -#define reg_marb_rw_no_snoop___slave___lsb 13 -#define reg_marb_rw_no_snoop___slave___width 1 -#define reg_marb_rw_no_snoop___slave___bit 13 -#define reg_marb_rw_no_snoop_offset 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -#define reg_marb_rw_no_snoop_rq___cpui___lsb 10 -#define reg_marb_rw_no_snoop_rq___cpui___width 1 -#define reg_marb_rw_no_snoop_rq___cpui___bit 10 -#define reg_marb_rw_no_snoop_rq___cpud___lsb 11 -#define reg_marb_rw_no_snoop_rq___cpud___width 1 -#define reg_marb_rw_no_snoop_rq___cpud___bit 11 -#define reg_marb_rw_no_snoop_rq_offset 836 - - -/* Constants */ -#define regk_marb_cpud 0x0000000b -#define regk_marb_cpui 0x0000000a -#define regk_marb_dma0 0x00000000 -#define regk_marb_dma1 0x00000001 -#define regk_marb_dma2 0x00000002 -#define regk_marb_dma3 0x00000003 -#define regk_marb_dma4 0x00000004 -#define regk_marb_dma5 0x00000005 -#define regk_marb_dma6 0x00000006 -#define regk_marb_dma7 0x00000007 -#define regk_marb_dma8 0x00000008 -#define regk_marb_dma9 0x00000009 -#define regk_marb_iop 0x0000000c -#define regk_marb_no 0x00000000 -#define regk_marb_r_stopped_default 0x00000000 -#define regk_marb_rw_ext_slots_default 0x00000000 -#define regk_marb_rw_ext_slots_size 0x00000040 -#define regk_marb_rw_int_slots_default 0x00000000 -#define regk_marb_rw_int_slots_size 0x00000040 -#define regk_marb_rw_intr_mask_default 0x00000000 -#define regk_marb_rw_no_snoop_default 0x00000000 -#define regk_marb_rw_no_snoop_rq_default 0x00000000 -#define regk_marb_rw_regs_slots_default 0x00000000 -#define regk_marb_rw_regs_slots_size 0x00000004 -#define regk_marb_rw_stop_mask_default 0x00000000 -#define regk_marb_slave 0x0000000d -#define regk_marb_yes 0x00000001 -#endif /* __marb_defs_asm_h */ -#ifndef __marb_bp_defs_asm_h -#define __marb_bp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_first_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_first_addr_offset 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -#define reg_marb_bp_rw_last_addr_offset 4 - -/* Register rw_op, scope marb_bp, type rw */ -#define reg_marb_bp_rw_op___rd___lsb 0 -#define reg_marb_bp_rw_op___rd___width 1 -#define reg_marb_bp_rw_op___rd___bit 0 -#define reg_marb_bp_rw_op___wr___lsb 1 -#define reg_marb_bp_rw_op___wr___width 1 -#define reg_marb_bp_rw_op___wr___bit 1 -#define reg_marb_bp_rw_op___rd_excl___lsb 2 -#define reg_marb_bp_rw_op___rd_excl___width 1 -#define reg_marb_bp_rw_op___rd_excl___bit 2 -#define reg_marb_bp_rw_op___pri_wr___lsb 3 -#define reg_marb_bp_rw_op___pri_wr___width 1 -#define reg_marb_bp_rw_op___pri_wr___bit 3 -#define reg_marb_bp_rw_op___us_rd___lsb 4 -#define reg_marb_bp_rw_op___us_rd___width 1 -#define reg_marb_bp_rw_op___us_rd___bit 4 -#define reg_marb_bp_rw_op___us_wr___lsb 5 -#define reg_marb_bp_rw_op___us_wr___width 1 -#define reg_marb_bp_rw_op___us_wr___bit 5 -#define reg_marb_bp_rw_op___us_rd_excl___lsb 6 -#define reg_marb_bp_rw_op___us_rd_excl___width 1 -#define reg_marb_bp_rw_op___us_rd_excl___bit 6 -#define reg_marb_bp_rw_op___us_pri_wr___lsb 7 -#define reg_marb_bp_rw_op___us_pri_wr___width 1 -#define reg_marb_bp_rw_op___us_pri_wr___bit 7 -#define reg_marb_bp_rw_op_offset 8 - -/* Register rw_clients, scope marb_bp, type rw */ -#define reg_marb_bp_rw_clients___dma0___lsb 0 -#define reg_marb_bp_rw_clients___dma0___width 1 -#define reg_marb_bp_rw_clients___dma0___bit 0 -#define reg_marb_bp_rw_clients___dma1___lsb 1 -#define reg_marb_bp_rw_clients___dma1___width 1 -#define reg_marb_bp_rw_clients___dma1___bit 1 -#define reg_marb_bp_rw_clients___dma2___lsb 2 -#define reg_marb_bp_rw_clients___dma2___width 1 -#define reg_marb_bp_rw_clients___dma2___bit 2 -#define reg_marb_bp_rw_clients___dma3___lsb 3 -#define reg_marb_bp_rw_clients___dma3___width 1 -#define reg_marb_bp_rw_clients___dma3___bit 3 -#define reg_marb_bp_rw_clients___dma4___lsb 4 -#define reg_marb_bp_rw_clients___dma4___width 1 -#define reg_marb_bp_rw_clients___dma4___bit 4 -#define reg_marb_bp_rw_clients___dma5___lsb 5 -#define reg_marb_bp_rw_clients___dma5___width 1 -#define reg_marb_bp_rw_clients___dma5___bit 5 -#define reg_marb_bp_rw_clients___dma6___lsb 6 -#define reg_marb_bp_rw_clients___dma6___width 1 -#define reg_marb_bp_rw_clients___dma6___bit 6 -#define reg_marb_bp_rw_clients___dma7___lsb 7 -#define reg_marb_bp_rw_clients___dma7___width 1 -#define reg_marb_bp_rw_clients___dma7___bit 7 -#define reg_marb_bp_rw_clients___dma8___lsb 8 -#define reg_marb_bp_rw_clients___dma8___width 1 -#define reg_marb_bp_rw_clients___dma8___bit 8 -#define reg_marb_bp_rw_clients___dma9___lsb 9 -#define reg_marb_bp_rw_clients___dma9___width 1 -#define reg_marb_bp_rw_clients___dma9___bit 9 -#define reg_marb_bp_rw_clients___cpui___lsb 10 -#define reg_marb_bp_rw_clients___cpui___width 1 -#define reg_marb_bp_rw_clients___cpui___bit 10 -#define reg_marb_bp_rw_clients___cpud___lsb 11 -#define reg_marb_bp_rw_clients___cpud___width 1 -#define reg_marb_bp_rw_clients___cpud___bit 11 -#define reg_marb_bp_rw_clients___iop___lsb 12 -#define reg_marb_bp_rw_clients___iop___width 1 -#define reg_marb_bp_rw_clients___iop___bit 12 -#define reg_marb_bp_rw_clients___slave___lsb 13 -#define reg_marb_bp_rw_clients___slave___width 1 -#define reg_marb_bp_rw_clients___slave___bit 13 -#define reg_marb_bp_rw_clients_offset 12 - -/* Register rw_options, scope marb_bp, type rw */ -#define reg_marb_bp_rw_options___wrap___lsb 0 -#define reg_marb_bp_rw_options___wrap___width 1 -#define reg_marb_bp_rw_options___wrap___bit 0 -#define reg_marb_bp_rw_options_offset 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_addr_offset 20 - -/* Register r_brk_op, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_op___rd___lsb 0 -#define reg_marb_bp_r_brk_op___rd___width 1 -#define reg_marb_bp_r_brk_op___rd___bit 0 -#define reg_marb_bp_r_brk_op___wr___lsb 1 -#define reg_marb_bp_r_brk_op___wr___width 1 -#define reg_marb_bp_r_brk_op___wr___bit 1 -#define reg_marb_bp_r_brk_op___rd_excl___lsb 2 -#define reg_marb_bp_r_brk_op___rd_excl___width 1 -#define reg_marb_bp_r_brk_op___rd_excl___bit 2 -#define reg_marb_bp_r_brk_op___pri_wr___lsb 3 -#define reg_marb_bp_r_brk_op___pri_wr___width 1 -#define reg_marb_bp_r_brk_op___pri_wr___bit 3 -#define reg_marb_bp_r_brk_op___us_rd___lsb 4 -#define reg_marb_bp_r_brk_op___us_rd___width 1 -#define reg_marb_bp_r_brk_op___us_rd___bit 4 -#define reg_marb_bp_r_brk_op___us_wr___lsb 5 -#define reg_marb_bp_r_brk_op___us_wr___width 1 -#define reg_marb_bp_r_brk_op___us_wr___bit 5 -#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6 -#define reg_marb_bp_r_brk_op___us_rd_excl___width 1 -#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6 -#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7 -#define reg_marb_bp_r_brk_op___us_pri_wr___width 1 -#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7 -#define reg_marb_bp_r_brk_op_offset 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_clients___dma0___lsb 0 -#define reg_marb_bp_r_brk_clients___dma0___width 1 -#define reg_marb_bp_r_brk_clients___dma0___bit 0 -#define reg_marb_bp_r_brk_clients___dma1___lsb 1 -#define reg_marb_bp_r_brk_clients___dma1___width 1 -#define reg_marb_bp_r_brk_clients___dma1___bit 1 -#define reg_marb_bp_r_brk_clients___dma2___lsb 2 -#define reg_marb_bp_r_brk_clients___dma2___width 1 -#define reg_marb_bp_r_brk_clients___dma2___bit 2 -#define reg_marb_bp_r_brk_clients___dma3___lsb 3 -#define reg_marb_bp_r_brk_clients___dma3___width 1 -#define reg_marb_bp_r_brk_clients___dma3___bit 3 -#define reg_marb_bp_r_brk_clients___dma4___lsb 4 -#define reg_marb_bp_r_brk_clients___dma4___width 1 -#define reg_marb_bp_r_brk_clients___dma4___bit 4 -#define reg_marb_bp_r_brk_clients___dma5___lsb 5 -#define reg_marb_bp_r_brk_clients___dma5___width 1 -#define reg_marb_bp_r_brk_clients___dma5___bit 5 -#define reg_marb_bp_r_brk_clients___dma6___lsb 6 -#define reg_marb_bp_r_brk_clients___dma6___width 1 -#define reg_marb_bp_r_brk_clients___dma6___bit 6 -#define reg_marb_bp_r_brk_clients___dma7___lsb 7 -#define reg_marb_bp_r_brk_clients___dma7___width 1 -#define reg_marb_bp_r_brk_clients___dma7___bit 7 -#define reg_marb_bp_r_brk_clients___dma8___lsb 8 -#define reg_marb_bp_r_brk_clients___dma8___width 1 -#define reg_marb_bp_r_brk_clients___dma8___bit 8 -#define reg_marb_bp_r_brk_clients___dma9___lsb 9 -#define reg_marb_bp_r_brk_clients___dma9___width 1 -#define reg_marb_bp_r_brk_clients___dma9___bit 9 -#define reg_marb_bp_r_brk_clients___cpui___lsb 10 -#define reg_marb_bp_r_brk_clients___cpui___width 1 -#define reg_marb_bp_r_brk_clients___cpui___bit 10 -#define reg_marb_bp_r_brk_clients___cpud___lsb 11 -#define reg_marb_bp_r_brk_clients___cpud___width 1 -#define reg_marb_bp_r_brk_clients___cpud___bit 11 -#define reg_marb_bp_r_brk_clients___iop___lsb 12 -#define reg_marb_bp_r_brk_clients___iop___width 1 -#define reg_marb_bp_r_brk_clients___iop___bit 12 -#define reg_marb_bp_r_brk_clients___slave___lsb 13 -#define reg_marb_bp_r_brk_clients___slave___width 1 -#define reg_marb_bp_r_brk_clients___slave___bit 13 -#define reg_marb_bp_r_brk_clients_offset 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_first_client___dma0___lsb 0 -#define reg_marb_bp_r_brk_first_client___dma0___width 1 -#define reg_marb_bp_r_brk_first_client___dma0___bit 0 -#define reg_marb_bp_r_brk_first_client___dma1___lsb 1 -#define reg_marb_bp_r_brk_first_client___dma1___width 1 -#define reg_marb_bp_r_brk_first_client___dma1___bit 1 -#define reg_marb_bp_r_brk_first_client___dma2___lsb 2 -#define reg_marb_bp_r_brk_first_client___dma2___width 1 -#define reg_marb_bp_r_brk_first_client___dma2___bit 2 -#define reg_marb_bp_r_brk_first_client___dma3___lsb 3 -#define reg_marb_bp_r_brk_first_client___dma3___width 1 -#define reg_marb_bp_r_brk_first_client___dma3___bit 3 -#define reg_marb_bp_r_brk_first_client___dma4___lsb 4 -#define reg_marb_bp_r_brk_first_client___dma4___width 1 -#define reg_marb_bp_r_brk_first_client___dma4___bit 4 -#define reg_marb_bp_r_brk_first_client___dma5___lsb 5 -#define reg_marb_bp_r_brk_first_client___dma5___width 1 -#define reg_marb_bp_r_brk_first_client___dma5___bit 5 -#define reg_marb_bp_r_brk_first_client___dma6___lsb 6 -#define reg_marb_bp_r_brk_first_client___dma6___width 1 -#define reg_marb_bp_r_brk_first_client___dma6___bit 6 -#define reg_marb_bp_r_brk_first_client___dma7___lsb 7 -#define reg_marb_bp_r_brk_first_client___dma7___width 1 -#define reg_marb_bp_r_brk_first_client___dma7___bit 7 -#define reg_marb_bp_r_brk_first_client___dma8___lsb 8 -#define reg_marb_bp_r_brk_first_client___dma8___width 1 -#define reg_marb_bp_r_brk_first_client___dma8___bit 8 -#define reg_marb_bp_r_brk_first_client___dma9___lsb 9 -#define reg_marb_bp_r_brk_first_client___dma9___width 1 -#define reg_marb_bp_r_brk_first_client___dma9___bit 9 -#define reg_marb_bp_r_brk_first_client___cpui___lsb 10 -#define reg_marb_bp_r_brk_first_client___cpui___width 1 -#define reg_marb_bp_r_brk_first_client___cpui___bit 10 -#define reg_marb_bp_r_brk_first_client___cpud___lsb 11 -#define reg_marb_bp_r_brk_first_client___cpud___width 1 -#define reg_marb_bp_r_brk_first_client___cpud___bit 11 -#define reg_marb_bp_r_brk_first_client___iop___lsb 12 -#define reg_marb_bp_r_brk_first_client___iop___width 1 -#define reg_marb_bp_r_brk_first_client___iop___bit 12 -#define reg_marb_bp_r_brk_first_client___slave___lsb 13 -#define reg_marb_bp_r_brk_first_client___slave___width 1 -#define reg_marb_bp_r_brk_first_client___slave___bit 13 -#define reg_marb_bp_r_brk_first_client_offset 32 - -/* Register r_brk_size, scope marb_bp, type r */ -#define reg_marb_bp_r_brk_size_offset 36 - -/* Register rw_ack, scope marb_bp, type rw */ -#define reg_marb_bp_rw_ack_offset 40 - - -/* Constants */ -#define regk_marb_bp_no 0x00000000 -#define regk_marb_bp_rw_op_default 0x00000000 -#define regk_marb_bp_rw_options_default 0x00000000 -#define regk_marb_bp_yes 0x00000001 -#endif /* __marb_bp_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h deleted file mode 100644 index 083174678961..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __mmu_defs_asm_h -#define __mmu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/mmu/doc/mmu_regs.r - * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp - * last modfied: Mon Apr 11 17:03:20 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r - * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mm_cfg, scope mmu, type rw */ -#define reg_mmu_rw_mm_cfg___seg_0___lsb 0 -#define reg_mmu_rw_mm_cfg___seg_0___width 1 -#define reg_mmu_rw_mm_cfg___seg_0___bit 0 -#define reg_mmu_rw_mm_cfg___seg_1___lsb 1 -#define reg_mmu_rw_mm_cfg___seg_1___width 1 -#define reg_mmu_rw_mm_cfg___seg_1___bit 1 -#define reg_mmu_rw_mm_cfg___seg_2___lsb 2 -#define reg_mmu_rw_mm_cfg___seg_2___width 1 -#define reg_mmu_rw_mm_cfg___seg_2___bit 2 -#define reg_mmu_rw_mm_cfg___seg_3___lsb 3 -#define reg_mmu_rw_mm_cfg___seg_3___width 1 -#define reg_mmu_rw_mm_cfg___seg_3___bit 3 -#define reg_mmu_rw_mm_cfg___seg_4___lsb 4 -#define reg_mmu_rw_mm_cfg___seg_4___width 1 -#define reg_mmu_rw_mm_cfg___seg_4___bit 4 -#define reg_mmu_rw_mm_cfg___seg_5___lsb 5 -#define reg_mmu_rw_mm_cfg___seg_5___width 1 -#define reg_mmu_rw_mm_cfg___seg_5___bit 5 -#define reg_mmu_rw_mm_cfg___seg_6___lsb 6 -#define reg_mmu_rw_mm_cfg___seg_6___width 1 -#define reg_mmu_rw_mm_cfg___seg_6___bit 6 -#define reg_mmu_rw_mm_cfg___seg_7___lsb 7 -#define reg_mmu_rw_mm_cfg___seg_7___width 1 -#define reg_mmu_rw_mm_cfg___seg_7___bit 7 -#define reg_mmu_rw_mm_cfg___seg_8___lsb 8 -#define reg_mmu_rw_mm_cfg___seg_8___width 1 -#define reg_mmu_rw_mm_cfg___seg_8___bit 8 -#define reg_mmu_rw_mm_cfg___seg_9___lsb 9 -#define reg_mmu_rw_mm_cfg___seg_9___width 1 -#define reg_mmu_rw_mm_cfg___seg_9___bit 9 -#define reg_mmu_rw_mm_cfg___seg_a___lsb 10 -#define reg_mmu_rw_mm_cfg___seg_a___width 1 -#define reg_mmu_rw_mm_cfg___seg_a___bit 10 -#define reg_mmu_rw_mm_cfg___seg_b___lsb 11 -#define reg_mmu_rw_mm_cfg___seg_b___width 1 -#define reg_mmu_rw_mm_cfg___seg_b___bit 11 -#define reg_mmu_rw_mm_cfg___seg_c___lsb 12 -#define reg_mmu_rw_mm_cfg___seg_c___width 1 -#define reg_mmu_rw_mm_cfg___seg_c___bit 12 -#define reg_mmu_rw_mm_cfg___seg_d___lsb 13 -#define reg_mmu_rw_mm_cfg___seg_d___width 1 -#define reg_mmu_rw_mm_cfg___seg_d___bit 13 -#define reg_mmu_rw_mm_cfg___seg_e___lsb 14 -#define reg_mmu_rw_mm_cfg___seg_e___width 1 -#define reg_mmu_rw_mm_cfg___seg_e___bit 14 -#define reg_mmu_rw_mm_cfg___seg_f___lsb 15 -#define reg_mmu_rw_mm_cfg___seg_f___width 1 -#define reg_mmu_rw_mm_cfg___seg_f___bit 15 -#define reg_mmu_rw_mm_cfg___inv___lsb 16 -#define reg_mmu_rw_mm_cfg___inv___width 1 -#define reg_mmu_rw_mm_cfg___inv___bit 16 -#define reg_mmu_rw_mm_cfg___ex___lsb 17 -#define reg_mmu_rw_mm_cfg___ex___width 1 -#define reg_mmu_rw_mm_cfg___ex___bit 17 -#define reg_mmu_rw_mm_cfg___acc___lsb 18 -#define reg_mmu_rw_mm_cfg___acc___width 1 -#define reg_mmu_rw_mm_cfg___acc___bit 18 -#define reg_mmu_rw_mm_cfg___we___lsb 19 -#define reg_mmu_rw_mm_cfg___we___width 1 -#define reg_mmu_rw_mm_cfg___we___bit 19 -#define reg_mmu_rw_mm_cfg_offset 0 - -/* Register rw_mm_kbase_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0 -#define reg_mmu_rw_mm_kbase_lo___base_0___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4 -#define reg_mmu_rw_mm_kbase_lo___base_1___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8 -#define reg_mmu_rw_mm_kbase_lo___base_2___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12 -#define reg_mmu_rw_mm_kbase_lo___base_3___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16 -#define reg_mmu_rw_mm_kbase_lo___base_4___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20 -#define reg_mmu_rw_mm_kbase_lo___base_5___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24 -#define reg_mmu_rw_mm_kbase_lo___base_6___width 4 -#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28 -#define reg_mmu_rw_mm_kbase_lo___base_7___width 4 -#define reg_mmu_rw_mm_kbase_lo_offset 4 - -/* Register rw_mm_kbase_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0 -#define reg_mmu_rw_mm_kbase_hi___base_8___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4 -#define reg_mmu_rw_mm_kbase_hi___base_9___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8 -#define reg_mmu_rw_mm_kbase_hi___base_a___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12 -#define reg_mmu_rw_mm_kbase_hi___base_b___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16 -#define reg_mmu_rw_mm_kbase_hi___base_c___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20 -#define reg_mmu_rw_mm_kbase_hi___base_d___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24 -#define reg_mmu_rw_mm_kbase_hi___base_e___width 4 -#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28 -#define reg_mmu_rw_mm_kbase_hi___base_f___width 4 -#define reg_mmu_rw_mm_kbase_hi_offset 8 - -/* Register r_mm_cause, scope mmu, type r */ -#define reg_mmu_r_mm_cause___pid___lsb 0 -#define reg_mmu_r_mm_cause___pid___width 8 -#define reg_mmu_r_mm_cause___op___lsb 8 -#define reg_mmu_r_mm_cause___op___width 2 -#define reg_mmu_r_mm_cause___vpn___lsb 13 -#define reg_mmu_r_mm_cause___vpn___width 19 -#define reg_mmu_r_mm_cause_offset 12 - -/* Register rw_mm_tlb_sel, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0 -#define reg_mmu_rw_mm_tlb_sel___idx___width 4 -#define reg_mmu_rw_mm_tlb_sel___set___lsb 4 -#define reg_mmu_rw_mm_tlb_sel___set___width 2 -#define reg_mmu_rw_mm_tlb_sel_offset 16 - -/* Register rw_mm_tlb_lo, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_lo___x___lsb 0 -#define reg_mmu_rw_mm_tlb_lo___x___width 1 -#define reg_mmu_rw_mm_tlb_lo___x___bit 0 -#define reg_mmu_rw_mm_tlb_lo___w___lsb 1 -#define reg_mmu_rw_mm_tlb_lo___w___width 1 -#define reg_mmu_rw_mm_tlb_lo___w___bit 1 -#define reg_mmu_rw_mm_tlb_lo___k___lsb 2 -#define reg_mmu_rw_mm_tlb_lo___k___width 1 -#define reg_mmu_rw_mm_tlb_lo___k___bit 2 -#define reg_mmu_rw_mm_tlb_lo___v___lsb 3 -#define reg_mmu_rw_mm_tlb_lo___v___width 1 -#define reg_mmu_rw_mm_tlb_lo___v___bit 3 -#define reg_mmu_rw_mm_tlb_lo___g___lsb 4 -#define reg_mmu_rw_mm_tlb_lo___g___width 1 -#define reg_mmu_rw_mm_tlb_lo___g___bit 4 -#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13 -#define reg_mmu_rw_mm_tlb_lo___pfn___width 19 -#define reg_mmu_rw_mm_tlb_lo_offset 20 - -/* Register rw_mm_tlb_hi, scope mmu, type rw */ -#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0 -#define reg_mmu_rw_mm_tlb_hi___pid___width 8 -#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13 -#define reg_mmu_rw_mm_tlb_hi___vpn___width 19 -#define reg_mmu_rw_mm_tlb_hi_offset 24 - - -/* Constants */ -#define regk_mmu_execute 0x00000000 -#define regk_mmu_flush 0x00000003 -#define regk_mmu_linear 0x00000001 -#define regk_mmu_no 0x00000000 -#define regk_mmu_off 0x00000000 -#define regk_mmu_on 0x00000001 -#define regk_mmu_page 0x00000000 -#define regk_mmu_read 0x00000001 -#define regk_mmu_write 0x00000002 -#define regk_mmu_yes 0x00000001 -#endif /* __mmu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h deleted file mode 100644 index fd66daa79259..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define R_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h deleted file mode 100644 index 72b3d231d80f..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __rt_trace_defs_asm_h -#define __rt_trace_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope rt_trace, type rw */ -#define reg_rt_trace_rw_cfg___en___lsb 0 -#define reg_rt_trace_rw_cfg___en___width 1 -#define reg_rt_trace_rw_cfg___en___bit 0 -#define reg_rt_trace_rw_cfg___mode___lsb 1 -#define reg_rt_trace_rw_cfg___mode___width 1 -#define reg_rt_trace_rw_cfg___mode___bit 1 -#define reg_rt_trace_rw_cfg___owner___lsb 2 -#define reg_rt_trace_rw_cfg___owner___width 1 -#define reg_rt_trace_rw_cfg___owner___bit 2 -#define reg_rt_trace_rw_cfg___wp___lsb 3 -#define reg_rt_trace_rw_cfg___wp___width 1 -#define reg_rt_trace_rw_cfg___wp___bit 3 -#define reg_rt_trace_rw_cfg___stall___lsb 4 -#define reg_rt_trace_rw_cfg___stall___width 1 -#define reg_rt_trace_rw_cfg___stall___bit 4 -#define reg_rt_trace_rw_cfg___wp_start___lsb 8 -#define reg_rt_trace_rw_cfg___wp_start___width 7 -#define reg_rt_trace_rw_cfg___wp_stop___lsb 16 -#define reg_rt_trace_rw_cfg___wp_stop___width 7 -#define reg_rt_trace_rw_cfg_offset 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0 -#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1 -#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1 -#define reg_rt_trace_rw_tap_ctrl_offset 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -#define reg_rt_trace_r_tap_stat___dav___lsb 0 -#define reg_rt_trace_r_tap_stat___dav___width 1 -#define reg_rt_trace_r_tap_stat___dav___bit 0 -#define reg_rt_trace_r_tap_stat___empty___lsb 1 -#define reg_rt_trace_r_tap_stat___empty___width 1 -#define reg_rt_trace_r_tap_stat___empty___bit 1 -#define reg_rt_trace_r_tap_stat_offset 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_data_offset 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -#define reg_rt_trace_rw_tap_hdata___op___lsb 0 -#define reg_rt_trace_rw_tap_hdata___op___width 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4 -#define reg_rt_trace_rw_tap_hdata___sub_op___width 4 -#define reg_rt_trace_rw_tap_hdata_offset 16 - -/* Register r_redir, scope rt_trace, type r */ -#define reg_rt_trace_r_redir_offset 20 - - -/* Constants */ -#define regk_rt_trace_brk 0x0000000c -#define regk_rt_trace_dbg 0x00000003 -#define regk_rt_trace_dbgdi 0x00000004 -#define regk_rt_trace_dbgdo 0x00000005 -#define regk_rt_trace_gmode 0x00000000 -#define regk_rt_trace_no 0x00000000 -#define regk_rt_trace_nop 0x00000000 -#define regk_rt_trace_normal 0x00000000 -#define regk_rt_trace_rdmem 0x00000007 -#define regk_rt_trace_rdmemb 0x00000009 -#define regk_rt_trace_rdpreg 0x00000002 -#define regk_rt_trace_rdreg 0x00000001 -#define regk_rt_trace_rdsreg 0x00000003 -#define regk_rt_trace_redir 0x00000006 -#define regk_rt_trace_ret 0x0000000b -#define regk_rt_trace_rw_cfg_default 0x00000000 -#define regk_rt_trace_trcfg 0x00000001 -#define regk_rt_trace_wp 0x00000001 -#define regk_rt_trace_wp0 0x00000001 -#define regk_rt_trace_wp1 0x00000002 -#define regk_rt_trace_wp2 0x00000004 -#define regk_rt_trace_wp3 0x00000008 -#define regk_rt_trace_wp4 0x00000010 -#define regk_rt_trace_wp5 0x00000020 -#define regk_rt_trace_wp6 0x00000040 -#define regk_rt_trace_wrmem 0x00000008 -#define regk_rt_trace_wrmemb 0x0000000a -#define regk_rt_trace_wrpreg 0x00000005 -#define regk_rt_trace_wrreg 0x00000004 -#define regk_rt_trace_wrsreg 0x00000006 -#define regk_rt_trace_yes 0x00000001 -#endif /* __rt_trace_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h deleted file mode 100644 index 944f4c7666b4..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h +++ /dev/null @@ -1,360 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ser_defs_asm_h -#define __ser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tr_ctrl, scope ser, type rw */ -#define reg_ser_rw_tr_ctrl___base_freq___lsb 0 -#define reg_ser_rw_tr_ctrl___base_freq___width 3 -#define reg_ser_rw_tr_ctrl___en___lsb 3 -#define reg_ser_rw_tr_ctrl___en___width 1 -#define reg_ser_rw_tr_ctrl___en___bit 3 -#define reg_ser_rw_tr_ctrl___par___lsb 4 -#define reg_ser_rw_tr_ctrl___par___width 2 -#define reg_ser_rw_tr_ctrl___par_en___lsb 6 -#define reg_ser_rw_tr_ctrl___par_en___width 1 -#define reg_ser_rw_tr_ctrl___par_en___bit 6 -#define reg_ser_rw_tr_ctrl___data_bits___lsb 7 -#define reg_ser_rw_tr_ctrl___data_bits___width 1 -#define reg_ser_rw_tr_ctrl___data_bits___bit 7 -#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8 -#define reg_ser_rw_tr_ctrl___stop_bits___width 1 -#define reg_ser_rw_tr_ctrl___stop_bits___bit 8 -#define reg_ser_rw_tr_ctrl___stop___lsb 9 -#define reg_ser_rw_tr_ctrl___stop___width 1 -#define reg_ser_rw_tr_ctrl___stop___bit 9 -#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10 -#define reg_ser_rw_tr_ctrl___rts_delay___width 3 -#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13 -#define reg_ser_rw_tr_ctrl___rts_setup___width 1 -#define reg_ser_rw_tr_ctrl___rts_setup___bit 13 -#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14 -#define reg_ser_rw_tr_ctrl___auto_rts___width 1 -#define reg_ser_rw_tr_ctrl___auto_rts___bit 14 -#define reg_ser_rw_tr_ctrl___txd___lsb 15 -#define reg_ser_rw_tr_ctrl___txd___width 1 -#define reg_ser_rw_tr_ctrl___txd___bit 15 -#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16 -#define reg_ser_rw_tr_ctrl___auto_cts___width 1 -#define reg_ser_rw_tr_ctrl___auto_cts___bit 16 -#define reg_ser_rw_tr_ctrl_offset 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -#define reg_ser_rw_tr_dma_en___en___lsb 0 -#define reg_ser_rw_tr_dma_en___en___width 1 -#define reg_ser_rw_tr_dma_en___en___bit 0 -#define reg_ser_rw_tr_dma_en_offset 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -#define reg_ser_rw_rec_ctrl___base_freq___lsb 0 -#define reg_ser_rw_rec_ctrl___base_freq___width 3 -#define reg_ser_rw_rec_ctrl___en___lsb 3 -#define reg_ser_rw_rec_ctrl___en___width 1 -#define reg_ser_rw_rec_ctrl___en___bit 3 -#define reg_ser_rw_rec_ctrl___par___lsb 4 -#define reg_ser_rw_rec_ctrl___par___width 2 -#define reg_ser_rw_rec_ctrl___par_en___lsb 6 -#define reg_ser_rw_rec_ctrl___par_en___width 1 -#define reg_ser_rw_rec_ctrl___par_en___bit 6 -#define reg_ser_rw_rec_ctrl___data_bits___lsb 7 -#define reg_ser_rw_rec_ctrl___data_bits___width 1 -#define reg_ser_rw_rec_ctrl___data_bits___bit 7 -#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8 -#define reg_ser_rw_rec_ctrl___dma_mode___width 1 -#define reg_ser_rw_rec_ctrl___dma_mode___bit 8 -#define reg_ser_rw_rec_ctrl___dma_err___lsb 9 -#define reg_ser_rw_rec_ctrl___dma_err___width 1 -#define reg_ser_rw_rec_ctrl___dma_err___bit 9 -#define reg_ser_rw_rec_ctrl___sampling___lsb 10 -#define reg_ser_rw_rec_ctrl___sampling___width 1 -#define reg_ser_rw_rec_ctrl___sampling___bit 10 -#define reg_ser_rw_rec_ctrl___timeout___lsb 11 -#define reg_ser_rw_rec_ctrl___timeout___width 3 -#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14 -#define reg_ser_rw_rec_ctrl___auto_eop___width 1 -#define reg_ser_rw_rec_ctrl___auto_eop___bit 14 -#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15 -#define reg_ser_rw_rec_ctrl___half_duplex___width 1 -#define reg_ser_rw_rec_ctrl___half_duplex___bit 15 -#define reg_ser_rw_rec_ctrl___rts_n___lsb 16 -#define reg_ser_rw_rec_ctrl___rts_n___width 1 -#define reg_ser_rw_rec_ctrl___rts_n___bit 16 -#define reg_ser_rw_rec_ctrl___loopback___lsb 17 -#define reg_ser_rw_rec_ctrl___loopback___width 1 -#define reg_ser_rw_rec_ctrl___loopback___bit 17 -#define reg_ser_rw_rec_ctrl_offset 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -#define reg_ser_rw_tr_baud_div___div___lsb 0 -#define reg_ser_rw_tr_baud_div___div___width 16 -#define reg_ser_rw_tr_baud_div_offset 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -#define reg_ser_rw_rec_baud_div___div___lsb 0 -#define reg_ser_rw_rec_baud_div___div___width 16 -#define reg_ser_rw_rec_baud_div_offset 16 - -/* Register rw_xoff, scope ser, type rw */ -#define reg_ser_rw_xoff___chr___lsb 0 -#define reg_ser_rw_xoff___chr___width 8 -#define reg_ser_rw_xoff___automatic___lsb 8 -#define reg_ser_rw_xoff___automatic___width 1 -#define reg_ser_rw_xoff___automatic___bit 8 -#define reg_ser_rw_xoff_offset 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -#define reg_ser_rw_xoff_clr___clr___lsb 0 -#define reg_ser_rw_xoff_clr___clr___width 1 -#define reg_ser_rw_xoff_clr___clr___bit 0 -#define reg_ser_rw_xoff_clr_offset 24 - -/* Register rw_dout, scope ser, type rw */ -#define reg_ser_rw_dout___data___lsb 0 -#define reg_ser_rw_dout___data___width 8 -#define reg_ser_rw_dout_offset 28 - -/* Register rs_stat_din, scope ser, type rs */ -#define reg_ser_rs_stat_din___data___lsb 0 -#define reg_ser_rs_stat_din___data___width 8 -#define reg_ser_rs_stat_din___dav___lsb 16 -#define reg_ser_rs_stat_din___dav___width 1 -#define reg_ser_rs_stat_din___dav___bit 16 -#define reg_ser_rs_stat_din___framing_err___lsb 17 -#define reg_ser_rs_stat_din___framing_err___width 1 -#define reg_ser_rs_stat_din___framing_err___bit 17 -#define reg_ser_rs_stat_din___par_err___lsb 18 -#define reg_ser_rs_stat_din___par_err___width 1 -#define reg_ser_rs_stat_din___par_err___bit 18 -#define reg_ser_rs_stat_din___orun___lsb 19 -#define reg_ser_rs_stat_din___orun___width 1 -#define reg_ser_rs_stat_din___orun___bit 19 -#define reg_ser_rs_stat_din___rec_err___lsb 20 -#define reg_ser_rs_stat_din___rec_err___width 1 -#define reg_ser_rs_stat_din___rec_err___bit 20 -#define reg_ser_rs_stat_din___rxd___lsb 21 -#define reg_ser_rs_stat_din___rxd___width 1 -#define reg_ser_rs_stat_din___rxd___bit 21 -#define reg_ser_rs_stat_din___tr_idle___lsb 22 -#define reg_ser_rs_stat_din___tr_idle___width 1 -#define reg_ser_rs_stat_din___tr_idle___bit 22 -#define reg_ser_rs_stat_din___tr_empty___lsb 23 -#define reg_ser_rs_stat_din___tr_empty___width 1 -#define reg_ser_rs_stat_din___tr_empty___bit 23 -#define reg_ser_rs_stat_din___tr_rdy___lsb 24 -#define reg_ser_rs_stat_din___tr_rdy___width 1 -#define reg_ser_rs_stat_din___tr_rdy___bit 24 -#define reg_ser_rs_stat_din___cts_n___lsb 25 -#define reg_ser_rs_stat_din___cts_n___width 1 -#define reg_ser_rs_stat_din___cts_n___bit 25 -#define reg_ser_rs_stat_din___xoff_detect___lsb 26 -#define reg_ser_rs_stat_din___xoff_detect___width 1 -#define reg_ser_rs_stat_din___xoff_detect___bit 26 -#define reg_ser_rs_stat_din___rts_n___lsb 27 -#define reg_ser_rs_stat_din___rts_n___width 1 -#define reg_ser_rs_stat_din___rts_n___bit 27 -#define reg_ser_rs_stat_din___txd___lsb 28 -#define reg_ser_rs_stat_din___txd___width 1 -#define reg_ser_rs_stat_din___txd___bit 28 -#define reg_ser_rs_stat_din_offset 32 - -/* Register r_stat_din, scope ser, type r */ -#define reg_ser_r_stat_din___data___lsb 0 -#define reg_ser_r_stat_din___data___width 8 -#define reg_ser_r_stat_din___dav___lsb 16 -#define reg_ser_r_stat_din___dav___width 1 -#define reg_ser_r_stat_din___dav___bit 16 -#define reg_ser_r_stat_din___framing_err___lsb 17 -#define reg_ser_r_stat_din___framing_err___width 1 -#define reg_ser_r_stat_din___framing_err___bit 17 -#define reg_ser_r_stat_din___par_err___lsb 18 -#define reg_ser_r_stat_din___par_err___width 1 -#define reg_ser_r_stat_din___par_err___bit 18 -#define reg_ser_r_stat_din___orun___lsb 19 -#define reg_ser_r_stat_din___orun___width 1 -#define reg_ser_r_stat_din___orun___bit 19 -#define reg_ser_r_stat_din___rec_err___lsb 20 -#define reg_ser_r_stat_din___rec_err___width 1 -#define reg_ser_r_stat_din___rec_err___bit 20 -#define reg_ser_r_stat_din___rxd___lsb 21 -#define reg_ser_r_stat_din___rxd___width 1 -#define reg_ser_r_stat_din___rxd___bit 21 -#define reg_ser_r_stat_din___tr_idle___lsb 22 -#define reg_ser_r_stat_din___tr_idle___width 1 -#define reg_ser_r_stat_din___tr_idle___bit 22 -#define reg_ser_r_stat_din___tr_empty___lsb 23 -#define reg_ser_r_stat_din___tr_empty___width 1 -#define reg_ser_r_stat_din___tr_empty___bit 23 -#define reg_ser_r_stat_din___tr_rdy___lsb 24 -#define reg_ser_r_stat_din___tr_rdy___width 1 -#define reg_ser_r_stat_din___tr_rdy___bit 24 -#define reg_ser_r_stat_din___cts_n___lsb 25 -#define reg_ser_r_stat_din___cts_n___width 1 -#define reg_ser_r_stat_din___cts_n___bit 25 -#define reg_ser_r_stat_din___xoff_detect___lsb 26 -#define reg_ser_r_stat_din___xoff_detect___width 1 -#define reg_ser_r_stat_din___xoff_detect___bit 26 -#define reg_ser_r_stat_din___rts_n___lsb 27 -#define reg_ser_r_stat_din___rts_n___width 1 -#define reg_ser_r_stat_din___rts_n___bit 27 -#define reg_ser_r_stat_din___txd___lsb 28 -#define reg_ser_r_stat_din___txd___width 1 -#define reg_ser_r_stat_din___txd___bit 28 -#define reg_ser_r_stat_din_offset 36 - -/* Register rw_rec_eop, scope ser, type rw */ -#define reg_ser_rw_rec_eop___set___lsb 0 -#define reg_ser_rw_rec_eop___set___width 1 -#define reg_ser_rw_rec_eop___set___bit 0 -#define reg_ser_rw_rec_eop_offset 40 - -/* Register rw_intr_mask, scope ser, type rw */ -#define reg_ser_rw_intr_mask___tr_rdy___lsb 0 -#define reg_ser_rw_intr_mask___tr_rdy___width 1 -#define reg_ser_rw_intr_mask___tr_rdy___bit 0 -#define reg_ser_rw_intr_mask___tr_empty___lsb 1 -#define reg_ser_rw_intr_mask___tr_empty___width 1 -#define reg_ser_rw_intr_mask___tr_empty___bit 1 -#define reg_ser_rw_intr_mask___tr_idle___lsb 2 -#define reg_ser_rw_intr_mask___tr_idle___width 1 -#define reg_ser_rw_intr_mask___tr_idle___bit 2 -#define reg_ser_rw_intr_mask___dav___lsb 3 -#define reg_ser_rw_intr_mask___dav___width 1 -#define reg_ser_rw_intr_mask___dav___bit 3 -#define reg_ser_rw_intr_mask_offset 44 - -/* Register rw_ack_intr, scope ser, type rw */ -#define reg_ser_rw_ack_intr___tr_rdy___lsb 0 -#define reg_ser_rw_ack_intr___tr_rdy___width 1 -#define reg_ser_rw_ack_intr___tr_rdy___bit 0 -#define reg_ser_rw_ack_intr___tr_empty___lsb 1 -#define reg_ser_rw_ack_intr___tr_empty___width 1 -#define reg_ser_rw_ack_intr___tr_empty___bit 1 -#define reg_ser_rw_ack_intr___tr_idle___lsb 2 -#define reg_ser_rw_ack_intr___tr_idle___width 1 -#define reg_ser_rw_ack_intr___tr_idle___bit 2 -#define reg_ser_rw_ack_intr___dav___lsb 3 -#define reg_ser_rw_ack_intr___dav___width 1 -#define reg_ser_rw_ack_intr___dav___bit 3 -#define reg_ser_rw_ack_intr_offset 48 - -/* Register r_intr, scope ser, type r */ -#define reg_ser_r_intr___tr_rdy___lsb 0 -#define reg_ser_r_intr___tr_rdy___width 1 -#define reg_ser_r_intr___tr_rdy___bit 0 -#define reg_ser_r_intr___tr_empty___lsb 1 -#define reg_ser_r_intr___tr_empty___width 1 -#define reg_ser_r_intr___tr_empty___bit 1 -#define reg_ser_r_intr___tr_idle___lsb 2 -#define reg_ser_r_intr___tr_idle___width 1 -#define reg_ser_r_intr___tr_idle___bit 2 -#define reg_ser_r_intr___dav___lsb 3 -#define reg_ser_r_intr___dav___width 1 -#define reg_ser_r_intr___dav___bit 3 -#define reg_ser_r_intr_offset 52 - -/* Register r_masked_intr, scope ser, type r */ -#define reg_ser_r_masked_intr___tr_rdy___lsb 0 -#define reg_ser_r_masked_intr___tr_rdy___width 1 -#define reg_ser_r_masked_intr___tr_rdy___bit 0 -#define reg_ser_r_masked_intr___tr_empty___lsb 1 -#define reg_ser_r_masked_intr___tr_empty___width 1 -#define reg_ser_r_masked_intr___tr_empty___bit 1 -#define reg_ser_r_masked_intr___tr_idle___lsb 2 -#define reg_ser_r_masked_intr___tr_idle___width 1 -#define reg_ser_r_masked_intr___tr_idle___bit 2 -#define reg_ser_r_masked_intr___dav___lsb 3 -#define reg_ser_r_masked_intr___dav___width 1 -#define reg_ser_r_masked_intr___dav___bit 3 -#define reg_ser_r_masked_intr_offset 56 - - -/* Constants */ -#define regk_ser_active 0x00000000 -#define regk_ser_bits1 0x00000000 -#define regk_ser_bits2 0x00000001 -#define regk_ser_bits7 0x00000001 -#define regk_ser_bits8 0x00000000 -#define regk_ser_del0_5 0x00000000 -#define regk_ser_del1 0x00000001 -#define regk_ser_del1_5 0x00000002 -#define regk_ser_del2 0x00000003 -#define regk_ser_del2_5 0x00000004 -#define regk_ser_del3 0x00000005 -#define regk_ser_del3_5 0x00000006 -#define regk_ser_del4 0x00000007 -#define regk_ser_even 0x00000000 -#define regk_ser_ext 0x00000001 -#define regk_ser_f100 0x00000007 -#define regk_ser_f29_493 0x00000004 -#define regk_ser_f32 0x00000005 -#define regk_ser_f32_768 0x00000006 -#define regk_ser_ignore 0x00000001 -#define regk_ser_inactive 0x00000001 -#define regk_ser_majority 0x00000001 -#define regk_ser_mark 0x00000002 -#define regk_ser_middle 0x00000000 -#define regk_ser_no 0x00000000 -#define regk_ser_odd 0x00000001 -#define regk_ser_off 0x00000000 -#define regk_ser_rw_intr_mask_default 0x00000000 -#define regk_ser_rw_rec_baud_div_default 0x00000000 -#define regk_ser_rw_rec_ctrl_default 0x00010000 -#define regk_ser_rw_tr_baud_div_default 0x00000000 -#define regk_ser_rw_tr_ctrl_default 0x00008000 -#define regk_ser_rw_tr_dma_en_default 0x00000000 -#define regk_ser_rw_xoff_default 0x00000000 -#define regk_ser_space 0x00000003 -#define regk_ser_stop 0x00000000 -#define regk_ser_yes 0x00000001 -#endif /* __ser_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h deleted file mode 100644 index 607b505100fa..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h +++ /dev/null @@ -1,463 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __sser_defs_asm_h -#define __sser_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope sser, type rw */ -#define reg_sser_rw_cfg___clk_div___lsb 0 -#define reg_sser_rw_cfg___clk_div___width 16 -#define reg_sser_rw_cfg___base_freq___lsb 16 -#define reg_sser_rw_cfg___base_freq___width 3 -#define reg_sser_rw_cfg___gate_clk___lsb 19 -#define reg_sser_rw_cfg___gate_clk___width 1 -#define reg_sser_rw_cfg___gate_clk___bit 19 -#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20 -#define reg_sser_rw_cfg___clkgate_ctrl___width 1 -#define reg_sser_rw_cfg___clkgate_ctrl___bit 20 -#define reg_sser_rw_cfg___clkgate_in___lsb 21 -#define reg_sser_rw_cfg___clkgate_in___width 1 -#define reg_sser_rw_cfg___clkgate_in___bit 21 -#define reg_sser_rw_cfg___clk_dir___lsb 22 -#define reg_sser_rw_cfg___clk_dir___width 1 -#define reg_sser_rw_cfg___clk_dir___bit 22 -#define reg_sser_rw_cfg___clk_od_mode___lsb 23 -#define reg_sser_rw_cfg___clk_od_mode___width 1 -#define reg_sser_rw_cfg___clk_od_mode___bit 23 -#define reg_sser_rw_cfg___out_clk_pol___lsb 24 -#define reg_sser_rw_cfg___out_clk_pol___width 1 -#define reg_sser_rw_cfg___out_clk_pol___bit 24 -#define reg_sser_rw_cfg___out_clk_src___lsb 25 -#define reg_sser_rw_cfg___out_clk_src___width 2 -#define reg_sser_rw_cfg___clk_in_sel___lsb 27 -#define reg_sser_rw_cfg___clk_in_sel___width 1 -#define reg_sser_rw_cfg___clk_in_sel___bit 27 -#define reg_sser_rw_cfg___hold_pol___lsb 28 -#define reg_sser_rw_cfg___hold_pol___width 1 -#define reg_sser_rw_cfg___hold_pol___bit 28 -#define reg_sser_rw_cfg___prepare___lsb 29 -#define reg_sser_rw_cfg___prepare___width 1 -#define reg_sser_rw_cfg___prepare___bit 29 -#define reg_sser_rw_cfg___en___lsb 30 -#define reg_sser_rw_cfg___en___width 1 -#define reg_sser_rw_cfg___en___bit 30 -#define reg_sser_rw_cfg_offset 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -#define reg_sser_rw_frm_cfg___wordrate___lsb 0 -#define reg_sser_rw_frm_cfg___wordrate___width 10 -#define reg_sser_rw_frm_cfg___rec_delay___lsb 10 -#define reg_sser_rw_frm_cfg___rec_delay___width 3 -#define reg_sser_rw_frm_cfg___tr_delay___lsb 13 -#define reg_sser_rw_frm_cfg___tr_delay___width 3 -#define reg_sser_rw_frm_cfg___early_wend___lsb 16 -#define reg_sser_rw_frm_cfg___early_wend___width 1 -#define reg_sser_rw_frm_cfg___early_wend___bit 16 -#define reg_sser_rw_frm_cfg___level___lsb 17 -#define reg_sser_rw_frm_cfg___level___width 2 -#define reg_sser_rw_frm_cfg___type___lsb 19 -#define reg_sser_rw_frm_cfg___type___width 1 -#define reg_sser_rw_frm_cfg___type___bit 19 -#define reg_sser_rw_frm_cfg___clk_pol___lsb 20 -#define reg_sser_rw_frm_cfg___clk_pol___width 1 -#define reg_sser_rw_frm_cfg___clk_pol___bit 20 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1 -#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21 -#define reg_sser_rw_frm_cfg___clk_src___lsb 22 -#define reg_sser_rw_frm_cfg___clk_src___width 1 -#define reg_sser_rw_frm_cfg___clk_src___bit 22 -#define reg_sser_rw_frm_cfg___out_off___lsb 23 -#define reg_sser_rw_frm_cfg___out_off___width 1 -#define reg_sser_rw_frm_cfg___out_off___bit 23 -#define reg_sser_rw_frm_cfg___out_on___lsb 24 -#define reg_sser_rw_frm_cfg___out_on___width 1 -#define reg_sser_rw_frm_cfg___out_on___bit 24 -#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25 -#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25 -#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26 -#define reg_sser_rw_frm_cfg___frame_pin_use___width 2 -#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28 -#define reg_sser_rw_frm_cfg___status_pin_dir___width 1 -#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28 -#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29 -#define reg_sser_rw_frm_cfg___status_pin_use___width 2 -#define reg_sser_rw_frm_cfg_offset 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -#define reg_sser_rw_tr_cfg___tr_en___lsb 0 -#define reg_sser_rw_tr_cfg___tr_en___width 1 -#define reg_sser_rw_tr_cfg___tr_en___bit 0 -#define reg_sser_rw_tr_cfg___stop___lsb 1 -#define reg_sser_rw_tr_cfg___stop___width 1 -#define reg_sser_rw_tr_cfg___stop___bit 1 -#define reg_sser_rw_tr_cfg___urun_stop___lsb 2 -#define reg_sser_rw_tr_cfg___urun_stop___width 1 -#define reg_sser_rw_tr_cfg___urun_stop___bit 2 -#define reg_sser_rw_tr_cfg___eop_stop___lsb 3 -#define reg_sser_rw_tr_cfg___eop_stop___width 1 -#define reg_sser_rw_tr_cfg___eop_stop___bit 3 -#define reg_sser_rw_tr_cfg___sample_size___lsb 4 -#define reg_sser_rw_tr_cfg___sample_size___width 6 -#define reg_sser_rw_tr_cfg___sh_dir___lsb 10 -#define reg_sser_rw_tr_cfg___sh_dir___width 1 -#define reg_sser_rw_tr_cfg___sh_dir___bit 10 -#define reg_sser_rw_tr_cfg___clk_pol___lsb 11 -#define reg_sser_rw_tr_cfg___clk_pol___width 1 -#define reg_sser_rw_tr_cfg___clk_pol___bit 11 -#define reg_sser_rw_tr_cfg___clk_src___lsb 12 -#define reg_sser_rw_tr_cfg___clk_src___width 1 -#define reg_sser_rw_tr_cfg___clk_src___bit 12 -#define reg_sser_rw_tr_cfg___use_dma___lsb 13 -#define reg_sser_rw_tr_cfg___use_dma___width 1 -#define reg_sser_rw_tr_cfg___use_dma___bit 13 -#define reg_sser_rw_tr_cfg___mode___lsb 14 -#define reg_sser_rw_tr_cfg___mode___width 2 -#define reg_sser_rw_tr_cfg___frm_src___lsb 16 -#define reg_sser_rw_tr_cfg___frm_src___width 1 -#define reg_sser_rw_tr_cfg___frm_src___bit 16 -#define reg_sser_rw_tr_cfg___use60958___lsb 17 -#define reg_sser_rw_tr_cfg___use60958___width 1 -#define reg_sser_rw_tr_cfg___use60958___bit 17 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18 -#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2 -#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20 -#define reg_sser_rw_tr_cfg___rate_ctrl___width 1 -#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20 -#define reg_sser_rw_tr_cfg___use_md___lsb 21 -#define reg_sser_rw_tr_cfg___use_md___width 1 -#define reg_sser_rw_tr_cfg___use_md___bit 21 -#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22 -#define reg_sser_rw_tr_cfg___dual_i2s___width 1 -#define reg_sser_rw_tr_cfg___dual_i2s___bit 22 -#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23 -#define reg_sser_rw_tr_cfg___data_pin_use___width 2 -#define reg_sser_rw_tr_cfg___od_mode___lsb 25 -#define reg_sser_rw_tr_cfg___od_mode___width 1 -#define reg_sser_rw_tr_cfg___od_mode___bit 25 -#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26 -#define reg_sser_rw_tr_cfg___bulk_wspace___width 2 -#define reg_sser_rw_tr_cfg_offset 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -#define reg_sser_rw_rec_cfg___rec_en___lsb 0 -#define reg_sser_rw_rec_cfg___rec_en___width 1 -#define reg_sser_rw_rec_cfg___rec_en___bit 0 -#define reg_sser_rw_rec_cfg___force_eop___lsb 1 -#define reg_sser_rw_rec_cfg___force_eop___width 1 -#define reg_sser_rw_rec_cfg___force_eop___bit 1 -#define reg_sser_rw_rec_cfg___stop___lsb 2 -#define reg_sser_rw_rec_cfg___stop___width 1 -#define reg_sser_rw_rec_cfg___stop___bit 2 -#define reg_sser_rw_rec_cfg___orun_stop___lsb 3 -#define reg_sser_rw_rec_cfg___orun_stop___width 1 -#define reg_sser_rw_rec_cfg___orun_stop___bit 3 -#define reg_sser_rw_rec_cfg___eop_stop___lsb 4 -#define reg_sser_rw_rec_cfg___eop_stop___width 1 -#define reg_sser_rw_rec_cfg___eop_stop___bit 4 -#define reg_sser_rw_rec_cfg___sample_size___lsb 5 -#define reg_sser_rw_rec_cfg___sample_size___width 6 -#define reg_sser_rw_rec_cfg___sh_dir___lsb 11 -#define reg_sser_rw_rec_cfg___sh_dir___width 1 -#define reg_sser_rw_rec_cfg___sh_dir___bit 11 -#define reg_sser_rw_rec_cfg___clk_pol___lsb 12 -#define reg_sser_rw_rec_cfg___clk_pol___width 1 -#define reg_sser_rw_rec_cfg___clk_pol___bit 12 -#define reg_sser_rw_rec_cfg___clk_src___lsb 13 -#define reg_sser_rw_rec_cfg___clk_src___width 1 -#define reg_sser_rw_rec_cfg___clk_src___bit 13 -#define reg_sser_rw_rec_cfg___use_dma___lsb 14 -#define reg_sser_rw_rec_cfg___use_dma___width 1 -#define reg_sser_rw_rec_cfg___use_dma___bit 14 -#define reg_sser_rw_rec_cfg___mode___lsb 15 -#define reg_sser_rw_rec_cfg___mode___width 2 -#define reg_sser_rw_rec_cfg___frm_src___lsb 17 -#define reg_sser_rw_rec_cfg___frm_src___width 2 -#define reg_sser_rw_rec_cfg___use60958___lsb 19 -#define reg_sser_rw_rec_cfg___use60958___width 1 -#define reg_sser_rw_rec_cfg___use60958___bit 19 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20 -#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5 -#define reg_sser_rw_rec_cfg___slave2_en___lsb 25 -#define reg_sser_rw_rec_cfg___slave2_en___width 1 -#define reg_sser_rw_rec_cfg___slave2_en___bit 25 -#define reg_sser_rw_rec_cfg___slave3_en___lsb 26 -#define reg_sser_rw_rec_cfg___slave3_en___width 1 -#define reg_sser_rw_rec_cfg___slave3_en___bit 26 -#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27 -#define reg_sser_rw_rec_cfg___fifo_thr___width 2 -#define reg_sser_rw_rec_cfg_offset 12 - -/* Register rw_tr_data, scope sser, type rw */ -#define reg_sser_rw_tr_data___data___lsb 0 -#define reg_sser_rw_tr_data___data___width 16 -#define reg_sser_rw_tr_data___md___lsb 16 -#define reg_sser_rw_tr_data___md___width 1 -#define reg_sser_rw_tr_data___md___bit 16 -#define reg_sser_rw_tr_data_offset 16 - -/* Register r_rec_data, scope sser, type r */ -#define reg_sser_r_rec_data___data___lsb 0 -#define reg_sser_r_rec_data___data___width 16 -#define reg_sser_r_rec_data___md___lsb 16 -#define reg_sser_r_rec_data___md___width 1 -#define reg_sser_r_rec_data___md___bit 16 -#define reg_sser_r_rec_data___ext_clk___lsb 17 -#define reg_sser_r_rec_data___ext_clk___width 1 -#define reg_sser_r_rec_data___ext_clk___bit 17 -#define reg_sser_r_rec_data___status_in___lsb 18 -#define reg_sser_r_rec_data___status_in___width 1 -#define reg_sser_r_rec_data___status_in___bit 18 -#define reg_sser_r_rec_data___frame_in___lsb 19 -#define reg_sser_r_rec_data___frame_in___width 1 -#define reg_sser_r_rec_data___frame_in___bit 19 -#define reg_sser_r_rec_data___din___lsb 20 -#define reg_sser_r_rec_data___din___width 1 -#define reg_sser_r_rec_data___din___bit 20 -#define reg_sser_r_rec_data___data_in___lsb 21 -#define reg_sser_r_rec_data___data_in___width 1 -#define reg_sser_r_rec_data___data_in___bit 21 -#define reg_sser_r_rec_data___clk_in___lsb 22 -#define reg_sser_r_rec_data___clk_in___width 1 -#define reg_sser_r_rec_data___clk_in___bit 22 -#define reg_sser_r_rec_data_offset 20 - -/* Register rw_extra, scope sser, type rw */ -#define reg_sser_rw_extra___clkoff_cycles___lsb 0 -#define reg_sser_rw_extra___clkoff_cycles___width 20 -#define reg_sser_rw_extra___clkoff_en___lsb 20 -#define reg_sser_rw_extra___clkoff_en___width 1 -#define reg_sser_rw_extra___clkoff_en___bit 20 -#define reg_sser_rw_extra___clkon_en___lsb 21 -#define reg_sser_rw_extra___clkon_en___width 1 -#define reg_sser_rw_extra___clkon_en___bit 21 -#define reg_sser_rw_extra___dout_delay___lsb 22 -#define reg_sser_rw_extra___dout_delay___width 5 -#define reg_sser_rw_extra_offset 24 - -/* Register rw_intr_mask, scope sser, type rw */ -#define reg_sser_rw_intr_mask___trdy___lsb 0 -#define reg_sser_rw_intr_mask___trdy___width 1 -#define reg_sser_rw_intr_mask___trdy___bit 0 -#define reg_sser_rw_intr_mask___rdav___lsb 1 -#define reg_sser_rw_intr_mask___rdav___width 1 -#define reg_sser_rw_intr_mask___rdav___bit 1 -#define reg_sser_rw_intr_mask___tidle___lsb 2 -#define reg_sser_rw_intr_mask___tidle___width 1 -#define reg_sser_rw_intr_mask___tidle___bit 2 -#define reg_sser_rw_intr_mask___rstop___lsb 3 -#define reg_sser_rw_intr_mask___rstop___width 1 -#define reg_sser_rw_intr_mask___rstop___bit 3 -#define reg_sser_rw_intr_mask___urun___lsb 4 -#define reg_sser_rw_intr_mask___urun___width 1 -#define reg_sser_rw_intr_mask___urun___bit 4 -#define reg_sser_rw_intr_mask___orun___lsb 5 -#define reg_sser_rw_intr_mask___orun___width 1 -#define reg_sser_rw_intr_mask___orun___bit 5 -#define reg_sser_rw_intr_mask___md_rec___lsb 6 -#define reg_sser_rw_intr_mask___md_rec___width 1 -#define reg_sser_rw_intr_mask___md_rec___bit 6 -#define reg_sser_rw_intr_mask___md_sent___lsb 7 -#define reg_sser_rw_intr_mask___md_sent___width 1 -#define reg_sser_rw_intr_mask___md_sent___bit 7 -#define reg_sser_rw_intr_mask___r958err___lsb 8 -#define reg_sser_rw_intr_mask___r958err___width 1 -#define reg_sser_rw_intr_mask___r958err___bit 8 -#define reg_sser_rw_intr_mask_offset 28 - -/* Register rw_ack_intr, scope sser, type rw */ -#define reg_sser_rw_ack_intr___trdy___lsb 0 -#define reg_sser_rw_ack_intr___trdy___width 1 -#define reg_sser_rw_ack_intr___trdy___bit 0 -#define reg_sser_rw_ack_intr___rdav___lsb 1 -#define reg_sser_rw_ack_intr___rdav___width 1 -#define reg_sser_rw_ack_intr___rdav___bit 1 -#define reg_sser_rw_ack_intr___tidle___lsb 2 -#define reg_sser_rw_ack_intr___tidle___width 1 -#define reg_sser_rw_ack_intr___tidle___bit 2 -#define reg_sser_rw_ack_intr___rstop___lsb 3 -#define reg_sser_rw_ack_intr___rstop___width 1 -#define reg_sser_rw_ack_intr___rstop___bit 3 -#define reg_sser_rw_ack_intr___urun___lsb 4 -#define reg_sser_rw_ack_intr___urun___width 1 -#define reg_sser_rw_ack_intr___urun___bit 4 -#define reg_sser_rw_ack_intr___orun___lsb 5 -#define reg_sser_rw_ack_intr___orun___width 1 -#define reg_sser_rw_ack_intr___orun___bit 5 -#define reg_sser_rw_ack_intr___md_rec___lsb 6 -#define reg_sser_rw_ack_intr___md_rec___width 1 -#define reg_sser_rw_ack_intr___md_rec___bit 6 -#define reg_sser_rw_ack_intr___md_sent___lsb 7 -#define reg_sser_rw_ack_intr___md_sent___width 1 -#define reg_sser_rw_ack_intr___md_sent___bit 7 -#define reg_sser_rw_ack_intr___r958err___lsb 8 -#define reg_sser_rw_ack_intr___r958err___width 1 -#define reg_sser_rw_ack_intr___r958err___bit 8 -#define reg_sser_rw_ack_intr_offset 32 - -/* Register r_intr, scope sser, type r */ -#define reg_sser_r_intr___trdy___lsb 0 -#define reg_sser_r_intr___trdy___width 1 -#define reg_sser_r_intr___trdy___bit 0 -#define reg_sser_r_intr___rdav___lsb 1 -#define reg_sser_r_intr___rdav___width 1 -#define reg_sser_r_intr___rdav___bit 1 -#define reg_sser_r_intr___tidle___lsb 2 -#define reg_sser_r_intr___tidle___width 1 -#define reg_sser_r_intr___tidle___bit 2 -#define reg_sser_r_intr___rstop___lsb 3 -#define reg_sser_r_intr___rstop___width 1 -#define reg_sser_r_intr___rstop___bit 3 -#define reg_sser_r_intr___urun___lsb 4 -#define reg_sser_r_intr___urun___width 1 -#define reg_sser_r_intr___urun___bit 4 -#define reg_sser_r_intr___orun___lsb 5 -#define reg_sser_r_intr___orun___width 1 -#define reg_sser_r_intr___orun___bit 5 -#define reg_sser_r_intr___md_rec___lsb 6 -#define reg_sser_r_intr___md_rec___width 1 -#define reg_sser_r_intr___md_rec___bit 6 -#define reg_sser_r_intr___md_sent___lsb 7 -#define reg_sser_r_intr___md_sent___width 1 -#define reg_sser_r_intr___md_sent___bit 7 -#define reg_sser_r_intr___r958err___lsb 8 -#define reg_sser_r_intr___r958err___width 1 -#define reg_sser_r_intr___r958err___bit 8 -#define reg_sser_r_intr_offset 36 - -/* Register r_masked_intr, scope sser, type r */ -#define reg_sser_r_masked_intr___trdy___lsb 0 -#define reg_sser_r_masked_intr___trdy___width 1 -#define reg_sser_r_masked_intr___trdy___bit 0 -#define reg_sser_r_masked_intr___rdav___lsb 1 -#define reg_sser_r_masked_intr___rdav___width 1 -#define reg_sser_r_masked_intr___rdav___bit 1 -#define reg_sser_r_masked_intr___tidle___lsb 2 -#define reg_sser_r_masked_intr___tidle___width 1 -#define reg_sser_r_masked_intr___tidle___bit 2 -#define reg_sser_r_masked_intr___rstop___lsb 3 -#define reg_sser_r_masked_intr___rstop___width 1 -#define reg_sser_r_masked_intr___rstop___bit 3 -#define reg_sser_r_masked_intr___urun___lsb 4 -#define reg_sser_r_masked_intr___urun___width 1 -#define reg_sser_r_masked_intr___urun___bit 4 -#define reg_sser_r_masked_intr___orun___lsb 5 -#define reg_sser_r_masked_intr___orun___width 1 -#define reg_sser_r_masked_intr___orun___bit 5 -#define reg_sser_r_masked_intr___md_rec___lsb 6 -#define reg_sser_r_masked_intr___md_rec___width 1 -#define reg_sser_r_masked_intr___md_rec___bit 6 -#define reg_sser_r_masked_intr___md_sent___lsb 7 -#define reg_sser_r_masked_intr___md_sent___width 1 -#define reg_sser_r_masked_intr___md_sent___bit 7 -#define reg_sser_r_masked_intr___r958err___lsb 8 -#define reg_sser_r_masked_intr___r958err___width 1 -#define reg_sser_r_masked_intr___r958err___bit 8 -#define reg_sser_r_masked_intr_offset 40 - - -/* Constants */ -#define regk_sser_both 0x00000002 -#define regk_sser_bulk 0x00000001 -#define regk_sser_clk100 0x00000000 -#define regk_sser_clk_in 0x00000000 -#define regk_sser_const0 0x00000003 -#define regk_sser_dout 0x00000002 -#define regk_sser_edge 0x00000000 -#define regk_sser_ext 0x00000001 -#define regk_sser_ext_clk 0x00000001 -#define regk_sser_f100 0x00000000 -#define regk_sser_f29_493 0x00000004 -#define regk_sser_f32 0x00000005 -#define regk_sser_f32_768 0x00000006 -#define regk_sser_frm 0x00000003 -#define regk_sser_gio0 0x00000000 -#define regk_sser_gio1 0x00000001 -#define regk_sser_hispeed 0x00000001 -#define regk_sser_hold 0x00000002 -#define regk_sser_in 0x00000000 -#define regk_sser_inf 0x00000003 -#define regk_sser_intern 0x00000000 -#define regk_sser_intern_clk 0x00000001 -#define regk_sser_intern_tb 0x00000000 -#define regk_sser_iso 0x00000000 -#define regk_sser_level 0x00000001 -#define regk_sser_lospeed 0x00000000 -#define regk_sser_lsbfirst 0x00000000 -#define regk_sser_msbfirst 0x00000001 -#define regk_sser_neg 0x00000001 -#define regk_sser_neg_lo 0x00000000 -#define regk_sser_no 0x00000000 -#define regk_sser_no_clk 0x00000007 -#define regk_sser_nojitter 0x00000002 -#define regk_sser_out 0x00000001 -#define regk_sser_pos 0x00000000 -#define regk_sser_pos_hi 0x00000001 -#define regk_sser_rec 0x00000000 -#define regk_sser_rw_cfg_default 0x00000000 -#define regk_sser_rw_extra_default 0x00000000 -#define regk_sser_rw_frm_cfg_default 0x00000000 -#define regk_sser_rw_intr_mask_default 0x00000000 -#define regk_sser_rw_rec_cfg_default 0x00000000 -#define regk_sser_rw_tr_cfg_default 0x01800000 -#define regk_sser_rw_tr_data_default 0x00000000 -#define regk_sser_thr16 0x00000001 -#define regk_sser_thr32 0x00000002 -#define regk_sser_thr8 0x00000000 -#define regk_sser_tr 0x00000001 -#define regk_sser_ts_out 0x00000003 -#define regk_sser_tx_bulk 0x00000002 -#define regk_sser_wiresave 0x00000002 -#define regk_sser_yes 0x00000001 -#endif /* __sser_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h deleted file mode 100644 index fab117b00ab6..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __strcop_defs_asm_h -#define __strcop_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strcop, type rw */ -#define reg_strcop_rw_cfg___td3___lsb 0 -#define reg_strcop_rw_cfg___td3___width 1 -#define reg_strcop_rw_cfg___td3___bit 0 -#define reg_strcop_rw_cfg___td2___lsb 1 -#define reg_strcop_rw_cfg___td2___width 1 -#define reg_strcop_rw_cfg___td2___bit 1 -#define reg_strcop_rw_cfg___td1___lsb 2 -#define reg_strcop_rw_cfg___td1___width 1 -#define reg_strcop_rw_cfg___td1___bit 2 -#define reg_strcop_rw_cfg___ipend___lsb 3 -#define reg_strcop_rw_cfg___ipend___width 1 -#define reg_strcop_rw_cfg___ipend___bit 3 -#define reg_strcop_rw_cfg___ignore_sync___lsb 4 -#define reg_strcop_rw_cfg___ignore_sync___width 1 -#define reg_strcop_rw_cfg___ignore_sync___bit 4 -#define reg_strcop_rw_cfg___en___lsb 5 -#define reg_strcop_rw_cfg___en___width 1 -#define reg_strcop_rw_cfg___en___bit 5 -#define reg_strcop_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strcop_big 0x00000001 -#define regk_strcop_d 0x00000001 -#define regk_strcop_e 0x00000000 -#define regk_strcop_little 0x00000000 -#define regk_strcop_rw_cfg_default 0x00000002 -#endif /* __strcop_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h deleted file mode 100644 index 73755fa8a526..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __strmux_defs_asm_h -#define __strmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope strmux, type rw */ -#define reg_strmux_rw_cfg___dma0___lsb 0 -#define reg_strmux_rw_cfg___dma0___width 3 -#define reg_strmux_rw_cfg___dma1___lsb 3 -#define reg_strmux_rw_cfg___dma1___width 3 -#define reg_strmux_rw_cfg___dma2___lsb 6 -#define reg_strmux_rw_cfg___dma2___width 3 -#define reg_strmux_rw_cfg___dma3___lsb 9 -#define reg_strmux_rw_cfg___dma3___width 3 -#define reg_strmux_rw_cfg___dma4___lsb 12 -#define reg_strmux_rw_cfg___dma4___width 3 -#define reg_strmux_rw_cfg___dma5___lsb 15 -#define reg_strmux_rw_cfg___dma5___width 3 -#define reg_strmux_rw_cfg___dma6___lsb 18 -#define reg_strmux_rw_cfg___dma6___width 3 -#define reg_strmux_rw_cfg___dma7___lsb 21 -#define reg_strmux_rw_cfg___dma7___width 3 -#define reg_strmux_rw_cfg___dma8___lsb 24 -#define reg_strmux_rw_cfg___dma8___width 3 -#define reg_strmux_rw_cfg___dma9___lsb 27 -#define reg_strmux_rw_cfg___dma9___width 3 -#define reg_strmux_rw_cfg_offset 0 - - -/* Constants */ -#define regk_strmux_ata 0x00000003 -#define regk_strmux_eth0 0x00000001 -#define regk_strmux_eth1 0x00000004 -#define regk_strmux_ext0 0x00000001 -#define regk_strmux_ext1 0x00000001 -#define regk_strmux_ext2 0x00000001 -#define regk_strmux_ext3 0x00000001 -#define regk_strmux_iop0 0x00000002 -#define regk_strmux_iop1 0x00000001 -#define regk_strmux_off 0x00000000 -#define regk_strmux_p21 0x00000004 -#define regk_strmux_rw_cfg_default 0x00000000 -#define regk_strmux_ser0 0x00000002 -#define regk_strmux_ser1 0x00000002 -#define regk_strmux_ser2 0x00000004 -#define regk_strmux_ser3 0x00000003 -#define regk_strmux_sser0 0x00000003 -#define regk_strmux_sser1 0x00000003 -#define regk_strmux_strcop 0x00000002 -#endif /* __strmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index cc67986d7437..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,230 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h deleted file mode 100644 index 2a8adbcf75d8..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h +++ /dev/null @@ -1,223 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ata_defs_h -#define __ata_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ata/rtl/ata_regs.r - * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp - * last modfied: Mon Apr 11 16:06:25 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r - * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ata */ - -/* Register rw_ctrl0, scope ata, type rw */ -typedef struct { - unsigned int pio_hold : 6; - unsigned int pio_strb : 6; - unsigned int pio_setup : 6; - unsigned int dma_hold : 6; - unsigned int dma_strb : 6; - unsigned int rst : 1; - unsigned int en : 1; -} reg_ata_rw_ctrl0; -#define REG_RD_ADDR_ata_rw_ctrl0 12 -#define REG_WR_ADDR_ata_rw_ctrl0 12 - -/* Register rw_ctrl1, scope ata, type rw */ -typedef struct { - unsigned int udma_tcyc : 4; - unsigned int udma_tdvs : 4; - unsigned int dummy1 : 24; -} reg_ata_rw_ctrl1; -#define REG_RD_ADDR_ata_rw_ctrl1 16 -#define REG_WR_ADDR_ata_rw_ctrl1 16 - -/* Register rw_ctrl2, scope ata, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 3; - unsigned int dma_size : 1; - unsigned int multi : 1; - unsigned int hsh : 2; - unsigned int trf_mode : 1; - unsigned int rw : 1; - unsigned int addr : 3; - unsigned int cs0 : 1; - unsigned int cs1 : 1; - unsigned int sel : 2; -} reg_ata_rw_ctrl2; -#define REG_RD_ADDR_ata_rw_ctrl2 0 -#define REG_WR_ADDR_ata_rw_ctrl2 0 - -/* Register rs_stat_data, scope ata, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_rs_stat_data; -#define REG_RD_ADDR_ata_rs_stat_data 4 - -/* Register r_stat_data, scope ata, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dav : 1; - unsigned int busy : 1; - unsigned int dummy1 : 14; -} reg_ata_r_stat_data; -#define REG_RD_ADDR_ata_r_stat_data 8 - -/* Register rw_trf_cnt, scope ata, type rw */ -typedef struct { - unsigned int cnt : 17; - unsigned int dummy1 : 15; -} reg_ata_rw_trf_cnt; -#define REG_RD_ADDR_ata_rw_trf_cnt 20 -#define REG_WR_ADDR_ata_rw_trf_cnt 20 - -/* Register r_stat_misc, scope ata, type r */ -typedef struct { - unsigned int crc : 16; - unsigned int dummy1 : 16; -} reg_ata_r_stat_misc; -#define REG_RD_ADDR_ata_r_stat_misc 24 - -/* Register rw_intr_mask, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_intr_mask; -#define REG_RD_ADDR_ata_rw_intr_mask 28 -#define REG_WR_ADDR_ata_rw_intr_mask 28 - -/* Register rw_ack_intr, scope ata, type rw */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_rw_ack_intr; -#define REG_RD_ADDR_ata_rw_ack_intr 32 -#define REG_WR_ADDR_ata_rw_ack_intr 32 - -/* Register r_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_intr; -#define REG_RD_ADDR_ata_r_intr 36 - -/* Register r_masked_intr, scope ata, type r */ -typedef struct { - unsigned int bus0 : 1; - unsigned int bus1 : 1; - unsigned int bus2 : 1; - unsigned int bus3 : 1; - unsigned int dummy1 : 28; -} reg_ata_r_masked_intr; -#define REG_RD_ADDR_ata_r_masked_intr 40 - - -/* Constants */ -enum { - regk_ata_active = 0x00000001, - regk_ata_byte = 0x00000001, - regk_ata_data = 0x00000001, - regk_ata_dma = 0x00000001, - regk_ata_inactive = 0x00000000, - regk_ata_no = 0x00000000, - regk_ata_nodata = 0x00000000, - regk_ata_pio = 0x00000000, - regk_ata_rd = 0x00000001, - regk_ata_reg = 0x00000000, - regk_ata_rw_ctrl0_default = 0x00000000, - regk_ata_rw_ctrl2_default = 0x00000000, - regk_ata_rw_intr_mask_default = 0x00000000, - regk_ata_udma = 0x00000002, - regk_ata_word = 0x00000000, - regk_ata_wr = 0x00000000, - regk_ata_yes = 0x00000001 -}; -#endif /* __ata_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h deleted file mode 100644 index 054841c45466..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h +++ /dev/null @@ -1,285 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h deleted file mode 100644 index 5c4abf5c0167..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,474 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h deleted file mode 100644 index 80c740b3c785..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h b/arch/cris/include/arch-v32/arch/hwregs/config_defs.h deleted file mode 100644 index 1c5da14f27f3..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h deleted file mode 100644 index 913f918bba14..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/crisp/doc/cpu_vect.r -version . */ - -#ifndef _______INST_CRISP_DOC_CPU_VECT_R -#define _______INST_CRISP_DOC_CPU_VECT_R -#define NMI_INTR_VECT 0x00 -#define RESERVED_1_INTR_VECT 0x01 -#define RESERVED_2_INTR_VECT 0x02 -#define SINGLE_STEP_INTR_VECT 0x03 -#define INSTR_TLB_REFILL_INTR_VECT 0x04 -#define INSTR_TLB_INV_INTR_VECT 0x05 -#define INSTR_TLB_ACC_INTR_VECT 0x06 -#define TLB_EX_INTR_VECT 0x07 -#define DATA_TLB_REFILL_INTR_VECT 0x08 -#define DATA_TLB_INV_INTR_VECT 0x09 -#define DATA_TLB_ACC_INTR_VECT 0x0a -#define DATA_TLB_WE_INTR_VECT 0x0b -#define HW_BP_INTR_VECT 0x0c -#define RESERVED_D_INTR_VECT 0x0d -#define RESERVED_E_INTR_VECT 0x0e -#define RESERVED_F_INTR_VECT 0x0f -#define BREAK_0_INTR_VECT 0x10 -#define BREAK_1_INTR_VECT 0x11 -#define BREAK_2_INTR_VECT 0x12 -#define BREAK_3_INTR_VECT 0x13 -#define BREAK_4_INTR_VECT 0x14 -#define BREAK_5_INTR_VECT 0x15 -#define BREAK_6_INTR_VECT 0x16 -#define BREAK_7_INTR_VECT 0x17 -#define BREAK_8_INTR_VECT 0x18 -#define BREAK_9_INTR_VECT 0x19 -#define BREAK_10_INTR_VECT 0x1a -#define BREAK_11_INTR_VECT 0x1b -#define BREAK_12_INTR_VECT 0x1c -#define BREAK_13_INTR_VECT 0x1d -#define BREAK_14_INTR_VECT 0x1e -#define BREAK_15_INTR_VECT 0x1f -#define MULTIPLE_INTR_VECT 0x30 - -#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma.h b/arch/cris/include/arch-v32/arch/hwregs/dma.h deleted file mode 100644 index dd24c6da09e0..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/dma.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * DMA C definitions and help macros - * - */ - -#ifndef dma_h -#define dma_h - -/* registers */ /* Really needed, since both are listed in sw.list? */ -#include - - -/* descriptors */ - -// ------------------------------------------------------------ dma_descr_group -typedef struct dma_descr_group { - struct dma_descr_group *next; - unsigned eol : 1; - unsigned tol : 1; - unsigned bol : 1; - unsigned : 1; - unsigned intr : 1; - unsigned : 2; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md : 16; - struct dma_descr_group *up; - union { - struct dma_descr_context *context; - struct dma_descr_group *group; - } down; -} dma_descr_group; - -// ---------------------------------------------------------- dma_descr_context -typedef struct dma_descr_context { - struct dma_descr_context *next; - unsigned eol : 1; - unsigned : 3; - unsigned intr : 1; - unsigned : 1; - unsigned store_mode : 1; - unsigned en : 1; - unsigned : 7; - unsigned dis : 1; - unsigned md0 : 16; - unsigned md1; - unsigned md2; - unsigned md3; - unsigned md4; - struct dma_descr_data *saved_data; - char *saved_data_buf; -} dma_descr_context; - -// ------------------------------------------------------------- dma_descr_data -typedef struct dma_descr_data { - struct dma_descr_data *next; - char *buf; - unsigned eol : 1; - unsigned : 2; - unsigned out_eop : 1; - unsigned intr : 1; - unsigned wait : 1; - unsigned : 2; - unsigned : 3; - unsigned in_eop : 1; - unsigned : 4; - unsigned md : 16; - char *after; -} dma_descr_data; - -// --------------------------------------------------------------------- macros - -// enable DMA channel -#define DMA_ENABLE( inst ) \ - do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\ - e.en = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, e); } while( 0 ) - -// reset DMA channel -#define DMA_RESET( inst ) \ - do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\ - r.en = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, r); } while( 0 ) - -// stop DMA channel -#define DMA_STOP( inst ) \ - do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\ - s.stop = regk_dma_yes; \ - REG_WR( dma, inst, rw_cfg, s); } while( 0 ) - -// continue DMA channel operation -#define DMA_CONTINUE( inst ) \ - do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\ - c.stop = regk_dma_no; \ - REG_WR( dma, inst, rw_cfg, c); } while( 0 ) - -// give stream command -#define DMA_WR_CMD( inst, cmd_par ) \ - do { reg_dma_rw_stream_cmd __x = {0}; \ - do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \ - __x.cmd = (cmd_par); \ - REG_WR(dma, inst, rw_stream_cmd, __x); \ - } while (0) - -// load: g,c,d:burst -#define DMA_START_GROUP( inst, group_descr ) \ - do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_g ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// load: c,d:burst -#define DMA_START_CONTEXT( inst, ctx_descr ) \ - do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \ - DMA_WR_CMD( inst, regk_dma_load_c ); \ - DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \ - } while( 0 ) - -// if the DMA is at the end of the data list, the last data descr is reloaded -#define DMA_CONTINUE_DATA( inst ) \ -do { reg_dma_rw_cmd c = {0}; \ - c.cont_data = regk_dma_yes;\ - REG_WR( dma, inst, rw_cmd, c ); } while( 0 ) - -#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h deleted file mode 100644 index a67826f5fe21..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h +++ /dev/null @@ -1,437 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __dma_defs_h -#define __dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp - * last modfied: Mon Apr 11 16:06:51 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r - * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope dma */ - -/* Register rw_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data; -#define REG_RD_ADDR_dma_rw_data 0 -#define REG_WR_ADDR_dma_rw_data 0 - -/* Register rw_data_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_next; -#define REG_RD_ADDR_dma_rw_data_next 4 -#define REG_WR_ADDR_dma_rw_data_next 4 - -/* Register rw_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_buf; -#define REG_RD_ADDR_dma_rw_data_buf 8 -#define REG_WR_ADDR_dma_rw_data_buf 8 - -/* Register rw_data_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 2; - unsigned int out_eop : 1; - unsigned int intr : 1; - unsigned int wait : 1; - unsigned int dummy2 : 26; -} reg_dma_rw_data_ctrl; -#define REG_RD_ADDR_dma_rw_data_ctrl 12 -#define REG_WR_ADDR_dma_rw_data_ctrl 12 - -/* Register rw_data_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 3; - unsigned int in_eop : 1; - unsigned int dummy2 : 28; -} reg_dma_rw_data_stat; -#define REG_RD_ADDR_dma_rw_data_stat 16 -#define REG_WR_ADDR_dma_rw_data_stat 16 - -/* Register rw_data_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md; -#define REG_RD_ADDR_dma_rw_data_md 20 -#define REG_WR_ADDR_dma_rw_data_md 20 - -/* Register rw_data_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_data_md_s; -#define REG_RD_ADDR_dma_rw_data_md_s 24 -#define REG_WR_ADDR_dma_rw_data_md_s 24 - -/* Register rw_data_after, scope dma, type rw */ -typedef unsigned int reg_dma_rw_data_after; -#define REG_RD_ADDR_dma_rw_data_after 28 -#define REG_WR_ADDR_dma_rw_data_after 28 - -/* Register rw_ctxt, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt; -#define REG_RD_ADDR_dma_rw_ctxt 32 -#define REG_WR_ADDR_dma_rw_ctxt 32 - -/* Register rw_ctxt_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_next; -#define REG_RD_ADDR_dma_rw_ctxt_next 36 -#define REG_WR_ADDR_dma_rw_ctxt_next 36 - -/* Register rw_ctxt_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int dummy1 : 3; - unsigned int intr : 1; - unsigned int dummy2 : 1; - unsigned int store_mode : 1; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_ctxt_ctrl; -#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40 -#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40 - -/* Register rw_ctxt_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_ctxt_stat; -#define REG_RD_ADDR_dma_rw_ctxt_stat 44 -#define REG_WR_ADDR_dma_rw_ctxt_stat 44 - -/* Register rw_ctxt_md0, scope dma, type rw */ -typedef struct { - unsigned int md0 : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0; -#define REG_RD_ADDR_dma_rw_ctxt_md0 48 -#define REG_WR_ADDR_dma_rw_ctxt_md0 48 - -/* Register rw_ctxt_md0_s, scope dma, type rw */ -typedef struct { - unsigned int md0_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_ctxt_md0_s; -#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52 -#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52 - -/* Register rw_ctxt_md1, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1; -#define REG_RD_ADDR_dma_rw_ctxt_md1 56 -#define REG_WR_ADDR_dma_rw_ctxt_md1 56 - -/* Register rw_ctxt_md1_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md1_s; -#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60 -#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60 - -/* Register rw_ctxt_md2, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2; -#define REG_RD_ADDR_dma_rw_ctxt_md2 64 -#define REG_WR_ADDR_dma_rw_ctxt_md2 64 - -/* Register rw_ctxt_md2_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md2_s; -#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68 -#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68 - -/* Register rw_ctxt_md3, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3; -#define REG_RD_ADDR_dma_rw_ctxt_md3 72 -#define REG_WR_ADDR_dma_rw_ctxt_md3 72 - -/* Register rw_ctxt_md3_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md3_s; -#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76 -#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76 - -/* Register rw_ctxt_md4, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4; -#define REG_RD_ADDR_dma_rw_ctxt_md4 80 -#define REG_WR_ADDR_dma_rw_ctxt_md4 80 - -/* Register rw_ctxt_md4_s, scope dma, type rw */ -typedef unsigned int reg_dma_rw_ctxt_md4_s; -#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84 -#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84 - -/* Register rw_saved_data, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data; -#define REG_RD_ADDR_dma_rw_saved_data 88 -#define REG_WR_ADDR_dma_rw_saved_data 88 - -/* Register rw_saved_data_buf, scope dma, type rw */ -typedef unsigned int reg_dma_rw_saved_data_buf; -#define REG_RD_ADDR_dma_rw_saved_data_buf 92 -#define REG_WR_ADDR_dma_rw_saved_data_buf 92 - -/* Register rw_group, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group; -#define REG_RD_ADDR_dma_rw_group 96 -#define REG_WR_ADDR_dma_rw_group 96 - -/* Register rw_group_next, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_next; -#define REG_RD_ADDR_dma_rw_group_next 100 -#define REG_WR_ADDR_dma_rw_group_next 100 - -/* Register rw_group_ctrl, scope dma, type rw */ -typedef struct { - unsigned int eol : 1; - unsigned int tol : 1; - unsigned int bol : 1; - unsigned int dummy1 : 1; - unsigned int intr : 1; - unsigned int dummy2 : 2; - unsigned int en : 1; - unsigned int dummy3 : 24; -} reg_dma_rw_group_ctrl; -#define REG_RD_ADDR_dma_rw_group_ctrl 104 -#define REG_WR_ADDR_dma_rw_group_ctrl 104 - -/* Register rw_group_stat, scope dma, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int dis : 1; - unsigned int dummy2 : 24; -} reg_dma_rw_group_stat; -#define REG_RD_ADDR_dma_rw_group_stat 108 -#define REG_WR_ADDR_dma_rw_group_stat 108 - -/* Register rw_group_md, scope dma, type rw */ -typedef struct { - unsigned int md : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md; -#define REG_RD_ADDR_dma_rw_group_md 112 -#define REG_WR_ADDR_dma_rw_group_md 112 - -/* Register rw_group_md_s, scope dma, type rw */ -typedef struct { - unsigned int md_s : 16; - unsigned int dummy1 : 16; -} reg_dma_rw_group_md_s; -#define REG_RD_ADDR_dma_rw_group_md_s 116 -#define REG_WR_ADDR_dma_rw_group_md_s 116 - -/* Register rw_group_up, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_up; -#define REG_RD_ADDR_dma_rw_group_up 120 -#define REG_WR_ADDR_dma_rw_group_up 120 - -/* Register rw_group_down, scope dma, type rw */ -typedef unsigned int reg_dma_rw_group_down; -#define REG_RD_ADDR_dma_rw_group_down 124 -#define REG_WR_ADDR_dma_rw_group_down 124 - -/* Register rw_cmd, scope dma, type rw */ -typedef struct { - unsigned int cont_data : 1; - unsigned int dummy1 : 31; -} reg_dma_rw_cmd; -#define REG_RD_ADDR_dma_rw_cmd 128 -#define REG_WR_ADDR_dma_rw_cmd 128 - -/* Register rw_cfg, scope dma, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int stop : 1; - unsigned int dummy1 : 30; -} reg_dma_rw_cfg; -#define REG_RD_ADDR_dma_rw_cfg 132 -#define REG_WR_ADDR_dma_rw_cfg 132 - -/* Register rw_stat, scope dma, type rw */ -typedef struct { - unsigned int mode : 5; - unsigned int list_state : 3; - unsigned int stream_cmd_src : 8; - unsigned int dummy1 : 8; - unsigned int buf : 8; -} reg_dma_rw_stat; -#define REG_RD_ADDR_dma_rw_stat 136 -#define REG_WR_ADDR_dma_rw_stat 136 - -/* Register rw_intr_mask, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_intr_mask; -#define REG_RD_ADDR_dma_rw_intr_mask 140 -#define REG_WR_ADDR_dma_rw_intr_mask 140 - -/* Register rw_ack_intr, scope dma, type rw */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_rw_ack_intr; -#define REG_RD_ADDR_dma_rw_ack_intr 144 -#define REG_WR_ADDR_dma_rw_ack_intr 144 - -/* Register r_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_intr; -#define REG_RD_ADDR_dma_r_intr 148 - -/* Register r_masked_intr, scope dma, type r */ -typedef struct { - unsigned int group : 1; - unsigned int ctxt : 1; - unsigned int data : 1; - unsigned int in_eop : 1; - unsigned int stream_cmd : 1; - unsigned int dummy1 : 27; -} reg_dma_r_masked_intr; -#define REG_RD_ADDR_dma_r_masked_intr 152 - -/* Register rw_stream_cmd, scope dma, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 7; - unsigned int busy : 1; -} reg_dma_rw_stream_cmd; -#define REG_RD_ADDR_dma_rw_stream_cmd 156 -#define REG_WR_ADDR_dma_rw_stream_cmd 156 - - -/* Constants */ -enum { - regk_dma_ack_pkt = 0x00000100, - regk_dma_anytime = 0x00000001, - regk_dma_array = 0x00000008, - regk_dma_burst = 0x00000020, - regk_dma_client = 0x00000002, - regk_dma_copy_next = 0x00000010, - regk_dma_copy_up = 0x00000020, - regk_dma_data_at_eol = 0x00000001, - regk_dma_dis_c = 0x00000010, - regk_dma_dis_g = 0x00000020, - regk_dma_idle = 0x00000001, - regk_dma_intern = 0x00000004, - regk_dma_load_c = 0x00000200, - regk_dma_load_c_n = 0x00000280, - regk_dma_load_c_next = 0x00000240, - regk_dma_load_d = 0x00000140, - regk_dma_load_g = 0x00000300, - regk_dma_load_g_down = 0x000003c0, - regk_dma_load_g_next = 0x00000340, - regk_dma_load_g_up = 0x00000380, - regk_dma_next_en = 0x00000010, - regk_dma_next_pkt = 0x00000010, - regk_dma_no = 0x00000000, - regk_dma_only_at_wait = 0x00000000, - regk_dma_restore = 0x00000020, - regk_dma_rst = 0x00000001, - regk_dma_running = 0x00000004, - regk_dma_rw_cfg_default = 0x00000000, - regk_dma_rw_cmd_default = 0x00000000, - regk_dma_rw_intr_mask_default = 0x00000000, - regk_dma_rw_stat_default = 0x00000101, - regk_dma_rw_stream_cmd_default = 0x00000000, - regk_dma_save_down = 0x00000020, - regk_dma_save_up = 0x00000020, - regk_dma_set_reg = 0x00000050, - regk_dma_set_w_size1 = 0x00000190, - regk_dma_set_w_size2 = 0x000001a0, - regk_dma_set_w_size4 = 0x000001c0, - regk_dma_stopped = 0x00000002, - regk_dma_store_c = 0x00000002, - regk_dma_store_descr = 0x00000000, - regk_dma_store_g = 0x00000004, - regk_dma_store_md = 0x00000001, - regk_dma_sw = 0x00000008, - regk_dma_update_down = 0x00000020, - regk_dma_yes = 0x00000001 -}; -#endif /* __dma_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h deleted file mode 100644 index d8021b44e5e6..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h +++ /dev/null @@ -1,379 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __eth_defs_h -#define __eth_defs_h - -/* - * This file is autogenerated from - * file: eth.r - * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp - * last modfied: Mon Jan 9 06:06:41 2006 - * - * by /n/asic/design/tools/rdesc/rdes2c eth.r - * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope eth */ - -/* Register rw_ma0_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma0_lo; -#define REG_RD_ADDR_eth_rw_ma0_lo 0 -#define REG_WR_ADDR_eth_rw_ma0_lo 0 - -/* Register rw_ma0_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma0_hi; -#define REG_RD_ADDR_eth_rw_ma0_hi 4 -#define REG_WR_ADDR_eth_rw_ma0_hi 4 - -/* Register rw_ma1_lo, scope eth, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_eth_rw_ma1_lo; -#define REG_RD_ADDR_eth_rw_ma1_lo 8 -#define REG_WR_ADDR_eth_rw_ma1_lo 8 - -/* Register rw_ma1_hi, scope eth, type rw */ -typedef struct { - unsigned int addr : 16; - unsigned int dummy1 : 16; -} reg_eth_rw_ma1_hi; -#define REG_RD_ADDR_eth_rw_ma1_hi 12 -#define REG_WR_ADDR_eth_rw_ma1_hi 12 - -/* Register rw_ga_lo, scope eth, type rw */ -typedef struct { - unsigned int tbl : 32; -} reg_eth_rw_ga_lo; -#define REG_RD_ADDR_eth_rw_ga_lo 16 -#define REG_WR_ADDR_eth_rw_ga_lo 16 - -/* Register rw_ga_hi, scope eth, type rw */ -typedef struct { - unsigned int tbl : 32; -} reg_eth_rw_ga_hi; -#define REG_RD_ADDR_eth_rw_ga_hi 20 -#define REG_WR_ADDR_eth_rw_ga_hi 20 - -/* Register rw_gen_ctrl, scope eth, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int phy : 2; - unsigned int protocol : 1; - unsigned int loopback : 1; - unsigned int flow_ctrl : 1; - unsigned int gtxclk_out : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 24; -} reg_eth_rw_gen_ctrl; -#define REG_RD_ADDR_eth_rw_gen_ctrl 24 -#define REG_WR_ADDR_eth_rw_gen_ctrl 24 - -/* Register rw_rec_ctrl, scope eth, type rw */ -typedef struct { - unsigned int ma0 : 1; - unsigned int ma1 : 1; - unsigned int individual : 1; - unsigned int broadcast : 1; - unsigned int undersize : 1; - unsigned int oversize : 1; - unsigned int bad_crc : 1; - unsigned int duplex : 1; - unsigned int max_size : 16; - unsigned int dummy1 : 8; -} reg_eth_rw_rec_ctrl; -#define REG_RD_ADDR_eth_rw_rec_ctrl 28 -#define REG_WR_ADDR_eth_rw_rec_ctrl 28 - -/* Register rw_tr_ctrl, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int pad : 1; - unsigned int retry : 1; - unsigned int ignore_col : 1; - unsigned int cancel : 1; - unsigned int hsh_delay : 1; - unsigned int ignore_crs : 1; - unsigned int carrier_ext : 1; - unsigned int dummy1 : 24; -} reg_eth_rw_tr_ctrl; -#define REG_RD_ADDR_eth_rw_tr_ctrl 32 -#define REG_WR_ADDR_eth_rw_tr_ctrl 32 - -/* Register rw_clr_err, scope eth, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_eth_rw_clr_err; -#define REG_RD_ADDR_eth_rw_clr_err 36 -#define REG_WR_ADDR_eth_rw_clr_err 36 - -/* Register rw_mgm_ctrl, scope eth, type rw */ -typedef struct { - unsigned int mdio : 1; - unsigned int mdoe : 1; - unsigned int mdc : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_mgm_ctrl; -#define REG_RD_ADDR_eth_rw_mgm_ctrl 40 -#define REG_WR_ADDR_eth_rw_mgm_ctrl 40 - -/* Register r_stat, scope eth, type r */ -typedef struct { - unsigned int mdio : 1; - unsigned int exc_col : 1; - unsigned int urun : 1; - unsigned int clk_125 : 1; - unsigned int dummy1 : 28; -} reg_eth_r_stat; -#define REG_RD_ADDR_eth_r_stat 44 - -/* Register rs_rec_cnt, scope eth, type rs */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_rs_rec_cnt; -#define REG_RD_ADDR_eth_rs_rec_cnt 48 - -/* Register r_rec_cnt, scope eth, type r */ -typedef struct { - unsigned int crc_err : 8; - unsigned int align_err : 8; - unsigned int oversize : 8; - unsigned int congestion : 8; -} reg_eth_r_rec_cnt; -#define REG_RD_ADDR_eth_r_rec_cnt 52 - -/* Register rs_tr_cnt, scope eth, type rs */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_rs_tr_cnt; -#define REG_RD_ADDR_eth_rs_tr_cnt 56 - -/* Register r_tr_cnt, scope eth, type r */ -typedef struct { - unsigned int single_col : 8; - unsigned int mult_col : 8; - unsigned int late_col : 8; - unsigned int deferred : 8; -} reg_eth_r_tr_cnt; -#define REG_RD_ADDR_eth_r_tr_cnt 60 - -/* Register rs_phy_cnt, scope eth, type rs */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_rs_phy_cnt; -#define REG_RD_ADDR_eth_rs_phy_cnt 64 - -/* Register r_phy_cnt, scope eth, type r */ -typedef struct { - unsigned int carrier_loss : 8; - unsigned int sqe_err : 8; - unsigned int dummy1 : 16; -} reg_eth_r_phy_cnt; -#define REG_RD_ADDR_eth_r_phy_cnt 68 - -/* Register rw_test_ctrl, scope eth, type rw */ -typedef struct { - unsigned int snmp_inc : 1; - unsigned int snmp : 1; - unsigned int backoff : 1; - unsigned int dummy1 : 29; -} reg_eth_rw_test_ctrl; -#define REG_RD_ADDR_eth_rw_test_ctrl 72 -#define REG_WR_ADDR_eth_rw_test_ctrl 72 - -/* Register rw_intr_mask, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_intr_mask; -#define REG_RD_ADDR_eth_rw_intr_mask 76 -#define REG_WR_ADDR_eth_rw_intr_mask 76 - -/* Register rw_ack_intr, scope eth, type rw */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_rw_ack_intr; -#define REG_RD_ADDR_eth_rw_ack_intr 80 -#define REG_WR_ADDR_eth_rw_ack_intr 80 - -/* Register r_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_intr; -#define REG_RD_ADDR_eth_r_intr 84 - -/* Register r_masked_intr, scope eth, type r */ -typedef struct { - unsigned int crc : 1; - unsigned int align : 1; - unsigned int oversize : 1; - unsigned int congestion : 1; - unsigned int single_col : 1; - unsigned int mult_col : 1; - unsigned int late_col : 1; - unsigned int deferred : 1; - unsigned int carrier_loss : 1; - unsigned int sqe_test_err : 1; - unsigned int orun : 1; - unsigned int urun : 1; - unsigned int exc_col : 1; - unsigned int mdio : 1; - unsigned int dummy1 : 18; -} reg_eth_r_masked_intr; -#define REG_RD_ADDR_eth_r_masked_intr 88 - - -/* Constants */ -enum { - regk_eth_discard = 0x00000000, - regk_eth_ether = 0x00000000, - regk_eth_full = 0x00000001, - regk_eth_gmii = 0x00000003, - regk_eth_gtxclk = 0x00000001, - regk_eth_half = 0x00000000, - regk_eth_hsh = 0x00000001, - regk_eth_mii = 0x00000001, - regk_eth_mii_arec = 0x00000002, - regk_eth_mii_clk = 0x00000000, - regk_eth_no = 0x00000000, - regk_eth_phyrst = 0x00000000, - regk_eth_rec = 0x00000001, - regk_eth_rw_ga_hi_default = 0x00000000, - regk_eth_rw_ga_lo_default = 0x00000000, - regk_eth_rw_gen_ctrl_default = 0x00000000, - regk_eth_rw_intr_mask_default = 0x00000000, - regk_eth_rw_ma0_hi_default = 0x00000000, - regk_eth_rw_ma0_lo_default = 0x00000000, - regk_eth_rw_ma1_hi_default = 0x00000000, - regk_eth_rw_ma1_lo_default = 0x00000000, - regk_eth_rw_mgm_ctrl_default = 0x00000000, - regk_eth_rw_test_ctrl_default = 0x00000000, - regk_eth_size1518 = 0x000005ee, - regk_eth_size1522 = 0x000005f2, - regk_eth_yes = 0x00000001 -}; -#endif /* __eth_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h b/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h deleted file mode 100644 index 5937ed7a5228..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __extmem_defs_h -#define __extmem_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ext_mem/mod/extmem_regs.r - * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp - * last modfied: Tue Mar 30 22:26:21 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r - * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope extmem */ - -/* Register rw_cse0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse0_cfg; -#define REG_RD_ADDR_extmem_rw_cse0_cfg 0 -#define REG_WR_ADDR_extmem_rw_cse0_cfg 0 - -/* Register rw_cse1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_cse1_cfg; -#define REG_RD_ADDR_extmem_rw_cse1_cfg 4 -#define REG_WR_ADDR_extmem_rw_cse1_cfg 4 - -/* Register rw_csr0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr0_cfg; -#define REG_RD_ADDR_extmem_rw_csr0_cfg 8 -#define REG_WR_ADDR_extmem_rw_csr0_cfg 8 - -/* Register rw_csr1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csr1_cfg; -#define REG_RD_ADDR_extmem_rw_csr1_cfg 12 -#define REG_WR_ADDR_extmem_rw_csr1_cfg 12 - -/* Register rw_csp0_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp0_cfg; -#define REG_RD_ADDR_extmem_rw_csp0_cfg 16 -#define REG_WR_ADDR_extmem_rw_csp0_cfg 16 - -/* Register rw_csp1_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp1_cfg; -#define REG_RD_ADDR_extmem_rw_csp1_cfg 20 -#define REG_WR_ADDR_extmem_rw_csp1_cfg 20 - -/* Register rw_csp2_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp2_cfg; -#define REG_RD_ADDR_extmem_rw_csp2_cfg 24 -#define REG_WR_ADDR_extmem_rw_csp2_cfg 24 - -/* Register rw_csp3_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp3_cfg; -#define REG_RD_ADDR_extmem_rw_csp3_cfg 28 -#define REG_WR_ADDR_extmem_rw_csp3_cfg 28 - -/* Register rw_csp4_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp4_cfg; -#define REG_RD_ADDR_extmem_rw_csp4_cfg 32 -#define REG_WR_ADDR_extmem_rw_csp4_cfg 32 - -/* Register rw_csp5_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp5_cfg; -#define REG_RD_ADDR_extmem_rw_csp5_cfg 36 -#define REG_WR_ADDR_extmem_rw_csp5_cfg 36 - -/* Register rw_csp6_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_csp6_cfg; -#define REG_RD_ADDR_extmem_rw_csp6_cfg 40 -#define REG_WR_ADDR_extmem_rw_csp6_cfg 40 - -/* Register rw_css_cfg, scope extmem, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int mode : 1; - unsigned int erc_en : 1; - unsigned int dummy1 : 6; - unsigned int size : 3; - unsigned int log : 1; - unsigned int en : 1; -} reg_extmem_rw_css_cfg; -#define REG_RD_ADDR_extmem_rw_css_cfg 44 -#define REG_WR_ADDR_extmem_rw_css_cfg 44 - -/* Register rw_status_handle, scope extmem, type rw */ -typedef struct { - unsigned int h : 32; -} reg_extmem_rw_status_handle; -#define REG_RD_ADDR_extmem_rw_status_handle 48 -#define REG_WR_ADDR_extmem_rw_status_handle 48 - -/* Register rw_wait_pin, scope extmem, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 15; - unsigned int start : 1; -} reg_extmem_rw_wait_pin; -#define REG_RD_ADDR_extmem_rw_wait_pin 52 -#define REG_WR_ADDR_extmem_rw_wait_pin 52 - -/* Register rw_gated_csp, scope extmem, type rw */ -typedef struct { - unsigned int dummy1 : 31; - unsigned int en : 1; -} reg_extmem_rw_gated_csp; -#define REG_RD_ADDR_extmem_rw_gated_csp 56 -#define REG_WR_ADDR_extmem_rw_gated_csp 56 - - -/* Constants */ -enum { - regk_extmem_b16 = 0x00000001, - regk_extmem_b32 = 0x00000000, - regk_extmem_bwe = 0x00000000, - regk_extmem_cwe = 0x00000001, - regk_extmem_no = 0x00000000, - regk_extmem_rw_cse0_cfg_default = 0x000006cf, - regk_extmem_rw_cse1_cfg_default = 0x000006cf, - regk_extmem_rw_csp0_cfg_default = 0x000006cf, - regk_extmem_rw_csp1_cfg_default = 0x000006cf, - regk_extmem_rw_csp2_cfg_default = 0x000006cf, - regk_extmem_rw_csp3_cfg_default = 0x000006cf, - regk_extmem_rw_csp4_cfg_default = 0x000006cf, - regk_extmem_rw_csp5_cfg_default = 0x000006cf, - regk_extmem_rw_csp6_cfg_default = 0x000006cf, - regk_extmem_rw_csr0_cfg_default = 0x000006cf, - regk_extmem_rw_csr1_cfg_default = 0x000006cf, - regk_extmem_rw_css_cfg_default = 0x000006cf, - regk_extmem_s128KB = 0x00000000, - regk_extmem_s16MB = 0x00000005, - regk_extmem_s1MB = 0x00000001, - regk_extmem_s2MB = 0x00000002, - regk_extmem_s32MB = 0x00000006, - regk_extmem_s4MB = 0x00000003, - regk_extmem_s64MB = 0x00000007, - regk_extmem_s8MB = 0x00000004, - regk_extmem_yes = 0x00000001 -}; -#endif /* __extmem_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile deleted file mode 100644 index 1b9467ae65c1..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile +++ /dev/null @@ -1,147 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $ -# Makefile to generate or copy the latest register definitions -# and related datastructures and helpermacros. -# The official place for these files is probably at: -RELEASE ?= r1_alfa5 -IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/ - -IOPROCDIR = /n/asic/design/io/io_proc/rtl - -IOPROCINCL_FILES = -IOPROCINCL_FILES2= -IOPROCINCL_FILES += iop_crc_par_defs.h -IOPROCINCL_FILES += iop_dmc_in_defs.h -IOPROCINCL_FILES += iop_dmc_out_defs.h -IOPROCINCL_FILES += iop_fifo_in_defs.h -IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h -IOPROCINCL_FILES += iop_fifo_out_defs.h -IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h -IOPROCINCL_FILES += iop_mpu_defs.h -IOPROCINCL_FILES2+= iop_mpu_macros.h -IOPROCINCL_FILES2+= iop_reg_space.h -IOPROCINCL_FILES += iop_sap_in_defs.h -IOPROCINCL_FILES += iop_sap_out_defs.h -IOPROCINCL_FILES += iop_scrc_in_defs.h -IOPROCINCL_FILES += iop_scrc_out_defs.h -IOPROCINCL_FILES += iop_spu_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_sw_cfg_defs.h -IOPROCINCL_FILES += iop_sw_cpu_defs.h -IOPROCINCL_FILES += iop_sw_mpu_defs.h -IOPROCINCL_FILES += iop_sw_spu_defs.h -# -IOPROCINCL_FILES += iop_timer_grp_defs.h -IOPROCINCL_FILES += iop_trigger_grp_defs.h -# in guiness/ -IOPROCINCL_FILES += iop_version_defs.h - -IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES)) -IOPROCASMINCL_FILES+= iop_reg_space_asm.h - - -IOPROCREGDESC = -IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r -#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r -IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r -IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r -IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r -IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r -IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r -IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r - - -RDES2C = /n/asic/bin/rdes2c -RDES2C = /n/asic/design/tools/rdesc/rdes2c -RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr -RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt - -## all - Just print help - you probably want to do 'make gen' -all: help - -## help - This help -help: - @grep '^## ' Makefile - -## gen - Generate include files -gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) - echo "INCL: $(IOPROCINCL_FILES)" - echo "INCL2: $(IOPROCINCL_FILES2)" - echo "ASMINCL: $(IOPROCASMINCL_FILES)" - -# From the official location... -iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ -iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h - cat $< | sed -e 's/\$$Id\:/id\:/g' >$@ - -## copy - Copy files from official location -copy: - @echo "## Copying and fixing iop files ##" - @for HFILE in $(IOPROCINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @for HFILE in $(IOPROCINCL_FILES2); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \ - done - @echo "## Copying and fixing iop asm files ##" - @for HFILE in $(IOPROCASMINCL_FILES); do \ - echo " $$HFILE"; \ - cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \ - done - -# I/O processor files: -## iop - Generate I/O processor include files -iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES) -iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r - $(RDES2C) $< -iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) $< -%_defs.h: $(IOPROCDIR)/%.r - $(RDES2C) $< -%_defs_asm.h: $(IOPROCDIR)/%.r - $(RDES2C) -asm $< -iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r - $(RDES2C) -asm $< - -## doc - Generate .axw files from register description. -doc: $(IOPROCREGDESC) - for RDES in $^; do \ - $(RDES2TXT) $$RDES; \ - done - -.PHONY: axw -## %.axw - Generate the specified .axw file (doesn't work for all files -## due to inconsistent naming of .r files. -%.axw: axw - @for RDES in $(IOPROCREGDESC); do \ - if echo "$$RDES" | grep $* ; then \ - $(RDES2TXT) $$RDES; \ - fi \ - done - -.PHONY: clean -## clean - Remove .h files and .axw files. -clean: - rm -rf $(IOPROCINCL_FILES) *.axw - -.PHONY: cleandoc -## cleandoc - Remove .axw files. -cleandoc: - rm -rf *.axw - diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h deleted file mode 100644 index 10443d789a66..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_crc_par_defs_asm_h -#define __iop_crc_par_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_cfg___mode___lsb 0 -#define reg_iop_crc_par_rw_cfg___mode___width 1 -#define reg_iop_crc_par_rw_cfg___mode___bit 0 -#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1 -#define reg_iop_crc_par_rw_cfg___crc_out___width 1 -#define reg_iop_crc_par_rw_cfg___crc_out___bit 1 -#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2 -#define reg_iop_crc_par_rw_cfg___rev_out___width 1 -#define reg_iop_crc_par_rw_cfg___rev_out___bit 2 -#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3 -#define reg_iop_crc_par_rw_cfg___inv_out___width 1 -#define reg_iop_crc_par_rw_cfg___inv_out___bit 3 -#define reg_iop_crc_par_rw_cfg___trig___lsb 4 -#define reg_iop_crc_par_rw_cfg___trig___width 2 -#define reg_iop_crc_par_rw_cfg___poly___lsb 6 -#define reg_iop_crc_par_rw_cfg___poly___width 3 -#define reg_iop_crc_par_rw_cfg_offset 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_init_crc_offset 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_correct_crc_offset 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_ctrl___en___lsb 0 -#define reg_iop_crc_par_rw_ctrl___en___width 1 -#define reg_iop_crc_par_rw_ctrl___en___bit 0 -#define reg_iop_crc_par_rw_ctrl_offset 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0 -#define reg_iop_crc_par_rw_set_last___tr_dif___width 1 -#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0 -#define reg_iop_crc_par_rw_set_last_offset 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_offset 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_offset 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_offset 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_offset 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr1byte_last___data___width 8 -#define reg_iop_crc_par_rw_wr1byte_last_offset 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr2byte_last___data___width 16 -#define reg_iop_crc_par_rw_wr2byte_last_offset 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr3byte_last___data___width 24 -#define reg_iop_crc_par_rw_wr3byte_last_offset 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0 -#define reg_iop_crc_par_rw_wr4byte_last___data___width 32 -#define reg_iop_crc_par_rw_wr4byte_last_offset 48 - -/* Register r_stat, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_stat___err___lsb 0 -#define reg_iop_crc_par_r_stat___err___width 1 -#define reg_iop_crc_par_r_stat___err___bit 0 -#define reg_iop_crc_par_r_stat___busy___lsb 1 -#define reg_iop_crc_par_r_stat___busy___width 1 -#define reg_iop_crc_par_r_stat___busy___bit 1 -#define reg_iop_crc_par_r_stat_offset 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_sh_reg_offset 56 - -/* Register r_crc, scope iop_crc_par, type r */ -#define reg_iop_crc_par_r_crc_offset 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0 -#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2 -#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64 - - -/* Constants */ -#define regk_iop_crc_par_calc 0x00000001 -#define regk_iop_crc_par_ccitt 0x00000002 -#define regk_iop_crc_par_check 0x00000000 -#define regk_iop_crc_par_crc16 0x00000001 -#define regk_iop_crc_par_crc32 0x00000000 -#define regk_iop_crc_par_crc5 0x00000003 -#define regk_iop_crc_par_crc5_11 0x00000004 -#define regk_iop_crc_par_dif_in 0x00000002 -#define regk_iop_crc_par_hi 0x00000000 -#define regk_iop_crc_par_neg 0x00000002 -#define regk_iop_crc_par_no 0x00000000 -#define regk_iop_crc_par_pos 0x00000001 -#define regk_iop_crc_par_pos_neg 0x00000003 -#define regk_iop_crc_par_rw_cfg_default 0x00000000 -#define regk_iop_crc_par_rw_ctrl_default 0x00000000 -#define regk_iop_crc_par_yes 0x00000001 -#endif /* __iop_crc_par_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h deleted file mode 100644 index fdee9bbe1fd4..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h +++ /dev/null @@ -1,322 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_dmc_in_defs_asm_h -#define __iop_dmc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0 -#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1 -#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3 -#define reg_iop_dmc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1 -#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2 -#define reg_iop_dmc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_in_r_stat___dif_en___width 1 -#define reg_iop_dmc_in_r_stat___dif_en___bit 0 -#define reg_iop_dmc_in_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_in_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_in_rw_stream_cmd_offset 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_offset 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1 -#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2 -#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3 -#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3 -#define reg_iop_dmc_in_rw_stream_ctrl_offset 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0 -#define reg_iop_dmc_in_r_stream_stat___sth___width 7 -#define reg_iop_dmc_in_r_stream_stat___full___lsb 16 -#define reg_iop_dmc_in_r_stream_stat___full___width 1 -#define reg_iop_dmc_in_r_stream_stat___full___bit 16 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1 -#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22 -#define reg_iop_dmc_in_r_stream_stat_offset 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_data_descr___stat___width 8 -#define reg_iop_dmc_in_r_data_descr___md___lsb 16 -#define reg_iop_dmc_in_r_data_descr___md___width 16 -#define reg_iop_dmc_in_r_data_descr_offset 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_r_ctxt_descr_offset 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_in_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_in_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_in_r_group_descr___stat___width 8 -#define reg_iop_dmc_in_r_group_descr___md___lsb 16 -#define reg_iop_dmc_in_r_group_descr___md___width 16 -#define reg_iop_dmc_in_r_group_descr_offset 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_data_descr___md___width 16 -#define reg_iop_dmc_in_rw_data_descr_offset 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_in_rw_ctxt_descr_offset 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_in_rw_group_descr___md___width 16 -#define reg_iop_dmc_in_rw_group_descr_offset 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4 -#define reg_iop_dmc_in_rw_intr_mask___sth___width 1 -#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4 -#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5 -#define reg_iop_dmc_in_rw_intr_mask___full___width 1 -#define reg_iop_dmc_in_rw_intr_mask___full___bit 5 -#define reg_iop_dmc_in_rw_intr_mask_offset 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4 -#define reg_iop_dmc_in_rw_ack_intr___sth___width 1 -#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4 -#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5 -#define reg_iop_dmc_in_rw_ack_intr___full___width 1 -#define reg_iop_dmc_in_rw_ack_intr___full___bit 5 -#define reg_iop_dmc_in_rw_ack_intr_offset 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_intr___data_md___width 1 -#define reg_iop_dmc_in_r_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_intr___group_md___width 1 -#define reg_iop_dmc_in_r_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_intr___sth___width 1 -#define reg_iop_dmc_in_r_intr___sth___bit 4 -#define reg_iop_dmc_in_r_intr___full___lsb 5 -#define reg_iop_dmc_in_r_intr___full___width 1 -#define reg_iop_dmc_in_r_intr___full___bit 5 -#define reg_iop_dmc_in_r_intr_offset 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_in_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_in_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4 -#define reg_iop_dmc_in_r_masked_intr___sth___width 1 -#define reg_iop_dmc_in_r_masked_intr___sth___bit 4 -#define reg_iop_dmc_in_r_masked_intr___full___lsb 5 -#define reg_iop_dmc_in_r_masked_intr___full___width 1 -#define reg_iop_dmc_in_r_masked_intr___full___bit 5 -#define reg_iop_dmc_in_r_masked_intr_offset 100 - - -/* Constants */ -#define regk_iop_dmc_in_ack_pkt 0x00000100 -#define regk_iop_dmc_in_array 0x00000008 -#define regk_iop_dmc_in_burst 0x00000020 -#define regk_iop_dmc_in_copy_next 0x00000010 -#define regk_iop_dmc_in_copy_up 0x00000020 -#define regk_iop_dmc_in_dis_c 0x00000010 -#define regk_iop_dmc_in_dis_g 0x00000020 -#define regk_iop_dmc_in_lim1 0x00000000 -#define regk_iop_dmc_in_lim16 0x00000004 -#define regk_iop_dmc_in_lim2 0x00000001 -#define regk_iop_dmc_in_lim32 0x00000005 -#define regk_iop_dmc_in_lim4 0x00000002 -#define regk_iop_dmc_in_lim64 0x00000006 -#define regk_iop_dmc_in_lim8 0x00000003 -#define regk_iop_dmc_in_load_c 0x00000200 -#define regk_iop_dmc_in_load_c_n 0x00000280 -#define regk_iop_dmc_in_load_c_next 0x00000240 -#define regk_iop_dmc_in_load_d 0x00000140 -#define regk_iop_dmc_in_load_g 0x00000300 -#define regk_iop_dmc_in_load_g_down 0x000003c0 -#define regk_iop_dmc_in_load_g_next 0x00000340 -#define regk_iop_dmc_in_load_g_up 0x00000380 -#define regk_iop_dmc_in_next_en 0x00000010 -#define regk_iop_dmc_in_next_pkt 0x00000010 -#define regk_iop_dmc_in_no 0x00000000 -#define regk_iop_dmc_in_restore 0x00000020 -#define regk_iop_dmc_in_rw_cfg_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_in_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000 -#define regk_iop_dmc_in_save_down 0x00000020 -#define regk_iop_dmc_in_save_up 0x00000020 -#define regk_iop_dmc_in_set_reg 0x00000050 -#define regk_iop_dmc_in_set_w_size1 0x00000190 -#define regk_iop_dmc_in_set_w_size2 0x000001a0 -#define regk_iop_dmc_in_set_w_size4 0x000001c0 -#define regk_iop_dmc_in_store_c 0x00000002 -#define regk_iop_dmc_in_store_descr 0x00000000 -#define regk_iop_dmc_in_store_g 0x00000004 -#define regk_iop_dmc_in_store_md 0x00000001 -#define regk_iop_dmc_in_update_down 0x00000020 -#define regk_iop_dmc_in_yes 0x00000001 -#endif /* __iop_dmc_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h deleted file mode 100644 index a97b741bd36a..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h +++ /dev/null @@ -1,350 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_dmc_out_defs_asm_h -#define __iop_dmc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0 -#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1 -#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16 -#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17 -#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3 -#define reg_iop_dmc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0 -#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1 -#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1 -#define reg_iop_dmc_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stat___dif_en___lsb 0 -#define reg_iop_dmc_out_r_stat___dif_en___width 1 -#define reg_iop_dmc_out_r_stat___dif_en___bit 0 -#define reg_iop_dmc_out_r_stat_offset 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0 -#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10 -#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16 -#define reg_iop_dmc_out_rw_stream_cmd___n___width 8 -#define reg_iop_dmc_out_rw_stream_cmd_offset 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -#define reg_iop_dmc_out_rs_stream_data_offset 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_data_offset 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0 -#define reg_iop_dmc_out_r_stream_stat___dth___width 7 -#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16 -#define reg_iop_dmc_out_r_stream_stat___dv___width 1 -#define reg_iop_dmc_out_r_stream_stat___dv___bit 16 -#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17 -#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1 -#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17 -#define reg_iop_dmc_out_r_stream_stat___last___lsb 18 -#define reg_iop_dmc_out_r_stream_stat___last___width 1 -#define reg_iop_dmc_out_r_stream_stat___last___bit 18 -#define reg_iop_dmc_out_r_stream_stat___size___lsb 19 -#define reg_iop_dmc_out_r_stream_stat___size___width 3 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1 -#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1 -#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1 -#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27 -#define reg_iop_dmc_out_r_stream_stat_offset 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_data_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_data_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_data_descr___stat___width 8 -#define reg_iop_dmc_out_r_data_descr___md___lsb 16 -#define reg_iop_dmc_out_r_data_descr___md___width 16 -#define reg_iop_dmc_out_r_data_descr_offset 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8 -#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_r_ctxt_descr_offset 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0 -#define reg_iop_dmc_out_r_group_descr___ctrl___width 8 -#define reg_iop_dmc_out_r_group_descr___stat___lsb 8 -#define reg_iop_dmc_out_r_group_descr___stat___width 8 -#define reg_iop_dmc_out_r_group_descr___md___lsb 16 -#define reg_iop_dmc_out_r_group_descr___md___width 16 -#define reg_iop_dmc_out_r_group_descr_offset 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_data_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_data_descr___md___width 16 -#define reg_iop_dmc_out_rw_data_descr_offset 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16 -#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16 -#define reg_iop_dmc_out_rw_ctxt_descr_offset 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_group_descr___md___lsb 16 -#define reg_iop_dmc_out_rw_group_descr___md___width 16 -#define reg_iop_dmc_out_rw_group_descr_offset 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0 -#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2 -#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1 -#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4 -#define reg_iop_dmc_out_rw_intr_mask___dth___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4 -#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5 -#define reg_iop_dmc_out_rw_intr_mask___dv___width 1 -#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5 -#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6 -#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1 -#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1 -#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_intr_mask_offset 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0 -#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2 -#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1 -#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4 -#define reg_iop_dmc_out_rw_ack_intr___dth___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4 -#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5 -#define reg_iop_dmc_out_rw_ack_intr___dv___width 1 -#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5 -#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6 -#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1 -#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1 -#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_rw_ack_intr_offset 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_intr___data_md___width 1 -#define reg_iop_dmc_out_r_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_intr___group_md___width 1 -#define reg_iop_dmc_out_r_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_intr___dth___width 1 -#define reg_iop_dmc_out_r_intr___dth___bit 4 -#define reg_iop_dmc_out_r_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_intr___dv___width 1 -#define reg_iop_dmc_out_r_intr___dv___bit 5 -#define reg_iop_dmc_out_r_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_intr___last_data___width 1 -#define reg_iop_dmc_out_r_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_intr_offset 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0 -#define reg_iop_dmc_out_r_masked_intr___data_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2 -#define reg_iop_dmc_out_r_masked_intr___group_md___width 1 -#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3 -#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4 -#define reg_iop_dmc_out_r_masked_intr___dth___width 1 -#define reg_iop_dmc_out_r_masked_intr___dth___bit 4 -#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5 -#define reg_iop_dmc_out_r_masked_intr___dv___width 1 -#define reg_iop_dmc_out_r_masked_intr___dv___bit 5 -#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6 -#define reg_iop_dmc_out_r_masked_intr___last_data___width 1 -#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1 -#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1 -#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8 -#define reg_iop_dmc_out_r_masked_intr_offset 96 - - -/* Constants */ -#define regk_iop_dmc_out_ack_pkt 0x00000100 -#define regk_iop_dmc_out_array 0x00000008 -#define regk_iop_dmc_out_burst 0x00000020 -#define regk_iop_dmc_out_copy_next 0x00000010 -#define regk_iop_dmc_out_copy_up 0x00000020 -#define regk_iop_dmc_out_dis_c 0x00000010 -#define regk_iop_dmc_out_dis_g 0x00000020 -#define regk_iop_dmc_out_lim1 0x00000000 -#define regk_iop_dmc_out_lim16 0x00000004 -#define regk_iop_dmc_out_lim2 0x00000001 -#define regk_iop_dmc_out_lim32 0x00000005 -#define regk_iop_dmc_out_lim4 0x00000002 -#define regk_iop_dmc_out_lim64 0x00000006 -#define regk_iop_dmc_out_lim8 0x00000003 -#define regk_iop_dmc_out_load_c 0x00000200 -#define regk_iop_dmc_out_load_c_n 0x00000280 -#define regk_iop_dmc_out_load_c_next 0x00000240 -#define regk_iop_dmc_out_load_d 0x00000140 -#define regk_iop_dmc_out_load_g 0x00000300 -#define regk_iop_dmc_out_load_g_down 0x000003c0 -#define regk_iop_dmc_out_load_g_next 0x00000340 -#define regk_iop_dmc_out_load_g_up 0x00000380 -#define regk_iop_dmc_out_next_en 0x00000010 -#define regk_iop_dmc_out_next_pkt 0x00000010 -#define regk_iop_dmc_out_no 0x00000000 -#define regk_iop_dmc_out_restore 0x00000020 -#define regk_iop_dmc_out_rw_cfg_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000 -#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000 -#define regk_iop_dmc_out_rw_data_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_group_descr_default 0x00000000 -#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000 -#define regk_iop_dmc_out_save_down 0x00000020 -#define regk_iop_dmc_out_save_up 0x00000020 -#define regk_iop_dmc_out_set_reg 0x00000050 -#define regk_iop_dmc_out_set_w_size1 0x00000190 -#define regk_iop_dmc_out_set_w_size2 0x000001a0 -#define regk_iop_dmc_out_set_w_size4 0x000001c0 -#define regk_iop_dmc_out_store_c 0x00000002 -#define regk_iop_dmc_out_store_descr 0x00000000 -#define regk_iop_dmc_out_store_g 0x00000004 -#define regk_iop_dmc_out_store_md 0x00000001 -#define regk_iop_dmc_out_update_down 0x00000020 -#define regk_iop_dmc_out_yes 0x00000001 -#endif /* __iop_dmc_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h deleted file mode 100644 index e2c0990246f2..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h +++ /dev/null @@ -1,235 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_in_defs_asm_h -#define __iop_fifo_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0 -#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_in_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_in_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_in_rw_cfg___trig___width 2 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_in_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_in_rw_cfg___mode___width 2 -#define reg_iop_fifo_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_r_stat___last___lsb 4 -#define reg_iop_fifo_in_r_stat___last___width 8 -#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_r_stat_offset 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd1byte___data___width 8 -#define reg_iop_fifo_in_rs_rd1byte_offset 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd1byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd1byte___data___width 8 -#define reg_iop_fifo_in_r_rd1byte_offset 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd2byte___data___width 16 -#define reg_iop_fifo_in_rs_rd2byte_offset 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd2byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd2byte___data___width 16 -#define reg_iop_fifo_in_r_rd2byte_offset 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd3byte___data___width 24 -#define reg_iop_fifo_in_rs_rd3byte_offset 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd3byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd3byte___data___width 24 -#define reg_iop_fifo_in_r_rd3byte_offset 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_rs_rd4byte___data___width 32 -#define reg_iop_fifo_in_rs_rd4byte_offset 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_rd4byte___data___lsb 0 -#define reg_iop_fifo_in_r_rd4byte___data___width 32 -#define reg_iop_fifo_in_r_rd4byte_offset 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_set_last_offset 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_rw_strb_dif_in_offset 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_rw_intr_mask_offset 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_rw_ack_intr_offset 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_intr___urun___width 1 -#define reg_iop_fifo_in_r_intr___urun___bit 0 -#define reg_iop_fifo_in_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_intr___last_data___width 1 -#define reg_iop_fifo_in_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_intr___dav___width 1 -#define reg_iop_fifo_in_r_intr___dav___bit 2 -#define reg_iop_fifo_in_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_intr___avail___width 1 -#define reg_iop_fifo_in_r_intr___avail___bit 3 -#define reg_iop_fifo_in_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_intr___orun___width 1 -#define reg_iop_fifo_in_r_intr___orun___bit 4 -#define reg_iop_fifo_in_r_intr_offset 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_r_masked_intr_offset 64 - - -/* Constants */ -#define regk_iop_fifo_in_dif_in 0x00000002 -#define regk_iop_fifo_in_hi 0x00000000 -#define regk_iop_fifo_in_neg 0x00000002 -#define regk_iop_fifo_in_no 0x00000000 -#define regk_iop_fifo_in_order16 0x00000001 -#define regk_iop_fifo_in_order24 0x00000002 -#define regk_iop_fifo_in_order32 0x00000003 -#define regk_iop_fifo_in_order8 0x00000000 -#define regk_iop_fifo_in_pos 0x00000001 -#define regk_iop_fifo_in_pos_neg 0x00000003 -#define regk_iop_fifo_in_rw_cfg_default 0x00000024 -#define regk_iop_fifo_in_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_rw_set_last_default 0x00000000 -#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000 -#define regk_iop_fifo_in_size16 0x00000002 -#define regk_iop_fifo_in_size24 0x00000001 -#define regk_iop_fifo_in_size32 0x00000000 -#define regk_iop_fifo_in_size8 0x00000003 -#define regk_iop_fifo_in_yes 0x00000001 -#endif /* __iop_fifo_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h deleted file mode 100644 index 50837b989c90..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_in_extra_defs_asm_h -#define __iop_fifo_in_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_wr_data_offset 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_in_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_in_extra_r_stat___last___width 8 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_in_extra_r_stat_offset 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0 -#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2 -#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_intr_offset 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_in_extra_r_masked_intr_offset 24 - - -/* Constants */ -#define regk_iop_fifo_in_extra_fifo_in 0x00000002 -#define regk_iop_fifo_in_extra_no 0x00000000 -#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_in_extra_yes 0x00000001 -#endif /* __iop_fifo_in_extra_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h deleted file mode 100644 index 9f06dddf33a0..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h +++ /dev/null @@ -1,255 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_out_defs_asm_h -#define __iop_fifo_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0 -#define reg_iop_fifo_out_rw_cfg___free_lim___width 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3 -#define reg_iop_fifo_out_rw_cfg___byte_order___width 2 -#define reg_iop_fifo_out_rw_cfg___trig___lsb 5 -#define reg_iop_fifo_out_rw_cfg___trig___width 2 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7 -#define reg_iop_fifo_out_rw_cfg___mode___lsb 8 -#define reg_iop_fifo_out_rw_cfg___mode___width 2 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1 -#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1 -#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11 -#define reg_iop_fifo_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1 -#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1 -#define reg_iop_fifo_out_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_r_stat___last___lsb 4 -#define reg_iop_fifo_out_r_stat___last___width 8 -#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_r_stat_offset 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_offset 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_offset 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_offset 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_offset 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8 -#define reg_iop_fifo_out_rw_wr1byte_last_offset 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16 -#define reg_iop_fifo_out_rw_wr2byte_last_offset 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24 -#define reg_iop_fifo_out_rw_wr3byte_last_offset 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0 -#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32 -#define reg_iop_fifo_out_rw_wr4byte_last_offset 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_set_last_offset 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -#define reg_iop_fifo_out_rs_rd_data_offset 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_rd_data_offset 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_strb_dif_out_offset 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_rw_intr_mask_offset 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_rw_ack_intr_offset 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_intr___urun___width 1 -#define reg_iop_fifo_out_r_intr___urun___bit 0 -#define reg_iop_fifo_out_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_intr___last_data___width 1 -#define reg_iop_fifo_out_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_intr___dav___width 1 -#define reg_iop_fifo_out_r_intr___dav___bit 2 -#define reg_iop_fifo_out_r_intr___free___lsb 3 -#define reg_iop_fifo_out_r_intr___free___width 1 -#define reg_iop_fifo_out_r_intr___free___bit 3 -#define reg_iop_fifo_out_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_intr___orun___width 1 -#define reg_iop_fifo_out_r_intr___orun___bit 4 -#define reg_iop_fifo_out_r_intr_offset 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_r_masked_intr_offset 72 - - -/* Constants */ -#define regk_iop_fifo_out_hi 0x00000000 -#define regk_iop_fifo_out_neg 0x00000002 -#define regk_iop_fifo_out_no 0x00000000 -#define regk_iop_fifo_out_order16 0x00000001 -#define regk_iop_fifo_out_order24 0x00000002 -#define regk_iop_fifo_out_order32 0x00000003 -#define regk_iop_fifo_out_order8 0x00000000 -#define regk_iop_fifo_out_pos 0x00000001 -#define regk_iop_fifo_out_pos_neg 0x00000003 -#define regk_iop_fifo_out_rw_cfg_default 0x00000024 -#define regk_iop_fifo_out_rw_ctrl_default 0x00000000 -#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_rw_set_last_default 0x00000000 -#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000 -#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000 -#define regk_iop_fifo_out_size16 0x00000002 -#define regk_iop_fifo_out_size24 0x00000001 -#define regk_iop_fifo_out_size32 0x00000000 -#define regk_iop_fifo_out_size8 0x00000003 -#define regk_iop_fifo_out_yes 0x00000001 -#endif /* __iop_fifo_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h deleted file mode 100644 index e8c488c389e4..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_out_extra_defs_asm_h -#define __iop_fifo_out_extra_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -#define reg_iop_fifo_out_extra_rs_rd_data_offset 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_rd_data_offset 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0 -#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4 -#define reg_iop_fifo_out_extra_r_stat___last___lsb 4 -#define reg_iop_fifo_out_extra_r_stat___last___width 8 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1 -#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1 -#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14 -#define reg_iop_fifo_out_extra_r_stat_offset 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1 -#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1 -#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_intr_offset 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2 -#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3 -#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1 -#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4 -#define reg_iop_fifo_out_extra_r_masked_intr_offset 28 - - -/* Constants */ -#define regk_iop_fifo_out_extra_no 0x00000000 -#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000 -#define regk_iop_fifo_out_extra_yes 0x00000001 -#endif /* __iop_fifo_out_extra_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h deleted file mode 100644 index 48869d445e07..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_mpu_defs_asm_h -#define __iop_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_r_offset 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_ctrl___en___lsb 0 -#define reg_iop_mpu_rw_ctrl___en___width 1 -#define reg_iop_mpu_rw_ctrl___en___bit 0 -#define reg_iop_mpu_rw_ctrl_offset 128 - -/* Register r_pc, scope iop_mpu, type r */ -#define reg_iop_mpu_r_pc___addr___lsb 0 -#define reg_iop_mpu_r_pc___addr___width 12 -#define reg_iop_mpu_r_pc_offset 132 - -/* Register r_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0 -#define reg_iop_mpu_r_stat___instr_reg_busy___width 1 -#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0 -#define reg_iop_mpu_r_stat___intr_busy___lsb 1 -#define reg_iop_mpu_r_stat___intr_busy___width 1 -#define reg_iop_mpu_r_stat___intr_busy___bit 1 -#define reg_iop_mpu_r_stat___intr_vect___lsb 2 -#define reg_iop_mpu_r_stat___intr_vect___width 16 -#define reg_iop_mpu_r_stat_offset 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_instr_offset 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_immediate_offset 144 - -/* Register r_trace, scope iop_mpu, type r */ -#define reg_iop_mpu_r_trace___intr_vect___lsb 0 -#define reg_iop_mpu_r_trace___intr_vect___width 16 -#define reg_iop_mpu_r_trace___pc___lsb 16 -#define reg_iop_mpu_r_trace___pc___width 12 -#define reg_iop_mpu_r_trace___en___lsb 28 -#define reg_iop_mpu_r_trace___en___width 1 -#define reg_iop_mpu_r_trace___en___bit 28 -#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29 -#define reg_iop_mpu_r_trace___instr_reg_busy___width 1 -#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29 -#define reg_iop_mpu_r_trace___intr_busy___lsb 30 -#define reg_iop_mpu_r_trace___intr_busy___width 1 -#define reg_iop_mpu_r_trace___intr_busy___bit 30 -#define reg_iop_mpu_r_trace_offset 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -#define reg_iop_mpu_r_wr_stat___r0___lsb 0 -#define reg_iop_mpu_r_wr_stat___r0___width 1 -#define reg_iop_mpu_r_wr_stat___r0___bit 0 -#define reg_iop_mpu_r_wr_stat___r1___lsb 1 -#define reg_iop_mpu_r_wr_stat___r1___width 1 -#define reg_iop_mpu_r_wr_stat___r1___bit 1 -#define reg_iop_mpu_r_wr_stat___r2___lsb 2 -#define reg_iop_mpu_r_wr_stat___r2___width 1 -#define reg_iop_mpu_r_wr_stat___r2___bit 2 -#define reg_iop_mpu_r_wr_stat___r3___lsb 3 -#define reg_iop_mpu_r_wr_stat___r3___width 1 -#define reg_iop_mpu_r_wr_stat___r3___bit 3 -#define reg_iop_mpu_r_wr_stat___r4___lsb 4 -#define reg_iop_mpu_r_wr_stat___r4___width 1 -#define reg_iop_mpu_r_wr_stat___r4___bit 4 -#define reg_iop_mpu_r_wr_stat___r5___lsb 5 -#define reg_iop_mpu_r_wr_stat___r5___width 1 -#define reg_iop_mpu_r_wr_stat___r5___bit 5 -#define reg_iop_mpu_r_wr_stat___r6___lsb 6 -#define reg_iop_mpu_r_wr_stat___r6___width 1 -#define reg_iop_mpu_r_wr_stat___r6___bit 6 -#define reg_iop_mpu_r_wr_stat___r7___lsb 7 -#define reg_iop_mpu_r_wr_stat___r7___width 1 -#define reg_iop_mpu_r_wr_stat___r7___bit 7 -#define reg_iop_mpu_r_wr_stat___r8___lsb 8 -#define reg_iop_mpu_r_wr_stat___r8___width 1 -#define reg_iop_mpu_r_wr_stat___r8___bit 8 -#define reg_iop_mpu_r_wr_stat___r9___lsb 9 -#define reg_iop_mpu_r_wr_stat___r9___width 1 -#define reg_iop_mpu_r_wr_stat___r9___bit 9 -#define reg_iop_mpu_r_wr_stat___r10___lsb 10 -#define reg_iop_mpu_r_wr_stat___r10___width 1 -#define reg_iop_mpu_r_wr_stat___r10___bit 10 -#define reg_iop_mpu_r_wr_stat___r11___lsb 11 -#define reg_iop_mpu_r_wr_stat___r11___width 1 -#define reg_iop_mpu_r_wr_stat___r11___bit 11 -#define reg_iop_mpu_r_wr_stat___r12___lsb 12 -#define reg_iop_mpu_r_wr_stat___r12___width 1 -#define reg_iop_mpu_r_wr_stat___r12___bit 12 -#define reg_iop_mpu_r_wr_stat___r13___lsb 13 -#define reg_iop_mpu_r_wr_stat___r13___width 1 -#define reg_iop_mpu_r_wr_stat___r13___bit 13 -#define reg_iop_mpu_r_wr_stat___r14___lsb 14 -#define reg_iop_mpu_r_wr_stat___r14___width 1 -#define reg_iop_mpu_r_wr_stat___r14___bit 14 -#define reg_iop_mpu_r_wr_stat___r15___lsb 15 -#define reg_iop_mpu_r_wr_stat___r15___width 1 -#define reg_iop_mpu_r_wr_stat___r15___bit 15 -#define reg_iop_mpu_r_wr_stat_offset 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_thread___addr___lsb 0 -#define reg_iop_mpu_rw_thread___addr___width 12 -#define reg_iop_mpu_rw_thread_offset 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -#define reg_iop_mpu_rw_intr___addr___lsb 0 -#define reg_iop_mpu_rw_intr___addr___width 12 -#define reg_iop_mpu_rw_intr_offset 196 - - -/* Constants */ -#define regk_iop_mpu_no 0x00000000 -#define regk_iop_mpu_r_pc_default 0x00000000 -#define regk_iop_mpu_rw_ctrl_default 0x00000000 -#define regk_iop_mpu_rw_intr_size 0x00000010 -#define regk_iop_mpu_rw_r_size 0x00000010 -#define regk_iop_mpu_rw_thread_default 0x00000000 -#define regk_iop_mpu_rw_thread_size 0x00000004 -#define regk_iop_mpu_yes 0x00000001 -#endif /* __iop_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index 615f869a6de9..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in0_extra 64 -#define iop_fifo_in1_extra 128 -#define iop_fifo_out0_extra 192 -#define iop_fifo_out1_extra 256 -#define iop_trigger_grp0 320 -#define iop_trigger_grp1 384 -#define iop_trigger_grp2 448 -#define iop_trigger_grp3 512 -#define iop_trigger_grp4 576 -#define iop_trigger_grp5 640 -#define iop_trigger_grp6 704 -#define iop_trigger_grp7 768 -#define iop_crc_par0 896 -#define iop_crc_par1 1024 -#define iop_dmc_in0 1152 -#define iop_dmc_in1 1280 -#define iop_dmc_out0 1408 -#define iop_dmc_out1 1536 -#define iop_fifo_in0 1664 -#define iop_fifo_in1 1792 -#define iop_fifo_out0 1920 -#define iop_fifo_out1 2048 -#define iop_scrc_in0 2176 -#define iop_scrc_in1 2304 -#define iop_scrc_out0 2432 -#define iop_scrc_out1 2560 -#define iop_timer_grp0 2688 -#define iop_timer_grp1 2816 -#define iop_timer_grp2 2944 -#define iop_timer_grp3 3072 -#define iop_sap_in 3328 -#define iop_sap_out 3584 -#define iop_spu0 3840 -#define iop_spu1 4096 -#define iop_sw_cfg 4352 -#define iop_sw_cpu 4608 -#define iop_sw_mpu 4864 -#define iop_sw_spu0 5120 -#define iop_sw_spu1 5376 -#define iop_mpu 5632 diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index fe8c90e015b0..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus0_sync_offset 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0 -#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5 -#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8 -#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10 -#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13 -#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16 -#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18 -#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21 -#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24 -#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26 -#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29 -#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1 -#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31 -#define reg_iop_sap_in_rw_bus1_sync_offset 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 1 -#define reg_iop_sap_in_rw_gio___delay___bit 7 -#define reg_iop_sap_in_rw_gio___logic___lsb 8 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 8 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio1 0x00000000 -#define regk_iop_sap_in_gio13 0x00000005 -#define regk_iop_sap_in_gio18 0x00000003 -#define regk_iop_sap_in_gio19 0x00000004 -#define regk_iop_sap_in_gio21 0x00000006 -#define regk_iop_sap_in_gio23 0x00000005 -#define regk_iop_sap_in_gio29 0x00000007 -#define regk_iop_sap_in_gio5 0x00000004 -#define regk_iop_sap_in_gio6 0x00000001 -#define regk_iop_sap_in_gio7 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000001 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202 -#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202 -#define regk_iop_sap_in_rw_gio_default 0x00000002 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004 -#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005 -#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007 -#define regk_iop_sap_in_tmr_clk200 0x00000000 -#define regk_iop_sap_in_two_clk200 0x00000002 -#define regk_iop_sap_in_yes 0x00000001 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index a5e46f0bbf6f..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,347 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14 -#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16 -#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18 -#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21 -#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23 -#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25 -#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus0_offset 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3 -#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6 -#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9 -#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18 -#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21 -#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23 -#define reg_iop_sap_out_rw_bus1_offset 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20 -#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic___width 1 -#define reg_iop_sap_out_rw_gio___out_logic___bit 10 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio_offset 28 - - -/* Constants */ -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000002 -#define regk_iop_sap_out_clk2 0x00000002 -#define regk_iop_sap_out_clk200 0x00000001 -#define regk_iop_sap_out_clk3 0x00000003 -#define regk_iop_sap_out_ext 0x00000003 -#define regk_iop_sap_out_gated 0x00000004 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio13 0x00000002 -#define regk_iop_sap_out_gio13_clk 0x0000000c -#define regk_iop_sap_out_gio15 0x00000001 -#define regk_iop_sap_out_gio18 0x00000003 -#define regk_iop_sap_out_gio18_clk 0x0000000d -#define regk_iop_sap_out_gio1_clk 0x00000008 -#define regk_iop_sap_out_gio21_clk 0x0000000e -#define regk_iop_sap_out_gio23 0x00000002 -#define regk_iop_sap_out_gio29_clk 0x0000000f -#define regk_iop_sap_out_gio31 0x00000003 -#define regk_iop_sap_out_gio5 0x00000001 -#define regk_iop_sap_out_gio5_clk 0x00000009 -#define regk_iop_sap_out_gio6_clk 0x0000000a -#define regk_iop_sap_out_gio7 0x00000000 -#define regk_iop_sap_out_gio7_clk 0x0000000b -#define regk_iop_sap_out_gio_in13 0x00000001 -#define regk_iop_sap_out_gio_in21 0x00000002 -#define regk_iop_sap_out_gio_in29 0x00000003 -#define regk_iop_sap_out_gio_in5 0x00000000 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_rw_bus0_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu0_gio0 0x00000002 -#define regk_iop_sap_out_spu0_gio1 0x00000003 -#define regk_iop_sap_out_spu0_gio12 0x00000004 -#define regk_iop_sap_out_spu0_gio13 0x00000004 -#define regk_iop_sap_out_spu0_gio14 0x00000004 -#define regk_iop_sap_out_spu0_gio15 0x00000004 -#define regk_iop_sap_out_spu0_gio2 0x00000002 -#define regk_iop_sap_out_spu0_gio3 0x00000003 -#define regk_iop_sap_out_spu0_gio4 0x00000002 -#define regk_iop_sap_out_spu0_gio5 0x00000003 -#define regk_iop_sap_out_spu0_gio6 0x00000002 -#define regk_iop_sap_out_spu0_gio7 0x00000003 -#define regk_iop_sap_out_spu1_gio0 0x00000005 -#define regk_iop_sap_out_spu1_gio1 0x00000006 -#define regk_iop_sap_out_spu1_gio12 0x00000007 -#define regk_iop_sap_out_spu1_gio13 0x00000007 -#define regk_iop_sap_out_spu1_gio14 0x00000007 -#define regk_iop_sap_out_spu1_gio15 0x00000007 -#define regk_iop_sap_out_spu1_gio2 0x00000005 -#define regk_iop_sap_out_spu1_gio3 0x00000006 -#define regk_iop_sap_out_spu1_gio4 0x00000005 -#define regk_iop_sap_out_spu1_gio5 0x00000006 -#define regk_iop_sap_out_spu1_gio6 0x00000005 -#define regk_iop_sap_out_spu1_gio7 0x00000006 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005 -#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006 -#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007 -#define regk_iop_sap_out_tmr 0x00000005 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h deleted file mode 100644 index 169aaf8d44b2..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_scrc_in_defs_asm_h -#define __iop_scrc_in_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_in_rw_cfg___trig___width 2 -#define reg_iop_scrc_in_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1 -#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0 -#define reg_iop_scrc_in_rw_ctrl_offset 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_stat___err___lsb 0 -#define reg_iop_scrc_in_r_stat___err___width 1 -#define reg_iop_scrc_in_r_stat___err___bit 0 -#define reg_iop_scrc_in_r_stat_offset 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_init_crc_offset 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -#define reg_iop_scrc_in_rs_computed_crc_offset 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -#define reg_iop_scrc_in_r_computed_crc_offset 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_crc_offset 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_correct_crc_offset 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0 -#define reg_iop_scrc_in_rw_wr1bit___data___width 2 -#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2 -#define reg_iop_scrc_in_rw_wr1bit___last___width 2 -#define reg_iop_scrc_in_rw_wr1bit_offset 32 - - -/* Constants */ -#define regk_iop_scrc_in_dif_in 0x00000002 -#define regk_iop_scrc_in_hi 0x00000000 -#define regk_iop_scrc_in_neg 0x00000002 -#define regk_iop_scrc_in_no 0x00000000 -#define regk_iop_scrc_in_pos 0x00000001 -#define regk_iop_scrc_in_pos_neg 0x00000003 -#define regk_iop_scrc_in_r_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000 -#define regk_iop_scrc_in_rw_cfg_default 0x00000000 -#define regk_iop_scrc_in_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_in_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_in_set0 0x00000000 -#define regk_iop_scrc_in_set1 0x00000001 -#define regk_iop_scrc_in_yes 0x00000001 -#endif /* __iop_scrc_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h deleted file mode 100644 index 0e9bca149bc6..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_scrc_out_defs_asm_h -#define __iop_scrc_out_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_cfg___trig___lsb 0 -#define reg_iop_scrc_out_rw_cfg___trig___width 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2 -#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1 -#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2 -#define reg_iop_scrc_out_rw_cfg_offset 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0 -#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0 -#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___width 1 -#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1 -#define reg_iop_scrc_out_rw_ctrl_offset 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_init_crc_offset 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_crc_offset 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -#define reg_iop_scrc_out_rw_data___val___lsb 0 -#define reg_iop_scrc_out_rw_data___val___width 1 -#define reg_iop_scrc_out_rw_data___val___bit 0 -#define reg_iop_scrc_out_rw_data_offset 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -#define reg_iop_scrc_out_r_computed_crc_offset 20 - - -/* Constants */ -#define regk_iop_scrc_out_crc 0x00000001 -#define regk_iop_scrc_out_data 0x00000000 -#define regk_iop_scrc_out_dif 0x00000001 -#define regk_iop_scrc_out_hi 0x00000000 -#define regk_iop_scrc_out_neg 0x00000002 -#define regk_iop_scrc_out_no 0x00000000 -#define regk_iop_scrc_out_pos 0x00000001 -#define regk_iop_scrc_out_pos_neg 0x00000003 -#define regk_iop_scrc_out_reg 0x00000000 -#define regk_iop_scrc_out_rw_cfg_default 0x00000000 -#define regk_iop_scrc_out_rw_crc_default 0x00000000 -#define regk_iop_scrc_out_rw_ctrl_default 0x00000000 -#define regk_iop_scrc_out_rw_data_default 0x00000000 -#define regk_iop_scrc_out_rw_init_crc_default 0x00000000 -#define regk_iop_scrc_out_yes 0x00000001 -#endif /* __iop_scrc_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h deleted file mode 100644 index cf2b64a9d42c..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h +++ /dev/null @@ -1,574 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_spu_defs_asm_h -#define __iop_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -#define reg_iop_spu_rw_r_offset 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_seq_pc___addr___lsb 0 -#define reg_iop_spu_rw_seq_pc___addr___width 12 -#define reg_iop_spu_rw_seq_pc_offset 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_pc___addr___lsb 0 -#define reg_iop_spu_rw_fsm_pc___addr___width 12 -#define reg_iop_spu_rw_fsm_pc_offset 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -#define reg_iop_spu_rw_ctrl___fsm___lsb 0 -#define reg_iop_spu_rw_ctrl___fsm___width 1 -#define reg_iop_spu_rw_ctrl___fsm___bit 0 -#define reg_iop_spu_rw_ctrl___en___lsb 1 -#define reg_iop_spu_rw_ctrl___en___width 1 -#define reg_iop_spu_rw_ctrl___en___bit 1 -#define reg_iop_spu_rw_ctrl_offset 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0 -#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8 -#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13 -#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16 -#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21 -#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24 -#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29 -#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3 -#define reg_iop_spu_rw_fsm_inputs3_0_offset 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0 -#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8 -#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13 -#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16 -#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21 -#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24 -#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29 -#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3 -#define reg_iop_spu_rw_fsm_inputs7_4_offset 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_offset 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus0_out_offset 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -#define reg_iop_spu_rw_bus1_out_offset 92 - -/* Register r_gio_in, scope iop_spu, type r */ -#define reg_iop_spu_r_gio_in_offset 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus0_in_offset 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -#define reg_iop_spu_r_bus1_in_offset 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_set_offset 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -#define reg_iop_spu_rw_gio_out_clr_offset 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -#define reg_iop_spu_rs_wr_stat___r0___lsb 0 -#define reg_iop_spu_rs_wr_stat___r0___width 1 -#define reg_iop_spu_rs_wr_stat___r0___bit 0 -#define reg_iop_spu_rs_wr_stat___r1___lsb 1 -#define reg_iop_spu_rs_wr_stat___r1___width 1 -#define reg_iop_spu_rs_wr_stat___r1___bit 1 -#define reg_iop_spu_rs_wr_stat___r2___lsb 2 -#define reg_iop_spu_rs_wr_stat___r2___width 1 -#define reg_iop_spu_rs_wr_stat___r2___bit 2 -#define reg_iop_spu_rs_wr_stat___r3___lsb 3 -#define reg_iop_spu_rs_wr_stat___r3___width 1 -#define reg_iop_spu_rs_wr_stat___r3___bit 3 -#define reg_iop_spu_rs_wr_stat___r4___lsb 4 -#define reg_iop_spu_rs_wr_stat___r4___width 1 -#define reg_iop_spu_rs_wr_stat___r4___bit 4 -#define reg_iop_spu_rs_wr_stat___r5___lsb 5 -#define reg_iop_spu_rs_wr_stat___r5___width 1 -#define reg_iop_spu_rs_wr_stat___r5___bit 5 -#define reg_iop_spu_rs_wr_stat___r6___lsb 6 -#define reg_iop_spu_rs_wr_stat___r6___width 1 -#define reg_iop_spu_rs_wr_stat___r6___bit 6 -#define reg_iop_spu_rs_wr_stat___r7___lsb 7 -#define reg_iop_spu_rs_wr_stat___r7___width 1 -#define reg_iop_spu_rs_wr_stat___r7___bit 7 -#define reg_iop_spu_rs_wr_stat___r8___lsb 8 -#define reg_iop_spu_rs_wr_stat___r8___width 1 -#define reg_iop_spu_rs_wr_stat___r8___bit 8 -#define reg_iop_spu_rs_wr_stat___r9___lsb 9 -#define reg_iop_spu_rs_wr_stat___r9___width 1 -#define reg_iop_spu_rs_wr_stat___r9___bit 9 -#define reg_iop_spu_rs_wr_stat___r10___lsb 10 -#define reg_iop_spu_rs_wr_stat___r10___width 1 -#define reg_iop_spu_rs_wr_stat___r10___bit 10 -#define reg_iop_spu_rs_wr_stat___r11___lsb 11 -#define reg_iop_spu_rs_wr_stat___r11___width 1 -#define reg_iop_spu_rs_wr_stat___r11___bit 11 -#define reg_iop_spu_rs_wr_stat___r12___lsb 12 -#define reg_iop_spu_rs_wr_stat___r12___width 1 -#define reg_iop_spu_rs_wr_stat___r12___bit 12 -#define reg_iop_spu_rs_wr_stat___r13___lsb 13 -#define reg_iop_spu_rs_wr_stat___r13___width 1 -#define reg_iop_spu_rs_wr_stat___r13___bit 13 -#define reg_iop_spu_rs_wr_stat___r14___lsb 14 -#define reg_iop_spu_rs_wr_stat___r14___width 1 -#define reg_iop_spu_rs_wr_stat___r14___bit 14 -#define reg_iop_spu_rs_wr_stat___r15___lsb 15 -#define reg_iop_spu_rs_wr_stat___r15___width 1 -#define reg_iop_spu_rs_wr_stat___r15___bit 15 -#define reg_iop_spu_rs_wr_stat_offset 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_wr_stat___r0___lsb 0 -#define reg_iop_spu_r_wr_stat___r0___width 1 -#define reg_iop_spu_r_wr_stat___r0___bit 0 -#define reg_iop_spu_r_wr_stat___r1___lsb 1 -#define reg_iop_spu_r_wr_stat___r1___width 1 -#define reg_iop_spu_r_wr_stat___r1___bit 1 -#define reg_iop_spu_r_wr_stat___r2___lsb 2 -#define reg_iop_spu_r_wr_stat___r2___width 1 -#define reg_iop_spu_r_wr_stat___r2___bit 2 -#define reg_iop_spu_r_wr_stat___r3___lsb 3 -#define reg_iop_spu_r_wr_stat___r3___width 1 -#define reg_iop_spu_r_wr_stat___r3___bit 3 -#define reg_iop_spu_r_wr_stat___r4___lsb 4 -#define reg_iop_spu_r_wr_stat___r4___width 1 -#define reg_iop_spu_r_wr_stat___r4___bit 4 -#define reg_iop_spu_r_wr_stat___r5___lsb 5 -#define reg_iop_spu_r_wr_stat___r5___width 1 -#define reg_iop_spu_r_wr_stat___r5___bit 5 -#define reg_iop_spu_r_wr_stat___r6___lsb 6 -#define reg_iop_spu_r_wr_stat___r6___width 1 -#define reg_iop_spu_r_wr_stat___r6___bit 6 -#define reg_iop_spu_r_wr_stat___r7___lsb 7 -#define reg_iop_spu_r_wr_stat___r7___width 1 -#define reg_iop_spu_r_wr_stat___r7___bit 7 -#define reg_iop_spu_r_wr_stat___r8___lsb 8 -#define reg_iop_spu_r_wr_stat___r8___width 1 -#define reg_iop_spu_r_wr_stat___r8___bit 8 -#define reg_iop_spu_r_wr_stat___r9___lsb 9 -#define reg_iop_spu_r_wr_stat___r9___width 1 -#define reg_iop_spu_r_wr_stat___r9___bit 9 -#define reg_iop_spu_r_wr_stat___r10___lsb 10 -#define reg_iop_spu_r_wr_stat___r10___width 1 -#define reg_iop_spu_r_wr_stat___r10___bit 10 -#define reg_iop_spu_r_wr_stat___r11___lsb 11 -#define reg_iop_spu_r_wr_stat___r11___width 1 -#define reg_iop_spu_r_wr_stat___r11___bit 11 -#define reg_iop_spu_r_wr_stat___r12___lsb 12 -#define reg_iop_spu_r_wr_stat___r12___width 1 -#define reg_iop_spu_r_wr_stat___r12___bit 12 -#define reg_iop_spu_r_wr_stat___r13___lsb 13 -#define reg_iop_spu_r_wr_stat___r13___width 1 -#define reg_iop_spu_r_wr_stat___r13___bit 13 -#define reg_iop_spu_r_wr_stat___r14___lsb 14 -#define reg_iop_spu_r_wr_stat___r14___width 1 -#define reg_iop_spu_r_wr_stat___r14___bit 14 -#define reg_iop_spu_r_wr_stat___r15___lsb 15 -#define reg_iop_spu_r_wr_stat___r15___width 1 -#define reg_iop_spu_r_wr_stat___r15___bit 15 -#define reg_iop_spu_r_wr_stat_offset 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124 - -/* Register r_stat_in, scope iop_spu, type r */ -#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0 -#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4 -#define reg_iop_spu_r_stat_in___fifo_out_last___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5 -#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6 -#define reg_iop_spu_r_stat_in___fifo_out_all___width 1 -#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1 -#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7 -#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8 -#define reg_iop_spu_r_stat_in___dmc_out_all___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8 -#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9 -#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9 -#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10 -#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10 -#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11 -#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11 -#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12 -#define reg_iop_spu_r_stat_in___dmc_out_last___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14 -#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15 -#define reg_iop_spu_r_stat_in___pcrc_correct___width 1 -#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15 -#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16 -#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4 -#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20 -#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20 -#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21 -#define reg_iop_spu_r_stat_in___dmc_in_full___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1 -#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22 -#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23 -#define reg_iop_spu_r_stat_in___spu_gio_out___width 4 -#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27 -#define reg_iop_spu_r_stat_in___sync_clk12___width 1 -#define reg_iop_spu_r_stat_in___sync_clk12___bit 27 -#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28 -#define reg_iop_spu_r_stat_in___scrc_out_data___width 1 -#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28 -#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29 -#define reg_iop_spu_r_stat_in___scrc_in_err___width 1 -#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29 -#define reg_iop_spu_r_stat_in___mc_busy___lsb 30 -#define reg_iop_spu_r_stat_in___mc_busy___width 1 -#define reg_iop_spu_r_stat_in___mc_busy___bit 30 -#define reg_iop_spu_r_stat_in___mc_owned___lsb 31 -#define reg_iop_spu_r_stat_in___mc_owned___width 1 -#define reg_iop_spu_r_stat_in___mc_owned___bit 31 -#define reg_iop_spu_r_stat_in_offset 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -#define reg_iop_spu_r_trigger_in_offset 132 - -/* Register r_special_stat, scope iop_spu, type r */ -#define reg_iop_spu_r_special_stat___c_flag___lsb 0 -#define reg_iop_spu_r_special_stat___c_flag___width 1 -#define reg_iop_spu_r_special_stat___c_flag___bit 0 -#define reg_iop_spu_r_special_stat___v_flag___lsb 1 -#define reg_iop_spu_r_special_stat___v_flag___width 1 -#define reg_iop_spu_r_special_stat___v_flag___bit 1 -#define reg_iop_spu_r_special_stat___z_flag___lsb 2 -#define reg_iop_spu_r_special_stat___z_flag___width 1 -#define reg_iop_spu_r_special_stat___z_flag___bit 2 -#define reg_iop_spu_r_special_stat___n_flag___lsb 3 -#define reg_iop_spu_r_special_stat___n_flag___width 1 -#define reg_iop_spu_r_special_stat___n_flag___bit 3 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1 -#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7 -#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8 -#define reg_iop_spu_r_special_stat___fsm_in0___width 1 -#define reg_iop_spu_r_special_stat___fsm_in0___bit 8 -#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9 -#define reg_iop_spu_r_special_stat___fsm_in1___width 1 -#define reg_iop_spu_r_special_stat___fsm_in1___bit 9 -#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10 -#define reg_iop_spu_r_special_stat___fsm_in2___width 1 -#define reg_iop_spu_r_special_stat___fsm_in2___bit 10 -#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11 -#define reg_iop_spu_r_special_stat___fsm_in3___width 1 -#define reg_iop_spu_r_special_stat___fsm_in3___bit 11 -#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12 -#define reg_iop_spu_r_special_stat___fsm_in4___width 1 -#define reg_iop_spu_r_special_stat___fsm_in4___bit 12 -#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13 -#define reg_iop_spu_r_special_stat___fsm_in5___width 1 -#define reg_iop_spu_r_special_stat___fsm_in5___bit 13 -#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14 -#define reg_iop_spu_r_special_stat___fsm_in6___width 1 -#define reg_iop_spu_r_special_stat___fsm_in6___bit 14 -#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15 -#define reg_iop_spu_r_special_stat___fsm_in7___width 1 -#define reg_iop_spu_r_special_stat___fsm_in7___bit 15 -#define reg_iop_spu_r_special_stat___event0___lsb 16 -#define reg_iop_spu_r_special_stat___event0___width 1 -#define reg_iop_spu_r_special_stat___event0___bit 16 -#define reg_iop_spu_r_special_stat___event1___lsb 17 -#define reg_iop_spu_r_special_stat___event1___width 1 -#define reg_iop_spu_r_special_stat___event1___bit 17 -#define reg_iop_spu_r_special_stat___event2___lsb 18 -#define reg_iop_spu_r_special_stat___event2___width 1 -#define reg_iop_spu_r_special_stat___event2___bit 18 -#define reg_iop_spu_r_special_stat___event3___lsb 19 -#define reg_iop_spu_r_special_stat___event3___width 1 -#define reg_iop_spu_r_special_stat___event3___bit 19 -#define reg_iop_spu_r_special_stat_offset 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -#define reg_iop_spu_rw_reg_access___addr___lsb 0 -#define reg_iop_spu_rw_reg_access___addr___width 13 -#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16 -#define reg_iop_spu_rw_reg_access___imm_hi___width 16 -#define reg_iop_spu_rw_reg_access_offset 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_cfg___addr___lsb 0 -#define reg_iop_spu_rw_event_cfg___addr___width 12 -#define reg_iop_spu_rw_event_cfg___src___lsb 12 -#define reg_iop_spu_rw_event_cfg___src___width 2 -#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14 -#define reg_iop_spu_rw_event_cfg___eq_en___width 1 -#define reg_iop_spu_rw_event_cfg___eq_en___bit 14 -#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15 -#define reg_iop_spu_rw_event_cfg___eq_inv___width 1 -#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15 -#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16 -#define reg_iop_spu_rw_event_cfg___gt_en___width 1 -#define reg_iop_spu_rw_event_cfg___gt_en___bit 16 -#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17 -#define reg_iop_spu_rw_event_cfg___gt_inv___width 1 -#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17 -#define reg_iop_spu_rw_event_cfg_offset 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_mask_offset 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_val_offset 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -#define reg_iop_spu_rw_event_ret___addr___lsb 0 -#define reg_iop_spu_rw_event_ret___addr___width 12 -#define reg_iop_spu_rw_event_ret_offset 192 - -/* Register r_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_trace___fsm___lsb 0 -#define reg_iop_spu_r_trace___fsm___width 1 -#define reg_iop_spu_r_trace___fsm___bit 0 -#define reg_iop_spu_r_trace___en___lsb 1 -#define reg_iop_spu_r_trace___en___width 1 -#define reg_iop_spu_r_trace___en___bit 1 -#define reg_iop_spu_r_trace___c_flag___lsb 2 -#define reg_iop_spu_r_trace___c_flag___width 1 -#define reg_iop_spu_r_trace___c_flag___bit 2 -#define reg_iop_spu_r_trace___v_flag___lsb 3 -#define reg_iop_spu_r_trace___v_flag___width 1 -#define reg_iop_spu_r_trace___v_flag___bit 3 -#define reg_iop_spu_r_trace___z_flag___lsb 4 -#define reg_iop_spu_r_trace___z_flag___width 1 -#define reg_iop_spu_r_trace___z_flag___bit 4 -#define reg_iop_spu_r_trace___n_flag___lsb 5 -#define reg_iop_spu_r_trace___n_flag___width 1 -#define reg_iop_spu_r_trace___n_flag___bit 5 -#define reg_iop_spu_r_trace___seq_addr___lsb 6 -#define reg_iop_spu_r_trace___seq_addr___width 12 -#define reg_iop_spu_r_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_trace___fsm_addr___width 12 -#define reg_iop_spu_r_trace_offset 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -#define reg_iop_spu_r_fsm_trace___fsm___lsb 0 -#define reg_iop_spu_r_fsm_trace___fsm___width 1 -#define reg_iop_spu_r_fsm_trace___fsm___bit 0 -#define reg_iop_spu_r_fsm_trace___en___lsb 1 -#define reg_iop_spu_r_fsm_trace___en___width 1 -#define reg_iop_spu_r_fsm_trace___en___bit 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2 -#define reg_iop_spu_r_fsm_trace___tmr_done___width 1 -#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2 -#define reg_iop_spu_r_fsm_trace___inp0___lsb 3 -#define reg_iop_spu_r_fsm_trace___inp0___width 1 -#define reg_iop_spu_r_fsm_trace___inp0___bit 3 -#define reg_iop_spu_r_fsm_trace___inp1___lsb 4 -#define reg_iop_spu_r_fsm_trace___inp1___width 1 -#define reg_iop_spu_r_fsm_trace___inp1___bit 4 -#define reg_iop_spu_r_fsm_trace___inp2___lsb 5 -#define reg_iop_spu_r_fsm_trace___inp2___width 1 -#define reg_iop_spu_r_fsm_trace___inp2___bit 5 -#define reg_iop_spu_r_fsm_trace___inp3___lsb 6 -#define reg_iop_spu_r_fsm_trace___inp3___width 1 -#define reg_iop_spu_r_fsm_trace___inp3___bit 6 -#define reg_iop_spu_r_fsm_trace___event0___lsb 7 -#define reg_iop_spu_r_fsm_trace___event0___width 1 -#define reg_iop_spu_r_fsm_trace___event0___bit 7 -#define reg_iop_spu_r_fsm_trace___event1___lsb 8 -#define reg_iop_spu_r_fsm_trace___event1___width 1 -#define reg_iop_spu_r_fsm_trace___event1___bit 8 -#define reg_iop_spu_r_fsm_trace___event2___lsb 9 -#define reg_iop_spu_r_fsm_trace___event2___width 1 -#define reg_iop_spu_r_fsm_trace___event2___bit 9 -#define reg_iop_spu_r_fsm_trace___event3___lsb 10 -#define reg_iop_spu_r_fsm_trace___event3___width 1 -#define reg_iop_spu_r_fsm_trace___event3___bit 10 -#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11 -#define reg_iop_spu_r_fsm_trace___gio_out___width 8 -#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20 -#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12 -#define reg_iop_spu_r_fsm_trace_offset 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -#define reg_iop_spu_rw_brp___addr___lsb 0 -#define reg_iop_spu_rw_brp___addr___width 12 -#define reg_iop_spu_rw_brp___fsm___lsb 12 -#define reg_iop_spu_rw_brp___fsm___width 1 -#define reg_iop_spu_rw_brp___fsm___bit 12 -#define reg_iop_spu_rw_brp___en___lsb 13 -#define reg_iop_spu_rw_brp___en___width 1 -#define reg_iop_spu_rw_brp___en___bit 13 -#define reg_iop_spu_rw_brp_offset 204 - - -/* Constants */ -#define regk_iop_spu_attn_hi 0x00000005 -#define regk_iop_spu_attn_lo 0x00000005 -#define regk_iop_spu_attn_r0 0x00000000 -#define regk_iop_spu_attn_r1 0x00000001 -#define regk_iop_spu_attn_r10 0x00000002 -#define regk_iop_spu_attn_r11 0x00000003 -#define regk_iop_spu_attn_r12 0x00000004 -#define regk_iop_spu_attn_r13 0x00000005 -#define regk_iop_spu_attn_r14 0x00000006 -#define regk_iop_spu_attn_r15 0x00000007 -#define regk_iop_spu_attn_r2 0x00000002 -#define regk_iop_spu_attn_r3 0x00000003 -#define regk_iop_spu_attn_r4 0x00000004 -#define regk_iop_spu_attn_r5 0x00000005 -#define regk_iop_spu_attn_r6 0x00000006 -#define regk_iop_spu_attn_r7 0x00000007 -#define regk_iop_spu_attn_r8 0x00000000 -#define regk_iop_spu_attn_r9 0x00000001 -#define regk_iop_spu_c 0x00000000 -#define regk_iop_spu_flag 0x00000002 -#define regk_iop_spu_gio_in 0x00000000 -#define regk_iop_spu_gio_out 0x00000005 -#define regk_iop_spu_gio_out0 0x00000008 -#define regk_iop_spu_gio_out1 0x00000009 -#define regk_iop_spu_gio_out2 0x0000000a -#define regk_iop_spu_gio_out3 0x0000000b -#define regk_iop_spu_gio_out4 0x0000000c -#define regk_iop_spu_gio_out5 0x0000000d -#define regk_iop_spu_gio_out6 0x0000000e -#define regk_iop_spu_gio_out7 0x0000000f -#define regk_iop_spu_n 0x00000003 -#define regk_iop_spu_no 0x00000000 -#define regk_iop_spu_r0 0x00000008 -#define regk_iop_spu_r1 0x00000009 -#define regk_iop_spu_r10 0x0000000a -#define regk_iop_spu_r11 0x0000000b -#define regk_iop_spu_r12 0x0000000c -#define regk_iop_spu_r13 0x0000000d -#define regk_iop_spu_r14 0x0000000e -#define regk_iop_spu_r15 0x0000000f -#define regk_iop_spu_r2 0x0000000a -#define regk_iop_spu_r3 0x0000000b -#define regk_iop_spu_r4 0x0000000c -#define regk_iop_spu_r5 0x0000000d -#define regk_iop_spu_r6 0x0000000e -#define regk_iop_spu_r7 0x0000000f -#define regk_iop_spu_r8 0x00000008 -#define regk_iop_spu_r9 0x00000009 -#define regk_iop_spu_reg_hi 0x00000002 -#define regk_iop_spu_reg_lo 0x00000002 -#define regk_iop_spu_rw_brp_default 0x00000000 -#define regk_iop_spu_rw_brp_size 0x00000004 -#define regk_iop_spu_rw_ctrl_default 0x00000000 -#define regk_iop_spu_rw_event_cfg_size 0x00000004 -#define regk_iop_spu_rw_event_mask_size 0x00000004 -#define regk_iop_spu_rw_event_val_size 0x00000004 -#define regk_iop_spu_rw_gio_out_default 0x00000000 -#define regk_iop_spu_rw_r_size 0x00000010 -#define regk_iop_spu_rw_reg_access_default 0x00000000 -#define regk_iop_spu_stat_in 0x00000002 -#define regk_iop_spu_statin_hi 0x00000004 -#define regk_iop_spu_statin_lo 0x00000004 -#define regk_iop_spu_trig 0x00000003 -#define regk_iop_spu_trigger 0x00000006 -#define regk_iop_spu_v 0x00000001 -#define regk_iop_spu_wsts_gioout_spec 0x00000001 -#define regk_iop_spu_xor 0x00000003 -#define regk_iop_spu_xor_bus0_r2_0 0x00000000 -#define regk_iop_spu_xor_bus0m_r2_0 0x00000002 -#define regk_iop_spu_xor_bus1_r3_0 0x00000001 -#define regk_iop_spu_xor_bus1m_r3_0 0x00000003 -#define regk_iop_spu_yes 0x00000001 -#define regk_iop_spu_z 0x00000002 -#endif /* __iop_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index 4f4c7340d39a..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,1053 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu0_owner_offset 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_spu1_owner_offset 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus0_mask_offset 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus1_mask_offset 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2 -#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2 -#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10 -#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14 -#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1 -#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18 -#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus0 0x00000000 -#define regk_iop_sw_cfg_bus0_rot16 0x00000004 -#define regk_iop_sw_cfg_bus0_rot24 0x00000006 -#define regk_iop_sw_cfg_bus0_rot8 0x00000002 -#define regk_iop_sw_cfg_bus1 0x00000001 -#define regk_iop_sw_cfg_bus1_rot16 0x00000005 -#define regk_iop_sw_cfg_bus1_rot24 0x00000007 -#define regk_iop_sw_cfg_bus1_rot8 0x00000003 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_dmc0 0x00000000 -#define regk_iop_sw_cfg_dmc1 0x00000001 -#define regk_iop_sw_cfg_gated_clk0 0x00000010 -#define regk_iop_sw_cfg_gated_clk1 0x00000011 -#define regk_iop_sw_cfg_gated_clk2 0x00000012 -#define regk_iop_sw_cfg_gated_clk3 0x00000013 -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in0 0x00000000 -#define regk_iop_sw_cfg_gio_in1 0x00000001 -#define regk_iop_sw_cfg_gio_in10 0x00000002 -#define regk_iop_sw_cfg_gio_in11 0x00000003 -#define regk_iop_sw_cfg_gio_in14 0x00000004 -#define regk_iop_sw_cfg_gio_in15 0x00000005 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in28 0x00000006 -#define regk_iop_sw_cfg_gio_in29 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003 -#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_par0 0x00000000 -#define regk_iop_sw_cfg_par1 0x00000001 -#define regk_iop_sw_cfg_pdp_out0 0x00000002 -#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000 -#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_pdp_out1 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003 -#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005 -#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002 -#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004 -#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out0 0x00000008 -#define regk_iop_sw_cfg_sdp_out1 0x00000009 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu0 0x00000002 -#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu0_g0 0x0000000e -#define regk_iop_sw_cfg_spu0_g1 0x0000000e -#define regk_iop_sw_cfg_spu0_g2 0x0000000e -#define regk_iop_sw_cfg_spu0_g3 0x0000000e -#define regk_iop_sw_cfg_spu0_g4 0x0000000e -#define regk_iop_sw_cfg_spu0_g5 0x0000000e -#define regk_iop_sw_cfg_spu0_g6 0x0000000e -#define regk_iop_sw_cfg_spu0_g7 0x0000000e -#define regk_iop_sw_cfg_spu0_gio0 0x00000000 -#define regk_iop_sw_cfg_spu0_gio1 0x00000001 -#define regk_iop_sw_cfg_spu0_gio2 0x00000000 -#define regk_iop_sw_cfg_spu0_gio5 0x00000005 -#define regk_iop_sw_cfg_spu0_gio6 0x00000006 -#define regk_iop_sw_cfg_spu0_gio7 0x00000007 -#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu0_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout2 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout3 0x00000002 -#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout4 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout5 0x00000004 -#define regk_iop_sw_cfg_spu0_gioout6 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout7 0x00000006 -#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e -#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e -#define regk_iop_sw_cfg_spu1 0x00000003 -#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006 -#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007 -#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007 -#define regk_iop_sw_cfg_spu1_g0 0x0000000f -#define regk_iop_sw_cfg_spu1_g1 0x0000000f -#define regk_iop_sw_cfg_spu1_g2 0x0000000f -#define regk_iop_sw_cfg_spu1_g3 0x0000000f -#define regk_iop_sw_cfg_spu1_g4 0x0000000f -#define regk_iop_sw_cfg_spu1_g5 0x0000000f -#define regk_iop_sw_cfg_spu1_g6 0x0000000f -#define regk_iop_sw_cfg_spu1_g7 0x0000000f -#define regk_iop_sw_cfg_spu1_gio0 0x00000002 -#define regk_iop_sw_cfg_spu1_gio1 0x00000003 -#define regk_iop_sw_cfg_spu1_gio2 0x00000002 -#define regk_iop_sw_cfg_spu1_gio5 0x00000005 -#define regk_iop_sw_cfg_spu1_gio6 0x00000006 -#define regk_iop_sw_cfg_spu1_gio7 0x00000007 -#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout0 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout1 0x00000001 -#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout2 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout3 0x00000003 -#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout4 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout5 0x00000005 -#define regk_iop_sw_cfg_spu1_gioout6 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout7 0x00000007 -#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f -#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004 -#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005 -#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005 -#define regk_iop_sw_cfg_timer_grp2 0x00000000 -#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c -#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006 -#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006 -#define regk_iop_sw_cfg_timer_grp3 0x00000000 -#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d -#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007 -#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000000 -#define regk_iop_sw_cfg_trig2_1 0x00000000 -#define regk_iop_sw_cfg_trig2_2 0x00000000 -#define regk_iop_sw_cfg_trig2_3 0x00000000 -#define regk_iop_sw_cfg_trig3_0 0x00000000 -#define regk_iop_sw_cfg_trig3_1 0x00000000 -#define regk_iop_sw_cfg_trig3_2 0x00000000 -#define regk_iop_sw_cfg_trig3_3 0x00000000 -#define regk_iop_sw_cfg_trig4_0 0x00000001 -#define regk_iop_sw_cfg_trig4_1 0x00000001 -#define regk_iop_sw_cfg_trig4_2 0x00000001 -#define regk_iop_sw_cfg_trig4_3 0x00000001 -#define regk_iop_sw_cfg_trig5_0 0x00000001 -#define regk_iop_sw_cfg_trig5_1 0x00000001 -#define regk_iop_sw_cfg_trig5_2 0x00000001 -#define regk_iop_sw_cfg_trig5_3 0x00000001 -#define regk_iop_sw_cfg_trig6_0 0x00000001 -#define regk_iop_sw_cfg_trig6_1 0x00000001 -#define regk_iop_sw_cfg_trig6_2 0x00000001 -#define regk_iop_sw_cfg_trig6_3 0x00000001 -#define regk_iop_sw_cfg_trig7_0 0x00000001 -#define regk_iop_sw_cfg_trig7_1 0x00000001 -#define regk_iop_sw_cfg_trig7_2 0x00000001 -#define regk_iop_sw_cfg_trig7_3 0x00000001 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index ef04a57a0680..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,1759 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_cpu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr2_mask_offset 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr2_offset 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr2_offset 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr2_offset 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31 -#define reg_iop_sw_cpu_rw_intr3_mask_offset 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr3_offset 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_intr3_offset 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31 -#define reg_iop_sw_cpu_r_masked_intr3_offset 144 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index 22292069e4fd..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1777 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_mpu_r_mc_stat_offset 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus0_in_offset 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus1_in_offset 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp0_offset 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp1_offset 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp2_offset 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_intr_grp3_offset 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu0 0x00000002 -#define regk_iop_sw_mpu_spu1 0x00000003 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 82729218621c..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,692 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7 -#define reg_iop_sw_spu_r_mc_stat_offset 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus0_in_offset 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus1_in_offset 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23 -#define reg_iop_sw_spu_r_hw_intr_offset 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31 -#define reg_iop_sw_spu_r_mpu_intr_offset 164 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h deleted file mode 100644 index 4f1cf73d86cd..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_timer_grp_defs_asm_h -#define __iop_timer_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_cfg___clk_src___width 1 -#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0 -#define reg_iop_timer_grp_rw_cfg___trig___lsb 1 -#define reg_iop_timer_grp_rw_cfg___trig___width 2 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3 -#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8 -#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11 -#define reg_iop_timer_grp_rw_cfg___clk_div___width 8 -#define reg_iop_timer_grp_rw_cfg_offset 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0 -#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1 -#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30 -#define reg_iop_timer_grp_rw_half_period_offset 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_half_period_len_offset 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0 -#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3 -#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5 -#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8 -#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11 -#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1 -#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17 -#define reg_iop_timer_grp_rw_tmr_cfg_offset 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0 -#define reg_iop_timer_grp_rw_tmr_len___val___width 16 -#define reg_iop_timer_grp_rw_tmr_len_offset 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_cmd___rst___lsb 0 -#define reg_iop_timer_grp_rw_cmd___rst___width 4 -#define reg_iop_timer_grp_rw_cmd___en___lsb 4 -#define reg_iop_timer_grp_rw_cmd___en___width 4 -#define reg_iop_timer_grp_rw_cmd___dis___lsb 8 -#define reg_iop_timer_grp_rw_cmd___dis___width 4 -#define reg_iop_timer_grp_rw_cmd___strb___lsb 12 -#define reg_iop_timer_grp_rw_cmd___strb___width 4 -#define reg_iop_timer_grp_rw_cmd_offset 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_rs_tmr_cnt_offset 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0 -#define reg_iop_timer_grp_r_tmr_cnt___val___width 16 -#define reg_iop_timer_grp_r_tmr_cnt_offset 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1 -#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3 -#define reg_iop_timer_grp_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1 -#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3 -#define reg_iop_timer_grp_rw_ack_intr_offset 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_intr_offset 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0 -#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0 -#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2 -#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2 -#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3 -#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1 -#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3 -#define reg_iop_timer_grp_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_iop_timer_grp_clk200 0x00000000 -#define regk_iop_timer_grp_clk_gen 0x00000002 -#define regk_iop_timer_grp_complete 0x00000002 -#define regk_iop_timer_grp_div_clk200 0x00000001 -#define regk_iop_timer_grp_div_clk_gen 0x00000003 -#define regk_iop_timer_grp_ext 0x00000001 -#define regk_iop_timer_grp_hi 0x00000000 -#define regk_iop_timer_grp_long_period 0x00000001 -#define regk_iop_timer_grp_neg 0x00000002 -#define regk_iop_timer_grp_no 0x00000000 -#define regk_iop_timer_grp_once 0x00000003 -#define regk_iop_timer_grp_pause 0x00000001 -#define regk_iop_timer_grp_pos 0x00000001 -#define regk_iop_timer_grp_pos_neg 0x00000003 -#define regk_iop_timer_grp_pulse 0x00000000 -#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004 -#define regk_iop_timer_grp_rw_cfg_default 0x00000002 -#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000 -#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900 -#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200 -#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00 -#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004 -#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000 -#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004 -#define regk_iop_timer_grp_short_period 0x00000000 -#define regk_iop_timer_grp_stop 0x00000000 -#define regk_iop_timer_grp_tmr 0x00000004 -#define regk_iop_timer_grp_toggle 0x00000001 -#define regk_iop_timer_grp_yes 0x00000001 -#endif /* __iop_timer_grp_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h deleted file mode 100644 index 7bc882c62952..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_trigger_grp_defs_asm_h -#define __iop_trigger_grp_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cfg___action___lsb 0 -#define reg_iop_trigger_grp_rw_cfg___action___width 2 -#define reg_iop_trigger_grp_rw_cfg___once___lsb 2 -#define reg_iop_trigger_grp_rw_cfg___once___width 1 -#define reg_iop_trigger_grp_rw_cfg___once___bit 2 -#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3 -#define reg_iop_trigger_grp_rw_cfg___trig___width 3 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1 -#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7 -#define reg_iop_trigger_grp_rw_cfg_offset 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0 -#define reg_iop_trigger_grp_rw_cmd___dis___width 4 -#define reg_iop_trigger_grp_rw_cmd___en___lsb 4 -#define reg_iop_trigger_grp_rw_cmd___en___width 4 -#define reg_iop_trigger_grp_rw_cmd_offset 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1 -#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3 -#define reg_iop_trigger_grp_rw_intr_mask_offset 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1 -#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3 -#define reg_iop_trigger_grp_rw_ack_intr_offset 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_intr_offset 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0 -#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0 -#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2 -#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2 -#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3 -#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1 -#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3 -#define reg_iop_trigger_grp_r_masked_intr_offset 32 - - -/* Constants */ -#define regk_iop_trigger_grp_fall 0x00000002 -#define regk_iop_trigger_grp_fall_lo 0x00000006 -#define regk_iop_trigger_grp_no 0x00000000 -#define regk_iop_trigger_grp_off 0x00000000 -#define regk_iop_trigger_grp_pulse 0x00000000 -#define regk_iop_trigger_grp_rise 0x00000001 -#define regk_iop_trigger_grp_rise_fall 0x00000003 -#define regk_iop_trigger_grp_rise_fall_hi 0x00000007 -#define regk_iop_trigger_grp_rise_fall_lo 0x00000004 -#define regk_iop_trigger_grp_rise_hi 0x00000005 -#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0 -#define regk_iop_trigger_grp_rw_cfg_size 0x00000004 -#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000 -#define regk_iop_trigger_grp_toggle 0x00000003 -#define regk_iop_trigger_grp_yes 0x00000001 -#endif /* __iop_trigger_grp_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index 2e239957e34a..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v1_0 0x00000001 -#endif /* __iop_version_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h deleted file mode 100644 index 8690034d9bec..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_crc_par_defs_h -#define __iop_crc_par_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_crc_par.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r - * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_crc_par */ - -/* Register rw_cfg, scope iop_crc_par, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int crc_out : 1; - unsigned int rev_out : 1; - unsigned int inv_out : 1; - unsigned int trig : 2; - unsigned int poly : 3; - unsigned int dummy1 : 23; -} reg_iop_crc_par_rw_cfg; -#define REG_RD_ADDR_iop_crc_par_rw_cfg 0 -#define REG_WR_ADDR_iop_crc_par_rw_cfg 0 - -/* Register rw_init_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_init_crc; -#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4 -#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4 - -/* Register rw_correct_crc, scope iop_crc_par, type rw */ -typedef unsigned int reg_iop_crc_par_rw_correct_crc; -#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8 -#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8 - -/* Register rw_ctrl, scope iop_crc_par, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_ctrl; -#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12 -#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12 - -/* Register rw_set_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int tr_dif : 1; - unsigned int dummy1 : 31; -} reg_iop_crc_par_rw_set_last; -#define REG_RD_ADDR_iop_crc_par_rw_set_last 16 -#define REG_WR_ADDR_iop_crc_par_rw_set_last 16 - -/* Register rw_wr1byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20 - -/* Register rw_wr2byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24 - -/* Register rw_wr3byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28 - -/* Register rw_wr4byte, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32 - -/* Register rw_wr1byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_crc_par_rw_wr1byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36 -#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36 - -/* Register rw_wr2byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_crc_par_rw_wr2byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40 -#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40 - -/* Register rw_wr3byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_crc_par_rw_wr3byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44 -#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44 - -/* Register rw_wr4byte_last, scope iop_crc_par, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_crc_par_rw_wr4byte_last; -#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48 -#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48 - -/* Register r_stat, scope iop_crc_par, type r */ -typedef struct { - unsigned int err : 1; - unsigned int busy : 1; - unsigned int dummy1 : 30; -} reg_iop_crc_par_r_stat; -#define REG_RD_ADDR_iop_crc_par_r_stat 52 - -/* Register r_sh_reg, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_sh_reg; -#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56 - -/* Register r_crc, scope iop_crc_par, type r */ -typedef unsigned int reg_iop_crc_par_r_crc; -#define REG_RD_ADDR_iop_crc_par_r_crc 60 - -/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_crc_par_rw_strb_rec_dif_in; -#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 -#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64 - - -/* Constants */ -enum { - regk_iop_crc_par_calc = 0x00000001, - regk_iop_crc_par_ccitt = 0x00000002, - regk_iop_crc_par_check = 0x00000000, - regk_iop_crc_par_crc16 = 0x00000001, - regk_iop_crc_par_crc32 = 0x00000000, - regk_iop_crc_par_crc5 = 0x00000003, - regk_iop_crc_par_crc5_11 = 0x00000004, - regk_iop_crc_par_dif_in = 0x00000002, - regk_iop_crc_par_hi = 0x00000000, - regk_iop_crc_par_neg = 0x00000002, - regk_iop_crc_par_no = 0x00000000, - regk_iop_crc_par_pos = 0x00000001, - regk_iop_crc_par_pos_neg = 0x00000003, - regk_iop_crc_par_rw_cfg_default = 0x00000000, - regk_iop_crc_par_rw_ctrl_default = 0x00000000, - regk_iop_crc_par_yes = 0x00000001 -}; -#endif /* __iop_crc_par_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h deleted file mode 100644 index 3dd4e870a3a5..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h +++ /dev/null @@ -1,326 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_dmc_in_defs_h -#define __iop_dmc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_in.r - * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r - * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_in */ - -/* Register rw_cfg, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int sth_intr : 3; - unsigned int last_dis_dif : 1; - unsigned int dummy1 : 28; -} reg_iop_dmc_in_rw_cfg; -#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int stream_clr : 1; - unsigned int dummy1 : 29; -} reg_iop_dmc_in_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_in_r_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_in_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12 - -/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16 - -/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20 - -/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int eop : 1; - unsigned int wait : 1; - unsigned int keep_md : 1; - unsigned int size : 3; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_stream_ctrl; -#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24 -#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24 - -/* Register r_stream_stat, scope iop_dmc_in, type r */ -typedef struct { - unsigned int sth : 7; - unsigned int dummy1 : 9; - unsigned int full : 1; - unsigned int last_pkt : 1; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int dummy2 : 9; -} reg_iop_dmc_in_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28 - -/* Register r_data_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_data_descr; -#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32 - -/* Register r_ctxt_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_in_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36 - -/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40 - -/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */ -typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44 - -/* Register r_group_descr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_in_r_group_descr; -#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56 - -/* Register rw_data_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60 -#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60 - -/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_in_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */ -typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 -#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72 - -/* Register rw_group_descr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_in_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84 -#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84 - -/* Register rw_intr_mask, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88 -#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88 - -/* Register rw_ack_intr, scope iop_dmc_in, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92 -#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92 - -/* Register r_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_intr; -#define REG_RD_ADDR_iop_dmc_in_r_intr 96 - -/* Register r_masked_intr, scope iop_dmc_in, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int sth : 1; - unsigned int full : 1; - unsigned int dummy1 : 26; -} reg_iop_dmc_in_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100 - - -/* Constants */ -enum { - regk_iop_dmc_in_ack_pkt = 0x00000100, - regk_iop_dmc_in_array = 0x00000008, - regk_iop_dmc_in_burst = 0x00000020, - regk_iop_dmc_in_copy_next = 0x00000010, - regk_iop_dmc_in_copy_up = 0x00000020, - regk_iop_dmc_in_dis_c = 0x00000010, - regk_iop_dmc_in_dis_g = 0x00000020, - regk_iop_dmc_in_lim1 = 0x00000000, - regk_iop_dmc_in_lim16 = 0x00000004, - regk_iop_dmc_in_lim2 = 0x00000001, - regk_iop_dmc_in_lim32 = 0x00000005, - regk_iop_dmc_in_lim4 = 0x00000002, - regk_iop_dmc_in_lim64 = 0x00000006, - regk_iop_dmc_in_lim8 = 0x00000003, - regk_iop_dmc_in_load_c = 0x00000200, - regk_iop_dmc_in_load_c_n = 0x00000280, - regk_iop_dmc_in_load_c_next = 0x00000240, - regk_iop_dmc_in_load_d = 0x00000140, - regk_iop_dmc_in_load_g = 0x00000300, - regk_iop_dmc_in_load_g_down = 0x000003c0, - regk_iop_dmc_in_load_g_next = 0x00000340, - regk_iop_dmc_in_load_g_up = 0x00000380, - regk_iop_dmc_in_next_en = 0x00000010, - regk_iop_dmc_in_next_pkt = 0x00000010, - regk_iop_dmc_in_no = 0x00000000, - regk_iop_dmc_in_restore = 0x00000020, - regk_iop_dmc_in_rw_cfg_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_in_rw_data_descr_default = 0x00000000, - regk_iop_dmc_in_rw_group_descr_default = 0x00000000, - regk_iop_dmc_in_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000, - regk_iop_dmc_in_save_down = 0x00000020, - regk_iop_dmc_in_save_up = 0x00000020, - regk_iop_dmc_in_set_reg = 0x00000050, - regk_iop_dmc_in_set_w_size1 = 0x00000190, - regk_iop_dmc_in_set_w_size2 = 0x000001a0, - regk_iop_dmc_in_set_w_size4 = 0x000001c0, - regk_iop_dmc_in_store_c = 0x00000002, - regk_iop_dmc_in_store_descr = 0x00000000, - regk_iop_dmc_in_store_g = 0x00000004, - regk_iop_dmc_in_store_md = 0x00000001, - regk_iop_dmc_in_update_down = 0x00000020, - regk_iop_dmc_in_yes = 0x00000001 -}; -#endif /* __iop_dmc_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h deleted file mode 100644 index 7ed17bc553c3..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_dmc_out_defs_h -#define __iop_dmc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_dmc_out.r - * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r - * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_dmc_out */ - -/* Register rw_cfg, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int trf_lim : 16; - unsigned int last_at_trf_lim : 1; - unsigned int dth_intr : 3; - unsigned int dummy1 : 12; -} reg_iop_dmc_out_rw_cfg; -#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dif_dis : 1; - unsigned int dummy1 : 30; -} reg_iop_dmc_out_rw_ctrl; -#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4 - -/* Register r_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dif_en : 1; - unsigned int dummy1 : 31; -} reg_iop_dmc_out_r_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stat 8 - -/* Register rw_stream_cmd, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int cmd : 10; - unsigned int dummy1 : 6; - unsigned int n : 8; - unsigned int dummy2 : 8; -} reg_iop_dmc_out_rw_stream_cmd; -#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12 -#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12 - -/* Register rs_stream_data, scope iop_dmc_out, type rs */ -typedef unsigned int reg_iop_dmc_out_rs_stream_data; -#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16 - -/* Register r_stream_data, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_stream_data; -#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20 - -/* Register r_stream_stat, scope iop_dmc_out, type r */ -typedef struct { - unsigned int dth : 7; - unsigned int dummy1 : 9; - unsigned int dv : 1; - unsigned int all_avail : 1; - unsigned int last : 1; - unsigned int size : 3; - unsigned int data_md_valid : 1; - unsigned int ctxt_md_valid : 1; - unsigned int group_md_valid : 1; - unsigned int stream_busy : 1; - unsigned int cmd_rdy : 1; - unsigned int cmd_rq : 1; - unsigned int dummy2 : 4; -} reg_iop_dmc_out_r_stream_stat; -#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24 - -/* Register r_data_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_data_descr; -#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28 - -/* Register r_ctxt_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md0 : 16; -} reg_iop_dmc_out_r_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32 - -/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36 - -/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */ -typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40 - -/* Register r_group_descr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int ctrl : 8; - unsigned int stat : 8; - unsigned int md : 16; -} reg_iop_dmc_out_r_group_descr; -#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52 - -/* Register rw_data_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_data_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56 -#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56 - -/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md0 : 16; -} reg_iop_dmc_out_rw_ctxt_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60 - -/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64 - -/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */ -typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2; -#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 -#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68 - -/* Register rw_group_descr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int dummy1 : 16; - unsigned int md : 16; -} reg_iop_dmc_out_rw_group_descr; -#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80 -#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80 - -/* Register rw_intr_mask, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_intr_mask; -#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84 -#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84 - -/* Register rw_ack_intr, scope iop_dmc_out, type rw */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_rw_ack_intr; -#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88 -#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88 - -/* Register r_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_intr; -#define REG_RD_ADDR_iop_dmc_out_r_intr 92 - -/* Register r_masked_intr, scope iop_dmc_out, type r */ -typedef struct { - unsigned int data_md : 1; - unsigned int ctxt_md : 1; - unsigned int group_md : 1; - unsigned int cmd_rdy : 1; - unsigned int dth : 1; - unsigned int dv : 1; - unsigned int last_data : 1; - unsigned int trf_lim : 1; - unsigned int cmd_rq : 1; - unsigned int dummy1 : 23; -} reg_iop_dmc_out_r_masked_intr; -#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96 - - -/* Constants */ -enum { - regk_iop_dmc_out_ack_pkt = 0x00000100, - regk_iop_dmc_out_array = 0x00000008, - regk_iop_dmc_out_burst = 0x00000020, - regk_iop_dmc_out_copy_next = 0x00000010, - regk_iop_dmc_out_copy_up = 0x00000020, - regk_iop_dmc_out_dis_c = 0x00000010, - regk_iop_dmc_out_dis_g = 0x00000020, - regk_iop_dmc_out_lim1 = 0x00000000, - regk_iop_dmc_out_lim16 = 0x00000004, - regk_iop_dmc_out_lim2 = 0x00000001, - regk_iop_dmc_out_lim32 = 0x00000005, - regk_iop_dmc_out_lim4 = 0x00000002, - regk_iop_dmc_out_lim64 = 0x00000006, - regk_iop_dmc_out_lim8 = 0x00000003, - regk_iop_dmc_out_load_c = 0x00000200, - regk_iop_dmc_out_load_c_n = 0x00000280, - regk_iop_dmc_out_load_c_next = 0x00000240, - regk_iop_dmc_out_load_d = 0x00000140, - regk_iop_dmc_out_load_g = 0x00000300, - regk_iop_dmc_out_load_g_down = 0x000003c0, - regk_iop_dmc_out_load_g_next = 0x00000340, - regk_iop_dmc_out_load_g_up = 0x00000380, - regk_iop_dmc_out_next_en = 0x00000010, - regk_iop_dmc_out_next_pkt = 0x00000010, - regk_iop_dmc_out_no = 0x00000000, - regk_iop_dmc_out_restore = 0x00000020, - regk_iop_dmc_out_rw_cfg_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000, - regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000, - regk_iop_dmc_out_rw_data_descr_default = 0x00000000, - regk_iop_dmc_out_rw_group_descr_default = 0x00000000, - regk_iop_dmc_out_rw_intr_mask_default = 0x00000000, - regk_iop_dmc_out_save_down = 0x00000020, - regk_iop_dmc_out_save_up = 0x00000020, - regk_iop_dmc_out_set_reg = 0x00000050, - regk_iop_dmc_out_set_w_size1 = 0x00000190, - regk_iop_dmc_out_set_w_size2 = 0x000001a0, - regk_iop_dmc_out_set_w_size4 = 0x000001c0, - regk_iop_dmc_out_store_c = 0x00000002, - regk_iop_dmc_out_store_descr = 0x00000000, - regk_iop_dmc_out_store_g = 0x00000004, - regk_iop_dmc_out_store_md = 0x00000001, - regk_iop_dmc_out_update_down = 0x00000020, - regk_iop_dmc_out_yes = 0x00000001 -}; -#endif /* __iop_dmc_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h deleted file mode 100644 index dc14868680e6..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h +++ /dev/null @@ -1,256 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_in_defs_h -#define __iop_fifo_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in.r - * id: - * last modfied: Mon Apr 11 16:10:07 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r - * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in */ - -/* Register rw_cfg, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int avail_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int dummy1 : 22; -} reg_iop_fifo_in_rw_cfg; -#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_in, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_r_stat; -#define REG_RD_ADDR_iop_fifo_in_r_stat 8 - -/* Register rs_rd1byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_rs_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12 - -/* Register r_rd1byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_in_r_rd1byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16 - -/* Register rs_rd2byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_rs_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20 - -/* Register r_rd2byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_in_r_rd2byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24 - -/* Register rs_rd3byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_rs_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28 - -/* Register r_rd3byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_in_r_rd3byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32 - -/* Register rs_rd4byte, scope iop_fifo_in, type rs */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_rs_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36 - -/* Register r_rd4byte, scope iop_fifo_in, type r */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_in_r_rd4byte; -#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40 - -/* Register rw_set_last, scope iop_fifo_in, type rw */ -typedef unsigned int reg_iop_fifo_in_rw_set_last; -#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44 - -/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48 -#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48 - -/* Register rw_intr_mask, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52 -#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52 - -/* Register rw_ack_intr, scope iop_fifo_in, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56 -#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56 - -/* Register r_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_intr; -#define REG_RD_ADDR_iop_fifo_in_r_intr 60 - -/* Register r_masked_intr, scope iop_fifo_in, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64 - - -/* Constants */ -enum { - regk_iop_fifo_in_dif_in = 0x00000002, - regk_iop_fifo_in_hi = 0x00000000, - regk_iop_fifo_in_neg = 0x00000002, - regk_iop_fifo_in_no = 0x00000000, - regk_iop_fifo_in_order16 = 0x00000001, - regk_iop_fifo_in_order24 = 0x00000002, - regk_iop_fifo_in_order32 = 0x00000003, - regk_iop_fifo_in_order8 = 0x00000000, - regk_iop_fifo_in_pos = 0x00000001, - regk_iop_fifo_in_pos_neg = 0x00000003, - regk_iop_fifo_in_rw_cfg_default = 0x00000024, - regk_iop_fifo_in_rw_ctrl_default = 0x00000000, - regk_iop_fifo_in_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_rw_set_last_default = 0x00000000, - regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000, - regk_iop_fifo_in_size16 = 0x00000002, - regk_iop_fifo_in_size24 = 0x00000001, - regk_iop_fifo_in_size32 = 0x00000000, - regk_iop_fifo_in_size8 = 0x00000003, - regk_iop_fifo_in_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h deleted file mode 100644 index ee7dc07a7862..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_in_extra_defs_h -#define __iop_fifo_in_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: - * last modfied: Mon Apr 11 16:10:08 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r - * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_in_extra */ - -/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */ -typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0 - -/* Register r_stat, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 18; -} reg_iop_fifo_in_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4 - -/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int last : 2; - unsigned int dummy1 : 30; -} reg_iop_fifo_in_extra_rw_strb_dif_in; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8 - -/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12 - -/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16 -#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16 - -/* Register r_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20 - -/* Register r_masked_intr, scope iop_fifo_in_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int avail : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_in_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24 - - -/* Constants */ -enum { - regk_iop_fifo_in_extra_fifo_in = 0x00000002, - regk_iop_fifo_in_extra_no = 0x00000000, - regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_in_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_in_extra_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h deleted file mode 100644 index ee8194fcfa82..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_out_defs_h -#define __iop_fifo_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out.r - * id: - * last modfied: Mon Apr 11 16:10:09 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r - * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out */ - -/* Register rw_cfg, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int free_lim : 3; - unsigned int byte_order : 2; - unsigned int trig : 2; - unsigned int last_dis_dif_in : 1; - unsigned int mode : 2; - unsigned int delay_out_last : 1; - unsigned int last_dis_dif_out : 1; - unsigned int dummy1 : 20; -} reg_iop_fifo_out_rw_cfg; -#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0 -#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int dummy1 : 30; -} reg_iop_fifo_out_rw_ctrl; -#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4 - -/* Register r_stat, scope iop_fifo_out, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_r_stat; -#define REG_RD_ADDR_iop_fifo_out_r_stat 8 - -/* Register rw_wr1byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12 - -/* Register rw_wr2byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16 - -/* Register rw_wr3byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20 - -/* Register rw_wr4byte, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24 - -/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_iop_fifo_out_rw_wr1byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28 -#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28 - -/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_iop_fifo_out_rw_wr2byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32 -#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32 - -/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 24; - unsigned int dummy1 : 8; -} reg_iop_fifo_out_rw_wr3byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36 -#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36 - -/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int data : 32; -} reg_iop_fifo_out_rw_wr4byte_last; -#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40 -#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40 - -/* Register rw_set_last, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_set_last; -#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44 -#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44 - -/* Register rs_rd_data, scope iop_fifo_out, type rs */ -typedef unsigned int reg_iop_fifo_out_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48 - -/* Register r_rd_data, scope iop_fifo_out, type r */ -typedef unsigned int reg_iop_fifo_out_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52 - -/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */ -typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56 -#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56 - -/* Register rw_intr_mask, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60 -#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60 - -/* Register rw_ack_intr, scope iop_fifo_out, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64 -#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64 - -/* Register r_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_intr; -#define REG_RD_ADDR_iop_fifo_out_r_intr 68 - -/* Register r_masked_intr, scope iop_fifo_out, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72 - - -/* Constants */ -enum { - regk_iop_fifo_out_hi = 0x00000000, - regk_iop_fifo_out_neg = 0x00000002, - regk_iop_fifo_out_no = 0x00000000, - regk_iop_fifo_out_order16 = 0x00000001, - regk_iop_fifo_out_order24 = 0x00000002, - regk_iop_fifo_out_order32 = 0x00000003, - regk_iop_fifo_out_order8 = 0x00000000, - regk_iop_fifo_out_pos = 0x00000001, - regk_iop_fifo_out_pos_neg = 0x00000003, - regk_iop_fifo_out_rw_cfg_default = 0x00000024, - regk_iop_fifo_out_rw_ctrl_default = 0x00000000, - regk_iop_fifo_out_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_rw_set_last_default = 0x00000000, - regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_default = 0x00000000, - regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000, - regk_iop_fifo_out_size16 = 0x00000002, - regk_iop_fifo_out_size24 = 0x00000001, - regk_iop_fifo_out_size32 = 0x00000000, - regk_iop_fifo_out_size8 = 0x00000003, - regk_iop_fifo_out_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h deleted file mode 100644 index b9721649f6fd..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_fifo_out_extra_defs_h -#define __iop_fifo_out_extra_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: - * last modfied: Mon Apr 11 16:10:10 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r - * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_fifo_out_extra */ - -/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */ -typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0 - -/* Register r_rd_data, scope iop_fifo_out_extra, type r */ -typedef unsigned int reg_iop_fifo_out_extra_r_rd_data; -#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4 - -/* Register r_stat, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int avail_bytes : 4; - unsigned int last : 8; - unsigned int dif_in_en : 1; - unsigned int dif_out_en : 1; - unsigned int zero_data_last : 1; - unsigned int dummy1 : 17; -} reg_iop_fifo_out_extra_r_stat; -#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8 - -/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */ -typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12 - -/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_intr_mask; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16 - -/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_rw_ack_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20 -#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20 - -/* Register r_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24 - -/* Register r_masked_intr, scope iop_fifo_out_extra, type r */ -typedef struct { - unsigned int urun : 1; - unsigned int last_data : 1; - unsigned int dav : 1; - unsigned int free : 1; - unsigned int orun : 1; - unsigned int dummy1 : 27; -} reg_iop_fifo_out_extra_r_masked_intr; -#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28 - - -/* Constants */ -enum { - regk_iop_fifo_out_extra_no = 0x00000000, - regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000, - regk_iop_fifo_out_extra_yes = 0x00000001 -}; -#endif /* __iop_fifo_out_extra_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h deleted file mode 100644 index 28e1c5903677..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h +++ /dev/null @@ -1,191 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_mpu_defs_h -#define __iop_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_mpu.r - * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r - * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_mpu */ - -#define STRIDE_iop_mpu_rw_r 4 -/* Register rw_r, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_r; -#define REG_RD_ADDR_iop_mpu_rw_r 0 -#define REG_WR_ADDR_iop_mpu_rw_r 0 - -/* Register rw_ctrl, scope iop_mpu, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_iop_mpu_rw_ctrl; -#define REG_RD_ADDR_iop_mpu_rw_ctrl 128 -#define REG_WR_ADDR_iop_mpu_rw_ctrl 128 - -/* Register r_pc, scope iop_mpu, type r */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_r_pc; -#define REG_RD_ADDR_iop_mpu_r_pc 132 - -/* Register r_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int intr_vect : 16; - unsigned int dummy1 : 14; -} reg_iop_mpu_r_stat; -#define REG_RD_ADDR_iop_mpu_r_stat 136 - -/* Register rw_instr, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_instr; -#define REG_RD_ADDR_iop_mpu_rw_instr 140 -#define REG_WR_ADDR_iop_mpu_rw_instr 140 - -/* Register rw_immediate, scope iop_mpu, type rw */ -typedef unsigned int reg_iop_mpu_rw_immediate; -#define REG_RD_ADDR_iop_mpu_rw_immediate 144 -#define REG_WR_ADDR_iop_mpu_rw_immediate 144 - -/* Register r_trace, scope iop_mpu, type r */ -typedef struct { - unsigned int intr_vect : 16; - unsigned int pc : 12; - unsigned int en : 1; - unsigned int instr_reg_busy : 1; - unsigned int intr_busy : 1; - unsigned int dummy1 : 1; -} reg_iop_mpu_r_trace; -#define REG_RD_ADDR_iop_mpu_r_trace 148 - -/* Register r_wr_stat, scope iop_mpu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_mpu_r_wr_stat; -#define REG_RD_ADDR_iop_mpu_r_wr_stat 152 - -#define STRIDE_iop_mpu_rw_thread 4 -/* Register rw_thread, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_thread; -#define REG_RD_ADDR_iop_mpu_rw_thread 156 -#define REG_WR_ADDR_iop_mpu_rw_thread 156 - -#define STRIDE_iop_mpu_rw_intr 4 -/* Register rw_intr, scope iop_mpu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_mpu_rw_intr; -#define REG_RD_ADDR_iop_mpu_rw_intr 196 -#define REG_WR_ADDR_iop_mpu_rw_intr 196 - - -/* Constants */ -enum { - regk_iop_mpu_no = 0x00000000, - regk_iop_mpu_r_pc_default = 0x00000000, - regk_iop_mpu_rw_ctrl_default = 0x00000000, - regk_iop_mpu_rw_intr_size = 0x00000010, - regk_iop_mpu_rw_r_size = 0x00000010, - regk_iop_mpu_rw_thread_default = 0x00000000, - regk_iop_mpu_rw_thread_size = 0x00000004, - regk_iop_mpu_yes = 0x00000001 -}; -#endif /* __iop_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h deleted file mode 100644 index 41f5178a65b8..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h +++ /dev/null @@ -1,765 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* ************************************************************************* */ -/* This file is autogenerated by IOPASM Version 1.2 */ -/* DO NOT EDIT THIS FILE - All changes will be lost! */ -/* ************************************************************************* */ - - - -#ifndef __IOP_MPU_MACROS_H__ -#define __IOP_MPU_MACROS_H__ - - -/* ************************************************************************* */ -/* REGISTER DEFINITIONS */ -/* ************************************************************************* */ -#define MPU_R0 (0x0) -#define MPU_R1 (0x1) -#define MPU_R2 (0x2) -#define MPU_R3 (0x3) -#define MPU_R4 (0x4) -#define MPU_R5 (0x5) -#define MPU_R6 (0x6) -#define MPU_R7 (0x7) -#define MPU_R8 (0x8) -#define MPU_R9 (0x9) -#define MPU_R10 (0xa) -#define MPU_R11 (0xb) -#define MPU_R12 (0xc) -#define MPU_R13 (0xd) -#define MPU_R14 (0xe) -#define MPU_R15 (0xf) -#define MPU_PC (0x2) -#define MPU_WSTS (0x3) -#define MPU_JADDR (0x4) -#define MPU_IRP (0x5) -#define MPU_SRP (0x6) -#define MPU_T0 (0x8) -#define MPU_T1 (0x9) -#define MPU_T2 (0xa) -#define MPU_T3 (0xb) -#define MPU_I0 (0x10) -#define MPU_I1 (0x11) -#define MPU_I2 (0x12) -#define MPU_I3 (0x13) -#define MPU_I4 (0x14) -#define MPU_I5 (0x15) -#define MPU_I6 (0x16) -#define MPU_I7 (0x17) -#define MPU_I8 (0x18) -#define MPU_I9 (0x19) -#define MPU_I10 (0x1a) -#define MPU_I11 (0x1b) -#define MPU_I12 (0x1c) -#define MPU_I13 (0x1d) -#define MPU_I14 (0x1e) -#define MPU_I15 (0x1f) -#define MPU_P2 (0x2) -#define MPU_P3 (0x3) -#define MPU_P5 (0x5) -#define MPU_P6 (0x6) -#define MPU_P8 (0x8) -#define MPU_P9 (0x9) -#define MPU_P10 (0xa) -#define MPU_P11 (0xb) -#define MPU_P16 (0x10) -#define MPU_P17 (0x12) -#define MPU_P18 (0x12) -#define MPU_P19 (0x13) -#define MPU_P20 (0x14) -#define MPU_P21 (0x15) -#define MPU_P22 (0x16) -#define MPU_P23 (0x17) -#define MPU_P24 (0x18) -#define MPU_P25 (0x19) -#define MPU_P26 (0x1a) -#define MPU_P27 (0x1b) -#define MPU_P28 (0x1c) -#define MPU_P29 (0x1d) -#define MPU_P30 (0x1e) -#define MPU_P31 (0x1f) -#define MPU_P1 (0x1) -#define MPU_REGA (0x1) - - - -/* ************************************************************************* */ -/* ADDRESS MACROS */ -/* ************************************************************************* */ -#define MK_DWORD_ADDR(ADDR) (ADDR >> 2) -#define MK_BYTE_ADDR(ADDR) (ADDR) - - - -/* ************************************************************************* */ -/* INSTRUCTION MACROS */ -/* ************************************************************************* */ -#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 21)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_DI() (0x40000001) - -#define MPU_EI() (0x40000003) - -#define MPU_HALT() (0x40000002) - -#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JNT() (0x61000000) - -#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0)) - -#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11)) - -#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_NOP() (0x40000000) - -#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_RET() (0x63003000) - -#define MPU_RETI() (0x63602800) - -#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\ - | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0)) - -#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16)) - -#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0)) - -#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 11)) - -#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\ - | ((N & ((1 << 16) - 1)) << 0)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\ - | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF) - -#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF) - -#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\ - | ((D & ((1 << 5) - 1)) << 21)) - -#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF) - - -#endif /* end of __IOP_MPU_MACROS_H__ */ -/* End of iop_mpu_macros.h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 95e9ce8c042a..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Autogenerated Changes here will be lost! - * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in0_extra (regi_iop + 64) -#define regi_iop_fifo_in1_extra (regi_iop + 128) -#define regi_iop_fifo_out0_extra (regi_iop + 192) -#define regi_iop_fifo_out1_extra (regi_iop + 256) -#define regi_iop_trigger_grp0 (regi_iop + 320) -#define regi_iop_trigger_grp1 (regi_iop + 384) -#define regi_iop_trigger_grp2 (regi_iop + 448) -#define regi_iop_trigger_grp3 (regi_iop + 512) -#define regi_iop_trigger_grp4 (regi_iop + 576) -#define regi_iop_trigger_grp5 (regi_iop + 640) -#define regi_iop_trigger_grp6 (regi_iop + 704) -#define regi_iop_trigger_grp7 (regi_iop + 768) -#define regi_iop_crc_par0 (regi_iop + 896) -#define regi_iop_crc_par1 (regi_iop + 1024) -#define regi_iop_dmc_in0 (regi_iop + 1152) -#define regi_iop_dmc_in1 (regi_iop + 1280) -#define regi_iop_dmc_out0 (regi_iop + 1408) -#define regi_iop_dmc_out1 (regi_iop + 1536) -#define regi_iop_fifo_in0 (regi_iop + 1664) -#define regi_iop_fifo_in1 (regi_iop + 1792) -#define regi_iop_fifo_out0 (regi_iop + 1920) -#define regi_iop_fifo_out1 (regi_iop + 2048) -#define regi_iop_scrc_in0 (regi_iop + 2176) -#define regi_iop_scrc_in1 (regi_iop + 2304) -#define regi_iop_scrc_out0 (regi_iop + 2432) -#define regi_iop_scrc_out1 (regi_iop + 2560) -#define regi_iop_timer_grp0 (regi_iop + 2688) -#define regi_iop_timer_grp1 (regi_iop + 2816) -#define regi_iop_timer_grp2 (regi_iop + 2944) -#define regi_iop_timer_grp3 (regi_iop + 3072) -#define regi_iop_sap_in (regi_iop + 3328) -#define regi_iop_sap_out (regi_iop + 3584) -#define regi_iop_spu0 (regi_iop + 3840) -#define regi_iop_spu1 (regi_iop + 4096) -#define regi_iop_sw_cfg (regi_iop + 4352) -#define regi_iop_sw_cpu (regi_iop + 4608) -#define regi_iop_sw_mpu (regi_iop + 4864) -#define regi_iop_sw_spu0 (regi_iop + 5120) -#define regi_iop_sw_spu1 (regi_iop + 5376) -#define regi_iop_mpu (regi_iop + 5632) diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 22a74eafb8b0..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_in.r - * id: - * last modfied: Mon Apr 11 16:08:45 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r - * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -/* Register rw_bus0_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus0_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 - -/* Register rw_bus1_sync, scope iop_sap_in, type rw */ -typedef struct { - unsigned int byte0_sel : 2; - unsigned int byte0_ext_src : 3; - unsigned int byte0_edge : 2; - unsigned int byte0_delay : 1; - unsigned int byte1_sel : 2; - unsigned int byte1_ext_src : 3; - unsigned int byte1_edge : 2; - unsigned int byte1_delay : 1; - unsigned int byte2_sel : 2; - unsigned int byte2_ext_src : 3; - unsigned int byte2_edge : 2; - unsigned int byte2_delay : 1; - unsigned int byte3_sel : 2; - unsigned int byte3_ext_src : 3; - unsigned int byte3_edge : 2; - unsigned int byte3_delay : 1; -} reg_iop_sap_in_rw_bus1_sync; -#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 -#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 1; - unsigned int logic : 2; - unsigned int dummy1 : 22; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 8 -#define REG_WR_ADDR_iop_sap_in_rw_gio 8 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio1 = 0x00000000, - regk_iop_sap_in_gio13 = 0x00000005, - regk_iop_sap_in_gio18 = 0x00000003, - regk_iop_sap_in_gio19 = 0x00000004, - regk_iop_sap_in_gio21 = 0x00000006, - regk_iop_sap_in_gio23 = 0x00000005, - regk_iop_sap_in_gio29 = 0x00000007, - regk_iop_sap_in_gio5 = 0x00000004, - regk_iop_sap_in_gio6 = 0x00000001, - regk_iop_sap_in_gio7 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, - regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, - regk_iop_sap_in_rw_gio_default = 0x00000002, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, - regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, - regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, - regk_iop_sap_in_tmr_clk200 = 0x00000000, - regk_iop_sap_in_two_clk200 = 0x00000002, - regk_iop_sap_in_yes = 0x00000001 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 380133910105..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,307 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_sap_out.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r - * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int clk2_src : 2; - unsigned int clk2_gate_src : 2; - unsigned int clk2_force_src : 3; - unsigned int clk3_src : 2; - unsigned int clk3_gate_src : 2; - unsigned int clk3_force_src : 3; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus0, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus0; -#define REG_RD_ADDR_iop_sap_out_rw_bus0 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus0 4 - -/* Register rw_bus1, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte2_clk_sel : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_bus1; -#define REG_RD_ADDR_iop_sap_out_rw_bus1 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus1 8 - -/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12 - -/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus0_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16 -#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16 - -/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 3; - unsigned int byte0_clk_ext : 3; - unsigned int byte0_gated_clk : 2; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_logic : 2; - unsigned int byte1_clk_sel : 3; - unsigned int byte1_clk_ext : 3; - unsigned int byte1_gated_clk : 2; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20 - -/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 3; - unsigned int byte2_clk_ext : 3; - unsigned int byte2_gated_clk : 2; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_logic : 2; - unsigned int byte3_clk_sel : 3; - unsigned int byte3_clk_ext : 3; - unsigned int byte3_gated_clk : 2; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus1_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24 -#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 4; - unsigned int out_gated_clk : 2; - unsigned int out_clk_inv : 1; - unsigned int out_logic : 1; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 3; - unsigned int oe_gated_clk : 2; - unsigned int oe_clk_inv : 1; - unsigned int oe_logic : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 28 -#define REG_WR_ADDR_iop_sap_out_rw_gio 28 - - -/* Constants */ -enum { - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000002, - regk_iop_sap_out_clk2 = 0x00000002, - regk_iop_sap_out_clk200 = 0x00000001, - regk_iop_sap_out_clk3 = 0x00000003, - regk_iop_sap_out_ext = 0x00000003, - regk_iop_sap_out_gated = 0x00000004, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio13 = 0x00000002, - regk_iop_sap_out_gio13_clk = 0x0000000c, - regk_iop_sap_out_gio15 = 0x00000001, - regk_iop_sap_out_gio18 = 0x00000003, - regk_iop_sap_out_gio18_clk = 0x0000000d, - regk_iop_sap_out_gio1_clk = 0x00000008, - regk_iop_sap_out_gio21_clk = 0x0000000e, - regk_iop_sap_out_gio23 = 0x00000002, - regk_iop_sap_out_gio29_clk = 0x0000000f, - regk_iop_sap_out_gio31 = 0x00000003, - regk_iop_sap_out_gio5 = 0x00000001, - regk_iop_sap_out_gio5_clk = 0x00000009, - regk_iop_sap_out_gio6_clk = 0x0000000a, - regk_iop_sap_out_gio7 = 0x00000000, - regk_iop_sap_out_gio7_clk = 0x0000000b, - regk_iop_sap_out_gio_in13 = 0x00000001, - regk_iop_sap_out_gio_in21 = 0x00000002, - regk_iop_sap_out_gio_in29 = 0x00000003, - regk_iop_sap_out_gio_in5 = 0x00000000, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_rw_bus0_default = 0x00000000, - regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_default = 0x00000000, - regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu0_gio0 = 0x00000002, - regk_iop_sap_out_spu0_gio1 = 0x00000003, - regk_iop_sap_out_spu0_gio12 = 0x00000004, - regk_iop_sap_out_spu0_gio13 = 0x00000004, - regk_iop_sap_out_spu0_gio14 = 0x00000004, - regk_iop_sap_out_spu0_gio15 = 0x00000004, - regk_iop_sap_out_spu0_gio2 = 0x00000002, - regk_iop_sap_out_spu0_gio3 = 0x00000003, - regk_iop_sap_out_spu0_gio4 = 0x00000002, - regk_iop_sap_out_spu0_gio5 = 0x00000003, - regk_iop_sap_out_spu0_gio6 = 0x00000002, - regk_iop_sap_out_spu0_gio7 = 0x00000003, - regk_iop_sap_out_spu1_gio0 = 0x00000005, - regk_iop_sap_out_spu1_gio1 = 0x00000006, - regk_iop_sap_out_spu1_gio12 = 0x00000007, - regk_iop_sap_out_spu1_gio13 = 0x00000007, - regk_iop_sap_out_spu1_gio14 = 0x00000007, - regk_iop_sap_out_spu1_gio15 = 0x00000007, - regk_iop_sap_out_spu1_gio2 = 0x00000005, - regk_iop_sap_out_spu1_gio3 = 0x00000006, - regk_iop_sap_out_spu1_gio4 = 0x00000005, - regk_iop_sap_out_spu1_gio5 = 0x00000006, - regk_iop_sap_out_spu1_gio6 = 0x00000005, - regk_iop_sap_out_spu1_gio7 = 0x00000006, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005, - regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006, - regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007, - regk_iop_sap_out_tmr = 0x00000005, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h deleted file mode 100644 index 65d662046ca9..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_scrc_in_defs_h -#define __iop_scrc_in_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_in.r - * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r - * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_in */ - -/* Register rw_cfg, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int dummy1 : 30; -} reg_iop_scrc_in_rw_cfg; -#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int dif_in_en : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4 - -/* Register r_stat, scope iop_scrc_in, type r */ -typedef struct { - unsigned int err : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_in_r_stat; -#define REG_RD_ADDR_iop_scrc_in_r_stat 8 - -/* Register rw_init_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12 -#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12 - -/* Register rs_computed_crc, scope iop_scrc_in, type rs */ -typedef unsigned int reg_iop_scrc_in_rs_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16 - -/* Register r_computed_crc, scope iop_scrc_in, type r */ -typedef unsigned int reg_iop_scrc_in_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20 - -/* Register rw_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_crc 24 -#define REG_WR_ADDR_iop_scrc_in_rw_crc 24 - -/* Register rw_correct_crc, scope iop_scrc_in, type rw */ -typedef unsigned int reg_iop_scrc_in_rw_correct_crc; -#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28 -#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28 - -/* Register rw_wr1bit, scope iop_scrc_in, type rw */ -typedef struct { - unsigned int data : 2; - unsigned int last : 2; - unsigned int dummy1 : 28; -} reg_iop_scrc_in_rw_wr1bit; -#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32 -#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32 - - -/* Constants */ -enum { - regk_iop_scrc_in_dif_in = 0x00000002, - regk_iop_scrc_in_hi = 0x00000000, - regk_iop_scrc_in_neg = 0x00000002, - regk_iop_scrc_in_no = 0x00000000, - regk_iop_scrc_in_pos = 0x00000001, - regk_iop_scrc_in_pos_neg = 0x00000003, - regk_iop_scrc_in_r_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rs_computed_crc_default = 0x00000000, - regk_iop_scrc_in_rw_cfg_default = 0x00000000, - regk_iop_scrc_in_rw_ctrl_default = 0x00000000, - regk_iop_scrc_in_rw_init_crc_default = 0x00000000, - regk_iop_scrc_in_set0 = 0x00000000, - regk_iop_scrc_in_set1 = 0x00000001, - regk_iop_scrc_in_yes = 0x00000001 -}; -#endif /* __iop_scrc_in_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h deleted file mode 100644 index ba39605b9737..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_scrc_out_defs_h -#define __iop_scrc_out_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_scrc_out.r - * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r - * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_scrc_out */ - -/* Register rw_cfg, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int trig : 2; - unsigned int inv_crc : 1; - unsigned int dummy1 : 29; -} reg_iop_scrc_out_rw_cfg; -#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 -#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 - -/* Register rw_ctrl, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int strb_src : 1; - unsigned int out_src : 1; - unsigned int dummy1 : 30; -} reg_iop_scrc_out_rw_ctrl; -#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 -#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 - -/* Register rw_init_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_init_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 -#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 - -/* Register rw_crc, scope iop_scrc_out, type rw */ -typedef unsigned int reg_iop_scrc_out_rw_crc; -#define REG_RD_ADDR_iop_scrc_out_rw_crc 12 -#define REG_WR_ADDR_iop_scrc_out_rw_crc 12 - -/* Register rw_data, scope iop_scrc_out, type rw */ -typedef struct { - unsigned int val : 1; - unsigned int dummy1 : 31; -} reg_iop_scrc_out_rw_data; -#define REG_RD_ADDR_iop_scrc_out_rw_data 16 -#define REG_WR_ADDR_iop_scrc_out_rw_data 16 - -/* Register r_computed_crc, scope iop_scrc_out, type r */ -typedef unsigned int reg_iop_scrc_out_r_computed_crc; -#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 - - -/* Constants */ -enum { - regk_iop_scrc_out_crc = 0x00000001, - regk_iop_scrc_out_data = 0x00000000, - regk_iop_scrc_out_dif = 0x00000001, - regk_iop_scrc_out_hi = 0x00000000, - regk_iop_scrc_out_neg = 0x00000002, - regk_iop_scrc_out_no = 0x00000000, - regk_iop_scrc_out_pos = 0x00000001, - regk_iop_scrc_out_pos_neg = 0x00000003, - regk_iop_scrc_out_reg = 0x00000000, - regk_iop_scrc_out_rw_cfg_default = 0x00000000, - regk_iop_scrc_out_rw_crc_default = 0x00000000, - regk_iop_scrc_out_rw_ctrl_default = 0x00000000, - regk_iop_scrc_out_rw_data_default = 0x00000000, - regk_iop_scrc_out_rw_init_crc_default = 0x00000000, - regk_iop_scrc_out_yes = 0x00000001 -}; -#endif /* __iop_scrc_out_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h deleted file mode 100644 index 7681fdab93fc..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_spu_defs_h -#define __iop_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_spu.r - * id: - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r - * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_spu */ - -#define STRIDE_iop_spu_rw_r 4 -/* Register rw_r, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_r; -#define REG_RD_ADDR_iop_spu_rw_r 0 -#define REG_WR_ADDR_iop_spu_rw_r 0 - -/* Register rw_seq_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_seq_pc; -#define REG_RD_ADDR_iop_spu_rw_seq_pc 64 -#define REG_WR_ADDR_iop_spu_rw_seq_pc 64 - -/* Register rw_fsm_pc, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_fsm_pc; -#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68 -#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68 - -/* Register rw_ctrl, scope iop_spu, type rw */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_iop_spu_rw_ctrl; -#define REG_RD_ADDR_iop_spu_rw_ctrl 72 -#define REG_WR_ADDR_iop_spu_rw_ctrl 72 - -/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */ -typedef struct { - unsigned int val0 : 5; - unsigned int src0 : 3; - unsigned int val1 : 5; - unsigned int src1 : 3; - unsigned int val2 : 5; - unsigned int src2 : 3; - unsigned int val3 : 5; - unsigned int src3 : 3; -} reg_iop_spu_rw_fsm_inputs3_0; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76 - -/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */ -typedef struct { - unsigned int val4 : 5; - unsigned int src4 : 3; - unsigned int val5 : 5; - unsigned int src5 : 3; - unsigned int val6 : 5; - unsigned int src6 : 3; - unsigned int val7 : 5; - unsigned int src7 : 3; -} reg_iop_spu_rw_fsm_inputs7_4; -#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80 -#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80 - -/* Register rw_gio_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out; -#define REG_RD_ADDR_iop_spu_rw_gio_out 84 -#define REG_WR_ADDR_iop_spu_rw_gio_out 84 - -/* Register rw_bus0_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus0_out; -#define REG_RD_ADDR_iop_spu_rw_bus0_out 88 -#define REG_WR_ADDR_iop_spu_rw_bus0_out 88 - -/* Register rw_bus1_out, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_bus1_out; -#define REG_RD_ADDR_iop_spu_rw_bus1_out 92 -#define REG_WR_ADDR_iop_spu_rw_bus1_out 92 - -/* Register r_gio_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_gio_in; -#define REG_RD_ADDR_iop_spu_r_gio_in 96 - -/* Register r_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus0_in; -#define REG_RD_ADDR_iop_spu_r_bus0_in 100 - -/* Register r_bus1_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_bus1_in; -#define REG_RD_ADDR_iop_spu_r_bus1_in 104 - -/* Register rw_gio_out_set, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_set; -#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108 -#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108 - -/* Register rw_gio_out_clr, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_gio_out_clr; -#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112 -#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112 - -/* Register rs_wr_stat, scope iop_spu, type rs */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_rs_wr_stat; -#define REG_RD_ADDR_iop_spu_rs_wr_stat 116 - -/* Register r_wr_stat, scope iop_spu, type r */ -typedef struct { - unsigned int r0 : 1; - unsigned int r1 : 1; - unsigned int r2 : 1; - unsigned int r3 : 1; - unsigned int r4 : 1; - unsigned int r5 : 1; - unsigned int r6 : 1; - unsigned int r7 : 1; - unsigned int r8 : 1; - unsigned int r9 : 1; - unsigned int r10 : 1; - unsigned int r11 : 1; - unsigned int r12 : 1; - unsigned int r13 : 1; - unsigned int r14 : 1; - unsigned int r15 : 1; - unsigned int dummy1 : 16; -} reg_iop_spu_r_wr_stat; -#define REG_RD_ADDR_iop_spu_r_wr_stat 120 - -/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in; -#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124 - -/* Register r_stat_in, scope iop_spu, type r */ -typedef struct { - unsigned int timer_grp_lo : 4; - unsigned int fifo_out_last : 1; - unsigned int fifo_out_rdy : 1; - unsigned int fifo_out_all : 1; - unsigned int fifo_in_rdy : 1; - unsigned int dmc_out_all : 1; - unsigned int dmc_out_dth : 1; - unsigned int dmc_out_eop : 1; - unsigned int dmc_out_dv : 1; - unsigned int dmc_out_last : 1; - unsigned int dmc_out_cmd_rq : 1; - unsigned int dmc_out_cmd_rdy : 1; - unsigned int pcrc_correct : 1; - unsigned int timer_grp_hi : 4; - unsigned int dmc_in_sth : 1; - unsigned int dmc_in_full : 1; - unsigned int dmc_in_cmd_rdy : 1; - unsigned int spu_gio_out : 4; - unsigned int sync_clk12 : 1; - unsigned int scrc_out_data : 1; - unsigned int scrc_in_err : 1; - unsigned int mc_busy : 1; - unsigned int mc_owned : 1; -} reg_iop_spu_r_stat_in; -#define REG_RD_ADDR_iop_spu_r_stat_in 128 - -/* Register r_trigger_in, scope iop_spu, type r */ -typedef unsigned int reg_iop_spu_r_trigger_in; -#define REG_RD_ADDR_iop_spu_r_trigger_in 132 - -/* Register r_special_stat, scope iop_spu, type r */ -typedef struct { - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int xor_bus0_r2_0 : 1; - unsigned int xor_bus1_r3_0 : 1; - unsigned int xor_bus0m_r2_0 : 1; - unsigned int xor_bus1m_r3_0 : 1; - unsigned int fsm_in0 : 1; - unsigned int fsm_in1 : 1; - unsigned int fsm_in2 : 1; - unsigned int fsm_in3 : 1; - unsigned int fsm_in4 : 1; - unsigned int fsm_in5 : 1; - unsigned int fsm_in6 : 1; - unsigned int fsm_in7 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int dummy1 : 12; -} reg_iop_spu_r_special_stat; -#define REG_RD_ADDR_iop_spu_r_special_stat 136 - -/* Register rw_reg_access, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 13; - unsigned int dummy1 : 3; - unsigned int imm_hi : 16; -} reg_iop_spu_rw_reg_access; -#define REG_RD_ADDR_iop_spu_rw_reg_access 140 -#define REG_WR_ADDR_iop_spu_rw_reg_access 140 - -#define STRIDE_iop_spu_rw_event_cfg 4 -/* Register rw_event_cfg, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int src : 2; - unsigned int eq_en : 1; - unsigned int eq_inv : 1; - unsigned int gt_en : 1; - unsigned int gt_inv : 1; - unsigned int dummy1 : 14; -} reg_iop_spu_rw_event_cfg; -#define REG_RD_ADDR_iop_spu_rw_event_cfg 144 -#define REG_WR_ADDR_iop_spu_rw_event_cfg 144 - -#define STRIDE_iop_spu_rw_event_mask 4 -/* Register rw_event_mask, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_mask; -#define REG_RD_ADDR_iop_spu_rw_event_mask 160 -#define REG_WR_ADDR_iop_spu_rw_event_mask 160 - -#define STRIDE_iop_spu_rw_event_val 4 -/* Register rw_event_val, scope iop_spu, type rw */ -typedef unsigned int reg_iop_spu_rw_event_val; -#define REG_RD_ADDR_iop_spu_rw_event_val 176 -#define REG_WR_ADDR_iop_spu_rw_event_val 176 - -/* Register rw_event_ret, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int dummy1 : 20; -} reg_iop_spu_rw_event_ret; -#define REG_RD_ADDR_iop_spu_rw_event_ret 192 -#define REG_WR_ADDR_iop_spu_rw_event_ret 192 - -/* Register r_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int c_flag : 1; - unsigned int v_flag : 1; - unsigned int z_flag : 1; - unsigned int n_flag : 1; - unsigned int seq_addr : 12; - unsigned int dummy1 : 2; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_trace; -#define REG_RD_ADDR_iop_spu_r_trace 196 - -/* Register r_fsm_trace, scope iop_spu, type r */ -typedef struct { - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int tmr_done : 1; - unsigned int inp0 : 1; - unsigned int inp1 : 1; - unsigned int inp2 : 1; - unsigned int inp3 : 1; - unsigned int event0 : 1; - unsigned int event1 : 1; - unsigned int event2 : 1; - unsigned int event3 : 1; - unsigned int gio_out : 8; - unsigned int dummy1 : 1; - unsigned int fsm_addr : 12; -} reg_iop_spu_r_fsm_trace; -#define REG_RD_ADDR_iop_spu_r_fsm_trace 200 - -#define STRIDE_iop_spu_rw_brp 4 -/* Register rw_brp, scope iop_spu, type rw */ -typedef struct { - unsigned int addr : 12; - unsigned int fsm : 1; - unsigned int en : 1; - unsigned int dummy1 : 18; -} reg_iop_spu_rw_brp; -#define REG_RD_ADDR_iop_spu_rw_brp 204 -#define REG_WR_ADDR_iop_spu_rw_brp 204 - - -/* Constants */ -enum { - regk_iop_spu_attn_hi = 0x00000005, - regk_iop_spu_attn_lo = 0x00000005, - regk_iop_spu_attn_r0 = 0x00000000, - regk_iop_spu_attn_r1 = 0x00000001, - regk_iop_spu_attn_r10 = 0x00000002, - regk_iop_spu_attn_r11 = 0x00000003, - regk_iop_spu_attn_r12 = 0x00000004, - regk_iop_spu_attn_r13 = 0x00000005, - regk_iop_spu_attn_r14 = 0x00000006, - regk_iop_spu_attn_r15 = 0x00000007, - regk_iop_spu_attn_r2 = 0x00000002, - regk_iop_spu_attn_r3 = 0x00000003, - regk_iop_spu_attn_r4 = 0x00000004, - regk_iop_spu_attn_r5 = 0x00000005, - regk_iop_spu_attn_r6 = 0x00000006, - regk_iop_spu_attn_r7 = 0x00000007, - regk_iop_spu_attn_r8 = 0x00000000, - regk_iop_spu_attn_r9 = 0x00000001, - regk_iop_spu_c = 0x00000000, - regk_iop_spu_flag = 0x00000002, - regk_iop_spu_gio_in = 0x00000000, - regk_iop_spu_gio_out = 0x00000005, - regk_iop_spu_gio_out0 = 0x00000008, - regk_iop_spu_gio_out1 = 0x00000009, - regk_iop_spu_gio_out2 = 0x0000000a, - regk_iop_spu_gio_out3 = 0x0000000b, - regk_iop_spu_gio_out4 = 0x0000000c, - regk_iop_spu_gio_out5 = 0x0000000d, - regk_iop_spu_gio_out6 = 0x0000000e, - regk_iop_spu_gio_out7 = 0x0000000f, - regk_iop_spu_n = 0x00000003, - regk_iop_spu_no = 0x00000000, - regk_iop_spu_r0 = 0x00000008, - regk_iop_spu_r1 = 0x00000009, - regk_iop_spu_r10 = 0x0000000a, - regk_iop_spu_r11 = 0x0000000b, - regk_iop_spu_r12 = 0x0000000c, - regk_iop_spu_r13 = 0x0000000d, - regk_iop_spu_r14 = 0x0000000e, - regk_iop_spu_r15 = 0x0000000f, - regk_iop_spu_r2 = 0x0000000a, - regk_iop_spu_r3 = 0x0000000b, - regk_iop_spu_r4 = 0x0000000c, - regk_iop_spu_r5 = 0x0000000d, - regk_iop_spu_r6 = 0x0000000e, - regk_iop_spu_r7 = 0x0000000f, - regk_iop_spu_r8 = 0x00000008, - regk_iop_spu_r9 = 0x00000009, - regk_iop_spu_reg_hi = 0x00000002, - regk_iop_spu_reg_lo = 0x00000002, - regk_iop_spu_rw_brp_default = 0x00000000, - regk_iop_spu_rw_brp_size = 0x00000004, - regk_iop_spu_rw_ctrl_default = 0x00000000, - regk_iop_spu_rw_event_cfg_size = 0x00000004, - regk_iop_spu_rw_event_mask_size = 0x00000004, - regk_iop_spu_rw_event_val_size = 0x00000004, - regk_iop_spu_rw_gio_out_default = 0x00000000, - regk_iop_spu_rw_r_size = 0x00000010, - regk_iop_spu_rw_reg_access_default = 0x00000000, - regk_iop_spu_stat_in = 0x00000002, - regk_iop_spu_statin_hi = 0x00000004, - regk_iop_spu_statin_lo = 0x00000004, - regk_iop_spu_trig = 0x00000003, - regk_iop_spu_trigger = 0x00000006, - regk_iop_spu_v = 0x00000001, - regk_iop_spu_wsts_gioout_spec = 0x00000001, - regk_iop_spu_xor = 0x00000003, - regk_iop_spu_xor_bus0_r2_0 = 0x00000000, - regk_iop_spu_xor_bus0m_r2_0 = 0x00000002, - regk_iop_spu_xor_bus1_r3_0 = 0x00000001, - regk_iop_spu_xor_bus1m_r3_0 = 0x00000003, - regk_iop_spu_yes = 0x00000001, - regk_iop_spu_z = 0x00000002 -}; -#endif /* __iop_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index 86e5c9b3e593..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,1043 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r - * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0 - -/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4 - -/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8 - -/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12 - -/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16 - -/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20 - -/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24 - -/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28 - -/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32 - -/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36 - -/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40 - -/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out0_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44 - -/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48 - -/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out1_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60 - -/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64 - -/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68 - -/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72 - -/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76 - -/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80 - -/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92 - -/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96 - -/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132 - -/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus0_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136 - -/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus0_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140 - -/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus1_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144 - -/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus1_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_byte0 : 2; - unsigned int bus0_byte1 : 2; - unsigned int bus0_byte2 : 2; - unsigned int bus0_byte3 : 2; - unsigned int bus1_byte0 : 2; - unsigned int bus1_byte1 : 2; - unsigned int bus1_byte2 : 2; - unsigned int bus1_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_lo : 3; - unsigned int bus0_hi : 3; - unsigned int bus0_lo_oe : 3; - unsigned int bus0_hi_oe : 3; - unsigned int bus1_lo : 3; - unsigned int bus1_hi : 3; - unsigned int bus1_lo_oe : 3; - unsigned int bus1_hi_oe : 3; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 4; - unsigned int gio0_oe : 2; - unsigned int gio1 : 4; - unsigned int gio1_oe : 2; - unsigned int gio2 : 4; - unsigned int gio2_oe : 2; - unsigned int gio3 : 4; - unsigned int gio3_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 4; - unsigned int gio4_oe : 2; - unsigned int gio5 : 4; - unsigned int gio5_oe : 2; - unsigned int gio6 : 4; - unsigned int gio6_oe : 2; - unsigned int gio7 : 4; - unsigned int gio7_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 4; - unsigned int gio8_oe : 2; - unsigned int gio9 : 4; - unsigned int gio9_oe : 2; - unsigned int gio10 : 4; - unsigned int gio10_oe : 2; - unsigned int gio11 : 4; - unsigned int gio11_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 4; - unsigned int gio12_oe : 2; - unsigned int gio13 : 4; - unsigned int gio13_oe : 2; - unsigned int gio14 : 4; - unsigned int gio14_oe : 2; - unsigned int gio15 : 4; - unsigned int gio15_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 4; - unsigned int gio16_oe : 2; - unsigned int gio17 : 4; - unsigned int gio17_oe : 2; - unsigned int gio18 : 4; - unsigned int gio18_oe : 2; - unsigned int gio19 : 4; - unsigned int gio19_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 4; - unsigned int gio20_oe : 2; - unsigned int gio21 : 4; - unsigned int gio21_oe : 2; - unsigned int gio22 : 4; - unsigned int gio22_oe : 2; - unsigned int gio23 : 4; - unsigned int gio23_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 4; - unsigned int gio24_oe : 2; - unsigned int gio25 : 4; - unsigned int gio25_oe : 2; - unsigned int gio26 : 4; - unsigned int gio26_oe : 2; - unsigned int gio27 : 4; - unsigned int gio27_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 4; - unsigned int gio28_oe : 2; - unsigned int gio29 : 4; - unsigned int gio29_oe : 2; - unsigned int gio30 : 4; - unsigned int gio30_oe : 2; - unsigned int gio31 : 4; - unsigned int gio31_oe : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196 - -/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200 - -/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 2; - unsigned int bus1_in : 2; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_spu1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212 - -/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216 - -/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 1; - unsigned int tmr1_en : 1; - unsigned int tmr2_en : 1; - unsigned int tmr3_en : 1; - unsigned int tmr0_dis : 1; - unsigned int tmr1_dis : 1; - unsigned int tmr2_dis : 1; - unsigned int tmr3_dis : 1; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_timer_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224 - -/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc0_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228 - -/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int dmc1_usr : 1; - unsigned int out_strb : 5; - unsigned int in_src : 3; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int out_src : 1; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_pdp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out0_strb : 3; - unsigned int sdp_out1_strb : 3; - unsigned int sdp_in0_data : 3; - unsigned int sdp_in0_last : 2; - unsigned int sdp_in0_strb : 3; - unsigned int sdp_in1_data : 3; - unsigned int sdp_in1_last : 2; - unsigned int sdp_in1_strb : 3; - unsigned int dummy1 : 10; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus0 = 0x00000000, - regk_iop_sw_cfg_bus0_rot16 = 0x00000004, - regk_iop_sw_cfg_bus0_rot24 = 0x00000006, - regk_iop_sw_cfg_bus0_rot8 = 0x00000002, - regk_iop_sw_cfg_bus1 = 0x00000001, - regk_iop_sw_cfg_bus1_rot16 = 0x00000005, - regk_iop_sw_cfg_bus1_rot24 = 0x00000007, - regk_iop_sw_cfg_bus1_rot8 = 0x00000003, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_dmc0 = 0x00000000, - regk_iop_sw_cfg_dmc1 = 0x00000001, - regk_iop_sw_cfg_gated_clk0 = 0x00000010, - regk_iop_sw_cfg_gated_clk1 = 0x00000011, - regk_iop_sw_cfg_gated_clk2 = 0x00000012, - regk_iop_sw_cfg_gated_clk3 = 0x00000013, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in0 = 0x00000000, - regk_iop_sw_cfg_gio_in1 = 0x00000001, - regk_iop_sw_cfg_gio_in10 = 0x00000002, - regk_iop_sw_cfg_gio_in11 = 0x00000003, - regk_iop_sw_cfg_gio_in14 = 0x00000004, - regk_iop_sw_cfg_gio_in15 = 0x00000005, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in28 = 0x00000006, - regk_iop_sw_cfg_gio_in29 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, - regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_par0 = 0x00000000, - regk_iop_sw_cfg_par1 = 0x00000001, - regk_iop_sw_cfg_pdp_out0 = 0x00000002, - regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, - regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_pdp_out1 = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, - regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, - regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, - regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, - regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out0 = 0x00000008, - regk_iop_sw_cfg_sdp_out1 = 0x00000009, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu0 = 0x00000002, - regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu0_g0 = 0x0000000e, - regk_iop_sw_cfg_spu0_g1 = 0x0000000e, - regk_iop_sw_cfg_spu0_g2 = 0x0000000e, - regk_iop_sw_cfg_spu0_g3 = 0x0000000e, - regk_iop_sw_cfg_spu0_g4 = 0x0000000e, - regk_iop_sw_cfg_spu0_g5 = 0x0000000e, - regk_iop_sw_cfg_spu0_g6 = 0x0000000e, - regk_iop_sw_cfg_spu0_g7 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio0 = 0x00000000, - regk_iop_sw_cfg_spu0_gio1 = 0x00000001, - regk_iop_sw_cfg_spu0_gio2 = 0x00000000, - regk_iop_sw_cfg_spu0_gio5 = 0x00000005, - regk_iop_sw_cfg_spu0_gio6 = 0x00000006, - regk_iop_sw_cfg_spu0_gio7 = 0x00000007, - regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, - regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, - regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, - regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, - regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, - regk_iop_sw_cfg_spu1 = 0x00000003, - regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, - regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, - regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, - regk_iop_sw_cfg_spu1_g0 = 0x0000000f, - regk_iop_sw_cfg_spu1_g1 = 0x0000000f, - regk_iop_sw_cfg_spu1_g2 = 0x0000000f, - regk_iop_sw_cfg_spu1_g3 = 0x0000000f, - regk_iop_sw_cfg_spu1_g4 = 0x0000000f, - regk_iop_sw_cfg_spu1_g5 = 0x0000000f, - regk_iop_sw_cfg_spu1_g6 = 0x0000000f, - regk_iop_sw_cfg_spu1_g7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gio0 = 0x00000002, - regk_iop_sw_cfg_spu1_gio1 = 0x00000003, - regk_iop_sw_cfg_spu1_gio2 = 0x00000002, - regk_iop_sw_cfg_spu1_gio5 = 0x00000005, - regk_iop_sw_cfg_spu1_gio6 = 0x00000006, - regk_iop_sw_cfg_spu1_gio7 = 0x00000007, - regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, - regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, - regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, - regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, - regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, - regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, - regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, - regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, - regk_iop_sw_cfg_timer_grp2 = 0x00000000, - regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, - regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, - regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, - regk_iop_sw_cfg_timer_grp3 = 0x00000000, - regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, - regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, - regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000000, - regk_iop_sw_cfg_trig2_1 = 0x00000000, - regk_iop_sw_cfg_trig2_2 = 0x00000000, - regk_iop_sw_cfg_trig2_3 = 0x00000000, - regk_iop_sw_cfg_trig3_0 = 0x00000000, - regk_iop_sw_cfg_trig3_1 = 0x00000000, - regk_iop_sw_cfg_trig3_2 = 0x00000000, - regk_iop_sw_cfg_trig3_3 = 0x00000000, - regk_iop_sw_cfg_trig4_0 = 0x00000001, - regk_iop_sw_cfg_trig4_1 = 0x00000001, - regk_iop_sw_cfg_trig4_2 = 0x00000001, - regk_iop_sw_cfg_trig4_3 = 0x00000001, - regk_iop_sw_cfg_trig5_0 = 0x00000001, - regk_iop_sw_cfg_trig5_1 = 0x00000001, - regk_iop_sw_cfg_trig5_2 = 0x00000001, - regk_iop_sw_cfg_trig5_3 = 0x00000001, - regk_iop_sw_cfg_trig6_0 = 0x00000001, - regk_iop_sw_cfg_trig6_1 = 0x00000001, - regk_iop_sw_cfg_trig6_2 = 0x00000001, - regk_iop_sw_cfg_trig6_3 = 0x00000001, - regk_iop_sw_cfg_trig7_0 = 0x00000001, - regk_iop_sw_cfg_trig7_1 = 0x00000001, - regk_iop_sw_cfg_trig7_2 = 0x00000001, - regk_iop_sw_cfg_trig7_3 = 0x00000001 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index 31055d3fcd76..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,854 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r - * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int spu1_8 : 1; - unsigned int spu1_9 : 1; - unsigned int spu1_10 : 1; - unsigned int spu1_11 : 1; - unsigned int spu1_12 : 1; - unsigned int spu1_13 : 1; - unsigned int spu1_14 : 1; - unsigned int spu1_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int spu0_8 : 1; - unsigned int spu0_9 : 1; - unsigned int spu0_10 : 1; - unsigned int spu0_11 : 1; - unsigned int spu0_12 : 1; - unsigned int spu0_13 : 1; - unsigned int spu0_14 : 1; - unsigned int spu0_15 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112 - -/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr2_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116 - -/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr2; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120 - -/* Register r_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124 - -/* Register r_masked_intr2, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int spu0_0 : 1; - unsigned int spu0_1 : 1; - unsigned int spu0_2 : 1; - unsigned int spu0_3 : 1; - unsigned int spu0_4 : 1; - unsigned int spu0_5 : 1; - unsigned int spu0_6 : 1; - unsigned int spu0_7 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out0_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr2; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128 - -/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_rw_intr3_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132 - -/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr3; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136 - -/* Register r_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140 - -/* Register r_masked_intr3, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int spu1_0 : 1; - unsigned int spu1_1 : 1; - unsigned int spu1_2 : 1; - unsigned int spu1_3 : 1; - unsigned int spu1_4 : 1; - unsigned int spu1_5 : 1; - unsigned int spu1_6 : 1; - unsigned int spu1_7 : 1; - unsigned int dmc_in1 : 1; - unsigned int dmc_out1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int fifo_out1_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; -} reg_iop_sw_cpu_r_masked_intr3; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index 5038c08e8a95..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,894 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r - * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24 - -/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28 - -/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40 - -/* Register r_bus0_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44 - -/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48 - -/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60 - -/* Register r_bus1_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr0 : 1; - unsigned int spu1_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr1 : 1; - unsigned int spu1_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr2 : 1; - unsigned int spu1_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr3 : 1; - unsigned int spu1_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr4 : 1; - unsigned int spu1_intr4 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr5 : 1; - unsigned int spu1_intr5 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr6 : 1; - unsigned int spu1_intr6 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr7 : 1; - unsigned int spu1_intr7 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr8 : 1; - unsigned int spu1_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr9 : 1; - unsigned int spu1_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr10 : 1; - unsigned int spu1_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr11 : 1; - unsigned int spu1_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int dummy1 : 6; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int dummy2 : 6; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int dummy3 : 6; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int dummy4 : 6; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu0_intr12 : 1; - unsigned int spu1_intr12 : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int spu0_intr13 : 1; - unsigned int spu1_intr13 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp4 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int dmc_in0 : 1; - unsigned int spu0_intr14 : 1; - unsigned int spu1_intr14 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp5 : 1; - unsigned int timer_grp2 : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int dmc_out1 : 1; - unsigned int spu0_intr15 : 1; - unsigned int spu1_intr15 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int dmc_in1 : 1; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu0 = 0x00000002, - regk_iop_sw_mpu_spu1 = 0x00000003, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index aeebd57af7f7..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,553 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: - * last modfied: Mon Apr 11 16:10:19 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r - * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu0_mem : 1; - unsigned int wr_spu1_mem : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu0 : 1; - unsigned int busy_spu1 : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu0 : 1; - unsigned int owned_by_spu1 : 1; - unsigned int dummy1 : 24; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20 - -/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24 - -/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus0_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28 - -/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32 - -/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus0_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36 - -/* Register r_bus0_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus0_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40 - -/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44 - -/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus1_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48 - -/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52 - -/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus1_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56 - -/* Register r_bus1_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus1_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80 - -/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84 - -/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88 - -/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92 - -/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus0_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96 - -/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100 - -/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104 - -/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108 - -/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus1_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int timer_grp2 : 1; - unsigned int timer_grp3 : 1; - unsigned int fifo_out0 : 1; - unsigned int fifo_out0_extra : 1; - unsigned int fifo_in0 : 1; - unsigned int fifo_in0_extra : 1; - unsigned int fifo_out1 : 1; - unsigned int fifo_out1_extra : 1; - unsigned int fifo_in1 : 1; - unsigned int fifo_in1_extra : 1; - unsigned int dmc_out0 : 1; - unsigned int dmc_in0 : 1; - unsigned int dmc_out1 : 1; - unsigned int dmc_in1 : 1; - unsigned int dummy1 : 8; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int other_spu_intr0 : 1; - unsigned int other_spu_intr1 : 1; - unsigned int other_spu_intr2 : 1; - unsigned int other_spu_intr3 : 1; - unsigned int other_spu_intr4 : 1; - unsigned int other_spu_intr5 : 1; - unsigned int other_spu_intr6 : 1; - unsigned int other_spu_intr7 : 1; - unsigned int other_spu_intr8 : 1; - unsigned int other_spu_intr9 : 1; - unsigned int other_spu_intr10 : 1; - unsigned int other_spu_intr11 : 1; - unsigned int other_spu_intr12 : 1; - unsigned int other_spu_intr13 : 1; - unsigned int other_spu_intr14 : 1; - unsigned int other_spu_intr15 : 1; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h deleted file mode 100644 index b4095422adf6..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_timer_grp_defs_h -#define __iop_timer_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_timer_grp.r - * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r - * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_timer_grp */ - -/* Register rw_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 1; - unsigned int trig : 2; - unsigned int clk_gen_div : 8; - unsigned int clk_div : 8; - unsigned int dummy1 : 13; -} reg_iop_timer_grp_rw_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0 - -/* Register rw_half_period, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int quota_lo : 15; - unsigned int quota_hi : 15; - unsigned int quota_hi_sel : 1; - unsigned int dummy1 : 1; -} reg_iop_timer_grp_rw_half_period; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4 - -/* Register rw_half_period_len, scope iop_timer_grp, type rw */ -typedef unsigned int reg_iop_timer_grp_rw_half_period_len; -#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8 -#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8 - -#define STRIDE_iop_timer_grp_rw_tmr_cfg 4 -/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int clk_src : 3; - unsigned int strb : 2; - unsigned int run_mode : 2; - unsigned int out_mode : 1; - unsigned int active_on_tmr : 2; - unsigned int inv : 1; - unsigned int en_by_tmr : 2; - unsigned int dis_by_tmr : 2; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int rst_at_en_strb : 1; - unsigned int dummy1 : 14; -} reg_iop_timer_grp_rw_tmr_cfg; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12 - -#define STRIDE_iop_timer_grp_rw_tmr_len 4 -/* Register rw_tmr_len, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_tmr_len; -#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44 -#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44 - -/* Register rw_cmd, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int rst : 4; - unsigned int en : 4; - unsigned int dis : 4; - unsigned int strb : 4; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rw_cmd; -#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60 -#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60 - -/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */ -typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64 - -#define STRIDE_iop_timer_grp_rs_tmr_cnt 8 -/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_rs_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68 - -#define STRIDE_iop_timer_grp_r_tmr_cnt 8 -/* Register r_tmr_cnt, scope iop_timer_grp, type r */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_timer_grp_r_tmr_cnt; -#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72 - -/* Register rw_intr_mask, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100 -#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100 - -/* Register rw_ack_intr, scope iop_timer_grp, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104 -#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104 - -/* Register r_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_intr; -#define REG_RD_ADDR_iop_timer_grp_r_intr 108 - -/* Register r_masked_intr, scope iop_timer_grp, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int tmr2 : 1; - unsigned int tmr3 : 1; - unsigned int dummy1 : 28; -} reg_iop_timer_grp_r_masked_intr; -#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112 - - -/* Constants */ -enum { - regk_iop_timer_grp_clk200 = 0x00000000, - regk_iop_timer_grp_clk_gen = 0x00000002, - regk_iop_timer_grp_complete = 0x00000002, - regk_iop_timer_grp_div_clk200 = 0x00000001, - regk_iop_timer_grp_div_clk_gen = 0x00000003, - regk_iop_timer_grp_ext = 0x00000001, - regk_iop_timer_grp_hi = 0x00000000, - regk_iop_timer_grp_long_period = 0x00000001, - regk_iop_timer_grp_neg = 0x00000002, - regk_iop_timer_grp_no = 0x00000000, - regk_iop_timer_grp_once = 0x00000003, - regk_iop_timer_grp_pause = 0x00000001, - regk_iop_timer_grp_pos = 0x00000001, - regk_iop_timer_grp_pos_neg = 0x00000003, - regk_iop_timer_grp_pulse = 0x00000000, - regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004, - regk_iop_timer_grp_rw_cfg_default = 0x00000002, - regk_iop_timer_grp_rw_intr_mask_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000, - regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900, - regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200, - regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00, - regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004, - regk_iop_timer_grp_rw_tmr_len_default = 0x00000000, - regk_iop_timer_grp_rw_tmr_len_size = 0x00000004, - regk_iop_timer_grp_short_period = 0x00000000, - regk_iop_timer_grp_stop = 0x00000000, - regk_iop_timer_grp_tmr = 0x00000004, - regk_iop_timer_grp_toggle = 0x00000001, - regk_iop_timer_grp_yes = 0x00000001 -}; -#endif /* __iop_timer_grp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h deleted file mode 100644 index aff694506e7f..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_trigger_grp_defs_h -#define __iop_trigger_grp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp - * last modfied: Mon Apr 11 16:08:46 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r - * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_trigger_grp */ - -#define STRIDE_iop_trigger_grp_rw_cfg 4 -/* Register rw_cfg, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int action : 2; - unsigned int once : 1; - unsigned int trig : 3; - unsigned int en_only_by_reg : 1; - unsigned int dis_only_by_reg : 1; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cfg; -#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0 -#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0 - -/* Register rw_cmd, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int dis : 4; - unsigned int en : 4; - unsigned int dummy1 : 24; -} reg_iop_trigger_grp_rw_cmd; -#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16 -#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16 - -/* Register rw_intr_mask, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_intr_mask; -#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20 -#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20 - -/* Register rw_ack_intr, scope iop_trigger_grp, type rw */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_rw_ack_intr; -#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24 -#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24 - -/* Register r_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_intr 28 - -/* Register r_masked_intr, scope iop_trigger_grp, type r */ -typedef struct { - unsigned int trig0 : 1; - unsigned int trig1 : 1; - unsigned int trig2 : 1; - unsigned int trig3 : 1; - unsigned int dummy1 : 28; -} reg_iop_trigger_grp_r_masked_intr; -#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32 - - -/* Constants */ -enum { - regk_iop_trigger_grp_fall = 0x00000002, - regk_iop_trigger_grp_fall_lo = 0x00000006, - regk_iop_trigger_grp_no = 0x00000000, - regk_iop_trigger_grp_off = 0x00000000, - regk_iop_trigger_grp_pulse = 0x00000000, - regk_iop_trigger_grp_rise = 0x00000001, - regk_iop_trigger_grp_rise_fall = 0x00000003, - regk_iop_trigger_grp_rise_fall_hi = 0x00000007, - regk_iop_trigger_grp_rise_fall_lo = 0x00000004, - regk_iop_trigger_grp_rise_hi = 0x00000005, - regk_iop_trigger_grp_rw_cfg_default = 0x000000c0, - regk_iop_trigger_grp_rw_cfg_size = 0x00000004, - regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000, - regk_iop_trigger_grp_toggle = 0x00000003, - regk_iop_trigger_grp_yes = 0x00000001 -}; -#endif /* __iop_trigger_grp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h deleted file mode 100644 index 53a4b8cda969..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/io_proc/rtl/guinness/iop_version.r - * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp - * last modfied: Mon Apr 11 16:08:44 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r - * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v1_0 = 0x00000001 -}; -#endif /* __iop_version_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h b/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h deleted file mode 100644 index 63b20dee2fd1..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __irq_nmi_defs_h -#define __irq_nmi_defs_h - -/* - * This file is autogenerated from - * file: ../../mod/irq_nmi.r - * id: - * last modfied: Thu Jan 22 09:22:43 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r - * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope irq_nmi */ - -/* Register rw_cmd, scope irq_nmi, type rw */ -typedef struct { - unsigned int delay : 16; - unsigned int op : 2; - unsigned int dummy1 : 14; -} reg_irq_nmi_rw_cmd; -#define REG_RD_ADDR_irq_nmi_rw_cmd 0 -#define REG_WR_ADDR_irq_nmi_rw_cmd 0 - - -/* Constants */ -enum { - regk_irq_nmi_ack_irq = 0x00000002, - regk_irq_nmi_ack_nmi = 0x00000003, - regk_irq_nmi_irq = 0x00000000, - regk_irq_nmi_nmi = 0x00000001 -}; -#endif /* __irq_nmi_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h deleted file mode 100644 index da29a8a22250..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h deleted file mode 100644 index 2858de48a5e0..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h +++ /dev/null @@ -1,476 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h b/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h deleted file mode 100644 index 8fabdd211507..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Read/write register macros used by *_defs.h - */ - -#ifndef reg_rdwr_h -#define reg_rdwr_h - -#ifndef REG_READ -#define REG_READ(type, addr) (*((volatile type *) (addr))) -#endif - -#ifndef REG_WRITE -#define REG_WRITE(type, addr, val) \ - do { *((volatile type *) (addr)) = (val); } while(0) -#endif - -#endif diff --git a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h b/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h deleted file mode 100644 index ebb6bbc6e778..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __rt_trace_defs_h -#define __rt_trace_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/rt_trace/rtl/rt_regs.r - * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp - * last modfied: Mon Apr 11 16:09:14 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r - * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope rt_trace */ - -/* Register rw_cfg, scope rt_trace, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int mode : 1; - unsigned int owner : 1; - unsigned int wp : 1; - unsigned int stall : 1; - unsigned int dummy1 : 3; - unsigned int wp_start : 7; - unsigned int dummy2 : 1; - unsigned int wp_stop : 7; - unsigned int dummy3 : 9; -} reg_rt_trace_rw_cfg; -#define REG_RD_ADDR_rt_trace_rw_cfg 0 -#define REG_WR_ADDR_rt_trace_rw_cfg 0 - -/* Register rw_tap_ctrl, scope rt_trace, type rw */ -typedef struct { - unsigned int ack_data : 1; - unsigned int ack_guru : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_rw_tap_ctrl; -#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4 -#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4 - -/* Register r_tap_stat, scope rt_trace, type r */ -typedef struct { - unsigned int dav : 1; - unsigned int empty : 1; - unsigned int dummy1 : 30; -} reg_rt_trace_r_tap_stat; -#define REG_RD_ADDR_rt_trace_r_tap_stat 8 - -/* Register rw_tap_data, scope rt_trace, type rw */ -typedef unsigned int reg_rt_trace_rw_tap_data; -#define REG_RD_ADDR_rt_trace_rw_tap_data 12 -#define REG_WR_ADDR_rt_trace_rw_tap_data 12 - -/* Register rw_tap_hdata, scope rt_trace, type rw */ -typedef struct { - unsigned int op : 4; - unsigned int sub_op : 4; - unsigned int dummy1 : 24; -} reg_rt_trace_rw_tap_hdata; -#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16 -#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16 - -/* Register r_redir, scope rt_trace, type r */ -typedef unsigned int reg_rt_trace_r_redir; -#define REG_RD_ADDR_rt_trace_r_redir 20 - - -/* Constants */ -enum { - regk_rt_trace_brk = 0x0000000c, - regk_rt_trace_dbg = 0x00000003, - regk_rt_trace_dbgdi = 0x00000004, - regk_rt_trace_dbgdo = 0x00000005, - regk_rt_trace_gmode = 0x00000000, - regk_rt_trace_no = 0x00000000, - regk_rt_trace_nop = 0x00000000, - regk_rt_trace_normal = 0x00000000, - regk_rt_trace_rdmem = 0x00000007, - regk_rt_trace_rdmemb = 0x00000009, - regk_rt_trace_rdpreg = 0x00000002, - regk_rt_trace_rdreg = 0x00000001, - regk_rt_trace_rdsreg = 0x00000003, - regk_rt_trace_redir = 0x00000006, - regk_rt_trace_ret = 0x0000000b, - regk_rt_trace_rw_cfg_default = 0x00000000, - regk_rt_trace_trcfg = 0x00000001, - regk_rt_trace_wp = 0x00000001, - regk_rt_trace_wp0 = 0x00000001, - regk_rt_trace_wp1 = 0x00000002, - regk_rt_trace_wp2 = 0x00000004, - regk_rt_trace_wp3 = 0x00000008, - regk_rt_trace_wp4 = 0x00000010, - regk_rt_trace_wp5 = 0x00000020, - regk_rt_trace_wp6 = 0x00000040, - regk_rt_trace_wrmem = 0x00000008, - regk_rt_trace_wrmemb = 0x0000000a, - regk_rt_trace_wrpreg = 0x00000005, - regk_rt_trace_wrreg = 0x00000004, - regk_rt_trace_wrsreg = 0x00000006, - regk_rt_trace_yes = 0x00000001 -}; -#endif /* __rt_trace_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h deleted file mode 100644 index 3b04cf9012cf..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h +++ /dev/null @@ -1,309 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ser_defs_h -#define __ser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/ser/rtl/ser_regs.r - * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp - * last modfied: Mon Apr 11 16:09:21 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r - * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ser */ - -/* Register rw_tr_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int stop_bits : 1; - unsigned int stop : 1; - unsigned int rts_delay : 3; - unsigned int rts_setup : 1; - unsigned int auto_rts : 1; - unsigned int txd : 1; - unsigned int auto_cts : 1; - unsigned int dummy1 : 15; -} reg_ser_rw_tr_ctrl; -#define REG_RD_ADDR_ser_rw_tr_ctrl 0 -#define REG_WR_ADDR_ser_rw_tr_ctrl 0 - -/* Register rw_tr_dma_en, scope ser, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_tr_dma_en; -#define REG_RD_ADDR_ser_rw_tr_dma_en 4 -#define REG_WR_ADDR_ser_rw_tr_dma_en 4 - -/* Register rw_rec_ctrl, scope ser, type rw */ -typedef struct { - unsigned int base_freq : 3; - unsigned int en : 1; - unsigned int par : 2; - unsigned int par_en : 1; - unsigned int data_bits : 1; - unsigned int dma_mode : 1; - unsigned int dma_err : 1; - unsigned int sampling : 1; - unsigned int timeout : 3; - unsigned int auto_eop : 1; - unsigned int half_duplex : 1; - unsigned int rts_n : 1; - unsigned int loopback : 1; - unsigned int dummy1 : 14; -} reg_ser_rw_rec_ctrl; -#define REG_RD_ADDR_ser_rw_rec_ctrl 8 -#define REG_WR_ADDR_ser_rw_rec_ctrl 8 - -/* Register rw_tr_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_tr_baud_div; -#define REG_RD_ADDR_ser_rw_tr_baud_div 12 -#define REG_WR_ADDR_ser_rw_tr_baud_div 12 - -/* Register rw_rec_baud_div, scope ser, type rw */ -typedef struct { - unsigned int div : 16; - unsigned int dummy1 : 16; -} reg_ser_rw_rec_baud_div; -#define REG_RD_ADDR_ser_rw_rec_baud_div 16 -#define REG_WR_ADDR_ser_rw_rec_baud_div 16 - -/* Register rw_xoff, scope ser, type rw */ -typedef struct { - unsigned int chr : 8; - unsigned int automatic : 1; - unsigned int dummy1 : 23; -} reg_ser_rw_xoff; -#define REG_RD_ADDR_ser_rw_xoff 20 -#define REG_WR_ADDR_ser_rw_xoff 20 - -/* Register rw_xoff_clr, scope ser, type rw */ -typedef struct { - unsigned int clr : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_xoff_clr; -#define REG_RD_ADDR_ser_rw_xoff_clr 24 -#define REG_WR_ADDR_ser_rw_xoff_clr 24 - -/* Register rw_dout, scope ser, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_ser_rw_dout; -#define REG_RD_ADDR_ser_rw_dout 28 -#define REG_WR_ADDR_ser_rw_dout 28 - -/* Register rs_stat_din, scope ser, type rs */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_rs_stat_din; -#define REG_RD_ADDR_ser_rs_stat_din 32 - -/* Register r_stat_din, scope ser, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 8; - unsigned int dav : 1; - unsigned int framing_err : 1; - unsigned int par_err : 1; - unsigned int orun : 1; - unsigned int rec_err : 1; - unsigned int rxd : 1; - unsigned int tr_idle : 1; - unsigned int tr_empty : 1; - unsigned int tr_rdy : 1; - unsigned int cts_n : 1; - unsigned int xoff_detect : 1; - unsigned int rts_n : 1; - unsigned int txd : 1; - unsigned int dummy2 : 3; -} reg_ser_r_stat_din; -#define REG_RD_ADDR_ser_r_stat_din 36 - -/* Register rw_rec_eop, scope ser, type rw */ -typedef struct { - unsigned int set : 1; - unsigned int dummy1 : 31; -} reg_ser_rw_rec_eop; -#define REG_RD_ADDR_ser_rw_rec_eop 40 -#define REG_WR_ADDR_ser_rw_rec_eop 40 - -/* Register rw_intr_mask, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_intr_mask; -#define REG_RD_ADDR_ser_rw_intr_mask 44 -#define REG_WR_ADDR_ser_rw_intr_mask 44 - -/* Register rw_ack_intr, scope ser, type rw */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_rw_ack_intr; -#define REG_RD_ADDR_ser_rw_ack_intr 48 -#define REG_WR_ADDR_ser_rw_ack_intr 48 - -/* Register r_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_intr; -#define REG_RD_ADDR_ser_r_intr 52 - -/* Register r_masked_intr, scope ser, type r */ -typedef struct { - unsigned int tr_rdy : 1; - unsigned int tr_empty : 1; - unsigned int tr_idle : 1; - unsigned int dav : 1; - unsigned int dummy1 : 28; -} reg_ser_r_masked_intr; -#define REG_RD_ADDR_ser_r_masked_intr 56 - - -/* Constants */ -enum { - regk_ser_active = 0x00000000, - regk_ser_bits1 = 0x00000000, - regk_ser_bits2 = 0x00000001, - regk_ser_bits7 = 0x00000001, - regk_ser_bits8 = 0x00000000, - regk_ser_del0_5 = 0x00000000, - regk_ser_del1 = 0x00000001, - regk_ser_del1_5 = 0x00000002, - regk_ser_del2 = 0x00000003, - regk_ser_del2_5 = 0x00000004, - regk_ser_del3 = 0x00000005, - regk_ser_del3_5 = 0x00000006, - regk_ser_del4 = 0x00000007, - regk_ser_even = 0x00000000, - regk_ser_ext = 0x00000001, - regk_ser_f100 = 0x00000007, - regk_ser_f29_493 = 0x00000004, - regk_ser_f32 = 0x00000005, - regk_ser_f32_768 = 0x00000006, - regk_ser_ignore = 0x00000001, - regk_ser_inactive = 0x00000001, - regk_ser_majority = 0x00000001, - regk_ser_mark = 0x00000002, - regk_ser_middle = 0x00000000, - regk_ser_no = 0x00000000, - regk_ser_odd = 0x00000001, - regk_ser_off = 0x00000000, - regk_ser_rw_intr_mask_default = 0x00000000, - regk_ser_rw_rec_baud_div_default = 0x00000000, - regk_ser_rw_rec_ctrl_default = 0x00010000, - regk_ser_rw_tr_baud_div_default = 0x00000000, - regk_ser_rw_tr_ctrl_default = 0x00008000, - regk_ser_rw_tr_dma_en_default = 0x00000000, - regk_ser_rw_xoff_default = 0x00000000, - regk_ser_space = 0x00000003, - regk_ser_stop = 0x00000000, - regk_ser_yes = 0x00000001 -}; -#endif /* __ser_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h deleted file mode 100644 index 02971f9b6558..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h +++ /dev/null @@ -1,332 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __sser_defs_h -#define __sser_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/syncser/rtl/sser_regs.r - * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp - * last modfied: Mon Apr 11 16:09:48 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r - * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope sser */ - -/* Register rw_cfg, scope sser, type rw */ -typedef struct { - unsigned int clk_div : 16; - unsigned int base_freq : 3; - unsigned int gate_clk : 1; - unsigned int clkgate_ctrl : 1; - unsigned int clkgate_in : 1; - unsigned int clk_dir : 1; - unsigned int clk_od_mode : 1; - unsigned int out_clk_pol : 1; - unsigned int out_clk_src : 2; - unsigned int clk_in_sel : 1; - unsigned int hold_pol : 1; - unsigned int prepare : 1; - unsigned int en : 1; - unsigned int dummy1 : 1; -} reg_sser_rw_cfg; -#define REG_RD_ADDR_sser_rw_cfg 0 -#define REG_WR_ADDR_sser_rw_cfg 0 - -/* Register rw_frm_cfg, scope sser, type rw */ -typedef struct { - unsigned int wordrate : 10; - unsigned int rec_delay : 3; - unsigned int tr_delay : 3; - unsigned int early_wend : 1; - unsigned int level : 2; - unsigned int type : 1; - unsigned int clk_pol : 1; - unsigned int fr_in_rxclk : 1; - unsigned int clk_src : 1; - unsigned int out_off : 1; - unsigned int out_on : 1; - unsigned int frame_pin_dir : 1; - unsigned int frame_pin_use : 2; - unsigned int status_pin_dir : 1; - unsigned int status_pin_use : 2; - unsigned int dummy1 : 1; -} reg_sser_rw_frm_cfg; -#define REG_RD_ADDR_sser_rw_frm_cfg 4 -#define REG_WR_ADDR_sser_rw_frm_cfg 4 - -/* Register rw_tr_cfg, scope sser, type rw */ -typedef struct { - unsigned int tr_en : 1; - unsigned int stop : 1; - unsigned int urun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 1; - unsigned int use60958 : 1; - unsigned int iec60958_ckdiv : 2; - unsigned int rate_ctrl : 1; - unsigned int use_md : 1; - unsigned int dual_i2s : 1; - unsigned int data_pin_use : 2; - unsigned int od_mode : 1; - unsigned int bulk_wspace : 2; - unsigned int dummy1 : 4; -} reg_sser_rw_tr_cfg; -#define REG_RD_ADDR_sser_rw_tr_cfg 8 -#define REG_WR_ADDR_sser_rw_tr_cfg 8 - -/* Register rw_rec_cfg, scope sser, type rw */ -typedef struct { - unsigned int rec_en : 1; - unsigned int force_eop : 1; - unsigned int stop : 1; - unsigned int orun_stop : 1; - unsigned int eop_stop : 1; - unsigned int sample_size : 6; - unsigned int sh_dir : 1; - unsigned int clk_pol : 1; - unsigned int clk_src : 1; - unsigned int use_dma : 1; - unsigned int mode : 2; - unsigned int frm_src : 2; - unsigned int use60958 : 1; - unsigned int iec60958_ui_len : 5; - unsigned int slave2_en : 1; - unsigned int slave3_en : 1; - unsigned int fifo_thr : 2; - unsigned int dummy1 : 3; -} reg_sser_rw_rec_cfg; -#define REG_RD_ADDR_sser_rw_rec_cfg 12 -#define REG_WR_ADDR_sser_rw_rec_cfg 12 - -/* Register rw_tr_data, scope sser, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int dummy1 : 15; -} reg_sser_rw_tr_data; -#define REG_RD_ADDR_sser_rw_tr_data 16 -#define REG_WR_ADDR_sser_rw_tr_data 16 - -/* Register r_rec_data, scope sser, type r */ -typedef struct { - unsigned int data : 16; - unsigned int md : 1; - unsigned int ext_clk : 1; - unsigned int status_in : 1; - unsigned int frame_in : 1; - unsigned int din : 1; - unsigned int data_in : 1; - unsigned int clk_in : 1; - unsigned int dummy1 : 9; -} reg_sser_r_rec_data; -#define REG_RD_ADDR_sser_r_rec_data 20 - -/* Register rw_extra, scope sser, type rw */ -typedef struct { - unsigned int clkoff_cycles : 20; - unsigned int clkoff_en : 1; - unsigned int clkon_en : 1; - unsigned int dout_delay : 5; - unsigned int dummy1 : 5; -} reg_sser_rw_extra; -#define REG_RD_ADDR_sser_rw_extra 24 -#define REG_WR_ADDR_sser_rw_extra 24 - -/* Register rw_intr_mask, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_intr_mask; -#define REG_RD_ADDR_sser_rw_intr_mask 28 -#define REG_WR_ADDR_sser_rw_intr_mask 28 - -/* Register rw_ack_intr, scope sser, type rw */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_rw_ack_intr; -#define REG_RD_ADDR_sser_rw_ack_intr 32 -#define REG_WR_ADDR_sser_rw_ack_intr 32 - -/* Register r_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_intr; -#define REG_RD_ADDR_sser_r_intr 36 - -/* Register r_masked_intr, scope sser, type r */ -typedef struct { - unsigned int trdy : 1; - unsigned int rdav : 1; - unsigned int tidle : 1; - unsigned int rstop : 1; - unsigned int urun : 1; - unsigned int orun : 1; - unsigned int md_rec : 1; - unsigned int md_sent : 1; - unsigned int r958err : 1; - unsigned int dummy1 : 23; -} reg_sser_r_masked_intr; -#define REG_RD_ADDR_sser_r_masked_intr 40 - - -/* Constants */ -enum { - regk_sser_both = 0x00000002, - regk_sser_bulk = 0x00000001, - regk_sser_clk100 = 0x00000000, - regk_sser_clk_in = 0x00000000, - regk_sser_const0 = 0x00000003, - regk_sser_dout = 0x00000002, - regk_sser_edge = 0x00000000, - regk_sser_ext = 0x00000001, - regk_sser_ext_clk = 0x00000001, - regk_sser_f100 = 0x00000000, - regk_sser_f29_493 = 0x00000004, - regk_sser_f32 = 0x00000005, - regk_sser_f32_768 = 0x00000006, - regk_sser_frm = 0x00000003, - regk_sser_gio0 = 0x00000000, - regk_sser_gio1 = 0x00000001, - regk_sser_hispeed = 0x00000001, - regk_sser_hold = 0x00000002, - regk_sser_in = 0x00000000, - regk_sser_inf = 0x00000003, - regk_sser_intern = 0x00000000, - regk_sser_intern_clk = 0x00000001, - regk_sser_intern_tb = 0x00000000, - regk_sser_iso = 0x00000000, - regk_sser_level = 0x00000001, - regk_sser_lospeed = 0x00000000, - regk_sser_lsbfirst = 0x00000000, - regk_sser_msbfirst = 0x00000001, - regk_sser_neg = 0x00000001, - regk_sser_neg_lo = 0x00000000, - regk_sser_no = 0x00000000, - regk_sser_no_clk = 0x00000007, - regk_sser_nojitter = 0x00000002, - regk_sser_out = 0x00000001, - regk_sser_pos = 0x00000000, - regk_sser_pos_hi = 0x00000001, - regk_sser_rec = 0x00000000, - regk_sser_rw_cfg_default = 0x00000000, - regk_sser_rw_extra_default = 0x00000000, - regk_sser_rw_frm_cfg_default = 0x00000000, - regk_sser_rw_intr_mask_default = 0x00000000, - regk_sser_rw_rec_cfg_default = 0x00000000, - regk_sser_rw_tr_cfg_default = 0x01800000, - regk_sser_rw_tr_data_default = 0x00000000, - regk_sser_thr16 = 0x00000001, - regk_sser_thr32 = 0x00000002, - regk_sser_thr8 = 0x00000000, - regk_sser_tr = 0x00000001, - regk_sser_ts_out = 0x00000003, - regk_sser_tx_bulk = 0x00000002, - regk_sser_wiresave = 0x00000002, - regk_sser_yes = 0x00000001 -}; -#endif /* __sser_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop.h b/arch/cris/include/arch-v32/arch/hwregs/strcop.h deleted file mode 100644 index 2c522b024ee7..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/strcop.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $ - -// Streamcop meta-data configuration structs - -struct strcop_meta_out { - unsigned char csumsel : 3; - unsigned char ciphsel : 3; - unsigned char ciphconf : 2; - unsigned char hashsel : 3; - unsigned char hashconf : 1; - unsigned char hashmode : 1; - unsigned char decrypt : 1; - unsigned char dlkey : 1; - unsigned char cbcmode : 1; -}; - -struct strcop_meta_in { - unsigned char dmasel : 3; - unsigned char sync : 1; - unsigned char res1 : 5; - unsigned char res2; -}; - -// Source definitions - -enum { - src_none = 0, - src_dma = 1, - src_des = 2, - src_sha1 = 3, - src_csum = 4, - src_aes = 5, - src_md5 = 6, - src_res = 7 -}; - -// Cipher definitions - -enum { - ciph_des = 0, - ciph_3des = 1, - ciph_aes = 2 -}; - -// Hash definitions - -enum { - hash_sha1 = 0, - hash_md5 = 1 -}; - -enum { - hash_noiv = 0, - hash_iv = 1 -}; - - diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h b/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h deleted file mode 100644 index 069b2ed9def5..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __strcop_defs_h -#define __strcop_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strcop/rtl/strcop_regs.r - * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp - * last modfied: Mon Apr 11 16:09:38 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r - * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strcop */ - -/* Register rw_cfg, scope strcop, type rw */ -typedef struct { - unsigned int td3 : 1; - unsigned int td2 : 1; - unsigned int td1 : 1; - unsigned int ipend : 1; - unsigned int ignore_sync : 1; - unsigned int en : 1; - unsigned int dummy1 : 26; -} reg_strcop_rw_cfg; -#define REG_RD_ADDR_strcop_rw_cfg 0 -#define REG_WR_ADDR_strcop_rw_cfg 0 - - -/* Constants */ -enum { - regk_strcop_big = 0x00000001, - regk_strcop_d = 0x00000001, - regk_strcop_e = 0x00000000, - regk_strcop_little = 0x00000000, - regk_strcop_rw_cfg_default = 0x00000002 -}; -#endif /* __strcop_defs_h */ diff --git a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h deleted file mode 100644 index c3fa0c06c558..000000000000 --- a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __SUPP_REG_H__ -#define __SUPP_REG_H__ - -/* Macros for reading and writing support/special registers. */ - -#ifndef STRINGIFYFY -#define STRINGIFYFY(i) #i -#endif - -#ifndef STRINGIFY -#define STRINGIFY(i) STRINGIFYFY(i) -#endif - -#define SPEC_REG_BZ "BZ" -#define SPEC_REG_VR "VR" -#define SPEC_REG_PID "PID" -#define SPEC_REG_SRS "SRS" -#define SPEC_REG_WZ "WZ" -#define SPEC_REG_EXS "EXS" -#define SPEC_REG_EDA "EDA" -#define SPEC_REG_MOF "MOF" -#define SPEC_REG_DZ "DZ" -#define SPEC_REG_EBP "EBP" -#define SPEC_REG_ERP "ERP" -#define SPEC_REG_SRP "SRP" -#define SPEC_REG_NRP "NRP" -#define SPEC_REG_CCS "CCS" -#define SPEC_REG_USP "USP" -#define SPEC_REG_SPC "SPC" - -#define RW_MM_CFG 0 -#define RW_MM_KBASE_LO 1 -#define RW_MM_KBASE_HI 2 -#define RW_MM_CAUSE 3 -#define RW_MM_TLB_SEL 4 -#define RW_MM_TLB_LO 5 -#define RW_MM_TLB_HI 6 -#define RW_MM_TLB_PGD 7 - -#define BANK_GC 0 -#define BANK_IM 1 -#define BANK_DM 2 -#define BANK_BP 3 - -#define RW_GC_CFG 0 -#define RW_GC_CCS 1 -#define RW_GC_SRS 2 -#define RW_GC_NRP 3 -#define RW_GC_EXS 4 -#define RW_GC_R0 8 -#define RW_GC_R1 9 - -#define SPEC_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $" r : : "r" (v)); - -#define SPEC_REG_RD(r,v) \ -__asm__ __volatile__ ("move $" r ",%0" : "=r" (v)); - -#define NOP() \ - __asm__ __volatile__ ("nop"); - -#define SUPP_BANK_SEL(b) \ - SPEC_REG_WR(SPEC_REG_SRS,b); \ - NOP(); \ - NOP(); \ - NOP(); - -#define SUPP_REG_WR(r,v) \ -__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - "nop\n\t" \ - : : "r" (v)); - -#define SUPP_REG_RD(r,v) \ -__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v)); - -#endif /* __SUPP_REG_H__ */ diff --git a/arch/cris/include/arch-v32/arch/intmem.h b/arch/cris/include/arch-v32/arch/intmem.h deleted file mode 100644 index 2bcb21c9b25f..000000000000 --- a/arch/cris/include/arch-v32/arch/intmem.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_INTMEM_H -#define _ASM_CRIS_INTMEM_H - -void* crisv32_intmem_alloc(unsigned size, unsigned align); -void crisv32_intmem_free(void* addr); -void* crisv32_intmem_phys_to_virt(unsigned long addr); -unsigned long crisv32_intmem_virt_to_phys(void *addr); - -#endif /* _ASM_CRIS_ARCH_INTMEM_H */ diff --git a/arch/cris/include/arch-v32/arch/irq.h b/arch/cris/include/arch-v32/arch/irq.h deleted file mode 100644 index 5259084001d4..000000000000 --- a/arch/cris/include/arch-v32/arch/irq.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_IRQ_H -#define _ASM_ARCH_IRQ_H - -#include - -/* Number of non-cpu interrupts. */ -#define NR_IRQS (NBR_INTR_VECT + 256) /* Exceptions + IRQs */ -#define FIRST_IRQ 0x31 /* Exception number for first IRQ */ -#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */ -#if NR_REAL_IRQS > 32 -#define MACH_IRQS 64 -#else -#define MACH_IRQS 32 -#endif - -#ifndef __ASSEMBLY__ -/* Global IRQ vector. */ -typedef void (*irqvectptr)(void); - -struct etrax_interrupt_vector { - irqvectptr v[256]; -}; - -extern struct etrax_interrupt_vector *etrax_irv; /* head.S */ - -void crisv32_mask_irq(int irq); -void crisv32_unmask_irq(int irq); - -void set_exception_vector(int n, irqvectptr addr); - -/* Save registers so that they match pt_regs. */ -#define SAVE_ALL \ - "subq 12,$sp\n\t" \ - "move $erp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srp,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $ccs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $spc,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $mof,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move $srs,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $acr,[$sp]\n\t" \ - "subq 14*4,$sp\n\t" \ - "movem $r13,[$sp]\n\t" \ - "subq 4,$sp\n\t" \ - "move.d $r10,[$sp]\n" - -#define STR2(x) #x -#define STR(x) STR2(x) - -#define IRQ_NAME2(nr) nr##_interrupt(void) -#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr) - -/* - * The reason for setting the S-bit when debugging the kernel is that we want - * hardware breakpoints to remain active while we are in an exception handler. - * Note that we cannot simply copy S1, since we may come here from user-space, - * or any context where the S-bit wasn't set. - */ -#ifdef CONFIG_ETRAX_KGDB -#define KGDB_FIXUP \ - "move $ccs, $r10\n\t" \ - "or.d (1<<9), $r10\n\t" \ - "move $r10, $ccs\n\t" -#else -#define KGDB_FIXUP "" -#endif - -/* - * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock - * and jump to ret_from_intr which is found in entry.S. - * - * The reason for blocking the IRQ is to allow an sti() before the handler, - * which will acknowledge the interrupt, is run. The actual blocking is made - * by crisv32_do_IRQ. - */ -#define BUILD_IRQ(nr) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp, $r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 1, $r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); -/* - * This is subtle. The timer interrupt is crucial and it should not be disabled - * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it - * would have been BLOCK'ed, and then softirq's are run before we return here to - * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run - * and the watchdog will kill us. - * - * Furthermore, if a lot of other irq's occur before we return here, the - * multiple_irq handler is run and it prioritizes the timer interrupt. However - * if we had BLOCK'edit here, we would not get the multiple_irq at all. - * - * The non-blocking here is based on the knowledge that the timer interrupt runs - * with interrupts disabled, and therefore there will not be an sti() before the - * timer irq handler is run to acknowledge the interrupt. - */ -#define BUILD_TIMER_IRQ(nr, mask) \ -void IRQ_NAME(nr); \ -__asm__ ( \ - ".text\n\t" \ - "IRQ" #nr "_interrupt:\n\t" \ - SAVE_ALL \ - KGDB_FIXUP \ - "move.d "#nr",$r10\n\t" \ - "move.d $sp,$r12\n\t" \ - "jsr crisv32_do_IRQ\n\t" \ - "moveq 0,$r11\n\t" \ - "jump ret_from_intr\n\t" \ - "nop\n\t"); - -#endif /* __ASSEMBLY__ */ -#endif /* _ASM_ARCH_IRQ_H */ diff --git a/arch/cris/include/arch-v32/arch/irqflags.h b/arch/cris/include/arch-v32/arch/irqflags.h deleted file mode 100644 index d55bf82de77c..000000000000 --- a/arch/cris/include/arch-v32/arch/irqflags.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H -#define __ASM_CRIS_ARCH_IRQFLAGS_H - -#include -#include - -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - asm volatile("move $ccs,%0" : "=rm" (flags) : : "memory"); - return flags; -} - -static inline void arch_local_irq_disable(void) -{ - asm volatile("di" : : : "memory"); -} - -static inline void arch_local_irq_enable(void) -{ - asm volatile("ei" : : : "memory"); -} - -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags = arch_local_save_flags(); - arch_local_irq_disable(); - return flags; -} - -static inline void arch_local_irq_restore(unsigned long flags) -{ - asm volatile("move %0,$ccs" : : "rm" (flags) : "memory"); -} - -static inline bool arch_irqs_disabled_flags(unsigned long flags) -{ - return !(flags & (1 << I_CCS_BITNR)); -} - -static inline bool arch_irqs_disabled(void) -{ - return arch_irqs_disabled_flags(arch_local_save_flags()); -} - -#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */ diff --git a/arch/cris/include/arch-v32/arch/memmap.h b/arch/cris/include/arch-v32/arch/memmap.h deleted file mode 100644 index 81985c0a6789..000000000000 --- a/arch/cris/include/arch-v32/arch/memmap.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/arch-v32/arch/mmu.h b/arch/cris/include/arch-v32/arch/mmu.h deleted file mode 100644 index a8eec1312de0..000000000000 --- a/arch/cris/include/arch-v32/arch/mmu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_MMU_H -#define _ASM_CRIS_ARCH_MMU_H - -/* MMU context type. */ -typedef struct -{ - unsigned int page_id; -} mm_context_t; - -/* Kernel memory segments. */ -#define KSEG_F 0xf0000000UL -#define KSEG_E 0xe0000000UL -#define KSEG_D 0xd0000000UL -#define KSEG_C 0xc0000000UL -#define KSEG_B 0xb0000000UL -#define KSEG_A 0xa0000000UL -#define KSEG_9 0x90000000UL -#define KSEG_8 0x80000000UL -#define KSEG_7 0x70000000UL -#define KSEG_6 0x60000000UL -#define KSEG_5 0x50000000UL -#define KSEG_4 0x40000000UL -#define KSEG_3 0x30000000UL -#define KSEG_2 0x20000000UL -#define KSEG_1 0x10000000UL -#define KSEG_0 0x00000000UL - -/* - * CRISv32 PTE bits: - * - * Bit: 31 30-13 12-5 4 3 2 1 0 - * +-------+-----+------+--------+-------+--------+-------+---------+ - * | cache | pfn | zero | global | valid | kernel | write | execute | - * +-------+-----+------+--------+-------+--------+-------+---------+ - */ - -/* - * Defines for accessing the bits. Also define some synonyms for use with - * the software-based defined bits below. - */ -#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */ -#define _PAGE_WE (1 << 1) /* Write bit. */ -#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */ -#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */ -#define _PAGE_VALID (1 << 3) /* Page is valid. */ -#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */ -#define _PAGE_GLOBAL (1 << 4) /* Global page. */ -#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */ - - -/* - * The hardware doesn't care about these bits, but the kernel uses them in - * software. - */ -#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */ -#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */ -#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */ -#define _PAGE_READ (1 << 8) /* Read enabled. */ -#define _PAGE_WRITE (1 << 9) /* Write enabled. */ - -/* Define some higher level generic page attributes. */ -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) -#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) - -#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) - -#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED) -#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ - _PAGE_ACCESSED | _PAGE_EXECUTE) - -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED) - -#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) -#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE) -#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE | __WRITEABLE) -#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \ - _PAGE_PRESENT | __READABLE) - -#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) - -/* CRISv32 can do page protection for execute. - * Write permissions imply read permissions. - * Note that the numbers are in Execute-Write-Read order! - */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READONLY -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_READONLY_EXEC -#define __P101 PAGE_READONLY_EXEC -#define __P110 PAGE_COPY_EXEC -#define __P111 PAGE_COPY_EXEC - -#define __S000 PAGE_NONE -#define __S001 PAGE_READONLY -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY_EXEC -#define __S101 PAGE_READONLY_EXEC -#define __S110 PAGE_SHARED_EXEC -#define __S111 PAGE_SHARED_EXEC - -#endif /* _ASM_CRIS_ARCH_MMU_H */ diff --git a/arch/cris/include/arch-v32/arch/offset.h b/arch/cris/include/arch-v32/arch/offset.h deleted file mode 100644 index 10a670443386..000000000000 --- a/arch/cris/include/arch-v32/arch/offset.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_OFFSETS_H__ -#define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by arch/cris/Makefile - * - */ - -#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */ -#define PT_r13 56 /* offsetof(struct pt_regs, r13) */ -#define PT_r12 52 /* offsetof(struct pt_regs, r12) */ -#define PT_r11 48 /* offsetof(struct pt_regs, r11) */ -#define PT_r10 44 /* offsetof(struct pt_regs, r10) */ -#define PT_r9 40 /* offsetof(struct pt_regs, r9) */ -#define PT_acr 60 /* offsetof(struct pt_regs, acr) */ -#define PT_srs 64 /* offsetof(struct pt_regs, srs) */ -#define PT_mof 68 /* offsetof(struct pt_regs, mof) */ -#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */ -#define PT_srp 80 /* offsetof(struct pt_regs, srp) */ - -#define TI_task 0 /* offsetof(struct thread_info, task) */ -#define TI_flags 8 /* offsetof(struct thread_info, flags) */ -#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */ - -#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */ -#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */ -#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */ - -#define TASK_pid 151 /* offsetof(struct task_struct, pid) */ - -#define LCLONE_VM 256 /* CLONE_VM */ -#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */ - -#endif diff --git a/arch/cris/include/arch-v32/arch/page.h b/arch/cris/include/arch-v32/arch/page.h deleted file mode 100644 index 7ac04f615193..000000000000 --- a/arch/cris/include/arch-v32/arch/page.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_PAGE_H -#define _ASM_CRIS_ARCH_PAGE_H - - -#ifdef __KERNEL__ - -#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */ - -/* - * Macros to convert between physical and virtual addresses. By stripping a - * selected bit it's possible to convert between KSEG_x and 0x40000000 where the - * DRAM really resides. DRAM is virtually at 0xc. - */ -#define __pa(x) ((unsigned long)(x) & 0x7fffffff) -#define __va(x) ((void *)((unsigned long)(x) | 0x80000000)) - -#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ - VM_MAYREAD | VM_MAYWRITE) - -#endif /* __KERNEL__ */ - -#endif /* _ASM_CRIS_ARCH_PAGE_H */ diff --git a/arch/cris/include/arch-v32/arch/pgtable.h b/arch/cris/include/arch-v32/arch/pgtable.h deleted file mode 100644 index e787b19b700e..000000000000 --- a/arch/cris/include/arch-v32/arch/pgtable.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_PGTABLE_H -#define _ASM_CRIS_ARCH_PGTABLE_H - -/* Define the kernels virtual memory area. */ - -/* See head.S for differences between ARTPEC-3 and ETRAX FS. */ -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -#define VMALLOC_START KSEG_E -#define VMALLOC_END KSEG_F -#else -#define VMALLOC_START KSEG_D -#define VMALLOC_END KSEG_E -#endif - -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) - -#endif /* _ASM_CRIS_ARCH_PGTABLE_H */ diff --git a/arch/cris/include/arch-v32/arch/processor.h b/arch/cris/include/arch-v32/arch/processor.h deleted file mode 100644 index 554088ab5f01..000000000000 --- a/arch/cris/include/arch-v32/arch/processor.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_PROCESSOR_H -#define _ASM_CRIS_ARCH_PROCESSOR_H - - -/* Return current instruction pointer. */ -#define current_text_addr() \ - ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;}) - -/* - * Since CRIS doesn't do hardware task-switching this hasn't really anything to - * do with the proccessor itself, it's just here for legacy reasons. This is - * used when task-switching using _resume defined in entry.S. The offsets here - * are hardcoded into _resume, so if this struct is changed, entry.S needs to be - * changed as well. - */ -struct thread_struct { - unsigned long ksp; /* Kernel stack pointer. */ - unsigned long usp; /* User stack pointer. */ - unsigned long ccs; /* Saved flags register. */ -}; - -/* - * User-space process size. This is hardcoded into a few places, so don't - * change it unless everything's clear! - */ -#define TASK_SIZE (0xB0000000UL) - -#define INIT_THREAD { } - -#define KSTK_EIP(tsk) \ -({ \ - unsigned long eip = 0; \ - unsigned long regs = (unsigned long)task_pt_regs(tsk); \ - if (regs > PAGE_SIZE && virt_addr_valid(regs)) \ - eip = ((struct pt_regs *)regs)->erp; \ - eip; \ -}) - -/* - * Give the thread a program location, set user-mode and switch user - * stackpointer. - */ -#define start_thread(regs, ip, usp) \ -do { \ - regs->erp = ip; \ - regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \ - wrusp(usp); \ -} while(0) - -/* Nothing special to do for v32 when handling a kernel bus fault fixup. */ -#define arch_fixup(regs) {}; - -#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */ diff --git a/arch/cris/include/arch-v32/arch/swab.h b/arch/cris/include/arch-v32/arch/swab.h deleted file mode 100644 index 280dd7093e4f..000000000000 --- a/arch/cris/include/arch-v32/arch/swab.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_SWAB_H -#define _ASM_CRIS_ARCH_SWAB_H - -#include - -#define __SWAB_64_THRU_32__ - -static inline __const__ __u32 -__arch_swab32(__u32 x) -{ - __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x)); - return (x); -} -#define __arch_swab32 __arch_swab32 - -static inline __const__ __u16 -__arch_swab16(__u16 x) -{ - __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x)); - return (x); -} -#define __arch_swab16 __arch_swab16 - -#endif /* _ASM_CRIS_ARCH_SWAB_H */ diff --git a/arch/cris/include/arch-v32/arch/system.h b/arch/cris/include/arch-v32/arch/system.h deleted file mode 100644 index 84f00e5d4652..000000000000 --- a/arch/cris/include/arch-v32/arch/system.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_SYSTEM_H -#define _ASM_CRIS_ARCH_SYSTEM_H - - -/* Read the CPU version register. */ -static inline unsigned long rdvr(void) -{ - unsigned char vr; - - __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr)); - return vr; -} - -#define cris_machine_name "crisv32" - -/* Read the user-mode stack pointer. */ -static inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp)); - return usp; -} - -/* Read the current stack pointer. */ -static inline unsigned long rdsp(void) -{ - unsigned long sp; - - __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp)); - return sp; -} - -/* Write the user-mode stack pointer. */ -#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp)) - -#endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/arch/cris/include/arch-v32/arch/thread_info.h b/arch/cris/include/arch-v32/arch/thread_info.h deleted file mode 100644 index 8514669e5fab..000000000000 --- a/arch/cris/include/arch-v32/arch/thread_info.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H -#define _ASM_CRIS_ARCH_THREAD_INFO_H - -/* Return a thread_info struct. */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - - __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL)); - return ti; -} - -#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */ diff --git a/arch/cris/include/arch-v32/arch/timex.h b/arch/cris/include/arch-v32/arch/timex.h deleted file mode 100644 index 2cd8e704a73b..000000000000 --- a/arch/cris/include/arch-v32/arch/timex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_TIMEX_H -#define _ASM_CRIS_ARCH_TIMEX_H - -#include -#include -#include - -/* - * The clock runs at 100MHz, we divide it by 1000000. If you change anything - * here you must check time.c as well. - */ - -#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */ - -/* The timer0 values gives 10 ns resolution but interrupts at HZ. */ -#define TIMER0_FREQ (CLOCK_TICK_RATE) -#define TIMER0_DIV (TIMER0_FREQ/(HZ)) - -/* Convert the value in step of 10 ns to 1us without overflow: */ -#define GET_JIFFIES_USEC() \ - ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100) - -extern unsigned long get_ns_in_jiffie(void); - -static inline unsigned long get_us_in_jiffie_highres(void) -{ - return get_ns_in_jiffie() / 1000; -} - -#endif - diff --git a/arch/cris/include/arch-v32/arch/tlb.h b/arch/cris/include/arch-v32/arch/tlb.h deleted file mode 100644 index 50452802738f..000000000000 --- a/arch/cris/include/arch-v32/arch/tlb.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_ARCH_TLB_H -#define _CRIS_ARCH_TLB_H - -/* - * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used - * to store the "process" it belongs to (=> fast mm context switch). The - * last page_id is never used so we can make TLB entries that never matches. - */ -#define NUM_TLB_ENTRIES 64 -#define NUM_PAGEID 256 -#define INVALID_PAGEID 255 -#define NO_CONTEXT -1 - -#endif /* _CRIS_ARCH_TLB_H */ diff --git a/arch/cris/include/arch-v32/arch/uaccess.h b/arch/cris/include/arch-v32/arch/uaccess.h deleted file mode 100644 index 214bd26efcd9..000000000000 --- a/arch/cris/include/arch-v32/arch/uaccess.h +++ /dev/null @@ -1,730 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Authors: Hans-Peter Nilsson (hp@axis.com) - * - */ -#ifndef _CRIS_ARCH_UACCESS_H -#define _CRIS_ARCH_UACCESS_H - -/* - * We don't tell gcc that we are accessing memory, but this is OK - * because we do not write to any memory gcc knows about, so there - * are no aliasing issues. - * - * Note that PC at a fault is the address *at* the faulting - * instruction for CRISv32. - */ -#define __put_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" %1,[%2]\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " nop\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err) \ - : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __put_user_asm_64(x, addr, err) do { \ - int dummy_for_put_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d %M2,[%1+]\n" \ - "4: move.d %H2,[%1]\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \ - : "r" (x), "1" (addr), "g" (-EFAULT), \ - "0" (err)); \ - } while (0) - -/* See comment before __put_user_asm. */ - -#define __get_user_asm(x, addr, err, op) \ - __asm__ __volatile__( \ - "2: "op" [%2],%1\n" \ - "4:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %3,%0\n" \ - " jump 4b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x) \ - : "r" (addr), "g" (-EFAULT), "0" (err)) - -#define __get_user_asm_64(x, addr, err) do { \ - int dummy_for_get_user_asm_64_; \ - __asm__ __volatile__( \ - "2: move.d [%2+],%M1\n" \ - "4: move.d [%2],%H1\n" \ - "5:\n" \ - " .section .fixup,\"ax\"\n" \ - "3: move.d %4,%0\n" \ - " jump 5b\n" \ - " moveq 0,%1\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .dword 2b,3b\n" \ - " .dword 4b,3b\n" \ - " .previous\n" \ - : "=r" (err), "=r" (x), \ - "=b" (dummy_for_get_user_asm_64_) \ - : "2" (addr), "g" (-EFAULT), "0" (err));\ - } while (0) - -/* - * Copy a null terminated string from userspace. - * - * Must return: - * -EFAULT for an exception - * count if we hit the buffer limit - * bytes copied if we hit a null byte - * (without the null byte) - */ -static inline long -__do_strncpy_from_user(char *dst, const char *src, long count) -{ - long res; - - if (count == 0) - return 0; - - /* - * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop. - * So do we. - * - * This code is deduced from: - * - * char tmp2; - * long tmp1, tmp3; - * tmp1 = count; - * while ((*dst++ = (tmp2 = *src++)) != 0 - * && --tmp1) - * ; - * - * res = count - tmp1; - * - * with tweaks. - */ - - __asm__ __volatile__ ( - " move.d %3,%0\n" - "5: move.b [%2+],$acr\n" - "1: beq 6f\n" - " move.b $acr,[%1+]\n" - - " subq 1,%0\n" - "2: bne 1b\n" - " move.b [%2+],$acr\n" - - "6: sub.d %3,%0\n" - " neg.d %0,%0\n" - "3:\n" - " .section .fixup,\"ax\"\n" - "4: move.d %7,%0\n" - " jump 3b\n" - " nop\n" - - /* The address for a fault at the first move is trivial. - The address for a fault at the second move is that of - the preceding branch insn, since the move insn is in - its delay-slot. Just so you don't get confused... */ - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 5b,4b\n" - " .dword 2b,4b\n" - " .previous" - : "=r" (res), "=b" (dst), "=b" (src), "=r" (count) - : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT) - : "acr"); - - return res; -} - -/* A few copy asms to build up the more complex ones from. - - Note again, a post-increment is performed regardless of whether a bus - fault occurred in that instruction, and PC for a faulted insn is the - address for the insn, or for the preceding branch when in a delay-slot. */ - -#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - COPY \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous\n" \ - : "=b" (to), "=b" (from), "=r" (ret) \ - : "0" (to), "1" (from), "2" (ret) \ - : "acr", "memory") - -#define __asm_copy_from_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - "2: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "3: addq 1,%2\n" \ - " jump 1b\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "3: addq 2,%2\n" \ - " jump 1b\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_2(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_3(to, from, ret) \ - __asm_copy_from_user_2x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - "2: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "3: addq 4,%2\n" \ - " jump 1b\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_from_user_4(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_5(to, from, ret) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - "4: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_6(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_7(to, from, ret) \ - __asm_copy_from_user_6x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_4x_cont(to, from, ret, \ - COPY \ - "4: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_from_user_8(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_9(to, from, ret) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - "6: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_10(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_11(to, from, ret) \ - __asm_copy_from_user_10x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_8x_cont(to, from, ret, \ - COPY \ - "6: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_from_user_12(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_13(to, from, ret) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - "8: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.w [%1+],$acr\n" \ - " move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_14(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_15(to, from, ret) \ - __asm_copy_from_user_14x_cont(to, from, ret, \ - "10: move.b [%1+],$acr\n" \ - " move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_12x_cont(to, from, ret, \ - COPY \ - "8: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_from_user_16(to, from, ret) \ - __asm_copy_from_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_16x_cont(to, from, ret, \ - COPY \ - "10: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_from_user_20(to, from, ret) \ - __asm_copy_from_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_from_user_20x_cont(to, from, ret, \ - COPY \ - "12: move.d [%1+],$acr\n" \ - " move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_from_user_24(to, from, ret) \ - __asm_copy_from_user_24x_cont(to, from, ret, "", "", "") - -/* And now, the to-user ones. */ - -#define __asm_copy_to_user_1(to, from, ret) \ - __asm_copy_user_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "2: move.b $acr,[%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%2\n", \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "2: move.w $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 2,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_2(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_3(to, from, ret) \ - __asm_copy_to_user_2x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_user_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "2: move.d $acr,[%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%2\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_copy_to_user_4(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_5(to, from, ret) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "4: move.b $acr,[%0+]\n", \ - "5: addq 1,%2\n", \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "4: move.w $acr,[%0+]\n", \ - FIXUP \ - "5: addq 2,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_6(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_7(to, from, ret) \ - __asm_copy_to_user_6x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_4x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "4: move.d $acr,[%0+]\n", \ - FIXUP \ - "5: addq 4,%2\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_copy_to_user_8(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_9(to, from, ret) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "6: move.b $acr,[%0+]\n", \ - "7: addq 1,%2\n", \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "6: move.w $acr,[%0+]\n", \ - FIXUP \ - "7: addq 2,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_10(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_11(to, from, ret) \ - __asm_copy_to_user_10x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_8x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "6: move.d $acr,[%0+]\n", \ - FIXUP \ - "7: addq 4,%2\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_copy_to_user_12(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_13(to, from, ret) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "8: move.b $acr,[%0+]\n", \ - "9: addq 1,%2\n", \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.w [%1+],$acr\n" \ - "8: move.w $acr,[%0+]\n", \ - FIXUP \ - "9: addq 2,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_14(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_15(to, from, ret) \ - __asm_copy_to_user_14x_cont(to, from, ret, \ - " move.b [%1+],$acr\n" \ - "10: move.b $acr,[%0+]\n", \ - "11: addq 1,%2\n", \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_12x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "8: move.d $acr,[%0+]\n", \ - FIXUP \ - "9: addq 4,%2\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_copy_to_user_16(to, from, ret) \ - __asm_copy_to_user_16x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_16x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "10: move.d $acr,[%0+]\n", \ - FIXUP \ - "11: addq 4,%2\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_copy_to_user_20(to, from, ret) \ - __asm_copy_to_user_20x_cont(to, from, ret, "", "", "") - -#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \ - __asm_copy_to_user_20x_cont(to, from, ret, \ - COPY \ - " move.d [%1+],$acr\n" \ - "12: move.d $acr,[%0+]\n", \ - FIXUP \ - "13: addq 4,%2\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_copy_to_user_24(to, from, ret) \ - __asm_copy_to_user_24x_cont(to, from, ret, "", "", "") - -/* Define a few clearing asms with exception handlers. */ - -/* This frame-asm is like the __asm_copy_user_cont one, but has one less - input. */ - -#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm__ __volatile__ ( \ - CLEAR \ - "1:\n" \ - " .section .fixup,\"ax\"\n" \ - FIXUP \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - TENTRY \ - " .previous" \ - : "=b" (to), "=r" (ret) \ - : "0" (to), "1" (ret) \ - : "memory") - -#define __asm_clear_1(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.b [%0+]\n", \ - "3: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_2(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n", \ - "3: jump 1b\n" \ - " addq 2,%1\n", \ - " .dword 2b,3b\n") - -#define __asm_clear_3(to, ret) \ - __asm_clear(to, ret, \ - "2: clear.w [%0+]\n" \ - "3: clear.b [%0+]\n", \ - "4: addq 2,%1\n" \ - "5: jump 1b\n" \ - " addq 1,%1\n", \ - " .dword 2b,4b\n" \ - " .dword 3b,5b\n") - -#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear(to, ret, \ - CLEAR \ - "2: clear.d [%0+]\n", \ - FIXUP \ - "3: jump 1b\n" \ - " addq 4,%1\n", \ - TENTRY \ - " .dword 2b,3b\n") - -#define __asm_clear_4(to, ret) \ - __asm_clear_4x_cont(to, ret, "", "", "") - -#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_4x_cont(to, ret, \ - CLEAR \ - "4: clear.d [%0+]\n", \ - FIXUP \ - "5: addq 4,%1\n", \ - TENTRY \ - " .dword 4b,5b\n") - -#define __asm_clear_8(to, ret) \ - __asm_clear_8x_cont(to, ret, "", "", "") - -#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_8x_cont(to, ret, \ - CLEAR \ - "6: clear.d [%0+]\n", \ - FIXUP \ - "7: addq 4,%1\n", \ - TENTRY \ - " .dword 6b,7b\n") - -#define __asm_clear_12(to, ret) \ - __asm_clear_12x_cont(to, ret, "", "", "") - -#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_12x_cont(to, ret, \ - CLEAR \ - "8: clear.d [%0+]\n", \ - FIXUP \ - "9: addq 4,%1\n", \ - TENTRY \ - " .dword 8b,9b\n") - -#define __asm_clear_16(to, ret) \ - __asm_clear_16x_cont(to, ret, "", "", "") - -#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_16x_cont(to, ret, \ - CLEAR \ - "10: clear.d [%0+]\n", \ - FIXUP \ - "11: addq 4,%1\n", \ - TENTRY \ - " .dword 10b,11b\n") - -#define __asm_clear_20(to, ret) \ - __asm_clear_20x_cont(to, ret, "", "", "") - -#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \ - __asm_clear_20x_cont(to, ret, \ - CLEAR \ - "12: clear.d [%0+]\n", \ - FIXUP \ - "13: addq 4,%1\n", \ - TENTRY \ - " .dword 12b,13b\n") - -#define __asm_clear_24(to, ret) \ - __asm_clear_24x_cont(to, ret, "", "", "") - -/* - * Return the size of a string (including the ending 0) - * - * Return length of string in userspace including terminating 0 - * or 0 for error. Return a value greater than N if too long. - */ - -static inline long -strnlen_user(const char *s, long n) -{ - long res, tmp1; - - if (!access_ok(VERIFY_READ, s, 0)) - return 0; - - /* - * This code is deduced from: - * - * tmp1 = n; - * while (tmp1-- > 0 && *s++) - * ; - * - * res = n - tmp1; - * - * (with tweaks). - */ - - __asm__ __volatile__ ( - " move.d %1,$acr\n" - " cmpq 0,$acr\n" - "0:\n" - " ble 1f\n" - " subq 1,$acr\n" - - "4: test.b [%0+]\n" - " bne 0b\n" - " cmpq 0,$acr\n" - "1:\n" - " move.d %1,%0\n" - " sub.d $acr,%0\n" - "2:\n" - " .section .fixup,\"ax\"\n" - - "3: jump 2b\n" - " clear.d %0\n" - - " .previous\n" - " .section __ex_table,\"a\"\n" - " .dword 4b,3b\n" - " .previous\n" - : "=r" (res), "=r" (tmp1) - : "0" (s), "1" (n) - : "acr"); - - return res; -} - -#endif diff --git a/arch/cris/include/arch-v32/arch/unistd.h b/arch/cris/include/arch-v32/arch/unistd.h deleted file mode 100644 index 764435b3b28e..000000000000 --- a/arch/cris/include/arch-v32/arch/unistd.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_UNISTD_H_ -#define _ASM_CRIS_ARCH_UNISTD_H_ - -/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ -/* - * Don't remove the .ifnc tests; they are an insurance against - * any hard-to-spot gcc register allocation bugs. - */ -#define _syscall0(type,name) \ -type name(void) \ -{ \ - register long __a __asm__ ("r10"); \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall1(type,name,type1,arg1) \ -type name(type1 arg1) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall2(type,name,type1,arg1,type2,arg2) \ -type name(type1 arg1,type2 arg2) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ -type name(type1 arg1,type2 arg2,type3 arg3) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ -type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d)\ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ - type5,arg5,type6,arg6) \ -type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \ -{ \ - register long __a __asm__ ("r10") = (long) arg1; \ - register long __b __asm__ ("r11") = (long) arg2; \ - register long __c __asm__ ("r12") = (long) arg3; \ - register long __d __asm__ ("r13") = (long) arg4; \ - register long __e __asm__ ("mof") = (long) arg5; \ - register long __f __asm__ ("srp") = (long) arg6; \ - register long __n_ __asm__ ("r9") = (__NR_##name); \ - __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \ - ".err\n\t" \ - ".endif\n\t" \ - "break 13" \ - : "=r" (__a) \ - : "r" (__n_), "0" (__a), "r" (__b), \ - "r" (__c), "r" (__d), "h" (__e), "x" (__f) \ - : "memory"); \ - if (__a >= 0) \ - return (type) __a; \ - errno = -__a; \ - return (type) -1; \ -} - -#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h b/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h deleted file mode 100644 index 7fafc370def2..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x7fe, - arbiter_cpu = 0x1800, - arbiter_all_clients = 0x7fff -}; - -enum { - arbiter_bar_all_clients = 0x1ff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli)) - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h deleted file mode 100644 index 92a74eab4395..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/dma.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */ - -#define NETWORK_ETH_TX_DMA_NBR 0 /* Ethernet 0 out. */ -#define NETWORK_ETH_RX_DMA_NBR 1 /* Ethernet 0 in. */ - -#define IO_PROC_DMA_TX_DMA_NBR 4 /* IO processor DMA0 out. */ -#define IO_PROC_DMA_RX_DMA_NBR 5 /* IO processor DMA0 in. */ - -#define ASYNC_SER3_TX_DMA_NBR 2 /* Asynchronous serial port 3 out. */ -#define ASYNC_SER3_RX_DMA_NBR 3 /* Asynchronous serial port 3 in. */ - -#define ASYNC_SER2_TX_DMA_NBR 6 /* Asynchronous serial port 2 out. */ -#define ASYNC_SER2_RX_DMA_NBR 7 /* Asynchronous serial port 2 in. */ - -#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ -#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ - -#define SYNC_SER_TX_DMA_NBR 6 /* Synchronous serial port 0 out. */ -#define SYNC_SER_RX_DMA_NBR 7 /* Synchronous serial port 0 in. */ - -#define ASYNC_SER0_TX_DMA_NBR 0 /* Asynchronous serial port 0 out. */ -#define ASYNC_SER0_RX_DMA_NBR 1 /* Asynchronous serial port 0 in. */ - -#define STRCOP_TX_DMA_NBR 2 /* Stream co-processor out. */ -#define STRCOP_RX_DMA_NBR 3 /* Stream co-processor in. */ - -#define dma_eth0 dma_eth -#define dma_eth1 dma_eth - -enum dma_owner { - dma_eth, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_ser4, - dma_iop, - dma_sser, - dma_strp, - dma_h264, - dma_jpeg -}; - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned bandwidth, enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h deleted file mode 100644 index 3d7f12ec1c54..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __clkgen_defs_asm_h -#define __clkgen_defs_asm_h - -/* - * This file is autogenerated from - * file: clkgen.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope clkgen, type r */ -#define reg_clkgen_r_bootsel___boot_mode___lsb 0 -#define reg_clkgen_r_bootsel___boot_mode___width 5 -#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5 -#define reg_clkgen_r_bootsel___intern_main_clk___width 1 -#define reg_clkgen_r_bootsel___intern_main_clk___bit 5 -#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6 -#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1 -#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6 -#define reg_clkgen_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope clkgen, type rw */ -#define reg_clkgen_rw_clk_ctrl___pll___lsb 0 -#define reg_clkgen_rw_clk_ctrl___pll___width 1 -#define reg_clkgen_rw_clk_ctrl___pll___bit 0 -#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1 -#define reg_clkgen_rw_clk_ctrl___cpu___width 1 -#define reg_clkgen_rw_clk_ctrl___cpu___bit 1 -#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2 -#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1 -#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2 -#define reg_clkgen_rw_clk_ctrl___vin___lsb 3 -#define reg_clkgen_rw_clk_ctrl___vin___width 1 -#define reg_clkgen_rw_clk_ctrl___vin___bit 3 -#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4 -#define reg_clkgen_rw_clk_ctrl___sclr___width 1 -#define reg_clkgen_rw_clk_ctrl___sclr___bit 4 -#define reg_clkgen_rw_clk_ctrl___h264___lsb 5 -#define reg_clkgen_rw_clk_ctrl___h264___width 1 -#define reg_clkgen_rw_clk_ctrl___h264___bit 5 -#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6 -#define reg_clkgen_rw_clk_ctrl___ddr2___width 1 -#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6 -#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7 -#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1 -#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7 -#define reg_clkgen_rw_clk_ctrl___eth___lsb 8 -#define reg_clkgen_rw_clk_ctrl___eth___width 1 -#define reg_clkgen_rw_clk_ctrl___eth___bit 8 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1 -#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1 -#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11 -#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12 -#define reg_clkgen_rw_clk_ctrl___jpeg___width 1 -#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1 -#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1 -#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1 -#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1 -#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16 -#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17 -#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1 -#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1 -#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1 -#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19 -#define reg_clkgen_rw_clk_ctrl_offset 4 - - -/* Constants */ -#define regk_clkgen_eth1000_rx 0x0000000c -#define regk_clkgen_eth1000_tx 0x0000000e -#define regk_clkgen_eth100_rx 0x0000001d -#define regk_clkgen_eth100_rx_half 0x0000001c -#define regk_clkgen_eth100_tx 0x0000001f -#define regk_clkgen_eth100_tx_half 0x0000001e -#define regk_clkgen_nand_3_2 0x00000000 -#define regk_clkgen_nand_3_2_0x30 0x00000002 -#define regk_clkgen_nand_3_2_0x30_pll 0x00000012 -#define regk_clkgen_nand_3_2_pll 0x00000010 -#define regk_clkgen_nand_3_3 0x00000001 -#define regk_clkgen_nand_3_3_0x30 0x00000003 -#define regk_clkgen_nand_3_3_0x30_pll 0x00000013 -#define regk_clkgen_nand_3_3_pll 0x00000011 -#define regk_clkgen_nand_4_2 0x00000004 -#define regk_clkgen_nand_4_2_0x30 0x00000006 -#define regk_clkgen_nand_4_2_0x30_pll 0x00000016 -#define regk_clkgen_nand_4_2_pll 0x00000014 -#define regk_clkgen_nand_4_3 0x00000005 -#define regk_clkgen_nand_4_3_0x30 0x00000007 -#define regk_clkgen_nand_4_3_0x30_pll 0x00000017 -#define regk_clkgen_nand_4_3_pll 0x00000015 -#define regk_clkgen_nand_5_2 0x00000008 -#define regk_clkgen_nand_5_2_0x30 0x0000000a -#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a -#define regk_clkgen_nand_5_2_pll 0x00000018 -#define regk_clkgen_nand_5_3 0x00000009 -#define regk_clkgen_nand_5_3_0x30 0x0000000b -#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b -#define regk_clkgen_nand_5_3_pll 0x00000019 -#define regk_clkgen_no 0x00000000 -#define regk_clkgen_rw_clk_ctrl_default 0x00000002 -#define regk_clkgen_ser 0x0000000d -#define regk_clkgen_ser_pll 0x0000000f -#define regk_clkgen_yes 0x00000001 -#endif /* __clkgen_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h deleted file mode 100644 index df79e5a7f02a..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ddr2_defs_asm_h -#define __ddr2_defs_asm_h - -/* - * This file is autogenerated from - * file: ddr2.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_cfg, scope ddr2, type rw */ -#define reg_ddr2_rw_cfg___col_width___lsb 0 -#define reg_ddr2_rw_cfg___col_width___width 4 -#define reg_ddr2_rw_cfg___nr_banks___lsb 4 -#define reg_ddr2_rw_cfg___nr_banks___width 1 -#define reg_ddr2_rw_cfg___nr_banks___bit 4 -#define reg_ddr2_rw_cfg___bw___lsb 5 -#define reg_ddr2_rw_cfg___bw___width 1 -#define reg_ddr2_rw_cfg___bw___bit 5 -#define reg_ddr2_rw_cfg___nr_ref___lsb 6 -#define reg_ddr2_rw_cfg___nr_ref___width 4 -#define reg_ddr2_rw_cfg___ref_interval___lsb 10 -#define reg_ddr2_rw_cfg___ref_interval___width 11 -#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21 -#define reg_ddr2_rw_cfg___odt_ctrl___width 2 -#define reg_ddr2_rw_cfg___odt_mem___lsb 23 -#define reg_ddr2_rw_cfg___odt_mem___width 1 -#define reg_ddr2_rw_cfg___odt_mem___bit 23 -#define reg_ddr2_rw_cfg___imp_strength___lsb 24 -#define reg_ddr2_rw_cfg___imp_strength___width 1 -#define reg_ddr2_rw_cfg___imp_strength___bit 24 -#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25 -#define reg_ddr2_rw_cfg___auto_imp_cal___width 1 -#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25 -#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26 -#define reg_ddr2_rw_cfg___imp_cal_override___width 1 -#define reg_ddr2_rw_cfg___imp_cal_override___bit 26 -#define reg_ddr2_rw_cfg___dll_override___lsb 27 -#define reg_ddr2_rw_cfg___dll_override___width 1 -#define reg_ddr2_rw_cfg___dll_override___bit 27 -#define reg_ddr2_rw_cfg_offset 0 - -/* Register rw_timing, scope ddr2, type rw */ -#define reg_ddr2_rw_timing___wr___lsb 0 -#define reg_ddr2_rw_timing___wr___width 3 -#define reg_ddr2_rw_timing___rcd___lsb 3 -#define reg_ddr2_rw_timing___rcd___width 3 -#define reg_ddr2_rw_timing___rp___lsb 6 -#define reg_ddr2_rw_timing___rp___width 3 -#define reg_ddr2_rw_timing___ras___lsb 9 -#define reg_ddr2_rw_timing___ras___width 4 -#define reg_ddr2_rw_timing___rfc___lsb 13 -#define reg_ddr2_rw_timing___rfc___width 7 -#define reg_ddr2_rw_timing___rc___lsb 20 -#define reg_ddr2_rw_timing___rc___width 5 -#define reg_ddr2_rw_timing___rtp___lsb 25 -#define reg_ddr2_rw_timing___rtp___width 2 -#define reg_ddr2_rw_timing___rtw___lsb 27 -#define reg_ddr2_rw_timing___rtw___width 3 -#define reg_ddr2_rw_timing___wtr___lsb 30 -#define reg_ddr2_rw_timing___wtr___width 2 -#define reg_ddr2_rw_timing_offset 4 - -/* Register rw_latency, scope ddr2, type rw */ -#define reg_ddr2_rw_latency___cas___lsb 0 -#define reg_ddr2_rw_latency___cas___width 3 -#define reg_ddr2_rw_latency___additive___lsb 3 -#define reg_ddr2_rw_latency___additive___width 3 -#define reg_ddr2_rw_latency_offset 8 - -/* Register rw_phy_cfg, scope ddr2, type rw */ -#define reg_ddr2_rw_phy_cfg___en___lsb 0 -#define reg_ddr2_rw_phy_cfg___en___width 1 -#define reg_ddr2_rw_phy_cfg___en___bit 0 -#define reg_ddr2_rw_phy_cfg_offset 12 - -/* Register rw_phy_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_phy_ctrl___rst___lsb 0 -#define reg_ddr2_rw_phy_ctrl___rst___width 1 -#define reg_ddr2_rw_phy_ctrl___rst___bit 0 -#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1 -#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1 -#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1 -#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2 -#define reg_ddr2_rw_phy_ctrl___cal_start___width 1 -#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2 -#define reg_ddr2_rw_phy_ctrl_offset 16 - -/* Register rw_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_ctrl___mrs_data___lsb 0 -#define reg_ddr2_rw_ctrl___mrs_data___width 16 -#define reg_ddr2_rw_ctrl___cmd___lsb 16 -#define reg_ddr2_rw_ctrl___cmd___width 8 -#define reg_ddr2_rw_ctrl_offset 20 - -/* Register rw_pwr_down, scope ddr2, type rw */ -#define reg_ddr2_rw_pwr_down___self_ref___lsb 0 -#define reg_ddr2_rw_pwr_down___self_ref___width 2 -#define reg_ddr2_rw_pwr_down___phy_en___lsb 2 -#define reg_ddr2_rw_pwr_down___phy_en___width 1 -#define reg_ddr2_rw_pwr_down___phy_en___bit 2 -#define reg_ddr2_rw_pwr_down_offset 24 - -/* Register r_stat, scope ddr2, type r */ -#define reg_ddr2_r_stat___dll_lock___lsb 0 -#define reg_ddr2_r_stat___dll_lock___width 1 -#define reg_ddr2_r_stat___dll_lock___bit 0 -#define reg_ddr2_r_stat___dll_delay_code___lsb 1 -#define reg_ddr2_r_stat___dll_delay_code___width 7 -#define reg_ddr2_r_stat___imp_cal_done___lsb 8 -#define reg_ddr2_r_stat___imp_cal_done___width 1 -#define reg_ddr2_r_stat___imp_cal_done___bit 8 -#define reg_ddr2_r_stat___imp_cal_fault___lsb 9 -#define reg_ddr2_r_stat___imp_cal_fault___width 1 -#define reg_ddr2_r_stat___imp_cal_fault___bit 9 -#define reg_ddr2_r_stat___cal_imp_pu___lsb 10 -#define reg_ddr2_r_stat___cal_imp_pu___width 4 -#define reg_ddr2_r_stat___cal_imp_pd___lsb 14 -#define reg_ddr2_r_stat___cal_imp_pd___width 4 -#define reg_ddr2_r_stat_offset 28 - -/* Register rw_imp_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0 -#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4 -#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4 -#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4 -#define reg_ddr2_rw_imp_ctrl_offset 32 - -#define STRIDE_ddr2_rw_dll_ctrl 4 -/* Register rw_dll_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_dll_ctrl___mode___lsb 0 -#define reg_ddr2_rw_dll_ctrl___mode___width 1 -#define reg_ddr2_rw_dll_ctrl___mode___bit 0 -#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1 -#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7 -#define reg_ddr2_rw_dll_ctrl_offset 36 - -#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 -/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ -#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21 -#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7 -#define reg_ddr2_rw_dqs_dll_ctrl_offset 52 - - -/* Constants */ -#define regk_ddr2_al0 0x00000000 -#define regk_ddr2_al1 0x00000008 -#define regk_ddr2_al2 0x00000010 -#define regk_ddr2_al3 0x00000018 -#define regk_ddr2_al4 0x00000020 -#define regk_ddr2_auto 0x00000003 -#define regk_ddr2_bank4 0x00000000 -#define regk_ddr2_bank8 0x00000001 -#define regk_ddr2_bl4 0x00000002 -#define regk_ddr2_bl8 0x00000003 -#define regk_ddr2_bt_il 0x00000008 -#define regk_ddr2_bt_seq 0x00000000 -#define regk_ddr2_bw16 0x00000001 -#define regk_ddr2_bw32 0x00000000 -#define regk_ddr2_cas2 0x00000020 -#define regk_ddr2_cas3 0x00000030 -#define regk_ddr2_cas4 0x00000040 -#define regk_ddr2_cas5 0x00000050 -#define regk_ddr2_deselect 0x000000c0 -#define regk_ddr2_dic_weak 0x00000002 -#define regk_ddr2_direct 0x00000001 -#define regk_ddr2_dis 0x00000000 -#define regk_ddr2_dll_dis 0x00000001 -#define regk_ddr2_dll_en 0x00000000 -#define regk_ddr2_dll_rst 0x00000100 -#define regk_ddr2_emrs 0x00000081 -#define regk_ddr2_emrs2 0x00000082 -#define regk_ddr2_emrs3 0x00000083 -#define regk_ddr2_full 0x00000001 -#define regk_ddr2_hi_ref_rate 0x00000080 -#define regk_ddr2_mrs 0x00000080 -#define regk_ddr2_no 0x00000000 -#define regk_ddr2_nop 0x000000b8 -#define regk_ddr2_ocd_adj 0x00000200 -#define regk_ddr2_ocd_default 0x00000380 -#define regk_ddr2_ocd_drive0 0x00000100 -#define regk_ddr2_ocd_drive1 0x00000080 -#define regk_ddr2_ocd_exit 0x00000000 -#define regk_ddr2_odt_dis 0x00000000 -#define regk_ddr2_offs 0x00000000 -#define regk_ddr2_pre 0x00000090 -#define regk_ddr2_pre_all 0x00000400 -#define regk_ddr2_pwr_down_fast 0x00000000 -#define regk_ddr2_pwr_down_slow 0x00001000 -#define regk_ddr2_ref 0x00000088 -#define regk_ddr2_rtt150 0x00000040 -#define regk_ddr2_rtt50 0x00000044 -#define regk_ddr2_rtt75 0x00000004 -#define regk_ddr2_rw_cfg_default 0x00186000 -#define regk_ddr2_rw_dll_ctrl_default 0x00000000 -#define regk_ddr2_rw_dll_ctrl_size 0x00000004 -#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000 -#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004 -#define regk_ddr2_rw_latency_default 0x00000000 -#define regk_ddr2_rw_phy_cfg_default 0x00000000 -#define regk_ddr2_rw_pwr_down_default 0x00000000 -#define regk_ddr2_rw_timing_default 0x00000000 -#define regk_ddr2_s1Gb 0x0000001a -#define regk_ddr2_s256Mb 0x0000000f -#define regk_ddr2_s2Gb 0x00000027 -#define regk_ddr2_s4Gb 0x00000042 -#define regk_ddr2_s512Mb 0x00000015 -#define regk_ddr2_temp0_85 0x00000618 -#define regk_ddr2_temp85_95 0x0000030c -#define regk_ddr2_term150 0x00000002 -#define regk_ddr2_term50 0x00000003 -#define regk_ddr2_term75 0x00000001 -#define regk_ddr2_test 0x00000080 -#define regk_ddr2_weak 0x00000000 -#define regk_ddr2_wr2 0x00000200 -#define regk_ddr2_wr3 0x00000400 -#define regk_ddr2_yes 0x00000001 -#endif /* __ddr2_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 04b7ff3f70a2..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,850 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: gio.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 32 -#define reg_gio_r_pa_din_offset 0 - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 32 -#define reg_gio_rw_pa_dout_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 32 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_pa_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte0_dout___data___lsb 0 -#define reg_gio_rw_pa_byte0_dout___data___width 8 -#define reg_gio_rw_pa_byte0_dout_offset 12 - -/* Register rw_pa_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte0_oe___oe___width 8 -#define reg_gio_rw_pa_byte0_oe_offset 16 - -/* Register rw_pa_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte1_dout___data___lsb 0 -#define reg_gio_rw_pa_byte1_dout___data___width 8 -#define reg_gio_rw_pa_byte1_dout_offset 20 - -/* Register rw_pa_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte1_oe___oe___width 8 -#define reg_gio_rw_pa_byte1_oe_offset 24 - -/* Register rw_pa_byte2_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte2_dout___data___lsb 0 -#define reg_gio_rw_pa_byte2_dout___data___width 8 -#define reg_gio_rw_pa_byte2_dout_offset 28 - -/* Register rw_pa_byte2_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte2_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte2_oe___oe___width 8 -#define reg_gio_rw_pa_byte2_oe_offset 32 - -/* Register rw_pa_byte3_dout, scope gio, type rw */ -#define reg_gio_rw_pa_byte3_dout___data___lsb 0 -#define reg_gio_rw_pa_byte3_dout___data___width 8 -#define reg_gio_rw_pa_byte3_dout_offset 36 - -/* Register rw_pa_byte3_oe, scope gio, type rw */ -#define reg_gio_rw_pa_byte3_oe___oe___lsb 0 -#define reg_gio_rw_pa_byte3_oe___oe___width 8 -#define reg_gio_rw_pa_byte3_oe_offset 40 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 32 -#define reg_gio_r_pb_din_offset 44 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 32 -#define reg_gio_rw_pb_dout_offset 48 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 32 -#define reg_gio_rw_pb_oe_offset 52 - -/* Register rw_pb_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte0_dout___data___lsb 0 -#define reg_gio_rw_pb_byte0_dout___data___width 8 -#define reg_gio_rw_pb_byte0_dout_offset 56 - -/* Register rw_pb_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte0_oe___oe___width 8 -#define reg_gio_rw_pb_byte0_oe_offset 60 - -/* Register rw_pb_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte1_dout___data___lsb 0 -#define reg_gio_rw_pb_byte1_dout___data___width 8 -#define reg_gio_rw_pb_byte1_dout_offset 64 - -/* Register rw_pb_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte1_oe___oe___width 8 -#define reg_gio_rw_pb_byte1_oe_offset 68 - -/* Register rw_pb_byte2_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte2_dout___data___lsb 0 -#define reg_gio_rw_pb_byte2_dout___data___width 8 -#define reg_gio_rw_pb_byte2_dout_offset 72 - -/* Register rw_pb_byte2_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte2_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte2_oe___oe___width 8 -#define reg_gio_rw_pb_byte2_oe_offset 76 - -/* Register rw_pb_byte3_dout, scope gio, type rw */ -#define reg_gio_rw_pb_byte3_dout___data___lsb 0 -#define reg_gio_rw_pb_byte3_dout___data___width 8 -#define reg_gio_rw_pb_byte3_dout_offset 80 - -/* Register rw_pb_byte3_oe, scope gio, type rw */ -#define reg_gio_rw_pb_byte3_oe___oe___lsb 0 -#define reg_gio_rw_pb_byte3_oe___oe___width 8 -#define reg_gio_rw_pb_byte3_oe_offset 84 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 16 -#define reg_gio_r_pc_din_offset 88 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 16 -#define reg_gio_rw_pc_dout_offset 92 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 16 -#define reg_gio_rw_pc_oe_offset 96 - -/* Register rw_pc_byte0_dout, scope gio, type rw */ -#define reg_gio_rw_pc_byte0_dout___data___lsb 0 -#define reg_gio_rw_pc_byte0_dout___data___width 8 -#define reg_gio_rw_pc_byte0_dout_offset 100 - -/* Register rw_pc_byte0_oe, scope gio, type rw */ -#define reg_gio_rw_pc_byte0_oe___oe___lsb 0 -#define reg_gio_rw_pc_byte0_oe___oe___width 8 -#define reg_gio_rw_pc_byte0_oe_offset 104 - -/* Register rw_pc_byte1_dout, scope gio, type rw */ -#define reg_gio_rw_pc_byte1_dout___data___lsb 0 -#define reg_gio_rw_pc_byte1_dout___data___width 8 -#define reg_gio_rw_pc_byte1_dout_offset 108 - -/* Register rw_pc_byte1_oe, scope gio, type rw */ -#define reg_gio_rw_pc_byte1_oe___oe___lsb 0 -#define reg_gio_rw_pc_byte1_oe___oe___width 8 -#define reg_gio_rw_pc_byte1_oe_offset 112 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 32 -#define reg_gio_r_pd_din_offset 116 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___intr0___lsb 0 -#define reg_gio_rw_intr_cfg___intr0___width 3 -#define reg_gio_rw_intr_cfg___intr1___lsb 3 -#define reg_gio_rw_intr_cfg___intr1___width 3 -#define reg_gio_rw_intr_cfg___intr2___lsb 6 -#define reg_gio_rw_intr_cfg___intr2___width 3 -#define reg_gio_rw_intr_cfg___intr3___lsb 9 -#define reg_gio_rw_intr_cfg___intr3___width 3 -#define reg_gio_rw_intr_cfg___intr4___lsb 12 -#define reg_gio_rw_intr_cfg___intr4___width 3 -#define reg_gio_rw_intr_cfg___intr5___lsb 15 -#define reg_gio_rw_intr_cfg___intr5___width 3 -#define reg_gio_rw_intr_cfg___intr6___lsb 18 -#define reg_gio_rw_intr_cfg___intr6___width 3 -#define reg_gio_rw_intr_cfg___intr7___lsb 21 -#define reg_gio_rw_intr_cfg___intr7___width 3 -#define reg_gio_rw_intr_cfg_offset 120 - -/* Register rw_intr_pins, scope gio, type rw */ -#define reg_gio_rw_intr_pins___intr0___lsb 0 -#define reg_gio_rw_intr_pins___intr0___width 4 -#define reg_gio_rw_intr_pins___intr1___lsb 4 -#define reg_gio_rw_intr_pins___intr1___width 4 -#define reg_gio_rw_intr_pins___intr2___lsb 8 -#define reg_gio_rw_intr_pins___intr2___width 4 -#define reg_gio_rw_intr_pins___intr3___lsb 12 -#define reg_gio_rw_intr_pins___intr3___width 4 -#define reg_gio_rw_intr_pins___intr4___lsb 16 -#define reg_gio_rw_intr_pins___intr4___width 4 -#define reg_gio_rw_intr_pins___intr5___lsb 20 -#define reg_gio_rw_intr_pins___intr5___width 4 -#define reg_gio_rw_intr_pins___intr6___lsb 24 -#define reg_gio_rw_intr_pins___intr6___width 4 -#define reg_gio_rw_intr_pins___intr7___lsb 28 -#define reg_gio_rw_intr_pins___intr7___width 4 -#define reg_gio_rw_intr_pins_offset 124 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___intr0___lsb 0 -#define reg_gio_rw_intr_mask___intr0___width 1 -#define reg_gio_rw_intr_mask___intr0___bit 0 -#define reg_gio_rw_intr_mask___intr1___lsb 1 -#define reg_gio_rw_intr_mask___intr1___width 1 -#define reg_gio_rw_intr_mask___intr1___bit 1 -#define reg_gio_rw_intr_mask___intr2___lsb 2 -#define reg_gio_rw_intr_mask___intr2___width 1 -#define reg_gio_rw_intr_mask___intr2___bit 2 -#define reg_gio_rw_intr_mask___intr3___lsb 3 -#define reg_gio_rw_intr_mask___intr3___width 1 -#define reg_gio_rw_intr_mask___intr3___bit 3 -#define reg_gio_rw_intr_mask___intr4___lsb 4 -#define reg_gio_rw_intr_mask___intr4___width 1 -#define reg_gio_rw_intr_mask___intr4___bit 4 -#define reg_gio_rw_intr_mask___intr5___lsb 5 -#define reg_gio_rw_intr_mask___intr5___width 1 -#define reg_gio_rw_intr_mask___intr5___bit 5 -#define reg_gio_rw_intr_mask___intr6___lsb 6 -#define reg_gio_rw_intr_mask___intr6___width 1 -#define reg_gio_rw_intr_mask___intr6___bit 6 -#define reg_gio_rw_intr_mask___intr7___lsb 7 -#define reg_gio_rw_intr_mask___intr7___width 1 -#define reg_gio_rw_intr_mask___intr7___bit 7 -#define reg_gio_rw_intr_mask___i2c0_done___lsb 8 -#define reg_gio_rw_intr_mask___i2c0_done___width 1 -#define reg_gio_rw_intr_mask___i2c0_done___bit 8 -#define reg_gio_rw_intr_mask___i2c1_done___lsb 9 -#define reg_gio_rw_intr_mask___i2c1_done___width 1 -#define reg_gio_rw_intr_mask___i2c1_done___bit 9 -#define reg_gio_rw_intr_mask_offset 128 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___intr0___lsb 0 -#define reg_gio_rw_ack_intr___intr0___width 1 -#define reg_gio_rw_ack_intr___intr0___bit 0 -#define reg_gio_rw_ack_intr___intr1___lsb 1 -#define reg_gio_rw_ack_intr___intr1___width 1 -#define reg_gio_rw_ack_intr___intr1___bit 1 -#define reg_gio_rw_ack_intr___intr2___lsb 2 -#define reg_gio_rw_ack_intr___intr2___width 1 -#define reg_gio_rw_ack_intr___intr2___bit 2 -#define reg_gio_rw_ack_intr___intr3___lsb 3 -#define reg_gio_rw_ack_intr___intr3___width 1 -#define reg_gio_rw_ack_intr___intr3___bit 3 -#define reg_gio_rw_ack_intr___intr4___lsb 4 -#define reg_gio_rw_ack_intr___intr4___width 1 -#define reg_gio_rw_ack_intr___intr4___bit 4 -#define reg_gio_rw_ack_intr___intr5___lsb 5 -#define reg_gio_rw_ack_intr___intr5___width 1 -#define reg_gio_rw_ack_intr___intr5___bit 5 -#define reg_gio_rw_ack_intr___intr6___lsb 6 -#define reg_gio_rw_ack_intr___intr6___width 1 -#define reg_gio_rw_ack_intr___intr6___bit 6 -#define reg_gio_rw_ack_intr___intr7___lsb 7 -#define reg_gio_rw_ack_intr___intr7___width 1 -#define reg_gio_rw_ack_intr___intr7___bit 7 -#define reg_gio_rw_ack_intr___i2c0_done___lsb 8 -#define reg_gio_rw_ack_intr___i2c0_done___width 1 -#define reg_gio_rw_ack_intr___i2c0_done___bit 8 -#define reg_gio_rw_ack_intr___i2c1_done___lsb 9 -#define reg_gio_rw_ack_intr___i2c1_done___width 1 -#define reg_gio_rw_ack_intr___i2c1_done___bit 9 -#define reg_gio_rw_ack_intr_offset 132 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___intr0___lsb 0 -#define reg_gio_r_intr___intr0___width 1 -#define reg_gio_r_intr___intr0___bit 0 -#define reg_gio_r_intr___intr1___lsb 1 -#define reg_gio_r_intr___intr1___width 1 -#define reg_gio_r_intr___intr1___bit 1 -#define reg_gio_r_intr___intr2___lsb 2 -#define reg_gio_r_intr___intr2___width 1 -#define reg_gio_r_intr___intr2___bit 2 -#define reg_gio_r_intr___intr3___lsb 3 -#define reg_gio_r_intr___intr3___width 1 -#define reg_gio_r_intr___intr3___bit 3 -#define reg_gio_r_intr___intr4___lsb 4 -#define reg_gio_r_intr___intr4___width 1 -#define reg_gio_r_intr___intr4___bit 4 -#define reg_gio_r_intr___intr5___lsb 5 -#define reg_gio_r_intr___intr5___width 1 -#define reg_gio_r_intr___intr5___bit 5 -#define reg_gio_r_intr___intr6___lsb 6 -#define reg_gio_r_intr___intr6___width 1 -#define reg_gio_r_intr___intr6___bit 6 -#define reg_gio_r_intr___intr7___lsb 7 -#define reg_gio_r_intr___intr7___width 1 -#define reg_gio_r_intr___intr7___bit 7 -#define reg_gio_r_intr___i2c0_done___lsb 8 -#define reg_gio_r_intr___i2c0_done___width 1 -#define reg_gio_r_intr___i2c0_done___bit 8 -#define reg_gio_r_intr___i2c1_done___lsb 9 -#define reg_gio_r_intr___i2c1_done___width 1 -#define reg_gio_r_intr___i2c1_done___bit 9 -#define reg_gio_r_intr_offset 136 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___intr0___lsb 0 -#define reg_gio_r_masked_intr___intr0___width 1 -#define reg_gio_r_masked_intr___intr0___bit 0 -#define reg_gio_r_masked_intr___intr1___lsb 1 -#define reg_gio_r_masked_intr___intr1___width 1 -#define reg_gio_r_masked_intr___intr1___bit 1 -#define reg_gio_r_masked_intr___intr2___lsb 2 -#define reg_gio_r_masked_intr___intr2___width 1 -#define reg_gio_r_masked_intr___intr2___bit 2 -#define reg_gio_r_masked_intr___intr3___lsb 3 -#define reg_gio_r_masked_intr___intr3___width 1 -#define reg_gio_r_masked_intr___intr3___bit 3 -#define reg_gio_r_masked_intr___intr4___lsb 4 -#define reg_gio_r_masked_intr___intr4___width 1 -#define reg_gio_r_masked_intr___intr4___bit 4 -#define reg_gio_r_masked_intr___intr5___lsb 5 -#define reg_gio_r_masked_intr___intr5___width 1 -#define reg_gio_r_masked_intr___intr5___bit 5 -#define reg_gio_r_masked_intr___intr6___lsb 6 -#define reg_gio_r_masked_intr___intr6___width 1 -#define reg_gio_r_masked_intr___intr6___bit 6 -#define reg_gio_r_masked_intr___intr7___lsb 7 -#define reg_gio_r_masked_intr___intr7___width 1 -#define reg_gio_r_masked_intr___intr7___bit 7 -#define reg_gio_r_masked_intr___i2c0_done___lsb 8 -#define reg_gio_r_masked_intr___i2c0_done___width 1 -#define reg_gio_r_masked_intr___i2c0_done___bit 8 -#define reg_gio_r_masked_intr___i2c1_done___lsb 9 -#define reg_gio_r_masked_intr___i2c1_done___width 1 -#define reg_gio_r_masked_intr___i2c1_done___bit 9 -#define reg_gio_r_masked_intr_offset 140 - -/* Register rw_i2c0_start, scope gio, type rw */ -#define reg_gio_rw_i2c0_start___run___lsb 0 -#define reg_gio_rw_i2c0_start___run___width 1 -#define reg_gio_rw_i2c0_start___run___bit 0 -#define reg_gio_rw_i2c0_start_offset 144 - -/* Register rw_i2c0_cfg, scope gio, type rw */ -#define reg_gio_rw_i2c0_cfg___en___lsb 0 -#define reg_gio_rw_i2c0_cfg___en___width 1 -#define reg_gio_rw_i2c0_cfg___en___bit 0 -#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1 -#define reg_gio_rw_i2c0_cfg___bit_order___width 1 -#define reg_gio_rw_i2c0_cfg___bit_order___bit 1 -#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2 -#define reg_gio_rw_i2c0_cfg___scl_io___width 1 -#define reg_gio_rw_i2c0_cfg___scl_io___bit 2 -#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3 -#define reg_gio_rw_i2c0_cfg___scl_inv___width 1 -#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3 -#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4 -#define reg_gio_rw_i2c0_cfg___sda_io___width 1 -#define reg_gio_rw_i2c0_cfg___sda_io___bit 4 -#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5 -#define reg_gio_rw_i2c0_cfg___sda_idle___width 1 -#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5 -#define reg_gio_rw_i2c0_cfg_offset 148 - -/* Register rw_i2c0_ctrl, scope gio, type rw */ -#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0 -#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6 -#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6 -#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6 -#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12 -#define reg_gio_rw_i2c0_ctrl___extra_start___width 3 -#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15 -#define reg_gio_rw_i2c0_ctrl___early_end___width 1 -#define reg_gio_rw_i2c0_ctrl___early_end___bit 15 -#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16 -#define reg_gio_rw_i2c0_ctrl___start_stop___width 1 -#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22 -#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23 -#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1 -#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23 -#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24 -#define reg_gio_rw_i2c0_ctrl___start_bit___width 1 -#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24 -#define reg_gio_rw_i2c0_ctrl___freq___lsb 25 -#define reg_gio_rw_i2c0_ctrl___freq___width 2 -#define reg_gio_rw_i2c0_ctrl_offset 152 - -/* Register rw_i2c0_data, scope gio, type rw */ -#define reg_gio_rw_i2c0_data___data0___lsb 0 -#define reg_gio_rw_i2c0_data___data0___width 8 -#define reg_gio_rw_i2c0_data___data1___lsb 8 -#define reg_gio_rw_i2c0_data___data1___width 8 -#define reg_gio_rw_i2c0_data___data2___lsb 16 -#define reg_gio_rw_i2c0_data___data2___width 8 -#define reg_gio_rw_i2c0_data___data3___lsb 24 -#define reg_gio_rw_i2c0_data___data3___width 8 -#define reg_gio_rw_i2c0_data_offset 156 - -/* Register rw_i2c0_data2, scope gio, type rw */ -#define reg_gio_rw_i2c0_data2___data4___lsb 0 -#define reg_gio_rw_i2c0_data2___data4___width 8 -#define reg_gio_rw_i2c0_data2___data5___lsb 8 -#define reg_gio_rw_i2c0_data2___data5___width 8 -#define reg_gio_rw_i2c0_data2___start_val___lsb 16 -#define reg_gio_rw_i2c0_data2___start_val___width 6 -#define reg_gio_rw_i2c0_data2___ack_val___lsb 22 -#define reg_gio_rw_i2c0_data2___ack_val___width 6 -#define reg_gio_rw_i2c0_data2_offset 160 - -/* Register rw_i2c1_start, scope gio, type rw */ -#define reg_gio_rw_i2c1_start___run___lsb 0 -#define reg_gio_rw_i2c1_start___run___width 1 -#define reg_gio_rw_i2c1_start___run___bit 0 -#define reg_gio_rw_i2c1_start_offset 164 - -/* Register rw_i2c1_cfg, scope gio, type rw */ -#define reg_gio_rw_i2c1_cfg___en___lsb 0 -#define reg_gio_rw_i2c1_cfg___en___width 1 -#define reg_gio_rw_i2c1_cfg___en___bit 0 -#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1 -#define reg_gio_rw_i2c1_cfg___bit_order___width 1 -#define reg_gio_rw_i2c1_cfg___bit_order___bit 1 -#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2 -#define reg_gio_rw_i2c1_cfg___scl_io___width 1 -#define reg_gio_rw_i2c1_cfg___scl_io___bit 2 -#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3 -#define reg_gio_rw_i2c1_cfg___scl_inv___width 1 -#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3 -#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4 -#define reg_gio_rw_i2c1_cfg___sda0_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4 -#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5 -#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5 -#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6 -#define reg_gio_rw_i2c1_cfg___sda1_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6 -#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7 -#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7 -#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8 -#define reg_gio_rw_i2c1_cfg___sda2_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8 -#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9 -#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9 -#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10 -#define reg_gio_rw_i2c1_cfg___sda3_io___width 1 -#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10 -#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11 -#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11 -#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12 -#define reg_gio_rw_i2c1_cfg___sda_sel___width 2 -#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14 -#define reg_gio_rw_i2c1_cfg___sen_idle___width 1 -#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14 -#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15 -#define reg_gio_rw_i2c1_cfg___sen_inv___width 1 -#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15 -#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16 -#define reg_gio_rw_i2c1_cfg___sen_sel___width 2 -#define reg_gio_rw_i2c1_cfg_offset 168 - -/* Register rw_i2c1_ctrl, scope gio, type rw */ -#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0 -#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6 -#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6 -#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6 -#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12 -#define reg_gio_rw_i2c1_ctrl___extra_start___width 3 -#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15 -#define reg_gio_rw_i2c1_ctrl___early_end___width 1 -#define reg_gio_rw_i2c1_ctrl___early_end___bit 15 -#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16 -#define reg_gio_rw_i2c1_ctrl___start_stop___width 1 -#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22 -#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23 -#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1 -#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23 -#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24 -#define reg_gio_rw_i2c1_ctrl___start_bit___width 1 -#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24 -#define reg_gio_rw_i2c1_ctrl___freq___lsb 25 -#define reg_gio_rw_i2c1_ctrl___freq___width 2 -#define reg_gio_rw_i2c1_ctrl_offset 172 - -/* Register rw_i2c1_data, scope gio, type rw */ -#define reg_gio_rw_i2c1_data___data0___lsb 0 -#define reg_gio_rw_i2c1_data___data0___width 8 -#define reg_gio_rw_i2c1_data___data1___lsb 8 -#define reg_gio_rw_i2c1_data___data1___width 8 -#define reg_gio_rw_i2c1_data___data2___lsb 16 -#define reg_gio_rw_i2c1_data___data2___width 8 -#define reg_gio_rw_i2c1_data___data3___lsb 24 -#define reg_gio_rw_i2c1_data___data3___width 8 -#define reg_gio_rw_i2c1_data_offset 176 - -/* Register rw_i2c1_data2, scope gio, type rw */ -#define reg_gio_rw_i2c1_data2___data4___lsb 0 -#define reg_gio_rw_i2c1_data2___data4___width 8 -#define reg_gio_rw_i2c1_data2___data5___lsb 8 -#define reg_gio_rw_i2c1_data2___data5___width 8 -#define reg_gio_rw_i2c1_data2___start_val___lsb 16 -#define reg_gio_rw_i2c1_data2___start_val___width 6 -#define reg_gio_rw_i2c1_data2___ack_val___lsb 22 -#define reg_gio_rw_i2c1_data2___ack_val___width 6 -#define reg_gio_rw_i2c1_data2_offset 180 - -/* Register r_ppwm_stat, scope gio, type r */ -#define reg_gio_r_ppwm_stat___freq___lsb 0 -#define reg_gio_r_ppwm_stat___freq___width 2 -#define reg_gio_r_ppwm_stat_offset 184 - -/* Register rw_ppwm_data, scope gio, type rw */ -#define reg_gio_rw_ppwm_data___data___lsb 0 -#define reg_gio_rw_ppwm_data___data___width 8 -#define reg_gio_rw_ppwm_data_offset 188 - -/* Register rw_pwm0_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm0_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm0_ctrl___mode___width 2 -#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm0_ctrl_offset 192 - -/* Register rw_pwm0_var, scope gio, type rw */ -#define reg_gio_rw_pwm0_var___lo___lsb 0 -#define reg_gio_rw_pwm0_var___lo___width 13 -#define reg_gio_rw_pwm0_var___hi___lsb 13 -#define reg_gio_rw_pwm0_var___hi___width 13 -#define reg_gio_rw_pwm0_var_offset 196 - -/* Register rw_pwm0_data, scope gio, type rw */ -#define reg_gio_rw_pwm0_data___data___lsb 0 -#define reg_gio_rw_pwm0_data___data___width 8 -#define reg_gio_rw_pwm0_data_offset 200 - -/* Register rw_pwm1_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm1_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm1_ctrl___mode___width 2 -#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm1_ctrl_offset 204 - -/* Register rw_pwm1_var, scope gio, type rw */ -#define reg_gio_rw_pwm1_var___lo___lsb 0 -#define reg_gio_rw_pwm1_var___lo___width 13 -#define reg_gio_rw_pwm1_var___hi___lsb 13 -#define reg_gio_rw_pwm1_var___hi___width 13 -#define reg_gio_rw_pwm1_var_offset 208 - -/* Register rw_pwm1_data, scope gio, type rw */ -#define reg_gio_rw_pwm1_data___data___lsb 0 -#define reg_gio_rw_pwm1_data___data___width 8 -#define reg_gio_rw_pwm1_data_offset 212 - -/* Register rw_pwm2_ctrl, scope gio, type rw */ -#define reg_gio_rw_pwm2_ctrl___mode___lsb 0 -#define reg_gio_rw_pwm2_ctrl___mode___width 2 -#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2 -#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1 -#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2 -#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3 -#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1 -#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3 -#define reg_gio_rw_pwm2_ctrl_offset 216 - -/* Register rw_pwm2_var, scope gio, type rw */ -#define reg_gio_rw_pwm2_var___lo___lsb 0 -#define reg_gio_rw_pwm2_var___lo___width 13 -#define reg_gio_rw_pwm2_var___hi___lsb 13 -#define reg_gio_rw_pwm2_var___hi___width 13 -#define reg_gio_rw_pwm2_var_offset 220 - -/* Register rw_pwm2_data, scope gio, type rw */ -#define reg_gio_rw_pwm2_data___data___lsb 0 -#define reg_gio_rw_pwm2_data___data___width 8 -#define reg_gio_rw_pwm2_data_offset 224 - -/* Register rw_pwm_in_cfg, scope gio, type rw */ -#define reg_gio_rw_pwm_in_cfg___pin___lsb 0 -#define reg_gio_rw_pwm_in_cfg___pin___width 3 -#define reg_gio_rw_pwm_in_cfg_offset 228 - -/* Register r_pwm_in_lo, scope gio, type r */ -#define reg_gio_r_pwm_in_lo___data___lsb 0 -#define reg_gio_r_pwm_in_lo___data___width 32 -#define reg_gio_r_pwm_in_lo_offset 232 - -/* Register r_pwm_in_hi, scope gio, type r */ -#define reg_gio_r_pwm_in_hi___data___lsb 0 -#define reg_gio_r_pwm_in_hi___data___width 32 -#define reg_gio_r_pwm_in_hi_offset 236 - -/* Register r_pwm_in_cnt, scope gio, type r */ -#define reg_gio_r_pwm_in_cnt___data___lsb 0 -#define reg_gio_r_pwm_in_cnt___data___width 32 -#define reg_gio_r_pwm_in_cnt_offset 240 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_f100k 0x00000000 -#define regk_gio_f1562 0x00000000 -#define regk_gio_f195 0x00000003 -#define regk_gio_f1m 0x00000002 -#define regk_gio_f390 0x00000002 -#define regk_gio_f400k 0x00000001 -#define regk_gio_f5m 0x00000003 -#define regk_gio_f781 0x00000001 -#define regk_gio_hi 0x00000001 -#define regk_gio_in 0x00000000 -#define regk_gio_intr_pa0 0x00000000 -#define regk_gio_intr_pa1 0x00000000 -#define regk_gio_intr_pa10 0x00000001 -#define regk_gio_intr_pa11 0x00000001 -#define regk_gio_intr_pa12 0x00000001 -#define regk_gio_intr_pa13 0x00000001 -#define regk_gio_intr_pa14 0x00000001 -#define regk_gio_intr_pa15 0x00000001 -#define regk_gio_intr_pa16 0x00000002 -#define regk_gio_intr_pa17 0x00000002 -#define regk_gio_intr_pa18 0x00000002 -#define regk_gio_intr_pa19 0x00000002 -#define regk_gio_intr_pa2 0x00000000 -#define regk_gio_intr_pa20 0x00000002 -#define regk_gio_intr_pa21 0x00000002 -#define regk_gio_intr_pa22 0x00000002 -#define regk_gio_intr_pa23 0x00000002 -#define regk_gio_intr_pa24 0x00000003 -#define regk_gio_intr_pa25 0x00000003 -#define regk_gio_intr_pa26 0x00000003 -#define regk_gio_intr_pa27 0x00000003 -#define regk_gio_intr_pa28 0x00000003 -#define regk_gio_intr_pa29 0x00000003 -#define regk_gio_intr_pa3 0x00000000 -#define regk_gio_intr_pa30 0x00000003 -#define regk_gio_intr_pa31 0x00000003 -#define regk_gio_intr_pa4 0x00000000 -#define regk_gio_intr_pa5 0x00000000 -#define regk_gio_intr_pa6 0x00000000 -#define regk_gio_intr_pa7 0x00000000 -#define regk_gio_intr_pa8 0x00000001 -#define regk_gio_intr_pa9 0x00000001 -#define regk_gio_intr_pb0 0x00000004 -#define regk_gio_intr_pb1 0x00000004 -#define regk_gio_intr_pb10 0x00000005 -#define regk_gio_intr_pb11 0x00000005 -#define regk_gio_intr_pb12 0x00000005 -#define regk_gio_intr_pb13 0x00000005 -#define regk_gio_intr_pb14 0x00000005 -#define regk_gio_intr_pb15 0x00000005 -#define regk_gio_intr_pb16 0x00000006 -#define regk_gio_intr_pb17 0x00000006 -#define regk_gio_intr_pb18 0x00000006 -#define regk_gio_intr_pb19 0x00000006 -#define regk_gio_intr_pb2 0x00000004 -#define regk_gio_intr_pb20 0x00000006 -#define regk_gio_intr_pb21 0x00000006 -#define regk_gio_intr_pb22 0x00000006 -#define regk_gio_intr_pb23 0x00000006 -#define regk_gio_intr_pb24 0x00000007 -#define regk_gio_intr_pb25 0x00000007 -#define regk_gio_intr_pb26 0x00000007 -#define regk_gio_intr_pb27 0x00000007 -#define regk_gio_intr_pb28 0x00000007 -#define regk_gio_intr_pb29 0x00000007 -#define regk_gio_intr_pb3 0x00000004 -#define regk_gio_intr_pb30 0x00000007 -#define regk_gio_intr_pb31 0x00000007 -#define regk_gio_intr_pb4 0x00000004 -#define regk_gio_intr_pb5 0x00000004 -#define regk_gio_intr_pb6 0x00000004 -#define regk_gio_intr_pb7 0x00000004 -#define regk_gio_intr_pb8 0x00000005 -#define regk_gio_intr_pb9 0x00000005 -#define regk_gio_intr_pc0 0x00000008 -#define regk_gio_intr_pc1 0x00000008 -#define regk_gio_intr_pc10 0x00000009 -#define regk_gio_intr_pc11 0x00000009 -#define regk_gio_intr_pc12 0x00000009 -#define regk_gio_intr_pc13 0x00000009 -#define regk_gio_intr_pc14 0x00000009 -#define regk_gio_intr_pc15 0x00000009 -#define regk_gio_intr_pc2 0x00000008 -#define regk_gio_intr_pc3 0x00000008 -#define regk_gio_intr_pc4 0x00000008 -#define regk_gio_intr_pc5 0x00000008 -#define regk_gio_intr_pc6 0x00000008 -#define regk_gio_intr_pc7 0x00000008 -#define regk_gio_intr_pc8 0x00000009 -#define regk_gio_intr_pc9 0x00000009 -#define regk_gio_intr_pd0 0x0000000c -#define regk_gio_intr_pd1 0x0000000c -#define regk_gio_intr_pd10 0x0000000d -#define regk_gio_intr_pd11 0x0000000d -#define regk_gio_intr_pd12 0x0000000d -#define regk_gio_intr_pd13 0x0000000d -#define regk_gio_intr_pd14 0x0000000d -#define regk_gio_intr_pd15 0x0000000d -#define regk_gio_intr_pd16 0x0000000e -#define regk_gio_intr_pd17 0x0000000e -#define regk_gio_intr_pd18 0x0000000e -#define regk_gio_intr_pd19 0x0000000e -#define regk_gio_intr_pd2 0x0000000c -#define regk_gio_intr_pd20 0x0000000e -#define regk_gio_intr_pd21 0x0000000e -#define regk_gio_intr_pd22 0x0000000e -#define regk_gio_intr_pd23 0x0000000e -#define regk_gio_intr_pd24 0x0000000f -#define regk_gio_intr_pd25 0x0000000f -#define regk_gio_intr_pd26 0x0000000f -#define regk_gio_intr_pd27 0x0000000f -#define regk_gio_intr_pd28 0x0000000f -#define regk_gio_intr_pd29 0x0000000f -#define regk_gio_intr_pd3 0x0000000c -#define regk_gio_intr_pd30 0x0000000f -#define regk_gio_intr_pd31 0x0000000f -#define regk_gio_intr_pd4 0x0000000c -#define regk_gio_intr_pd5 0x0000000c -#define regk_gio_intr_pd6 0x0000000c -#define regk_gio_intr_pd7 0x0000000c -#define regk_gio_intr_pd8 0x0000000d -#define regk_gio_intr_pd9 0x0000000d -#define regk_gio_lo 0x00000002 -#define regk_gio_lsb 0x00000000 -#define regk_gio_msb 0x00000001 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_no_switch 0x0000003f -#define regk_gio_none 0x00000007 -#define regk_gio_off 0x00000000 -#define regk_gio_opendrain 0x00000000 -#define regk_gio_out 0x00000001 -#define regk_gio_posedge 0x00000005 -#define regk_gio_pwm_hfp 0x00000002 -#define regk_gio_pwm_pa0 0x00000001 -#define regk_gio_pwm_pa19 0x00000004 -#define regk_gio_pwm_pa6 0x00000002 -#define regk_gio_pwm_pa7 0x00000003 -#define regk_gio_pwm_pb26 0x00000005 -#define regk_gio_pwm_pd23 0x00000006 -#define regk_gio_pwm_pd31 0x00000007 -#define regk_gio_pwm_std 0x00000001 -#define regk_gio_pwm_var 0x00000003 -#define regk_gio_rw_i2c0_cfg_default 0x00000020 -#define regk_gio_rw_i2c0_ctrl_default 0x00010000 -#define regk_gio_rw_i2c0_start_default 0x00000000 -#define regk_gio_rw_i2c1_cfg_default 0x00000aa0 -#define regk_gio_rw_i2c1_ctrl_default 0x00010000 -#define regk_gio_rw_i2c1_start_default 0x00000000 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_ppwm_data_default 0x00000000 -#define regk_gio_rw_pwm0_ctrl_default 0x00000000 -#define regk_gio_rw_pwm1_ctrl_default 0x00000000 -#define regk_gio_rw_pwm2_ctrl_default 0x00000000 -#define regk_gio_rw_pwm_in_cfg_default 0x00000000 -#define regk_gio_sda0 0x00000000 -#define regk_gio_sda1 0x00000001 -#define regk_gio_sda2 0x00000002 -#define regk_gio_sda3 0x00000003 -#define regk_gio_sen 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index a73168a8e93a..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,573 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: pinmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___eth___lsb 0 -#define reg_pinmux_rw_hwprot___eth___width 1 -#define reg_pinmux_rw_hwprot___eth___bit 0 -#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1 -#define reg_pinmux_rw_hwprot___eth_mdio___width 1 -#define reg_pinmux_rw_hwprot___eth_mdio___bit 1 -#define reg_pinmux_rw_hwprot___geth___lsb 2 -#define reg_pinmux_rw_hwprot___geth___width 1 -#define reg_pinmux_rw_hwprot___geth___bit 2 -#define reg_pinmux_rw_hwprot___tg___lsb 3 -#define reg_pinmux_rw_hwprot___tg___width 1 -#define reg_pinmux_rw_hwprot___tg___bit 3 -#define reg_pinmux_rw_hwprot___tg_clk___lsb 4 -#define reg_pinmux_rw_hwprot___tg_clk___width 1 -#define reg_pinmux_rw_hwprot___tg_clk___bit 4 -#define reg_pinmux_rw_hwprot___vout___lsb 5 -#define reg_pinmux_rw_hwprot___vout___width 1 -#define reg_pinmux_rw_hwprot___vout___bit 5 -#define reg_pinmux_rw_hwprot___vout_sync___lsb 6 -#define reg_pinmux_rw_hwprot___vout_sync___width 1 -#define reg_pinmux_rw_hwprot___vout_sync___bit 6 -#define reg_pinmux_rw_hwprot___ser1___lsb 7 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 7 -#define reg_pinmux_rw_hwprot___ser2___lsb 8 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 8 -#define reg_pinmux_rw_hwprot___ser3___lsb 9 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 9 -#define reg_pinmux_rw_hwprot___ser4___lsb 10 -#define reg_pinmux_rw_hwprot___ser4___width 1 -#define reg_pinmux_rw_hwprot___ser4___bit 10 -#define reg_pinmux_rw_hwprot___sser___lsb 11 -#define reg_pinmux_rw_hwprot___sser___width 1 -#define reg_pinmux_rw_hwprot___sser___bit 11 -#define reg_pinmux_rw_hwprot___pwm0___lsb 12 -#define reg_pinmux_rw_hwprot___pwm0___width 1 -#define reg_pinmux_rw_hwprot___pwm0___bit 12 -#define reg_pinmux_rw_hwprot___pwm1___lsb 13 -#define reg_pinmux_rw_hwprot___pwm1___width 1 -#define reg_pinmux_rw_hwprot___pwm1___bit 13 -#define reg_pinmux_rw_hwprot___pwm2___lsb 14 -#define reg_pinmux_rw_hwprot___pwm2___width 1 -#define reg_pinmux_rw_hwprot___pwm2___bit 14 -#define reg_pinmux_rw_hwprot___timer0___lsb 15 -#define reg_pinmux_rw_hwprot___timer0___width 1 -#define reg_pinmux_rw_hwprot___timer0___bit 15 -#define reg_pinmux_rw_hwprot___timer1___lsb 16 -#define reg_pinmux_rw_hwprot___timer1___width 1 -#define reg_pinmux_rw_hwprot___timer1___bit 16 -#define reg_pinmux_rw_hwprot___pio___lsb 17 -#define reg_pinmux_rw_hwprot___pio___width 1 -#define reg_pinmux_rw_hwprot___pio___bit 17 -#define reg_pinmux_rw_hwprot___i2c0___lsb 18 -#define reg_pinmux_rw_hwprot___i2c0___width 1 -#define reg_pinmux_rw_hwprot___i2c0___bit 18 -#define reg_pinmux_rw_hwprot___i2c1___lsb 19 -#define reg_pinmux_rw_hwprot___i2c1___width 1 -#define reg_pinmux_rw_hwprot___i2c1___bit 19 -#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20 -#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20 -#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21 -#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21 -#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22 -#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22 -#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23 -#define reg_pinmux_rw_hwprot___i2c1_sen___width 1 -#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23 -#define reg_pinmux_rw_hwprot_offset 0 - -/* Register rw_gio_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pa___pa0___lsb 0 -#define reg_pinmux_rw_gio_pa___pa0___width 1 -#define reg_pinmux_rw_gio_pa___pa0___bit 0 -#define reg_pinmux_rw_gio_pa___pa1___lsb 1 -#define reg_pinmux_rw_gio_pa___pa1___width 1 -#define reg_pinmux_rw_gio_pa___pa1___bit 1 -#define reg_pinmux_rw_gio_pa___pa2___lsb 2 -#define reg_pinmux_rw_gio_pa___pa2___width 1 -#define reg_pinmux_rw_gio_pa___pa2___bit 2 -#define reg_pinmux_rw_gio_pa___pa3___lsb 3 -#define reg_pinmux_rw_gio_pa___pa3___width 1 -#define reg_pinmux_rw_gio_pa___pa3___bit 3 -#define reg_pinmux_rw_gio_pa___pa4___lsb 4 -#define reg_pinmux_rw_gio_pa___pa4___width 1 -#define reg_pinmux_rw_gio_pa___pa4___bit 4 -#define reg_pinmux_rw_gio_pa___pa5___lsb 5 -#define reg_pinmux_rw_gio_pa___pa5___width 1 -#define reg_pinmux_rw_gio_pa___pa5___bit 5 -#define reg_pinmux_rw_gio_pa___pa6___lsb 6 -#define reg_pinmux_rw_gio_pa___pa6___width 1 -#define reg_pinmux_rw_gio_pa___pa6___bit 6 -#define reg_pinmux_rw_gio_pa___pa7___lsb 7 -#define reg_pinmux_rw_gio_pa___pa7___width 1 -#define reg_pinmux_rw_gio_pa___pa7___bit 7 -#define reg_pinmux_rw_gio_pa___pa8___lsb 8 -#define reg_pinmux_rw_gio_pa___pa8___width 1 -#define reg_pinmux_rw_gio_pa___pa8___bit 8 -#define reg_pinmux_rw_gio_pa___pa9___lsb 9 -#define reg_pinmux_rw_gio_pa___pa9___width 1 -#define reg_pinmux_rw_gio_pa___pa9___bit 9 -#define reg_pinmux_rw_gio_pa___pa10___lsb 10 -#define reg_pinmux_rw_gio_pa___pa10___width 1 -#define reg_pinmux_rw_gio_pa___pa10___bit 10 -#define reg_pinmux_rw_gio_pa___pa11___lsb 11 -#define reg_pinmux_rw_gio_pa___pa11___width 1 -#define reg_pinmux_rw_gio_pa___pa11___bit 11 -#define reg_pinmux_rw_gio_pa___pa12___lsb 12 -#define reg_pinmux_rw_gio_pa___pa12___width 1 -#define reg_pinmux_rw_gio_pa___pa12___bit 12 -#define reg_pinmux_rw_gio_pa___pa13___lsb 13 -#define reg_pinmux_rw_gio_pa___pa13___width 1 -#define reg_pinmux_rw_gio_pa___pa13___bit 13 -#define reg_pinmux_rw_gio_pa___pa14___lsb 14 -#define reg_pinmux_rw_gio_pa___pa14___width 1 -#define reg_pinmux_rw_gio_pa___pa14___bit 14 -#define reg_pinmux_rw_gio_pa___pa15___lsb 15 -#define reg_pinmux_rw_gio_pa___pa15___width 1 -#define reg_pinmux_rw_gio_pa___pa15___bit 15 -#define reg_pinmux_rw_gio_pa___pa16___lsb 16 -#define reg_pinmux_rw_gio_pa___pa16___width 1 -#define reg_pinmux_rw_gio_pa___pa16___bit 16 -#define reg_pinmux_rw_gio_pa___pa17___lsb 17 -#define reg_pinmux_rw_gio_pa___pa17___width 1 -#define reg_pinmux_rw_gio_pa___pa17___bit 17 -#define reg_pinmux_rw_gio_pa___pa18___lsb 18 -#define reg_pinmux_rw_gio_pa___pa18___width 1 -#define reg_pinmux_rw_gio_pa___pa18___bit 18 -#define reg_pinmux_rw_gio_pa___pa19___lsb 19 -#define reg_pinmux_rw_gio_pa___pa19___width 1 -#define reg_pinmux_rw_gio_pa___pa19___bit 19 -#define reg_pinmux_rw_gio_pa___pa20___lsb 20 -#define reg_pinmux_rw_gio_pa___pa20___width 1 -#define reg_pinmux_rw_gio_pa___pa20___bit 20 -#define reg_pinmux_rw_gio_pa___pa21___lsb 21 -#define reg_pinmux_rw_gio_pa___pa21___width 1 -#define reg_pinmux_rw_gio_pa___pa21___bit 21 -#define reg_pinmux_rw_gio_pa___pa22___lsb 22 -#define reg_pinmux_rw_gio_pa___pa22___width 1 -#define reg_pinmux_rw_gio_pa___pa22___bit 22 -#define reg_pinmux_rw_gio_pa___pa23___lsb 23 -#define reg_pinmux_rw_gio_pa___pa23___width 1 -#define reg_pinmux_rw_gio_pa___pa23___bit 23 -#define reg_pinmux_rw_gio_pa___pa24___lsb 24 -#define reg_pinmux_rw_gio_pa___pa24___width 1 -#define reg_pinmux_rw_gio_pa___pa24___bit 24 -#define reg_pinmux_rw_gio_pa___pa25___lsb 25 -#define reg_pinmux_rw_gio_pa___pa25___width 1 -#define reg_pinmux_rw_gio_pa___pa25___bit 25 -#define reg_pinmux_rw_gio_pa___pa26___lsb 26 -#define reg_pinmux_rw_gio_pa___pa26___width 1 -#define reg_pinmux_rw_gio_pa___pa26___bit 26 -#define reg_pinmux_rw_gio_pa___pa27___lsb 27 -#define reg_pinmux_rw_gio_pa___pa27___width 1 -#define reg_pinmux_rw_gio_pa___pa27___bit 27 -#define reg_pinmux_rw_gio_pa___pa28___lsb 28 -#define reg_pinmux_rw_gio_pa___pa28___width 1 -#define reg_pinmux_rw_gio_pa___pa28___bit 28 -#define reg_pinmux_rw_gio_pa___pa29___lsb 29 -#define reg_pinmux_rw_gio_pa___pa29___width 1 -#define reg_pinmux_rw_gio_pa___pa29___bit 29 -#define reg_pinmux_rw_gio_pa___pa30___lsb 30 -#define reg_pinmux_rw_gio_pa___pa30___width 1 -#define reg_pinmux_rw_gio_pa___pa30___bit 30 -#define reg_pinmux_rw_gio_pa___pa31___lsb 31 -#define reg_pinmux_rw_gio_pa___pa31___width 1 -#define reg_pinmux_rw_gio_pa___pa31___bit 31 -#define reg_pinmux_rw_gio_pa_offset 4 - -/* Register rw_gio_pb, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pb___pb0___lsb 0 -#define reg_pinmux_rw_gio_pb___pb0___width 1 -#define reg_pinmux_rw_gio_pb___pb0___bit 0 -#define reg_pinmux_rw_gio_pb___pb1___lsb 1 -#define reg_pinmux_rw_gio_pb___pb1___width 1 -#define reg_pinmux_rw_gio_pb___pb1___bit 1 -#define reg_pinmux_rw_gio_pb___pb2___lsb 2 -#define reg_pinmux_rw_gio_pb___pb2___width 1 -#define reg_pinmux_rw_gio_pb___pb2___bit 2 -#define reg_pinmux_rw_gio_pb___pb3___lsb 3 -#define reg_pinmux_rw_gio_pb___pb3___width 1 -#define reg_pinmux_rw_gio_pb___pb3___bit 3 -#define reg_pinmux_rw_gio_pb___pb4___lsb 4 -#define reg_pinmux_rw_gio_pb___pb4___width 1 -#define reg_pinmux_rw_gio_pb___pb4___bit 4 -#define reg_pinmux_rw_gio_pb___pb5___lsb 5 -#define reg_pinmux_rw_gio_pb___pb5___width 1 -#define reg_pinmux_rw_gio_pb___pb5___bit 5 -#define reg_pinmux_rw_gio_pb___pb6___lsb 6 -#define reg_pinmux_rw_gio_pb___pb6___width 1 -#define reg_pinmux_rw_gio_pb___pb6___bit 6 -#define reg_pinmux_rw_gio_pb___pb7___lsb 7 -#define reg_pinmux_rw_gio_pb___pb7___width 1 -#define reg_pinmux_rw_gio_pb___pb7___bit 7 -#define reg_pinmux_rw_gio_pb___pb8___lsb 8 -#define reg_pinmux_rw_gio_pb___pb8___width 1 -#define reg_pinmux_rw_gio_pb___pb8___bit 8 -#define reg_pinmux_rw_gio_pb___pb9___lsb 9 -#define reg_pinmux_rw_gio_pb___pb9___width 1 -#define reg_pinmux_rw_gio_pb___pb9___bit 9 -#define reg_pinmux_rw_gio_pb___pb10___lsb 10 -#define reg_pinmux_rw_gio_pb___pb10___width 1 -#define reg_pinmux_rw_gio_pb___pb10___bit 10 -#define reg_pinmux_rw_gio_pb___pb11___lsb 11 -#define reg_pinmux_rw_gio_pb___pb11___width 1 -#define reg_pinmux_rw_gio_pb___pb11___bit 11 -#define reg_pinmux_rw_gio_pb___pb12___lsb 12 -#define reg_pinmux_rw_gio_pb___pb12___width 1 -#define reg_pinmux_rw_gio_pb___pb12___bit 12 -#define reg_pinmux_rw_gio_pb___pb13___lsb 13 -#define reg_pinmux_rw_gio_pb___pb13___width 1 -#define reg_pinmux_rw_gio_pb___pb13___bit 13 -#define reg_pinmux_rw_gio_pb___pb14___lsb 14 -#define reg_pinmux_rw_gio_pb___pb14___width 1 -#define reg_pinmux_rw_gio_pb___pb14___bit 14 -#define reg_pinmux_rw_gio_pb___pb15___lsb 15 -#define reg_pinmux_rw_gio_pb___pb15___width 1 -#define reg_pinmux_rw_gio_pb___pb15___bit 15 -#define reg_pinmux_rw_gio_pb___pb16___lsb 16 -#define reg_pinmux_rw_gio_pb___pb16___width 1 -#define reg_pinmux_rw_gio_pb___pb16___bit 16 -#define reg_pinmux_rw_gio_pb___pb17___lsb 17 -#define reg_pinmux_rw_gio_pb___pb17___width 1 -#define reg_pinmux_rw_gio_pb___pb17___bit 17 -#define reg_pinmux_rw_gio_pb___pb18___lsb 18 -#define reg_pinmux_rw_gio_pb___pb18___width 1 -#define reg_pinmux_rw_gio_pb___pb18___bit 18 -#define reg_pinmux_rw_gio_pb___pb19___lsb 19 -#define reg_pinmux_rw_gio_pb___pb19___width 1 -#define reg_pinmux_rw_gio_pb___pb19___bit 19 -#define reg_pinmux_rw_gio_pb___pb20___lsb 20 -#define reg_pinmux_rw_gio_pb___pb20___width 1 -#define reg_pinmux_rw_gio_pb___pb20___bit 20 -#define reg_pinmux_rw_gio_pb___pb21___lsb 21 -#define reg_pinmux_rw_gio_pb___pb21___width 1 -#define reg_pinmux_rw_gio_pb___pb21___bit 21 -#define reg_pinmux_rw_gio_pb___pb22___lsb 22 -#define reg_pinmux_rw_gio_pb___pb22___width 1 -#define reg_pinmux_rw_gio_pb___pb22___bit 22 -#define reg_pinmux_rw_gio_pb___pb23___lsb 23 -#define reg_pinmux_rw_gio_pb___pb23___width 1 -#define reg_pinmux_rw_gio_pb___pb23___bit 23 -#define reg_pinmux_rw_gio_pb___pb24___lsb 24 -#define reg_pinmux_rw_gio_pb___pb24___width 1 -#define reg_pinmux_rw_gio_pb___pb24___bit 24 -#define reg_pinmux_rw_gio_pb___pb25___lsb 25 -#define reg_pinmux_rw_gio_pb___pb25___width 1 -#define reg_pinmux_rw_gio_pb___pb25___bit 25 -#define reg_pinmux_rw_gio_pb___pb26___lsb 26 -#define reg_pinmux_rw_gio_pb___pb26___width 1 -#define reg_pinmux_rw_gio_pb___pb26___bit 26 -#define reg_pinmux_rw_gio_pb___pb27___lsb 27 -#define reg_pinmux_rw_gio_pb___pb27___width 1 -#define reg_pinmux_rw_gio_pb___pb27___bit 27 -#define reg_pinmux_rw_gio_pb___pb28___lsb 28 -#define reg_pinmux_rw_gio_pb___pb28___width 1 -#define reg_pinmux_rw_gio_pb___pb28___bit 28 -#define reg_pinmux_rw_gio_pb___pb29___lsb 29 -#define reg_pinmux_rw_gio_pb___pb29___width 1 -#define reg_pinmux_rw_gio_pb___pb29___bit 29 -#define reg_pinmux_rw_gio_pb___pb30___lsb 30 -#define reg_pinmux_rw_gio_pb___pb30___width 1 -#define reg_pinmux_rw_gio_pb___pb30___bit 30 -#define reg_pinmux_rw_gio_pb___pb31___lsb 31 -#define reg_pinmux_rw_gio_pb___pb31___width 1 -#define reg_pinmux_rw_gio_pb___pb31___bit 31 -#define reg_pinmux_rw_gio_pb_offset 8 - -/* Register rw_gio_pc, scope pinmux, type rw */ -#define reg_pinmux_rw_gio_pc___pc0___lsb 0 -#define reg_pinmux_rw_gio_pc___pc0___width 1 -#define reg_pinmux_rw_gio_pc___pc0___bit 0 -#define reg_pinmux_rw_gio_pc___pc1___lsb 1 -#define reg_pinmux_rw_gio_pc___pc1___width 1 -#define reg_pinmux_rw_gio_pc___pc1___bit 1 -#define reg_pinmux_rw_gio_pc___pc2___lsb 2 -#define reg_pinmux_rw_gio_pc___pc2___width 1 -#define reg_pinmux_rw_gio_pc___pc2___bit 2 -#define reg_pinmux_rw_gio_pc___pc3___lsb 3 -#define reg_pinmux_rw_gio_pc___pc3___width 1 -#define reg_pinmux_rw_gio_pc___pc3___bit 3 -#define reg_pinmux_rw_gio_pc___pc4___lsb 4 -#define reg_pinmux_rw_gio_pc___pc4___width 1 -#define reg_pinmux_rw_gio_pc___pc4___bit 4 -#define reg_pinmux_rw_gio_pc___pc5___lsb 5 -#define reg_pinmux_rw_gio_pc___pc5___width 1 -#define reg_pinmux_rw_gio_pc___pc5___bit 5 -#define reg_pinmux_rw_gio_pc___pc6___lsb 6 -#define reg_pinmux_rw_gio_pc___pc6___width 1 -#define reg_pinmux_rw_gio_pc___pc6___bit 6 -#define reg_pinmux_rw_gio_pc___pc7___lsb 7 -#define reg_pinmux_rw_gio_pc___pc7___width 1 -#define reg_pinmux_rw_gio_pc___pc7___bit 7 -#define reg_pinmux_rw_gio_pc___pc8___lsb 8 -#define reg_pinmux_rw_gio_pc___pc8___width 1 -#define reg_pinmux_rw_gio_pc___pc8___bit 8 -#define reg_pinmux_rw_gio_pc___pc9___lsb 9 -#define reg_pinmux_rw_gio_pc___pc9___width 1 -#define reg_pinmux_rw_gio_pc___pc9___bit 9 -#define reg_pinmux_rw_gio_pc___pc10___lsb 10 -#define reg_pinmux_rw_gio_pc___pc10___width 1 -#define reg_pinmux_rw_gio_pc___pc10___bit 10 -#define reg_pinmux_rw_gio_pc___pc11___lsb 11 -#define reg_pinmux_rw_gio_pc___pc11___width 1 -#define reg_pinmux_rw_gio_pc___pc11___bit 11 -#define reg_pinmux_rw_gio_pc___pc12___lsb 12 -#define reg_pinmux_rw_gio_pc___pc12___width 1 -#define reg_pinmux_rw_gio_pc___pc12___bit 12 -#define reg_pinmux_rw_gio_pc___pc13___lsb 13 -#define reg_pinmux_rw_gio_pc___pc13___width 1 -#define reg_pinmux_rw_gio_pc___pc13___bit 13 -#define reg_pinmux_rw_gio_pc___pc14___lsb 14 -#define reg_pinmux_rw_gio_pc___pc14___width 1 -#define reg_pinmux_rw_gio_pc___pc14___bit 14 -#define reg_pinmux_rw_gio_pc___pc15___lsb 15 -#define reg_pinmux_rw_gio_pc___pc15___width 1 -#define reg_pinmux_rw_gio_pc___pc15___bit 15 -#define reg_pinmux_rw_gio_pc_offset 12 - -/* Register rw_iop_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pa___pa0___lsb 0 -#define reg_pinmux_rw_iop_pa___pa0___width 1 -#define reg_pinmux_rw_iop_pa___pa0___bit 0 -#define reg_pinmux_rw_iop_pa___pa1___lsb 1 -#define reg_pinmux_rw_iop_pa___pa1___width 1 -#define reg_pinmux_rw_iop_pa___pa1___bit 1 -#define reg_pinmux_rw_iop_pa___pa2___lsb 2 -#define reg_pinmux_rw_iop_pa___pa2___width 1 -#define reg_pinmux_rw_iop_pa___pa2___bit 2 -#define reg_pinmux_rw_iop_pa___pa3___lsb 3 -#define reg_pinmux_rw_iop_pa___pa3___width 1 -#define reg_pinmux_rw_iop_pa___pa3___bit 3 -#define reg_pinmux_rw_iop_pa___pa4___lsb 4 -#define reg_pinmux_rw_iop_pa___pa4___width 1 -#define reg_pinmux_rw_iop_pa___pa4___bit 4 -#define reg_pinmux_rw_iop_pa___pa5___lsb 5 -#define reg_pinmux_rw_iop_pa___pa5___width 1 -#define reg_pinmux_rw_iop_pa___pa5___bit 5 -#define reg_pinmux_rw_iop_pa___pa6___lsb 6 -#define reg_pinmux_rw_iop_pa___pa6___width 1 -#define reg_pinmux_rw_iop_pa___pa6___bit 6 -#define reg_pinmux_rw_iop_pa___pa7___lsb 7 -#define reg_pinmux_rw_iop_pa___pa7___width 1 -#define reg_pinmux_rw_iop_pa___pa7___bit 7 -#define reg_pinmux_rw_iop_pa___pa8___lsb 8 -#define reg_pinmux_rw_iop_pa___pa8___width 1 -#define reg_pinmux_rw_iop_pa___pa8___bit 8 -#define reg_pinmux_rw_iop_pa___pa9___lsb 9 -#define reg_pinmux_rw_iop_pa___pa9___width 1 -#define reg_pinmux_rw_iop_pa___pa9___bit 9 -#define reg_pinmux_rw_iop_pa___pa10___lsb 10 -#define reg_pinmux_rw_iop_pa___pa10___width 1 -#define reg_pinmux_rw_iop_pa___pa10___bit 10 -#define reg_pinmux_rw_iop_pa___pa11___lsb 11 -#define reg_pinmux_rw_iop_pa___pa11___width 1 -#define reg_pinmux_rw_iop_pa___pa11___bit 11 -#define reg_pinmux_rw_iop_pa___pa12___lsb 12 -#define reg_pinmux_rw_iop_pa___pa12___width 1 -#define reg_pinmux_rw_iop_pa___pa12___bit 12 -#define reg_pinmux_rw_iop_pa___pa13___lsb 13 -#define reg_pinmux_rw_iop_pa___pa13___width 1 -#define reg_pinmux_rw_iop_pa___pa13___bit 13 -#define reg_pinmux_rw_iop_pa___pa14___lsb 14 -#define reg_pinmux_rw_iop_pa___pa14___width 1 -#define reg_pinmux_rw_iop_pa___pa14___bit 14 -#define reg_pinmux_rw_iop_pa___pa15___lsb 15 -#define reg_pinmux_rw_iop_pa___pa15___width 1 -#define reg_pinmux_rw_iop_pa___pa15___bit 15 -#define reg_pinmux_rw_iop_pa___pa16___lsb 16 -#define reg_pinmux_rw_iop_pa___pa16___width 1 -#define reg_pinmux_rw_iop_pa___pa16___bit 16 -#define reg_pinmux_rw_iop_pa___pa17___lsb 17 -#define reg_pinmux_rw_iop_pa___pa17___width 1 -#define reg_pinmux_rw_iop_pa___pa17___bit 17 -#define reg_pinmux_rw_iop_pa___pa18___lsb 18 -#define reg_pinmux_rw_iop_pa___pa18___width 1 -#define reg_pinmux_rw_iop_pa___pa18___bit 18 -#define reg_pinmux_rw_iop_pa___pa19___lsb 19 -#define reg_pinmux_rw_iop_pa___pa19___width 1 -#define reg_pinmux_rw_iop_pa___pa19___bit 19 -#define reg_pinmux_rw_iop_pa___pa20___lsb 20 -#define reg_pinmux_rw_iop_pa___pa20___width 1 -#define reg_pinmux_rw_iop_pa___pa20___bit 20 -#define reg_pinmux_rw_iop_pa___pa21___lsb 21 -#define reg_pinmux_rw_iop_pa___pa21___width 1 -#define reg_pinmux_rw_iop_pa___pa21___bit 21 -#define reg_pinmux_rw_iop_pa___pa22___lsb 22 -#define reg_pinmux_rw_iop_pa___pa22___width 1 -#define reg_pinmux_rw_iop_pa___pa22___bit 22 -#define reg_pinmux_rw_iop_pa___pa23___lsb 23 -#define reg_pinmux_rw_iop_pa___pa23___width 1 -#define reg_pinmux_rw_iop_pa___pa23___bit 23 -#define reg_pinmux_rw_iop_pa___pa24___lsb 24 -#define reg_pinmux_rw_iop_pa___pa24___width 1 -#define reg_pinmux_rw_iop_pa___pa24___bit 24 -#define reg_pinmux_rw_iop_pa___pa25___lsb 25 -#define reg_pinmux_rw_iop_pa___pa25___width 1 -#define reg_pinmux_rw_iop_pa___pa25___bit 25 -#define reg_pinmux_rw_iop_pa___pa26___lsb 26 -#define reg_pinmux_rw_iop_pa___pa26___width 1 -#define reg_pinmux_rw_iop_pa___pa26___bit 26 -#define reg_pinmux_rw_iop_pa___pa27___lsb 27 -#define reg_pinmux_rw_iop_pa___pa27___width 1 -#define reg_pinmux_rw_iop_pa___pa27___bit 27 -#define reg_pinmux_rw_iop_pa___pa28___lsb 28 -#define reg_pinmux_rw_iop_pa___pa28___width 1 -#define reg_pinmux_rw_iop_pa___pa28___bit 28 -#define reg_pinmux_rw_iop_pa___pa29___lsb 29 -#define reg_pinmux_rw_iop_pa___pa29___width 1 -#define reg_pinmux_rw_iop_pa___pa29___bit 29 -#define reg_pinmux_rw_iop_pa___pa30___lsb 30 -#define reg_pinmux_rw_iop_pa___pa30___width 1 -#define reg_pinmux_rw_iop_pa___pa30___bit 30 -#define reg_pinmux_rw_iop_pa___pa31___lsb 31 -#define reg_pinmux_rw_iop_pa___pa31___width 1 -#define reg_pinmux_rw_iop_pa___pa31___bit 31 -#define reg_pinmux_rw_iop_pa_offset 16 - -/* Register rw_iop_pb, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pb___pb0___lsb 0 -#define reg_pinmux_rw_iop_pb___pb0___width 1 -#define reg_pinmux_rw_iop_pb___pb0___bit 0 -#define reg_pinmux_rw_iop_pb___pb1___lsb 1 -#define reg_pinmux_rw_iop_pb___pb1___width 1 -#define reg_pinmux_rw_iop_pb___pb1___bit 1 -#define reg_pinmux_rw_iop_pb___pb2___lsb 2 -#define reg_pinmux_rw_iop_pb___pb2___width 1 -#define reg_pinmux_rw_iop_pb___pb2___bit 2 -#define reg_pinmux_rw_iop_pb___pb3___lsb 3 -#define reg_pinmux_rw_iop_pb___pb3___width 1 -#define reg_pinmux_rw_iop_pb___pb3___bit 3 -#define reg_pinmux_rw_iop_pb___pb4___lsb 4 -#define reg_pinmux_rw_iop_pb___pb4___width 1 -#define reg_pinmux_rw_iop_pb___pb4___bit 4 -#define reg_pinmux_rw_iop_pb___pb5___lsb 5 -#define reg_pinmux_rw_iop_pb___pb5___width 1 -#define reg_pinmux_rw_iop_pb___pb5___bit 5 -#define reg_pinmux_rw_iop_pb___pb6___lsb 6 -#define reg_pinmux_rw_iop_pb___pb6___width 1 -#define reg_pinmux_rw_iop_pb___pb6___bit 6 -#define reg_pinmux_rw_iop_pb___pb7___lsb 7 -#define reg_pinmux_rw_iop_pb___pb7___width 1 -#define reg_pinmux_rw_iop_pb___pb7___bit 7 -#define reg_pinmux_rw_iop_pb_offset 20 - -/* Register rw_iop_pio, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_pio___d0___lsb 0 -#define reg_pinmux_rw_iop_pio___d0___width 1 -#define reg_pinmux_rw_iop_pio___d0___bit 0 -#define reg_pinmux_rw_iop_pio___d1___lsb 1 -#define reg_pinmux_rw_iop_pio___d1___width 1 -#define reg_pinmux_rw_iop_pio___d1___bit 1 -#define reg_pinmux_rw_iop_pio___d2___lsb 2 -#define reg_pinmux_rw_iop_pio___d2___width 1 -#define reg_pinmux_rw_iop_pio___d2___bit 2 -#define reg_pinmux_rw_iop_pio___d3___lsb 3 -#define reg_pinmux_rw_iop_pio___d3___width 1 -#define reg_pinmux_rw_iop_pio___d3___bit 3 -#define reg_pinmux_rw_iop_pio___d4___lsb 4 -#define reg_pinmux_rw_iop_pio___d4___width 1 -#define reg_pinmux_rw_iop_pio___d4___bit 4 -#define reg_pinmux_rw_iop_pio___d5___lsb 5 -#define reg_pinmux_rw_iop_pio___d5___width 1 -#define reg_pinmux_rw_iop_pio___d5___bit 5 -#define reg_pinmux_rw_iop_pio___d6___lsb 6 -#define reg_pinmux_rw_iop_pio___d6___width 1 -#define reg_pinmux_rw_iop_pio___d6___bit 6 -#define reg_pinmux_rw_iop_pio___d7___lsb 7 -#define reg_pinmux_rw_iop_pio___d7___width 1 -#define reg_pinmux_rw_iop_pio___d7___bit 7 -#define reg_pinmux_rw_iop_pio___rd_n___lsb 8 -#define reg_pinmux_rw_iop_pio___rd_n___width 1 -#define reg_pinmux_rw_iop_pio___rd_n___bit 8 -#define reg_pinmux_rw_iop_pio___wr_n___lsb 9 -#define reg_pinmux_rw_iop_pio___wr_n___width 1 -#define reg_pinmux_rw_iop_pio___wr_n___bit 9 -#define reg_pinmux_rw_iop_pio___a0___lsb 10 -#define reg_pinmux_rw_iop_pio___a0___width 1 -#define reg_pinmux_rw_iop_pio___a0___bit 10 -#define reg_pinmux_rw_iop_pio___a1___lsb 11 -#define reg_pinmux_rw_iop_pio___a1___width 1 -#define reg_pinmux_rw_iop_pio___a1___bit 11 -#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12 -#define reg_pinmux_rw_iop_pio___ce0_n___width 1 -#define reg_pinmux_rw_iop_pio___ce0_n___bit 12 -#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13 -#define reg_pinmux_rw_iop_pio___ce1_n___width 1 -#define reg_pinmux_rw_iop_pio___ce1_n___bit 13 -#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14 -#define reg_pinmux_rw_iop_pio___ce2_n___width 1 -#define reg_pinmux_rw_iop_pio___ce2_n___bit 14 -#define reg_pinmux_rw_iop_pio___rdy___lsb 15 -#define reg_pinmux_rw_iop_pio___rdy___width 1 -#define reg_pinmux_rw_iop_pio___rdy___bit 15 -#define reg_pinmux_rw_iop_pio_offset 24 - -/* Register rw_iop_usb, scope pinmux, type rw */ -#define reg_pinmux_rw_iop_usb___usb0___lsb 0 -#define reg_pinmux_rw_iop_usb___usb0___width 1 -#define reg_pinmux_rw_iop_usb___usb0___bit 0 -#define reg_pinmux_rw_iop_usb_offset 28 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_gio_pa_default 0x00000000 -#define regk_pinmux_rw_gio_pb_default 0x00000000 -#define regk_pinmux_rw_gio_pc_default 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_iop_pa_default 0x00000000 -#define regk_pinmux_rw_iop_pb_default 0x00000000 -#define regk_pinmux_rw_iop_pio_default 0x00000000 -#define regk_pinmux_rw_iop_usb_default 0x00000001 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h deleted file mode 100644 index 463bb9e2c38e..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h +++ /dev/null @@ -1,338 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pio_defs_asm_h -#define __pio_defs_asm_h - -/* - * This file is autogenerated from - * file: pio.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_data, scope pio, type rw */ -#define reg_pio_rw_data_offset 64 - -/* Register rw_io_access0, scope pio, type rw */ -#define reg_pio_rw_io_access0___data___lsb 0 -#define reg_pio_rw_io_access0___data___width 8 -#define reg_pio_rw_io_access0_offset 0 - -/* Register rw_io_access1, scope pio, type rw */ -#define reg_pio_rw_io_access1___data___lsb 0 -#define reg_pio_rw_io_access1___data___width 8 -#define reg_pio_rw_io_access1_offset 4 - -/* Register rw_io_access2, scope pio, type rw */ -#define reg_pio_rw_io_access2___data___lsb 0 -#define reg_pio_rw_io_access2___data___width 8 -#define reg_pio_rw_io_access2_offset 8 - -/* Register rw_io_access3, scope pio, type rw */ -#define reg_pio_rw_io_access3___data___lsb 0 -#define reg_pio_rw_io_access3___data___width 8 -#define reg_pio_rw_io_access3_offset 12 - -/* Register rw_io_access4, scope pio, type rw */ -#define reg_pio_rw_io_access4___data___lsb 0 -#define reg_pio_rw_io_access4___data___width 8 -#define reg_pio_rw_io_access4_offset 16 - -/* Register rw_io_access5, scope pio, type rw */ -#define reg_pio_rw_io_access5___data___lsb 0 -#define reg_pio_rw_io_access5___data___width 8 -#define reg_pio_rw_io_access5_offset 20 - -/* Register rw_io_access6, scope pio, type rw */ -#define reg_pio_rw_io_access6___data___lsb 0 -#define reg_pio_rw_io_access6___data___width 8 -#define reg_pio_rw_io_access6_offset 24 - -/* Register rw_io_access7, scope pio, type rw */ -#define reg_pio_rw_io_access7___data___lsb 0 -#define reg_pio_rw_io_access7___data___width 8 -#define reg_pio_rw_io_access7_offset 28 - -/* Register rw_io_access8, scope pio, type rw */ -#define reg_pio_rw_io_access8___data___lsb 0 -#define reg_pio_rw_io_access8___data___width 8 -#define reg_pio_rw_io_access8_offset 32 - -/* Register rw_io_access9, scope pio, type rw */ -#define reg_pio_rw_io_access9___data___lsb 0 -#define reg_pio_rw_io_access9___data___width 8 -#define reg_pio_rw_io_access9_offset 36 - -/* Register rw_io_access10, scope pio, type rw */ -#define reg_pio_rw_io_access10___data___lsb 0 -#define reg_pio_rw_io_access10___data___width 8 -#define reg_pio_rw_io_access10_offset 40 - -/* Register rw_io_access11, scope pio, type rw */ -#define reg_pio_rw_io_access11___data___lsb 0 -#define reg_pio_rw_io_access11___data___width 8 -#define reg_pio_rw_io_access11_offset 44 - -/* Register rw_io_access12, scope pio, type rw */ -#define reg_pio_rw_io_access12___data___lsb 0 -#define reg_pio_rw_io_access12___data___width 8 -#define reg_pio_rw_io_access12_offset 48 - -/* Register rw_io_access13, scope pio, type rw */ -#define reg_pio_rw_io_access13___data___lsb 0 -#define reg_pio_rw_io_access13___data___width 8 -#define reg_pio_rw_io_access13_offset 52 - -/* Register rw_io_access14, scope pio, type rw */ -#define reg_pio_rw_io_access14___data___lsb 0 -#define reg_pio_rw_io_access14___data___width 8 -#define reg_pio_rw_io_access14_offset 56 - -/* Register rw_io_access15, scope pio, type rw */ -#define reg_pio_rw_io_access15___data___lsb 0 -#define reg_pio_rw_io_access15___data___width 8 -#define reg_pio_rw_io_access15_offset 60 - -/* Register rw_ce0_cfg, scope pio, type rw */ -#define reg_pio_rw_ce0_cfg___lw___lsb 0 -#define reg_pio_rw_ce0_cfg___lw___width 6 -#define reg_pio_rw_ce0_cfg___ew___lsb 6 -#define reg_pio_rw_ce0_cfg___ew___width 3 -#define reg_pio_rw_ce0_cfg___zw___lsb 9 -#define reg_pio_rw_ce0_cfg___zw___width 3 -#define reg_pio_rw_ce0_cfg___aw___lsb 12 -#define reg_pio_rw_ce0_cfg___aw___width 2 -#define reg_pio_rw_ce0_cfg___mode___lsb 14 -#define reg_pio_rw_ce0_cfg___mode___width 2 -#define reg_pio_rw_ce0_cfg_offset 68 - -/* Register rw_ce1_cfg, scope pio, type rw */ -#define reg_pio_rw_ce1_cfg___lw___lsb 0 -#define reg_pio_rw_ce1_cfg___lw___width 6 -#define reg_pio_rw_ce1_cfg___ew___lsb 6 -#define reg_pio_rw_ce1_cfg___ew___width 3 -#define reg_pio_rw_ce1_cfg___zw___lsb 9 -#define reg_pio_rw_ce1_cfg___zw___width 3 -#define reg_pio_rw_ce1_cfg___aw___lsb 12 -#define reg_pio_rw_ce1_cfg___aw___width 2 -#define reg_pio_rw_ce1_cfg___mode___lsb 14 -#define reg_pio_rw_ce1_cfg___mode___width 2 -#define reg_pio_rw_ce1_cfg_offset 72 - -/* Register rw_ce2_cfg, scope pio, type rw */ -#define reg_pio_rw_ce2_cfg___lw___lsb 0 -#define reg_pio_rw_ce2_cfg___lw___width 6 -#define reg_pio_rw_ce2_cfg___ew___lsb 6 -#define reg_pio_rw_ce2_cfg___ew___width 3 -#define reg_pio_rw_ce2_cfg___zw___lsb 9 -#define reg_pio_rw_ce2_cfg___zw___width 3 -#define reg_pio_rw_ce2_cfg___aw___lsb 12 -#define reg_pio_rw_ce2_cfg___aw___width 2 -#define reg_pio_rw_ce2_cfg___mode___lsb 14 -#define reg_pio_rw_ce2_cfg___mode___width 2 -#define reg_pio_rw_ce2_cfg_offset 76 - -/* Register rw_dout, scope pio, type rw */ -#define reg_pio_rw_dout___data___lsb 0 -#define reg_pio_rw_dout___data___width 8 -#define reg_pio_rw_dout___rd_n___lsb 8 -#define reg_pio_rw_dout___rd_n___width 1 -#define reg_pio_rw_dout___rd_n___bit 8 -#define reg_pio_rw_dout___wr_n___lsb 9 -#define reg_pio_rw_dout___wr_n___width 1 -#define reg_pio_rw_dout___wr_n___bit 9 -#define reg_pio_rw_dout___a0___lsb 10 -#define reg_pio_rw_dout___a0___width 1 -#define reg_pio_rw_dout___a0___bit 10 -#define reg_pio_rw_dout___a1___lsb 11 -#define reg_pio_rw_dout___a1___width 1 -#define reg_pio_rw_dout___a1___bit 11 -#define reg_pio_rw_dout___ce0_n___lsb 12 -#define reg_pio_rw_dout___ce0_n___width 1 -#define reg_pio_rw_dout___ce0_n___bit 12 -#define reg_pio_rw_dout___ce1_n___lsb 13 -#define reg_pio_rw_dout___ce1_n___width 1 -#define reg_pio_rw_dout___ce1_n___bit 13 -#define reg_pio_rw_dout___ce2_n___lsb 14 -#define reg_pio_rw_dout___ce2_n___width 1 -#define reg_pio_rw_dout___ce2_n___bit 14 -#define reg_pio_rw_dout___rdy___lsb 15 -#define reg_pio_rw_dout___rdy___width 1 -#define reg_pio_rw_dout___rdy___bit 15 -#define reg_pio_rw_dout_offset 80 - -/* Register rw_oe, scope pio, type rw */ -#define reg_pio_rw_oe___data___lsb 0 -#define reg_pio_rw_oe___data___width 8 -#define reg_pio_rw_oe___rd_n___lsb 8 -#define reg_pio_rw_oe___rd_n___width 1 -#define reg_pio_rw_oe___rd_n___bit 8 -#define reg_pio_rw_oe___wr_n___lsb 9 -#define reg_pio_rw_oe___wr_n___width 1 -#define reg_pio_rw_oe___wr_n___bit 9 -#define reg_pio_rw_oe___a0___lsb 10 -#define reg_pio_rw_oe___a0___width 1 -#define reg_pio_rw_oe___a0___bit 10 -#define reg_pio_rw_oe___a1___lsb 11 -#define reg_pio_rw_oe___a1___width 1 -#define reg_pio_rw_oe___a1___bit 11 -#define reg_pio_rw_oe___ce0_n___lsb 12 -#define reg_pio_rw_oe___ce0_n___width 1 -#define reg_pio_rw_oe___ce0_n___bit 12 -#define reg_pio_rw_oe___ce1_n___lsb 13 -#define reg_pio_rw_oe___ce1_n___width 1 -#define reg_pio_rw_oe___ce1_n___bit 13 -#define reg_pio_rw_oe___ce2_n___lsb 14 -#define reg_pio_rw_oe___ce2_n___width 1 -#define reg_pio_rw_oe___ce2_n___bit 14 -#define reg_pio_rw_oe___rdy___lsb 15 -#define reg_pio_rw_oe___rdy___width 1 -#define reg_pio_rw_oe___rdy___bit 15 -#define reg_pio_rw_oe_offset 84 - -/* Register rw_man_ctrl, scope pio, type rw */ -#define reg_pio_rw_man_ctrl___data___lsb 0 -#define reg_pio_rw_man_ctrl___data___width 8 -#define reg_pio_rw_man_ctrl___rd_n___lsb 8 -#define reg_pio_rw_man_ctrl___rd_n___width 1 -#define reg_pio_rw_man_ctrl___rd_n___bit 8 -#define reg_pio_rw_man_ctrl___wr_n___lsb 9 -#define reg_pio_rw_man_ctrl___wr_n___width 1 -#define reg_pio_rw_man_ctrl___wr_n___bit 9 -#define reg_pio_rw_man_ctrl___a0___lsb 10 -#define reg_pio_rw_man_ctrl___a0___width 1 -#define reg_pio_rw_man_ctrl___a0___bit 10 -#define reg_pio_rw_man_ctrl___a1___lsb 11 -#define reg_pio_rw_man_ctrl___a1___width 1 -#define reg_pio_rw_man_ctrl___a1___bit 11 -#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 -#define reg_pio_rw_man_ctrl___ce0_n___width 1 -#define reg_pio_rw_man_ctrl___ce0_n___bit 12 -#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 -#define reg_pio_rw_man_ctrl___ce1_n___width 1 -#define reg_pio_rw_man_ctrl___ce1_n___bit 13 -#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 -#define reg_pio_rw_man_ctrl___ce2_n___width 1 -#define reg_pio_rw_man_ctrl___ce2_n___bit 14 -#define reg_pio_rw_man_ctrl___rdy___lsb 15 -#define reg_pio_rw_man_ctrl___rdy___width 1 -#define reg_pio_rw_man_ctrl___rdy___bit 15 -#define reg_pio_rw_man_ctrl_offset 88 - -/* Register r_din, scope pio, type r */ -#define reg_pio_r_din___data___lsb 0 -#define reg_pio_r_din___data___width 8 -#define reg_pio_r_din___rd_n___lsb 8 -#define reg_pio_r_din___rd_n___width 1 -#define reg_pio_r_din___rd_n___bit 8 -#define reg_pio_r_din___wr_n___lsb 9 -#define reg_pio_r_din___wr_n___width 1 -#define reg_pio_r_din___wr_n___bit 9 -#define reg_pio_r_din___a0___lsb 10 -#define reg_pio_r_din___a0___width 1 -#define reg_pio_r_din___a0___bit 10 -#define reg_pio_r_din___a1___lsb 11 -#define reg_pio_r_din___a1___width 1 -#define reg_pio_r_din___a1___bit 11 -#define reg_pio_r_din___ce0_n___lsb 12 -#define reg_pio_r_din___ce0_n___width 1 -#define reg_pio_r_din___ce0_n___bit 12 -#define reg_pio_r_din___ce1_n___lsb 13 -#define reg_pio_r_din___ce1_n___width 1 -#define reg_pio_r_din___ce1_n___bit 13 -#define reg_pio_r_din___ce2_n___lsb 14 -#define reg_pio_r_din___ce2_n___width 1 -#define reg_pio_r_din___ce2_n___bit 14 -#define reg_pio_r_din___rdy___lsb 15 -#define reg_pio_r_din___rdy___width 1 -#define reg_pio_r_din___rdy___bit 15 -#define reg_pio_r_din_offset 92 - -/* Register r_stat, scope pio, type r */ -#define reg_pio_r_stat___busy___lsb 0 -#define reg_pio_r_stat___busy___width 1 -#define reg_pio_r_stat___busy___bit 0 -#define reg_pio_r_stat_offset 96 - -/* Register rw_intr_mask, scope pio, type rw */ -#define reg_pio_rw_intr_mask___rdy___lsb 0 -#define reg_pio_rw_intr_mask___rdy___width 1 -#define reg_pio_rw_intr_mask___rdy___bit 0 -#define reg_pio_rw_intr_mask_offset 100 - -/* Register rw_ack_intr, scope pio, type rw */ -#define reg_pio_rw_ack_intr___rdy___lsb 0 -#define reg_pio_rw_ack_intr___rdy___width 1 -#define reg_pio_rw_ack_intr___rdy___bit 0 -#define reg_pio_rw_ack_intr_offset 104 - -/* Register r_intr, scope pio, type r */ -#define reg_pio_r_intr___rdy___lsb 0 -#define reg_pio_r_intr___rdy___width 1 -#define reg_pio_r_intr___rdy___bit 0 -#define reg_pio_r_intr_offset 108 - -/* Register r_masked_intr, scope pio, type r */ -#define reg_pio_r_masked_intr___rdy___lsb 0 -#define reg_pio_r_masked_intr___rdy___width 1 -#define reg_pio_r_masked_intr___rdy___bit 0 -#define reg_pio_r_masked_intr_offset 112 - - -/* Constants */ -#define regk_pio_a2 0x00000003 -#define regk_pio_no 0x00000000 -#define regk_pio_normal 0x00000000 -#define regk_pio_rd 0x00000001 -#define regk_pio_rw_ce0_cfg_default 0x00000000 -#define regk_pio_rw_ce1_cfg_default 0x00000000 -#define regk_pio_rw_ce2_cfg_default 0x00000000 -#define regk_pio_rw_intr_mask_default 0x00000000 -#define regk_pio_rw_man_ctrl_default 0x00000000 -#define regk_pio_rw_oe_default 0x00000000 -#define regk_pio_wr 0x00000002 -#define regk_pio_wr_ce2 0x00000003 -#define regk_pio_yes 0x00000001 -#define regk_pio_yes_all 0x000000ff -#endif /* __pio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h deleted file mode 100644 index e3bf8e0692a6..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __reg_map_asm_h -#define __reg_map_asm_h - -/* - * This file is autogenerated from - * file: reg.rmap - * - * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_ccd 0xb0000000 -#define regi_ccd_top 0xb0000000 -#define regi_ccd_dp 0xb0000400 -#define regi_ccd_stat 0xb0000800 -#define regi_ccd_tg 0xb0001000 -#define regi_cfg 0xb0002000 -#define regi_clkgen 0xb0004000 -#define regi_ddr2_ctrl 0xb0006000 -#define regi_dma0 0xb0008000 -#define regi_dma1 0xb000a000 -#define regi_dma11 0xb000c000 -#define regi_dma2 0xb000e000 -#define regi_dma3 0xb0010000 -#define regi_dma4 0xb0012000 -#define regi_dma5 0xb0014000 -#define regi_dma6 0xb0016000 -#define regi_dma7 0xb0018000 -#define regi_dma9 0xb001a000 -#define regi_eth 0xb001c000 -#define regi_gio 0xb0020000 -#define regi_h264 0xb0022000 -#define regi_hist 0xb0026000 -#define regi_iop 0xb0028000 -#define regi_iop_version 0xb0028000 -#define regi_iop_fifo_in_extra 0xb0028040 -#define regi_iop_fifo_out_extra 0xb0028080 -#define regi_iop_trigger_grp0 0xb00280c0 -#define regi_iop_trigger_grp1 0xb0028100 -#define regi_iop_trigger_grp2 0xb0028140 -#define regi_iop_trigger_grp3 0xb0028180 -#define regi_iop_trigger_grp4 0xb00281c0 -#define regi_iop_trigger_grp5 0xb0028200 -#define regi_iop_trigger_grp6 0xb0028240 -#define regi_iop_trigger_grp7 0xb0028280 -#define regi_iop_crc_par 0xb0028300 -#define regi_iop_dmc_in 0xb0028380 -#define regi_iop_dmc_out 0xb0028400 -#define regi_iop_fifo_in 0xb0028480 -#define regi_iop_fifo_out 0xb0028500 -#define regi_iop_scrc_in 0xb0028580 -#define regi_iop_scrc_out 0xb0028600 -#define regi_iop_timer_grp0 0xb0028680 -#define regi_iop_timer_grp1 0xb0028700 -#define regi_iop_sap_in 0xb0028800 -#define regi_iop_sap_out 0xb0028900 -#define regi_iop_spu 0xb0028a00 -#define regi_iop_sw_cfg 0xb0028b00 -#define regi_iop_sw_cpu 0xb0028c00 -#define regi_iop_sw_mpu 0xb0028d00 -#define regi_iop_sw_spu 0xb0028e00 -#define regi_iop_mpu 0xb0029000 -#define regi_irq 0xb002a000 -#define regi_jpeg 0xb002c000 -#define regi_l2cache 0xb0030000 -#define regi_marb_bar 0xb0032000 -#define regi_marb_bar_bp0 0xb0032140 -#define regi_marb_bar_bp1 0xb0032180 -#define regi_marb_bar_bp2 0xb00321c0 -#define regi_marb_bar_bp3 0xb0032200 -#define regi_marb_foo 0xb0034000 -#define regi_marb_foo_bp0 0xb0034280 -#define regi_marb_foo_bp1 0xb00342c0 -#define regi_marb_foo_bp2 0xb0034300 -#define regi_marb_foo_bp3 0xb0034340 -#define regi_pinmux 0xb0038000 -#define regi_pio 0xb0036000 -#define regi_sclr 0xb003a000 -#define regi_sclr_fifo 0xb003c000 -#define regi_ser0 0xb003e000 -#define regi_ser1 0xb0040000 -#define regi_ser2 0xb0042000 -#define regi_ser3 0xb0044000 -#define regi_ser4 0xb0046000 -#define regi_sser 0xb0048000 -#define regi_strcop 0xb004a000 -#define regi_strdma0 0xb004e000 -#define regi_strdma1 0xb0050000 -#define regi_strdma2 0xb0052000 -#define regi_strdma3 0xb0054000 -#define regi_strdma5 0xb0056000 -#define regi_strmux 0xb004c000 -#define regi_timer0 0xb0058000 -#define regi_timer1 0xb005a000 -#define regi_trace 0xb005c000 -#define regi_vin 0xb005e000 -#define regi_vout 0xb0060000 -#endif /* __reg_map_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 82da59c382c2..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: timer.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_f90 0x00000003 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_vclk 0x00000002 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h deleted file mode 100644 index 32d58fed3b03..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __clkgen_defs_h -#define __clkgen_defs_h - -/* - * This file is autogenerated from - * file: clkgen.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope clkgen */ - -/* Register r_bootsel, scope clkgen, type r */ -typedef struct { - unsigned int boot_mode : 5; - unsigned int intern_main_clk : 1; - unsigned int extern_usb2_clk : 1; - unsigned int dummy1 : 25; -} reg_clkgen_r_bootsel; -#define REG_RD_ADDR_clkgen_r_bootsel 0 - -/* Register rw_clk_ctrl, scope clkgen, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop_usb : 1; - unsigned int vin : 1; - unsigned int sclr : 1; - unsigned int h264 : 1; - unsigned int ddr2 : 1; - unsigned int vout_hist : 1; - unsigned int eth : 1; - unsigned int ccd_tg_200 : 1; - unsigned int dma0_1_eth : 1; - unsigned int ccd_tg_100 : 1; - unsigned int jpeg : 1; - unsigned int sser_ser_dma6_7 : 1; - unsigned int strdma0_2_video : 1; - unsigned int dma2_3_strcop : 1; - unsigned int dma4_5_iop : 1; - unsigned int dma9_11 : 1; - unsigned int memarb_bar_ddr : 1; - unsigned int sclr_h264 : 1; - unsigned int dummy1 : 12; -} reg_clkgen_rw_clk_ctrl; -#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4 -#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4 - - -/* Constants */ -enum { - regk_clkgen_eth1000_rx = 0x0000000c, - regk_clkgen_eth1000_tx = 0x0000000e, - regk_clkgen_eth100_rx = 0x0000001d, - regk_clkgen_eth100_rx_half = 0x0000001c, - regk_clkgen_eth100_tx = 0x0000001f, - regk_clkgen_eth100_tx_half = 0x0000001e, - regk_clkgen_nand_3_2 = 0x00000000, - regk_clkgen_nand_3_2_0x30 = 0x00000002, - regk_clkgen_nand_3_2_0x30_pll = 0x00000012, - regk_clkgen_nand_3_2_pll = 0x00000010, - regk_clkgen_nand_3_3 = 0x00000001, - regk_clkgen_nand_3_3_0x30 = 0x00000003, - regk_clkgen_nand_3_3_0x30_pll = 0x00000013, - regk_clkgen_nand_3_3_pll = 0x00000011, - regk_clkgen_nand_4_2 = 0x00000004, - regk_clkgen_nand_4_2_0x30 = 0x00000006, - regk_clkgen_nand_4_2_0x30_pll = 0x00000016, - regk_clkgen_nand_4_2_pll = 0x00000014, - regk_clkgen_nand_4_3 = 0x00000005, - regk_clkgen_nand_4_3_0x30 = 0x00000007, - regk_clkgen_nand_4_3_0x30_pll = 0x00000017, - regk_clkgen_nand_4_3_pll = 0x00000015, - regk_clkgen_nand_5_2 = 0x00000008, - regk_clkgen_nand_5_2_0x30 = 0x0000000a, - regk_clkgen_nand_5_2_0x30_pll = 0x0000001a, - regk_clkgen_nand_5_2_pll = 0x00000018, - regk_clkgen_nand_5_3 = 0x00000009, - regk_clkgen_nand_5_3_0x30 = 0x0000000b, - regk_clkgen_nand_5_3_0x30_pll = 0x0000001b, - regk_clkgen_nand_5_3_pll = 0x00000019, - regk_clkgen_no = 0x00000000, - regk_clkgen_rw_clk_ctrl_default = 0x00000002, - regk_clkgen_ser = 0x0000000d, - regk_clkgen_ser_pll = 0x0000000f, - regk_clkgen_yes = 0x00000001 -}; -#endif /* __clkgen_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h deleted file mode 100644 index 84684c335d7d..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ddr2_defs_h -#define __ddr2_defs_h - -/* - * This file is autogenerated from - * file: ddr2.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope ddr2 */ - -/* Register rw_cfg, scope ddr2, type rw */ -typedef struct { - unsigned int col_width : 4; - unsigned int nr_banks : 1; - unsigned int bw : 1; - unsigned int nr_ref : 4; - unsigned int ref_interval : 11; - unsigned int odt_ctrl : 2; - unsigned int odt_mem : 1; - unsigned int imp_strength : 1; - unsigned int auto_imp_cal : 1; - unsigned int imp_cal_override : 1; - unsigned int dll_override : 1; - unsigned int dummy1 : 4; -} reg_ddr2_rw_cfg; -#define REG_RD_ADDR_ddr2_rw_cfg 0 -#define REG_WR_ADDR_ddr2_rw_cfg 0 - -/* Register rw_timing, scope ddr2, type rw */ -typedef struct { - unsigned int wr : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int ras : 4; - unsigned int rfc : 7; - unsigned int rc : 5; - unsigned int rtp : 2; - unsigned int rtw : 3; - unsigned int wtr : 2; -} reg_ddr2_rw_timing; -#define REG_RD_ADDR_ddr2_rw_timing 4 -#define REG_WR_ADDR_ddr2_rw_timing 4 - -/* Register rw_latency, scope ddr2, type rw */ -typedef struct { - unsigned int cas : 3; - unsigned int additive : 3; - unsigned int dummy1 : 26; -} reg_ddr2_rw_latency; -#define REG_RD_ADDR_ddr2_rw_latency 8 -#define REG_WR_ADDR_ddr2_rw_latency 8 - -/* Register rw_phy_cfg, scope ddr2, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_ddr2_rw_phy_cfg; -#define REG_RD_ADDR_ddr2_rw_phy_cfg 12 -#define REG_WR_ADDR_ddr2_rw_phy_cfg 12 - -/* Register rw_phy_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int rst : 1; - unsigned int cal_rst : 1; - unsigned int cal_start : 1; - unsigned int dummy1 : 29; -} reg_ddr2_rw_phy_ctrl; -#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16 -#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16 - -/* Register rw_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int mrs_data : 16; - unsigned int cmd : 8; - unsigned int dummy1 : 8; -} reg_ddr2_rw_ctrl; -#define REG_RD_ADDR_ddr2_rw_ctrl 20 -#define REG_WR_ADDR_ddr2_rw_ctrl 20 - -/* Register rw_pwr_down, scope ddr2, type rw */ -typedef struct { - unsigned int self_ref : 2; - unsigned int phy_en : 1; - unsigned int dummy1 : 29; -} reg_ddr2_rw_pwr_down; -#define REG_RD_ADDR_ddr2_rw_pwr_down 24 -#define REG_WR_ADDR_ddr2_rw_pwr_down 24 - -/* Register r_stat, scope ddr2, type r */ -typedef struct { - unsigned int dll_lock : 1; - unsigned int dll_delay_code : 7; - unsigned int imp_cal_done : 1; - unsigned int imp_cal_fault : 1; - unsigned int cal_imp_pu : 4; - unsigned int cal_imp_pd : 4; - unsigned int dummy1 : 14; -} reg_ddr2_r_stat; -#define REG_RD_ADDR_ddr2_r_stat 28 - -/* Register rw_imp_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int imp_pu : 4; - unsigned int imp_pd : 4; - unsigned int dummy1 : 24; -} reg_ddr2_rw_imp_ctrl; -#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32 -#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32 - -#define STRIDE_ddr2_rw_dll_ctrl 4 -/* Register rw_dll_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int mode : 1; - unsigned int clk_delay : 7; - unsigned int dummy1 : 24; -} reg_ddr2_rw_dll_ctrl; -#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36 -#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36 - -#define STRIDE_ddr2_rw_dqs_dll_ctrl 4 -/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */ -typedef struct { - unsigned int dqs90_delay : 7; - unsigned int dqs180_delay : 7; - unsigned int dqs270_delay : 7; - unsigned int dqs360_delay : 7; - unsigned int dummy1 : 4; -} reg_ddr2_rw_dqs_dll_ctrl; -#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52 -#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52 - - -/* Constants */ -enum { - regk_ddr2_al0 = 0x00000000, - regk_ddr2_al1 = 0x00000008, - regk_ddr2_al2 = 0x00000010, - regk_ddr2_al3 = 0x00000018, - regk_ddr2_al4 = 0x00000020, - regk_ddr2_auto = 0x00000003, - regk_ddr2_bank4 = 0x00000000, - regk_ddr2_bank8 = 0x00000001, - regk_ddr2_bl4 = 0x00000002, - regk_ddr2_bl8 = 0x00000003, - regk_ddr2_bt_il = 0x00000008, - regk_ddr2_bt_seq = 0x00000000, - regk_ddr2_bw16 = 0x00000001, - regk_ddr2_bw32 = 0x00000000, - regk_ddr2_cas2 = 0x00000020, - regk_ddr2_cas3 = 0x00000030, - regk_ddr2_cas4 = 0x00000040, - regk_ddr2_cas5 = 0x00000050, - regk_ddr2_deselect = 0x000000c0, - regk_ddr2_dic_weak = 0x00000002, - regk_ddr2_direct = 0x00000001, - regk_ddr2_dis = 0x00000000, - regk_ddr2_dll_dis = 0x00000001, - regk_ddr2_dll_en = 0x00000000, - regk_ddr2_dll_rst = 0x00000100, - regk_ddr2_emrs = 0x00000081, - regk_ddr2_emrs2 = 0x00000082, - regk_ddr2_emrs3 = 0x00000083, - regk_ddr2_full = 0x00000001, - regk_ddr2_hi_ref_rate = 0x00000080, - regk_ddr2_mrs = 0x00000080, - regk_ddr2_no = 0x00000000, - regk_ddr2_nop = 0x000000b8, - regk_ddr2_ocd_adj = 0x00000200, - regk_ddr2_ocd_default = 0x00000380, - regk_ddr2_ocd_drive0 = 0x00000100, - regk_ddr2_ocd_drive1 = 0x00000080, - regk_ddr2_ocd_exit = 0x00000000, - regk_ddr2_odt_dis = 0x00000000, - regk_ddr2_offs = 0x00000000, - regk_ddr2_pre = 0x00000090, - regk_ddr2_pre_all = 0x00000400, - regk_ddr2_pwr_down_fast = 0x00000000, - regk_ddr2_pwr_down_slow = 0x00001000, - regk_ddr2_ref = 0x00000088, - regk_ddr2_rtt150 = 0x00000040, - regk_ddr2_rtt50 = 0x00000044, - regk_ddr2_rtt75 = 0x00000004, - regk_ddr2_rw_cfg_default = 0x00186000, - regk_ddr2_rw_dll_ctrl_default = 0x00000000, - regk_ddr2_rw_dll_ctrl_size = 0x00000004, - regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000, - regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004, - regk_ddr2_rw_latency_default = 0x00000000, - regk_ddr2_rw_phy_cfg_default = 0x00000000, - regk_ddr2_rw_pwr_down_default = 0x00000000, - regk_ddr2_rw_timing_default = 0x00000000, - regk_ddr2_s1Gb = 0x0000001a, - regk_ddr2_s256Mb = 0x0000000f, - regk_ddr2_s2Gb = 0x00000027, - regk_ddr2_s4Gb = 0x00000042, - regk_ddr2_s512Mb = 0x00000015, - regk_ddr2_temp0_85 = 0x00000618, - regk_ddr2_temp85_95 = 0x0000030c, - regk_ddr2_term150 = 0x00000002, - regk_ddr2_term50 = 0x00000003, - regk_ddr2_term75 = 0x00000001, - regk_ddr2_test = 0x00000080, - regk_ddr2_weak = 0x00000000, - regk_ddr2_wr2 = 0x00000200, - regk_ddr2_wr3 = 0x00000400, - regk_ddr2_yes = 0x00000001 -}; -#endif /* __ddr2_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h deleted file mode 100644 index 83ab1f495612..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h +++ /dev/null @@ -1,838 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: gio.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 0 - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 32; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 4 -#define REG_WR_ADDR_gio_rw_pa_dout 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 32; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_pa_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte0_dout; -#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 -#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 - -/* Register rw_pa_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte0_oe; -#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 -#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 - -/* Register rw_pa_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte1_dout; -#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 -#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 - -/* Register rw_pa_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte1_oe; -#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 -#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 - -/* Register rw_pa_byte2_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte2_dout; -#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 -#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 - -/* Register rw_pa_byte2_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte2_oe; -#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 -#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 - -/* Register rw_pa_byte3_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte3_dout; -#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 -#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 - -/* Register rw_pa_byte3_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_byte3_oe; -#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 -#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 44 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 32; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 48 -#define REG_WR_ADDR_gio_rw_pb_dout 48 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 32; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 52 -#define REG_WR_ADDR_gio_rw_pb_oe 52 - -/* Register rw_pb_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte0_dout; -#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 -#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 - -/* Register rw_pb_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte0_oe; -#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 -#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 - -/* Register rw_pb_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte1_dout; -#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 -#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 - -/* Register rw_pb_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte1_oe; -#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 -#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 - -/* Register rw_pb_byte2_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte2_dout; -#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 -#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 - -/* Register rw_pb_byte2_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte2_oe; -#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 -#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 - -/* Register rw_pb_byte3_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte3_dout; -#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 -#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 - -/* Register rw_pb_byte3_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pb_byte3_oe; -#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 -#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 88 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 16; - unsigned int dummy1 : 16; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 92 -#define REG_WR_ADDR_gio_rw_pc_dout 92 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 16; - unsigned int dummy1 : 16; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 96 -#define REG_WR_ADDR_gio_rw_pc_oe 96 - -/* Register rw_pc_byte0_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte0_dout; -#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 -#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 - -/* Register rw_pc_byte0_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte0_oe; -#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 -#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 - -/* Register rw_pc_byte1_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte1_dout; -#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 -#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 - -/* Register rw_pc_byte1_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pc_byte1_oe; -#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 -#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 116 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 3; - unsigned int intr1 : 3; - unsigned int intr2 : 3; - unsigned int intr3 : 3; - unsigned int intr4 : 3; - unsigned int intr5 : 3; - unsigned int intr6 : 3; - unsigned int intr7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 120 -#define REG_WR_ADDR_gio_rw_intr_cfg 120 - -/* Register rw_intr_pins, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 4; - unsigned int intr1 : 4; - unsigned int intr2 : 4; - unsigned int intr3 : 4; - unsigned int intr4 : 4; - unsigned int intr5 : 4; - unsigned int intr6 : 4; - unsigned int intr7 : 4; -} reg_gio_rw_intr_pins; -#define REG_RD_ADDR_gio_rw_intr_pins 124 -#define REG_WR_ADDR_gio_rw_intr_pins 124 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 128 -#define REG_WR_ADDR_gio_rw_intr_mask 128 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 132 -#define REG_WR_ADDR_gio_rw_ack_intr 132 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 136 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int i2c0_done : 1; - unsigned int i2c1_done : 1; - unsigned int dummy1 : 22; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 140 - -/* Register rw_i2c0_start, scope gio, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_gio_rw_i2c0_start; -#define REG_RD_ADDR_gio_rw_i2c0_start 144 -#define REG_WR_ADDR_gio_rw_i2c0_start 144 - -/* Register rw_i2c0_cfg, scope gio, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int bit_order : 1; - unsigned int scl_io : 1; - unsigned int scl_inv : 1; - unsigned int sda_io : 1; - unsigned int sda_idle : 1; - unsigned int dummy1 : 26; -} reg_gio_rw_i2c0_cfg; -#define REG_RD_ADDR_gio_rw_i2c0_cfg 148 -#define REG_WR_ADDR_gio_rw_i2c0_cfg 148 - -/* Register rw_i2c0_ctrl, scope gio, type rw */ -typedef struct { - unsigned int trf_bits : 6; - unsigned int switch_dir : 6; - unsigned int extra_start : 3; - unsigned int early_end : 1; - unsigned int start_stop : 1; - unsigned int ack_dir0 : 1; - unsigned int ack_dir1 : 1; - unsigned int ack_dir2 : 1; - unsigned int ack_dir3 : 1; - unsigned int ack_dir4 : 1; - unsigned int ack_dir5 : 1; - unsigned int ack_bit : 1; - unsigned int start_bit : 1; - unsigned int freq : 2; - unsigned int dummy1 : 5; -} reg_gio_rw_i2c0_ctrl; -#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 -#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 - -/* Register rw_i2c0_data, scope gio, type rw */ -typedef struct { - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int data2 : 8; - unsigned int data3 : 8; -} reg_gio_rw_i2c0_data; -#define REG_RD_ADDR_gio_rw_i2c0_data 156 -#define REG_WR_ADDR_gio_rw_i2c0_data 156 - -/* Register rw_i2c0_data2, scope gio, type rw */ -typedef struct { - unsigned int data4 : 8; - unsigned int data5 : 8; - unsigned int start_val : 6; - unsigned int ack_val : 6; - unsigned int dummy1 : 4; -} reg_gio_rw_i2c0_data2; -#define REG_RD_ADDR_gio_rw_i2c0_data2 160 -#define REG_WR_ADDR_gio_rw_i2c0_data2 160 - -/* Register rw_i2c1_start, scope gio, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_gio_rw_i2c1_start; -#define REG_RD_ADDR_gio_rw_i2c1_start 164 -#define REG_WR_ADDR_gio_rw_i2c1_start 164 - -/* Register rw_i2c1_cfg, scope gio, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int bit_order : 1; - unsigned int scl_io : 1; - unsigned int scl_inv : 1; - unsigned int sda0_io : 1; - unsigned int sda0_idle : 1; - unsigned int sda1_io : 1; - unsigned int sda1_idle : 1; - unsigned int sda2_io : 1; - unsigned int sda2_idle : 1; - unsigned int sda3_io : 1; - unsigned int sda3_idle : 1; - unsigned int sda_sel : 2; - unsigned int sen_idle : 1; - unsigned int sen_inv : 1; - unsigned int sen_sel : 2; - unsigned int dummy1 : 14; -} reg_gio_rw_i2c1_cfg; -#define REG_RD_ADDR_gio_rw_i2c1_cfg 168 -#define REG_WR_ADDR_gio_rw_i2c1_cfg 168 - -/* Register rw_i2c1_ctrl, scope gio, type rw */ -typedef struct { - unsigned int trf_bits : 6; - unsigned int switch_dir : 6; - unsigned int extra_start : 3; - unsigned int early_end : 1; - unsigned int start_stop : 1; - unsigned int ack_dir0 : 1; - unsigned int ack_dir1 : 1; - unsigned int ack_dir2 : 1; - unsigned int ack_dir3 : 1; - unsigned int ack_dir4 : 1; - unsigned int ack_dir5 : 1; - unsigned int ack_bit : 1; - unsigned int start_bit : 1; - unsigned int freq : 2; - unsigned int dummy1 : 5; -} reg_gio_rw_i2c1_ctrl; -#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 -#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 - -/* Register rw_i2c1_data, scope gio, type rw */ -typedef struct { - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int data2 : 8; - unsigned int data3 : 8; -} reg_gio_rw_i2c1_data; -#define REG_RD_ADDR_gio_rw_i2c1_data 176 -#define REG_WR_ADDR_gio_rw_i2c1_data 176 - -/* Register rw_i2c1_data2, scope gio, type rw */ -typedef struct { - unsigned int data4 : 8; - unsigned int data5 : 8; - unsigned int start_val : 6; - unsigned int ack_val : 6; - unsigned int dummy1 : 4; -} reg_gio_rw_i2c1_data2; -#define REG_RD_ADDR_gio_rw_i2c1_data2 180 -#define REG_WR_ADDR_gio_rw_i2c1_data2 180 - -/* Register r_ppwm_stat, scope gio, type r */ -typedef struct { - unsigned int freq : 2; - unsigned int dummy1 : 30; -} reg_gio_r_ppwm_stat; -#define REG_RD_ADDR_gio_r_ppwm_stat 184 - -/* Register rw_ppwm_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_ppwm_data; -#define REG_RD_ADDR_gio_rw_ppwm_data 188 -#define REG_WR_ADDR_gio_rw_ppwm_data 188 - -/* Register rw_pwm0_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm0_ctrl; -#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 -#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 - -/* Register rw_pwm0_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm0_var; -#define REG_RD_ADDR_gio_rw_pwm0_var 196 -#define REG_WR_ADDR_gio_rw_pwm0_var 196 - -/* Register rw_pwm0_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm0_data; -#define REG_RD_ADDR_gio_rw_pwm0_data 200 -#define REG_WR_ADDR_gio_rw_pwm0_data 200 - -/* Register rw_pwm1_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm1_ctrl; -#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 -#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 - -/* Register rw_pwm1_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm1_var; -#define REG_RD_ADDR_gio_rw_pwm1_var 208 -#define REG_WR_ADDR_gio_rw_pwm1_var 208 - -/* Register rw_pwm1_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm1_data; -#define REG_RD_ADDR_gio_rw_pwm1_data 212 -#define REG_WR_ADDR_gio_rw_pwm1_data 212 - -/* Register rw_pwm2_ctrl, scope gio, type rw */ -typedef struct { - unsigned int mode : 2; - unsigned int ccd_override : 1; - unsigned int ccd_val : 1; - unsigned int dummy1 : 28; -} reg_gio_rw_pwm2_ctrl; -#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 -#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 - -/* Register rw_pwm2_var, scope gio, type rw */ -typedef struct { - unsigned int lo : 13; - unsigned int hi : 13; - unsigned int dummy1 : 6; -} reg_gio_rw_pwm2_var; -#define REG_RD_ADDR_gio_rw_pwm2_var 220 -#define REG_WR_ADDR_gio_rw_pwm2_var 220 - -/* Register rw_pwm2_data, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pwm2_data; -#define REG_RD_ADDR_gio_rw_pwm2_data 224 -#define REG_WR_ADDR_gio_rw_pwm2_data 224 - -/* Register rw_pwm_in_cfg, scope gio, type rw */ -typedef struct { - unsigned int pin : 3; - unsigned int dummy1 : 29; -} reg_gio_rw_pwm_in_cfg; -#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 -#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 - -/* Register r_pwm_in_lo, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_lo; -#define REG_RD_ADDR_gio_r_pwm_in_lo 232 - -/* Register r_pwm_in_hi, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_hi; -#define REG_RD_ADDR_gio_r_pwm_in_hi 236 - -/* Register r_pwm_in_cnt, scope gio, type r */ -typedef struct { - unsigned int data : 32; -} reg_gio_r_pwm_in_cnt; -#define REG_RD_ADDR_gio_r_pwm_in_cnt 240 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_f100k = 0x00000000, - regk_gio_f1562 = 0x00000000, - regk_gio_f195 = 0x00000003, - regk_gio_f1m = 0x00000002, - regk_gio_f390 = 0x00000002, - regk_gio_f400k = 0x00000001, - regk_gio_f5m = 0x00000003, - regk_gio_f781 = 0x00000001, - regk_gio_hi = 0x00000001, - regk_gio_in = 0x00000000, - regk_gio_intr_pa0 = 0x00000000, - regk_gio_intr_pa1 = 0x00000000, - regk_gio_intr_pa10 = 0x00000001, - regk_gio_intr_pa11 = 0x00000001, - regk_gio_intr_pa12 = 0x00000001, - regk_gio_intr_pa13 = 0x00000001, - regk_gio_intr_pa14 = 0x00000001, - regk_gio_intr_pa15 = 0x00000001, - regk_gio_intr_pa16 = 0x00000002, - regk_gio_intr_pa17 = 0x00000002, - regk_gio_intr_pa18 = 0x00000002, - regk_gio_intr_pa19 = 0x00000002, - regk_gio_intr_pa2 = 0x00000000, - regk_gio_intr_pa20 = 0x00000002, - regk_gio_intr_pa21 = 0x00000002, - regk_gio_intr_pa22 = 0x00000002, - regk_gio_intr_pa23 = 0x00000002, - regk_gio_intr_pa24 = 0x00000003, - regk_gio_intr_pa25 = 0x00000003, - regk_gio_intr_pa26 = 0x00000003, - regk_gio_intr_pa27 = 0x00000003, - regk_gio_intr_pa28 = 0x00000003, - regk_gio_intr_pa29 = 0x00000003, - regk_gio_intr_pa3 = 0x00000000, - regk_gio_intr_pa30 = 0x00000003, - regk_gio_intr_pa31 = 0x00000003, - regk_gio_intr_pa4 = 0x00000000, - regk_gio_intr_pa5 = 0x00000000, - regk_gio_intr_pa6 = 0x00000000, - regk_gio_intr_pa7 = 0x00000000, - regk_gio_intr_pa8 = 0x00000001, - regk_gio_intr_pa9 = 0x00000001, - regk_gio_intr_pb0 = 0x00000004, - regk_gio_intr_pb1 = 0x00000004, - regk_gio_intr_pb10 = 0x00000005, - regk_gio_intr_pb11 = 0x00000005, - regk_gio_intr_pb12 = 0x00000005, - regk_gio_intr_pb13 = 0x00000005, - regk_gio_intr_pb14 = 0x00000005, - regk_gio_intr_pb15 = 0x00000005, - regk_gio_intr_pb16 = 0x00000006, - regk_gio_intr_pb17 = 0x00000006, - regk_gio_intr_pb18 = 0x00000006, - regk_gio_intr_pb19 = 0x00000006, - regk_gio_intr_pb2 = 0x00000004, - regk_gio_intr_pb20 = 0x00000006, - regk_gio_intr_pb21 = 0x00000006, - regk_gio_intr_pb22 = 0x00000006, - regk_gio_intr_pb23 = 0x00000006, - regk_gio_intr_pb24 = 0x00000007, - regk_gio_intr_pb25 = 0x00000007, - regk_gio_intr_pb26 = 0x00000007, - regk_gio_intr_pb27 = 0x00000007, - regk_gio_intr_pb28 = 0x00000007, - regk_gio_intr_pb29 = 0x00000007, - regk_gio_intr_pb3 = 0x00000004, - regk_gio_intr_pb30 = 0x00000007, - regk_gio_intr_pb31 = 0x00000007, - regk_gio_intr_pb4 = 0x00000004, - regk_gio_intr_pb5 = 0x00000004, - regk_gio_intr_pb6 = 0x00000004, - regk_gio_intr_pb7 = 0x00000004, - regk_gio_intr_pb8 = 0x00000005, - regk_gio_intr_pb9 = 0x00000005, - regk_gio_intr_pc0 = 0x00000008, - regk_gio_intr_pc1 = 0x00000008, - regk_gio_intr_pc10 = 0x00000009, - regk_gio_intr_pc11 = 0x00000009, - regk_gio_intr_pc12 = 0x00000009, - regk_gio_intr_pc13 = 0x00000009, - regk_gio_intr_pc14 = 0x00000009, - regk_gio_intr_pc15 = 0x00000009, - regk_gio_intr_pc2 = 0x00000008, - regk_gio_intr_pc3 = 0x00000008, - regk_gio_intr_pc4 = 0x00000008, - regk_gio_intr_pc5 = 0x00000008, - regk_gio_intr_pc6 = 0x00000008, - regk_gio_intr_pc7 = 0x00000008, - regk_gio_intr_pc8 = 0x00000009, - regk_gio_intr_pc9 = 0x00000009, - regk_gio_intr_pd0 = 0x0000000c, - regk_gio_intr_pd1 = 0x0000000c, - regk_gio_intr_pd10 = 0x0000000d, - regk_gio_intr_pd11 = 0x0000000d, - regk_gio_intr_pd12 = 0x0000000d, - regk_gio_intr_pd13 = 0x0000000d, - regk_gio_intr_pd14 = 0x0000000d, - regk_gio_intr_pd15 = 0x0000000d, - regk_gio_intr_pd16 = 0x0000000e, - regk_gio_intr_pd17 = 0x0000000e, - regk_gio_intr_pd18 = 0x0000000e, - regk_gio_intr_pd19 = 0x0000000e, - regk_gio_intr_pd2 = 0x0000000c, - regk_gio_intr_pd20 = 0x0000000e, - regk_gio_intr_pd21 = 0x0000000e, - regk_gio_intr_pd22 = 0x0000000e, - regk_gio_intr_pd23 = 0x0000000e, - regk_gio_intr_pd24 = 0x0000000f, - regk_gio_intr_pd25 = 0x0000000f, - regk_gio_intr_pd26 = 0x0000000f, - regk_gio_intr_pd27 = 0x0000000f, - regk_gio_intr_pd28 = 0x0000000f, - regk_gio_intr_pd29 = 0x0000000f, - regk_gio_intr_pd3 = 0x0000000c, - regk_gio_intr_pd30 = 0x0000000f, - regk_gio_intr_pd31 = 0x0000000f, - regk_gio_intr_pd4 = 0x0000000c, - regk_gio_intr_pd5 = 0x0000000c, - regk_gio_intr_pd6 = 0x0000000c, - regk_gio_intr_pd7 = 0x0000000c, - regk_gio_intr_pd8 = 0x0000000d, - regk_gio_intr_pd9 = 0x0000000d, - regk_gio_lo = 0x00000002, - regk_gio_lsb = 0x00000000, - regk_gio_msb = 0x00000001, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_no_switch = 0x0000003f, - regk_gio_none = 0x00000007, - regk_gio_off = 0x00000000, - regk_gio_opendrain = 0x00000000, - regk_gio_out = 0x00000001, - regk_gio_posedge = 0x00000005, - regk_gio_pwm_hfp = 0x00000002, - regk_gio_pwm_pa0 = 0x00000001, - regk_gio_pwm_pa19 = 0x00000004, - regk_gio_pwm_pa6 = 0x00000002, - regk_gio_pwm_pa7 = 0x00000003, - regk_gio_pwm_pb26 = 0x00000005, - regk_gio_pwm_pd23 = 0x00000006, - regk_gio_pwm_pd31 = 0x00000007, - regk_gio_pwm_std = 0x00000001, - regk_gio_pwm_var = 0x00000003, - regk_gio_rw_i2c0_cfg_default = 0x00000020, - regk_gio_rw_i2c0_ctrl_default = 0x00010000, - regk_gio_rw_i2c0_start_default = 0x00000000, - regk_gio_rw_i2c1_cfg_default = 0x00000aa0, - regk_gio_rw_i2c1_ctrl_default = 0x00010000, - regk_gio_rw_i2c1_start_default = 0x00000000, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_ppwm_data_default = 0x00000000, - regk_gio_rw_pwm0_ctrl_default = 0x00000000, - regk_gio_rw_pwm1_ctrl_default = 0x00000000, - regk_gio_rw_pwm2_ctrl_default = 0x00000000, - regk_gio_rw_pwm_in_cfg_default = 0x00000000, - regk_gio_sda0 = 0x00000000, - regk_gio_sda1 = 0x00000001, - regk_gio_sda2 = 0x00000002, - regk_gio_sda3 = 0x00000003, - regk_gio_sen = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h deleted file mode 100644 index 55dab5bd7bd3..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr - from intr_vect.r */ - -#ifndef _INTR_VECT_R -#define _INTR_VECT_R -#define TIMER0_INTR_VECT 0x31 -#define TIMER1_INTR_VECT 0x32 -#define DMA0_INTR_VECT 0x33 -#define DMA1_INTR_VECT 0x34 -#define DMA2_INTR_VECT 0x35 -#define DMA3_INTR_VECT 0x36 -#define DMA4_INTR_VECT 0x37 -#define DMA5_INTR_VECT 0x38 -#define DMA6_INTR_VECT 0x39 -#define DMA7_INTR_VECT 0x3a -#define DMA9_INTR_VECT 0x3b -#define DMA11_INTR_VECT 0x3c -#define GIO_INTR_VECT 0x3d -#define IOP0_INTR_VECT 0x3e -#define IOP1_INTR_VECT 0x3f -#define SER0_INTR_VECT 0x40 -#define SER1_INTR_VECT 0x41 -#define SER2_INTR_VECT 0x42 -#define SER3_INTR_VECT 0x43 -#define SER4_INTR_VECT 0x44 -#define SSER_INTR_VECT 0x45 -#define STRDMA0_INTR_VECT 0x46 -#define STRDMA1_INTR_VECT 0x47 -#define STRDMA2_INTR_VECT 0x48 -#define STRDMA3_INTR_VECT 0x49 -#define STRDMA5_INTR_VECT 0x4a -#define VIN_INTR_VECT 0x4b -#define VOUT_INTR_VECT 0x4c -#define JPEG_INTR_VECT 0x4d -#define H264_INTR_VECT 0x4e -#define HISTO_INTR_VECT 0x4f -#define CCD_INTR_VECT 0x50 -#define ETH_INTR_VECT 0x51 -#define MEMARB_BAR_INTR_VECT 0x52 -#define MEMARB_FOO_INTR_VECT 0x53 -#define PIO_INTR_VECT 0x54 -#define SCLR_INTR_VECT 0x55 -#define SCLR_FIFO_INTR_VECT 0x56 -#define IPI_INTR_VECT 0x57 -#define NBR_INTR_VECT 0x58 -#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h deleted file mode 100644 index 71a28d1ed74a..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,342 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: intr_vect.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - - -#define STRIDE_intr_vect_rw_mask 4 -/* Register rw_mask0, scope intr_vect, type rw */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_rw_mask0; -#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0 -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 -#define REG_RD_ADDR_intr_vect_rw_mask0 0 -#define REG_WR_ADDR_intr_vect_rw_mask0 0 - -#define STRIDE_intr_vect_r_vect 4 -/* Register r_vect0, scope intr_vect, type r */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_r_vect0; -#define reg_intr_vect_r_vect reg_intr_vect_r_vect0 -#define REG_RD_ADDR_intr_vect_r_vect 8 -#define REG_RD_ADDR_intr_vect_r_vect0 8 - -#define STRIDE_intr_vect_r_masked_vect 4 -/* Register r_masked_vect0, scope intr_vect, type r */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_r_masked_vect0; -#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0 -#define REG_RD_ADDR_intr_vect_r_masked_vect0 16 -#define REG_RD_ADDR_intr_vect_r_masked_vect 16 - -#define STRIDE_intr_vect_rw_xmask 4 -/* Register rw_xmask0, scope intr_vect, type rw */ -typedef struct { - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int gio : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int strdma0 : 1; - unsigned int strdma1 : 1; - unsigned int strdma2 : 1; - unsigned int strdma3 : 1; - unsigned int strdma5 : 1; - unsigned int vin : 1; - unsigned int vout : 1; - unsigned int jpeg : 1; - unsigned int h264 : 1; - unsigned int histo : 1; - unsigned int ccd : 1; -} reg_intr_vect_rw_xmask0; -#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0 -#define REG_RD_ADDR_intr_vect_rw_xmask0 24 -#define REG_WR_ADDR_intr_vect_rw_xmask0 24 -#define REG_RD_ADDR_intr_vect_rw_xmask 24 -#define REG_WR_ADDR_intr_vect_rw_xmask 24 - -/* Register rw_mask1, scope intr_vect, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_rw_mask1; -#define REG_RD_ADDR_intr_vect_rw_mask1 4 -#define REG_WR_ADDR_intr_vect_rw_mask1 4 - -/* Register r_vect1, scope intr_vect, type r */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_r_vect1; -#define REG_RD_ADDR_intr_vect_r_vect1 12 - -/* Register r_masked_vect1, scope intr_vect, type r */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_r_masked_vect1; -#define REG_RD_ADDR_intr_vect_r_masked_vect1 20 - -/* Register rw_xmask1, scope intr_vect, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int memarb_bar : 1; - unsigned int memarb_foo : 1; - unsigned int pio : 1; - unsigned int sclr : 1; - unsigned int sclr_fifo : 1; - unsigned int dummy1 : 26; -} reg_intr_vect_rw_xmask1; -#define REG_RD_ADDR_intr_vect_rw_xmask1 28 -#define REG_WR_ADDR_intr_vect_rw_xmask1 28 - -/* Register rw_xmask_ctrl, scope intr_vect, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_rw_xmask_ctrl; -#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32 -#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int watchdog0 : 1; - unsigned int watchdog1 : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 64 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 68 - - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 72 -#define REG_WR_ADDR_intr_vect_rw_ipi 72 - -/* Constants */ -enum { - regk_intr_vect_no = 0x00000000, - regk_intr_vect_rw_mask0_default = 0x00000000, - regk_intr_vect_rw_mask1_default = 0x00000000, - regk_intr_vect_rw_xmask0_default = 0x00000000, - regk_intr_vect_rw_xmask1_default = 0x00000000, - regk_intr_vect_rw_xmask_ctrl_default = 0x00000000, - regk_intr_vect_yes = 0x00000001 -}; -#endif /* __intr_vect_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index 5e5f4d94aecf..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in_extra 64 -#define iop_fifo_out_extra 128 -#define iop_trigger_grp0 192 -#define iop_trigger_grp1 256 -#define iop_trigger_grp2 320 -#define iop_trigger_grp3 384 -#define iop_trigger_grp4 448 -#define iop_trigger_grp5 512 -#define iop_trigger_grp6 576 -#define iop_trigger_grp7 640 -#define iop_crc_par 768 -#define iop_dmc_in 896 -#define iop_dmc_out 1024 -#define iop_fifo_in 1152 -#define iop_fifo_out 1280 -#define iop_scrc_in 1408 -#define iop_scrc_out 1536 -#define iop_timer_grp0 1664 -#define iop_timer_grp1 1792 -#define iop_sap_in 2048 -#define iop_sap_out 2304 -#define iop_spu 2560 -#define iop_sw_cfg 2816 -#define iop_sw_cpu 3072 -#define iop_sw_mpu 3328 -#define iop_sw_spu 3584 -#define iop_mpu 4096 diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index ee0587ec433c..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 -#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 -#define reg_iop_sap_in_rw_bus_byte___delay___width 2 -#define reg_iop_sap_in_rw_bus_byte_offset 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 2 -#define reg_iop_sap_in_rw_gio___logic___lsb 9 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio0 0x00000000 -#define regk_iop_sap_in_gio12 0x00000003 -#define regk_iop_sap_in_gio16 0x00000004 -#define regk_iop_sap_in_gio20 0x00000005 -#define regk_iop_sap_in_gio24 0x00000006 -#define regk_iop_sap_in_gio28 0x00000007 -#define regk_iop_sap_in_gio4 0x00000001 -#define regk_iop_sap_in_gio8 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_one 0x00000001 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 -#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 -#define regk_iop_sap_in_rw_gio_default 0x00000000 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 -#define regk_iop_sap_in_tmr_clk200 0x00000001 -#define regk_iop_sap_in_two 0x00000002 -#define regk_iop_sap_in_two_clk200 0x00000000 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 9bbe0b920c93..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 -#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 -#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 -#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 -#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 -#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 -#define reg_iop_sap_out_rw_bus_offset 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 -#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 -#define reg_iop_sap_out_rw_gio___out_delay___width 1 -#define reg_iop_sap_out_rw_gio___out_delay___bit 7 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 -#define reg_iop_sap_out_rw_gio___out_logic___width 2 -#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 -#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_delay___width 1 -#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 -#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 -#define reg_iop_sap_out_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_out_always 0x00000001 -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000004 -#define regk_iop_sap_out_clk200 0x00000000 -#define regk_iop_sap_out_ext 0x00000002 -#define regk_iop_sap_out_gated 0x00000003 -#define regk_iop_sap_out_gio0 0x00000000 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio16 0x00000002 -#define regk_iop_sap_out_gio17 0x00000002 -#define regk_iop_sap_out_gio24 0x00000003 -#define regk_iop_sap_out_gio25 0x00000003 -#define regk_iop_sap_out_gio8 0x00000001 -#define regk_iop_sap_out_gio9 0x00000001 -#define regk_iop_sap_out_gio_out10 0x00000005 -#define regk_iop_sap_out_gio_out18 0x00000006 -#define regk_iop_sap_out_gio_out2 0x00000004 -#define regk_iop_sap_out_gio_out26 0x00000007 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_one 0x00000001 -#define regk_iop_sap_out_rw_bus_default 0x00000000 -#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu_gio6 0x00000002 -#define regk_iop_sap_out_spu_gio7 0x00000003 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 -#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 -#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 -#define regk_iop_sap_out_tmr200 0x00000001 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index c4b8bc386cb6..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,740 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 -#define reg_iop_sw_cfg_rw_spu_owner_offset 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus_mask_offset 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 -#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus 0x00000000 -#define regk_iop_sw_cfg_bus_rot16 0x00000002 -#define regk_iop_sw_cfg_bus_rot24 0x00000003 -#define regk_iop_sw_cfg_bus_rot8 0x00000001 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_gated_clk0 0x0000000e -#define regk_iop_sw_cfg_gated_clk1 0x0000000f -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_pdp_out 0x00000001 -#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 -#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out 0x00000004 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 -#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 -#define regk_iop_sw_cfg_spu_g0 0x00000007 -#define regk_iop_sw_cfg_spu_g1 0x00000007 -#define regk_iop_sw_cfg_spu_g2 0x00000007 -#define regk_iop_sw_cfg_spu_g3 0x00000007 -#define regk_iop_sw_cfg_spu_g4 0x00000007 -#define regk_iop_sw_cfg_spu_g5 0x00000007 -#define regk_iop_sw_cfg_spu_g6 0x00000007 -#define regk_iop_sw_cfg_spu_g7 0x00000007 -#define regk_iop_sw_cfg_spu_gio0 0x00000000 -#define regk_iop_sw_cfg_spu_gio1 0x00000001 -#define regk_iop_sw_cfg_spu_gio5 0x00000005 -#define regk_iop_sw_cfg_spu_gio6 0x00000006 -#define regk_iop_sw_cfg_spu_gio7 0x00000007 -#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu_gioout10 0x00000007 -#define regk_iop_sw_cfg_spu_gioout11 0x00000007 -#define regk_iop_sw_cfg_spu_gioout12 0x00000007 -#define regk_iop_sw_cfg_spu_gioout13 0x00000007 -#define regk_iop_sw_cfg_spu_gioout14 0x00000007 -#define regk_iop_sw_cfg_spu_gioout15 0x00000007 -#define regk_iop_sw_cfg_spu_gioout16 0x00000007 -#define regk_iop_sw_cfg_spu_gioout17 0x00000007 -#define regk_iop_sw_cfg_spu_gioout18 0x00000007 -#define regk_iop_sw_cfg_spu_gioout19 0x00000007 -#define regk_iop_sw_cfg_spu_gioout2 0x00000001 -#define regk_iop_sw_cfg_spu_gioout20 0x00000007 -#define regk_iop_sw_cfg_spu_gioout21 0x00000007 -#define regk_iop_sw_cfg_spu_gioout22 0x00000007 -#define regk_iop_sw_cfg_spu_gioout23 0x00000007 -#define regk_iop_sw_cfg_spu_gioout24 0x00000007 -#define regk_iop_sw_cfg_spu_gioout25 0x00000007 -#define regk_iop_sw_cfg_spu_gioout26 0x00000007 -#define regk_iop_sw_cfg_spu_gioout27 0x00000007 -#define regk_iop_sw_cfg_spu_gioout28 0x00000007 -#define regk_iop_sw_cfg_spu_gioout29 0x00000007 -#define regk_iop_sw_cfg_spu_gioout3 0x00000001 -#define regk_iop_sw_cfg_spu_gioout30 0x00000007 -#define regk_iop_sw_cfg_spu_gioout31 0x00000007 -#define regk_iop_sw_cfg_spu_gioout4 0x00000002 -#define regk_iop_sw_cfg_spu_gioout5 0x00000002 -#define regk_iop_sw_cfg_spu_gioout6 0x00000003 -#define regk_iop_sw_cfg_spu_gioout7 0x00000003 -#define regk_iop_sw_cfg_spu_gioout8 0x00000007 -#define regk_iop_sw_cfg_spu_gioout9 0x00000007 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000001 -#define regk_iop_sw_cfg_trig2_1 0x00000001 -#define regk_iop_sw_cfg_trig2_2 0x00000001 -#define regk_iop_sw_cfg_trig2_3 0x00000001 -#define regk_iop_sw_cfg_trig3_0 0x00000001 -#define regk_iop_sw_cfg_trig3_1 0x00000001 -#define regk_iop_sw_cfg_trig3_2 0x00000001 -#define regk_iop_sw_cfg_trig3_3 0x00000001 -#define regk_iop_sw_cfg_trig4_0 0x00000002 -#define regk_iop_sw_cfg_trig4_1 0x00000002 -#define regk_iop_sw_cfg_trig4_2 0x00000002 -#define regk_iop_sw_cfg_trig4_3 0x00000002 -#define regk_iop_sw_cfg_trig5_0 0x00000002 -#define regk_iop_sw_cfg_trig5_1 0x00000002 -#define regk_iop_sw_cfg_trig5_2 0x00000002 -#define regk_iop_sw_cfg_trig5_3 0x00000002 -#define regk_iop_sw_cfg_trig6_0 0x00000003 -#define regk_iop_sw_cfg_trig6_1 0x00000003 -#define regk_iop_sw_cfg_trig6_2 0x00000003 -#define regk_iop_sw_cfg_trig6_3 0x00000003 -#define regk_iop_sw_cfg_trig7_0 0x00000003 -#define regk_iop_sw_cfg_trig7_1 0x00000003 -#define regk_iop_sw_cfg_trig7_2 0x00000003 -#define regk_iop_sw_cfg_trig7_3 0x00000003 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index 89f36dc1f96d..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,951 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mpu_trace_offset 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 104 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index 45e19d79dba9..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1087 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0_offset 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1_offset 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2_offset 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3_offset 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu 0x00000002 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 55afb6e320e4..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,524 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_trace_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_spu_r_mc_stat_offset 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus_in_offset 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 -#define reg_iop_sw_spu_r_hw_intr_offset 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr_offset 132 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index 79ff8fafd3bf..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v2_0 0x00000002 -#endif /* __iop_version_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 23d731f36145..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in_extra (regi_iop + 64) -#define regi_iop_fifo_out_extra (regi_iop + 128) -#define regi_iop_trigger_grp0 (regi_iop + 192) -#define regi_iop_trigger_grp1 (regi_iop + 256) -#define regi_iop_trigger_grp2 (regi_iop + 320) -#define regi_iop_trigger_grp3 (regi_iop + 384) -#define regi_iop_trigger_grp4 (regi_iop + 448) -#define regi_iop_trigger_grp5 (regi_iop + 512) -#define regi_iop_trigger_grp6 (regi_iop + 576) -#define regi_iop_trigger_grp7 (regi_iop + 640) -#define regi_iop_crc_par (regi_iop + 768) -#define regi_iop_dmc_in (regi_iop + 896) -#define regi_iop_dmc_out (regi_iop + 1024) -#define regi_iop_fifo_in (regi_iop + 1152) -#define regi_iop_fifo_out (regi_iop + 1280) -#define regi_iop_scrc_in (regi_iop + 1408) -#define regi_iop_scrc_out (regi_iop + 1536) -#define regi_iop_timer_grp0 (regi_iop + 1664) -#define regi_iop_timer_grp1 (regi_iop + 1792) -#define regi_iop_sap_in (regi_iop + 2048) -#define regi_iop_sap_out (regi_iop + 2304) -#define regi_iop_spu (regi_iop + 2560) -#define regi_iop_sw_cfg (regi_iop + 2816) -#define regi_iop_sw_cpu (regi_iop + 3072) -#define regi_iop_sw_mpu (regi_iop + 3328) -#define regi_iop_sw_spu (regi_iop + 3584) -#define regi_iop_mpu (regi_iop + 4096) diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 1d6c09a3230d..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int dummy1 : 23; -} reg_iop_sap_in_rw_bus_byte; -#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int logic : 2; - unsigned int dummy1 : 21; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 16 -#define REG_WR_ADDR_iop_sap_in_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio0 = 0x00000000, - regk_iop_sap_in_gio12 = 0x00000003, - regk_iop_sap_in_gio16 = 0x00000004, - regk_iop_sap_in_gio20 = 0x00000005, - regk_iop_sap_in_gio24 = 0x00000006, - regk_iop_sap_in_gio28 = 0x00000007, - regk_iop_sap_in_gio4 = 0x00000001, - regk_iop_sap_in_gio8 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_one = 0x00000001, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus_byte_default = 0x00000000, - regk_iop_sap_in_rw_bus_byte_size = 0x00000004, - regk_iop_sap_in_rw_gio_default = 0x00000000, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, - regk_iop_sap_in_tmr_clk200 = 0x00000001, - regk_iop_sap_in_two = 0x00000002, - regk_iop_sap_in_two_clk200 = 0x00000000 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 1cbd30efadb7..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,232 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int dummy1 : 18; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_bus; -#define REG_RD_ADDR_iop_sap_out_rw_bus 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte0_logic : 2; - unsigned int byte0_logic_src : 2; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte1_logic : 2; - unsigned int byte1_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte2_logic : 2; - unsigned int byte2_logic_src : 2; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int byte3_logic : 2; - unsigned int byte3_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 2; - unsigned int out_gated_clk : 1; - unsigned int out_clk_inv : 1; - unsigned int out_delay : 1; - unsigned int out_logic : 2; - unsigned int out_logic_src : 2; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 2; - unsigned int oe_gated_clk : 1; - unsigned int oe_clk_inv : 1; - unsigned int oe_delay : 1; - unsigned int oe_logic : 2; - unsigned int oe_logic_src : 2; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 16 -#define REG_WR_ADDR_iop_sap_out_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_out_always = 0x00000001, - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000004, - regk_iop_sap_out_clk200 = 0x00000000, - regk_iop_sap_out_ext = 0x00000002, - regk_iop_sap_out_gated = 0x00000003, - regk_iop_sap_out_gio0 = 0x00000000, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio16 = 0x00000002, - regk_iop_sap_out_gio17 = 0x00000002, - regk_iop_sap_out_gio24 = 0x00000003, - regk_iop_sap_out_gio25 = 0x00000003, - regk_iop_sap_out_gio8 = 0x00000001, - regk_iop_sap_out_gio9 = 0x00000001, - regk_iop_sap_out_gio_out10 = 0x00000005, - regk_iop_sap_out_gio_out18 = 0x00000006, - regk_iop_sap_out_gio_out2 = 0x00000004, - regk_iop_sap_out_gio_out26 = 0x00000007, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_one = 0x00000001, - regk_iop_sap_out_rw_bus_default = 0x00000000, - regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu_gio6 = 0x00000002, - regk_iop_sap_out_spu_gio7 = 0x00000003, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, - regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, - regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, - regk_iop_sap_out_tmr200 = 0x00000001, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index 07050b053bb4..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,726 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 1; - unsigned int dummy1 : 31; -} reg_iop_sw_cfg_rw_spu_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_byte0 : 2; - unsigned int bus_byte1 : 2; - unsigned int bus_byte2 : 2; - unsigned int bus_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_lo : 2; - unsigned int bus_hi : 2; - unsigned int bus_lo_oe : 2; - unsigned int bus_hi_oe : 2; - unsigned int dummy1 : 24; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 3; - unsigned int gio0_oe : 1; - unsigned int gio1 : 3; - unsigned int gio1_oe : 1; - unsigned int gio2 : 3; - unsigned int gio2_oe : 1; - unsigned int gio3 : 3; - unsigned int gio3_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 3; - unsigned int gio4_oe : 1; - unsigned int gio5 : 3; - unsigned int gio5_oe : 1; - unsigned int gio6 : 3; - unsigned int gio6_oe : 1; - unsigned int gio7 : 3; - unsigned int gio7_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 3; - unsigned int gio8_oe : 1; - unsigned int gio9 : 3; - unsigned int gio9_oe : 1; - unsigned int gio10 : 3; - unsigned int gio10_oe : 1; - unsigned int gio11 : 3; - unsigned int gio11_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 3; - unsigned int gio12_oe : 1; - unsigned int gio13 : 3; - unsigned int gio13_oe : 1; - unsigned int gio14 : 3; - unsigned int gio14_oe : 1; - unsigned int gio15 : 3; - unsigned int gio15_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 3; - unsigned int gio16_oe : 1; - unsigned int gio17 : 3; - unsigned int gio17_oe : 1; - unsigned int gio18 : 3; - unsigned int gio18_oe : 1; - unsigned int gio19 : 3; - unsigned int gio19_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 3; - unsigned int gio20_oe : 1; - unsigned int gio21 : 3; - unsigned int gio21_oe : 1; - unsigned int gio22 : 3; - unsigned int gio22_oe : 1; - unsigned int gio23 : 3; - unsigned int gio23_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 3; - unsigned int gio24_oe : 1; - unsigned int gio25 : 3; - unsigned int gio25_oe : 1; - unsigned int gio26 : 3; - unsigned int gio26_oe : 1; - unsigned int gio27 : 3; - unsigned int gio27_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 3; - unsigned int gio28_oe : 1; - unsigned int gio29 : 3; - unsigned int gio29_oe : 1; - unsigned int gio30 : 3; - unsigned int gio30_oe : 1; - unsigned int gio31 : 3; - unsigned int gio31_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 1; - unsigned int bus1_in : 1; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int out_strb : 4; - unsigned int in_src : 2; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int dummy1 : 17; -} reg_iop_sw_cfg_rw_pdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out_strb : 3; - unsigned int sdp_in_data : 3; - unsigned int sdp_in_last : 2; - unsigned int sdp_in_strb : 3; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus = 0x00000000, - regk_iop_sw_cfg_bus_rot16 = 0x00000002, - regk_iop_sw_cfg_bus_rot24 = 0x00000003, - regk_iop_sw_cfg_bus_rot8 = 0x00000001, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_gated_clk0 = 0x0000000e, - regk_iop_sw_cfg_gated_clk1 = 0x0000000f, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_pdp_out = 0x00000001, - regk_iop_sw_cfg_pdp_out_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out_lo = 0x00000000, - regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out = 0x00000004, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, - regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, - regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, - regk_iop_sw_cfg_spu_g0 = 0x00000007, - regk_iop_sw_cfg_spu_g1 = 0x00000007, - regk_iop_sw_cfg_spu_g2 = 0x00000007, - regk_iop_sw_cfg_spu_g3 = 0x00000007, - regk_iop_sw_cfg_spu_g4 = 0x00000007, - regk_iop_sw_cfg_spu_g5 = 0x00000007, - regk_iop_sw_cfg_spu_g6 = 0x00000007, - regk_iop_sw_cfg_spu_g7 = 0x00000007, - regk_iop_sw_cfg_spu_gio0 = 0x00000000, - regk_iop_sw_cfg_spu_gio1 = 0x00000001, - regk_iop_sw_cfg_spu_gio5 = 0x00000005, - regk_iop_sw_cfg_spu_gio6 = 0x00000006, - regk_iop_sw_cfg_spu_gio7 = 0x00000007, - regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu_gioout10 = 0x00000007, - regk_iop_sw_cfg_spu_gioout11 = 0x00000007, - regk_iop_sw_cfg_spu_gioout12 = 0x00000007, - regk_iop_sw_cfg_spu_gioout13 = 0x00000007, - regk_iop_sw_cfg_spu_gioout14 = 0x00000007, - regk_iop_sw_cfg_spu_gioout15 = 0x00000007, - regk_iop_sw_cfg_spu_gioout16 = 0x00000007, - regk_iop_sw_cfg_spu_gioout17 = 0x00000007, - regk_iop_sw_cfg_spu_gioout18 = 0x00000007, - regk_iop_sw_cfg_spu_gioout19 = 0x00000007, - regk_iop_sw_cfg_spu_gioout2 = 0x00000001, - regk_iop_sw_cfg_spu_gioout20 = 0x00000007, - regk_iop_sw_cfg_spu_gioout21 = 0x00000007, - regk_iop_sw_cfg_spu_gioout22 = 0x00000007, - regk_iop_sw_cfg_spu_gioout23 = 0x00000007, - regk_iop_sw_cfg_spu_gioout24 = 0x00000007, - regk_iop_sw_cfg_spu_gioout25 = 0x00000007, - regk_iop_sw_cfg_spu_gioout26 = 0x00000007, - regk_iop_sw_cfg_spu_gioout27 = 0x00000007, - regk_iop_sw_cfg_spu_gioout28 = 0x00000007, - regk_iop_sw_cfg_spu_gioout29 = 0x00000007, - regk_iop_sw_cfg_spu_gioout3 = 0x00000001, - regk_iop_sw_cfg_spu_gioout30 = 0x00000007, - regk_iop_sw_cfg_spu_gioout31 = 0x00000007, - regk_iop_sw_cfg_spu_gioout4 = 0x00000002, - regk_iop_sw_cfg_spu_gioout5 = 0x00000002, - regk_iop_sw_cfg_spu_gioout6 = 0x00000003, - regk_iop_sw_cfg_spu_gioout7 = 0x00000003, - regk_iop_sw_cfg_spu_gioout8 = 0x00000007, - regk_iop_sw_cfg_spu_gioout9 = 0x00000007, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000001, - regk_iop_sw_cfg_trig2_1 = 0x00000001, - regk_iop_sw_cfg_trig2_2 = 0x00000001, - regk_iop_sw_cfg_trig2_3 = 0x00000001, - regk_iop_sw_cfg_trig3_0 = 0x00000001, - regk_iop_sw_cfg_trig3_1 = 0x00000001, - regk_iop_sw_cfg_trig3_2 = 0x00000001, - regk_iop_sw_cfg_trig3_3 = 0x00000001, - regk_iop_sw_cfg_trig4_0 = 0x00000002, - regk_iop_sw_cfg_trig4_1 = 0x00000002, - regk_iop_sw_cfg_trig4_2 = 0x00000002, - regk_iop_sw_cfg_trig4_3 = 0x00000002, - regk_iop_sw_cfg_trig5_0 = 0x00000002, - regk_iop_sw_cfg_trig5_1 = 0x00000002, - regk_iop_sw_cfg_trig5_2 = 0x00000002, - regk_iop_sw_cfg_trig5_3 = 0x00000002, - regk_iop_sw_cfg_trig6_0 = 0x00000003, - regk_iop_sw_cfg_trig6_1 = 0x00000003, - regk_iop_sw_cfg_trig6_2 = 0x00000003, - regk_iop_sw_cfg_trig6_3 = 0x00000003, - regk_iop_sw_cfg_trig7_0 = 0x00000003, - regk_iop_sw_cfg_trig7_1 = 0x00000003, - regk_iop_sw_cfg_trig7_2 = 0x00000003, - regk_iop_sw_cfg_trig7_3 = 0x00000003 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index b4acdae4f653..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,523 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index bc1abb5fb308..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,649 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr1 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr2 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr3 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr5 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr6 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr7 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr9 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr10 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr11 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr13 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr14 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr15 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu = 0x00000002, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index 82b64360a4d3..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,442 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out : 1; - unsigned int fifo_out_extra : 1; - unsigned int fifo_in : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_out : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h deleted file mode 100644 index d944c6ce5f9b..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v2_0 = 0x00000002 -}; -#endif /* __iop_version_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h deleted file mode 100644 index 5c72116f1067..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __l2cache_defs_h -#define __l2cache_defs_h - -/* - * This file is autogenerated from - * file: l2cache.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope l2cache */ - -/* Register rw_cfg, scope l2cache, type rw */ -typedef struct { - unsigned int en : 1; - unsigned int dummy1 : 31; -} reg_l2cache_rw_cfg; -#define REG_RD_ADDR_l2cache_rw_cfg 0 -#define REG_WR_ADDR_l2cache_rw_cfg 0 - -/* Register rw_ctrl, scope l2cache, type rw */ -typedef struct { - unsigned int dummy1 : 7; - unsigned int cbase : 9; - unsigned int dummy2 : 4; - unsigned int csize : 10; - unsigned int dummy3 : 2; -} reg_l2cache_rw_ctrl; -#define REG_RD_ADDR_l2cache_rw_ctrl 4 -#define REG_WR_ADDR_l2cache_rw_ctrl 4 - -/* Register rw_idxop, scope l2cache, type rw */ -typedef struct { - unsigned int idx : 10; - unsigned int dummy1 : 14; - unsigned int way : 3; - unsigned int dummy2 : 2; - unsigned int cmd : 3; -} reg_l2cache_rw_idxop; -#define REG_RD_ADDR_l2cache_rw_idxop 8 -#define REG_WR_ADDR_l2cache_rw_idxop 8 - -/* Register rw_addrop_addr, scope l2cache, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_l2cache_rw_addrop_addr; -#define REG_RD_ADDR_l2cache_rw_addrop_addr 12 -#define REG_WR_ADDR_l2cache_rw_addrop_addr 12 - -/* Register rw_addrop_ctrl, scope l2cache, type rw */ -typedef struct { - unsigned int size : 16; - unsigned int dummy1 : 13; - unsigned int cmd : 3; -} reg_l2cache_rw_addrop_ctrl; -#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16 -#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16 - - -/* Constants */ -enum { - regk_l2cache_flush = 0x00000001, - regk_l2cache_no = 0x00000000, - regk_l2cache_rw_addrop_addr_default = 0x00000000, - regk_l2cache_rw_addrop_ctrl_default = 0x00000000, - regk_l2cache_rw_cfg_default = 0x00000000, - regk_l2cache_rw_ctrl_default = 0x00000000, - regk_l2cache_rw_idxop_default = 0x00000000, - regk_l2cache_yes = 0x00000001 -}; -#endif /* __l2cache_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h deleted file mode 100644 index 84f68755a75c..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h +++ /dev/null @@ -1,483 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_bar_defs_h -#define __marb_bar_defs_h - -/* - * This file is autogenerated from - * file: marb_bar.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bar */ - -#define STRIDE_marb_bar_rw_ddr2_slots 4 -/* Register rw_ddr2_slots, scope marb_bar, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_ddr2_slots; -#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0 -#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0 - -/* Register rw_h264_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_h264_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256 -#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256 - -/* Register rw_h264_wr_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_h264_wr_burst; -#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260 -#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260 - -/* Register rw_ccd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_ccd_burst; -#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264 -#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264 - -/* Register rw_vin_wr_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vin_wr_burst; -#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268 -#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268 - -/* Register rw_vin_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vin_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272 -#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272 - -/* Register rw_sclr_rd_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_sclr_rd_burst; -#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276 -#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276 - -/* Register rw_vout_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_vout_burst; -#define REG_RD_ADDR_marb_bar_rw_vout_burst 280 -#define REG_WR_ADDR_marb_bar_rw_vout_burst 280 - -/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_sclr_fifo_burst; -#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284 -#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284 - -/* Register rw_l2cache_burst, scope marb_bar, type rw */ -typedef struct { - unsigned int ddr2_bsize : 2; - unsigned int dummy1 : 30; -} reg_marb_bar_rw_l2cache_burst; -#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288 -#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288 - -/* Register rw_intr_mask, scope marb_bar, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_intr_mask; -#define REG_RD_ADDR_marb_bar_rw_intr_mask 292 -#define REG_WR_ADDR_marb_bar_rw_intr_mask 292 - -/* Register rw_ack_intr, scope marb_bar, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_rw_ack_intr; -#define REG_RD_ADDR_marb_bar_rw_ack_intr 296 -#define REG_WR_ADDR_marb_bar_rw_ack_intr 296 - -/* Register r_intr, scope marb_bar, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_r_intr; -#define REG_RD_ADDR_marb_bar_r_intr 300 - -/* Register r_masked_intr, scope marb_bar, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_bar_r_masked_intr; -#define REG_RD_ADDR_marb_bar_r_masked_intr 304 - -/* Register rw_stop_mask, scope marb_bar, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_rw_stop_mask; -#define REG_RD_ADDR_marb_bar_rw_stop_mask 308 -#define REG_WR_ADDR_marb_bar_rw_stop_mask 308 - -/* Register r_stopped, scope marb_bar, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_r_stopped; -#define REG_RD_ADDR_marb_bar_r_stopped 312 - -/* Register rw_no_snoop, scope marb_bar, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_rw_no_snoop; -#define REG_RD_ADDR_marb_bar_rw_no_snoop 576 -#define REG_WR_ADDR_marb_bar_rw_no_snoop 576 - - -/* Constants */ -enum { - regk_marb_bar_ccd = 0x00000002, - regk_marb_bar_h264_rd = 0x00000000, - regk_marb_bar_h264_wr = 0x00000001, - regk_marb_bar_l2cache = 0x00000008, - regk_marb_bar_no = 0x00000000, - regk_marb_bar_r_stopped_default = 0x00000000, - regk_marb_bar_rw_ccd_burst_default = 0x00000000, - regk_marb_bar_rw_ddr2_slots_default = 0x00000000, - regk_marb_bar_rw_ddr2_slots_size = 0x00000040, - regk_marb_bar_rw_h264_rd_burst_default = 0x00000000, - regk_marb_bar_rw_h264_wr_burst_default = 0x00000000, - regk_marb_bar_rw_intr_mask_default = 0x00000000, - regk_marb_bar_rw_l2cache_burst_default = 0x00000000, - regk_marb_bar_rw_no_snoop_default = 0x00000000, - regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000, - regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000, - regk_marb_bar_rw_stop_mask_default = 0x00000000, - regk_marb_bar_rw_vin_rd_burst_default = 0x00000000, - regk_marb_bar_rw_vin_wr_burst_default = 0x00000000, - regk_marb_bar_rw_vout_burst_default = 0x00000000, - regk_marb_bar_sclr_fifo = 0x00000007, - regk_marb_bar_sclr_rd = 0x00000005, - regk_marb_bar_vin_rd = 0x00000004, - regk_marb_bar_vin_wr = 0x00000003, - regk_marb_bar_vout = 0x00000006, - regk_marb_bar_yes = 0x00000001 -}; -#endif /* __marb_bar_defs_h */ -#ifndef __marb_bar_bp_defs_h -#define __marb_bar_bp_defs_h - -/* - * This file is autogenerated from - * file: marb_bar.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bar_bp */ - -/* Register rw_first_addr, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bar_bp_rw_op; -#define REG_RD_ADDR_marb_bar_bp_rw_op 8 -#define REG_WR_ADDR_marb_bar_bp_rw_op 8 - -/* Register rw_clients, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_rw_clients; -#define REG_RD_ADDR_marb_bar_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bar_bp_rw_clients 12 - -/* Register rw_options, scope marb_bar_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bar_bp_rw_options; -#define REG_RD_ADDR_marb_bar_bp_rw_options 16 -#define REG_WR_ADDR_marb_bar_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bar_bp, type r */ -typedef unsigned int reg_marb_bar_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bar_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bar_bp_r_brk_op; -#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bar_bp, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bar_bp, type r */ -typedef struct { - unsigned int h264_rd : 1; - unsigned int h264_wr : 1; - unsigned int ccd : 1; - unsigned int vin_wr : 1; - unsigned int vin_rd : 1; - unsigned int sclr_rd : 1; - unsigned int vout : 1; - unsigned int sclr_fifo : 1; - unsigned int l2cache : 1; - unsigned int dummy1 : 23; -} reg_marb_bar_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bar_bp, type r */ -typedef unsigned int reg_marb_bar_bp_r_brk_size; -#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bar_bp, type rw */ -typedef unsigned int reg_marb_bar_bp_rw_ack; -#define REG_RD_ADDR_marb_bar_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bar_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bar_bp_no = 0x00000000, - regk_marb_bar_bp_rw_op_default = 0x00000000, - regk_marb_bar_bp_rw_options_default = 0x00000000, - regk_marb_bar_bp_yes = 0x00000001 -}; -#endif /* __marb_bar_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h deleted file mode 100644 index 13539bc5d613..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h +++ /dev/null @@ -1,627 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_foo_defs_h -#define __marb_foo_defs_h - -/* - * This file is autogenerated from - * file: marb_foo.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_foo */ - -#define STRIDE_marb_foo_rw_intm_slots 4 -/* Register rw_intm_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_intm_slots; -#define REG_RD_ADDR_marb_foo_rw_intm_slots 0 -#define REG_WR_ADDR_marb_foo_rw_intm_slots 0 - -#define STRIDE_marb_foo_rw_l2_slots 4 -/* Register rw_l2_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_l2_slots; -#define REG_RD_ADDR_marb_foo_rw_l2_slots 256 -#define REG_WR_ADDR_marb_foo_rw_l2_slots 256 - -#define STRIDE_marb_foo_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb_foo, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_regs_slots; -#define REG_RD_ADDR_marb_foo_rw_regs_slots 512 -#define REG_WR_ADDR_marb_foo_rw_regs_slots 512 - -/* Register rw_sclr_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_sclr_burst; -#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528 -#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528 - -/* Register rw_dma0_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma0_burst; -#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532 -#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532 - -/* Register rw_dma1_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma1_burst; -#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536 -#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536 - -/* Register rw_dma2_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma2_burst; -#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540 -#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540 - -/* Register rw_dma3_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma3_burst; -#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544 -#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544 - -/* Register rw_dma4_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma4_burst; -#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548 -#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548 - -/* Register rw_dma5_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma5_burst; -#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552 -#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552 - -/* Register rw_dma6_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma6_burst; -#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556 -#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556 - -/* Register rw_dma7_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma7_burst; -#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560 -#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560 - -/* Register rw_dma9_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma9_burst; -#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564 -#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564 - -/* Register rw_dma11_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_dma11_burst; -#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568 -#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568 - -/* Register rw_cpui_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_cpui_burst; -#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572 -#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572 - -/* Register rw_cpud_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_cpud_burst; -#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576 -#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576 - -/* Register rw_iop_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_iop_burst; -#define REG_RD_ADDR_marb_foo_rw_iop_burst 580 -#define REG_WR_ADDR_marb_foo_rw_iop_burst 580 - -/* Register rw_ccdstat_burst, scope marb_foo, type rw */ -typedef struct { - unsigned int intm_bsize : 2; - unsigned int l2_bsize : 2; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_ccdstat_burst; -#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584 -#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584 - -/* Register rw_intr_mask, scope marb_foo, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_intr_mask; -#define REG_RD_ADDR_marb_foo_rw_intr_mask 588 -#define REG_WR_ADDR_marb_foo_rw_intr_mask 588 - -/* Register rw_ack_intr, scope marb_foo, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_rw_ack_intr; -#define REG_RD_ADDR_marb_foo_rw_ack_intr 592 -#define REG_WR_ADDR_marb_foo_rw_ack_intr 592 - -/* Register r_intr, scope marb_foo, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_r_intr; -#define REG_RD_ADDR_marb_foo_r_intr 596 - -/* Register r_masked_intr, scope marb_foo, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_foo_r_masked_intr; -#define REG_RD_ADDR_marb_foo_r_masked_intr 600 - -/* Register rw_stop_mask, scope marb_foo, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_rw_stop_mask; -#define REG_RD_ADDR_marb_foo_rw_stop_mask 604 -#define REG_WR_ADDR_marb_foo_rw_stop_mask 604 - -/* Register r_stopped, scope marb_foo, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_r_stopped; -#define REG_RD_ADDR_marb_foo_r_stopped 608 - -/* Register rw_no_snoop, scope marb_foo, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_rw_no_snoop; -#define REG_RD_ADDR_marb_foo_rw_no_snoop 896 -#define REG_WR_ADDR_marb_foo_rw_no_snoop 896 - -/* Register rw_no_snoop_rq, scope marb_foo, type rw */ -typedef struct { - unsigned int dummy1 : 11; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 19; -} reg_marb_foo_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900 -#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900 - - -/* Constants */ -enum { - regk_marb_foo_ccdstat = 0x0000000e, - regk_marb_foo_cpud = 0x0000000c, - regk_marb_foo_cpui = 0x0000000b, - regk_marb_foo_dma0 = 0x00000001, - regk_marb_foo_dma1 = 0x00000002, - regk_marb_foo_dma11 = 0x0000000a, - regk_marb_foo_dma2 = 0x00000003, - regk_marb_foo_dma3 = 0x00000004, - regk_marb_foo_dma4 = 0x00000005, - regk_marb_foo_dma5 = 0x00000006, - regk_marb_foo_dma6 = 0x00000007, - regk_marb_foo_dma7 = 0x00000008, - regk_marb_foo_dma9 = 0x00000009, - regk_marb_foo_iop = 0x0000000d, - regk_marb_foo_no = 0x00000000, - regk_marb_foo_r_stopped_default = 0x00000000, - regk_marb_foo_rw_ccdstat_burst_default = 0x00000000, - regk_marb_foo_rw_cpud_burst_default = 0x00000000, - regk_marb_foo_rw_cpui_burst_default = 0x00000000, - regk_marb_foo_rw_dma0_burst_default = 0x00000000, - regk_marb_foo_rw_dma11_burst_default = 0x00000000, - regk_marb_foo_rw_dma1_burst_default = 0x00000000, - regk_marb_foo_rw_dma2_burst_default = 0x00000000, - regk_marb_foo_rw_dma3_burst_default = 0x00000000, - regk_marb_foo_rw_dma4_burst_default = 0x00000000, - regk_marb_foo_rw_dma5_burst_default = 0x00000000, - regk_marb_foo_rw_dma6_burst_default = 0x00000000, - regk_marb_foo_rw_dma7_burst_default = 0x00000000, - regk_marb_foo_rw_dma9_burst_default = 0x00000000, - regk_marb_foo_rw_intm_slots_default = 0x00000000, - regk_marb_foo_rw_intm_slots_size = 0x00000040, - regk_marb_foo_rw_intr_mask_default = 0x00000000, - regk_marb_foo_rw_iop_burst_default = 0x00000000, - regk_marb_foo_rw_l2_slots_default = 0x00000000, - regk_marb_foo_rw_l2_slots_size = 0x00000040, - regk_marb_foo_rw_no_snoop_default = 0x00000000, - regk_marb_foo_rw_no_snoop_rq_default = 0x00000000, - regk_marb_foo_rw_regs_slots_default = 0x00000000, - regk_marb_foo_rw_regs_slots_size = 0x00000004, - regk_marb_foo_rw_sclr_burst_default = 0x00000000, - regk_marb_foo_rw_stop_mask_default = 0x00000000, - regk_marb_foo_sclr = 0x00000000, - regk_marb_foo_yes = 0x00000001 -}; -#endif /* __marb_foo_defs_h */ -#ifndef __marb_foo_bp_defs_h -#define __marb_foo_bp_defs_h - -/* - * This file is autogenerated from - * file: marb_foo.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_foo_bp */ - -/* Register rw_first_addr, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_first_addr; -#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_last_addr; -#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_foo_bp_rw_op; -#define REG_RD_ADDR_marb_foo_bp_rw_op 8 -#define REG_WR_ADDR_marb_foo_bp_rw_op 8 - -/* Register rw_clients, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_rw_clients; -#define REG_RD_ADDR_marb_foo_bp_rw_clients 12 -#define REG_WR_ADDR_marb_foo_bp_rw_clients 12 - -/* Register rw_options, scope marb_foo_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_foo_bp_rw_options; -#define REG_RD_ADDR_marb_foo_bp_rw_options 16 -#define REG_WR_ADDR_marb_foo_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_foo_bp, type r */ -typedef unsigned int reg_marb_foo_bp_r_brk_addr; -#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_foo_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_foo_bp_r_brk_op; -#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_foo_bp, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_r_brk_clients; -#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_foo_bp, type r */ -typedef struct { - unsigned int sclr : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma9 : 1; - unsigned int dma11 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int ccdstat : 1; - unsigned int dummy1 : 17; -} reg_marb_foo_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_foo_bp, type r */ -typedef unsigned int reg_marb_foo_bp_r_brk_size; -#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_foo_bp, type rw */ -typedef unsigned int reg_marb_foo_bp_rw_ack; -#define REG_RD_ADDR_marb_foo_bp_rw_ack 40 -#define REG_WR_ADDR_marb_foo_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_foo_bp_no = 0x00000000, - regk_marb_foo_bp_rw_op_default = 0x00000000, - regk_marb_foo_bp_rw_options_default = 0x00000000, - regk_marb_foo_bp_yes = 0x00000001 -}; -#endif /* __marb_foo_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h deleted file mode 100644 index d604042a52bf..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h +++ /dev/null @@ -1,313 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: pinmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int eth : 1; - unsigned int eth_mdio : 1; - unsigned int geth : 1; - unsigned int tg : 1; - unsigned int tg_clk : 1; - unsigned int vout : 1; - unsigned int vout_sync : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int ser4 : 1; - unsigned int sser : 1; - unsigned int pwm0 : 1; - unsigned int pwm1 : 1; - unsigned int pwm2 : 1; - unsigned int timer0 : 1; - unsigned int timer1 : 1; - unsigned int pio : 1; - unsigned int i2c0 : 1; - unsigned int i2c1 : 1; - unsigned int i2c1_sda1 : 1; - unsigned int i2c1_sda2 : 1; - unsigned int i2c1_sda3 : 1; - unsigned int i2c1_sen : 1; - unsigned int dummy1 : 8; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 0 -#define REG_WR_ADDR_pinmux_rw_hwprot 0 - -/* Register rw_gio_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int pa8 : 1; - unsigned int pa9 : 1; - unsigned int pa10 : 1; - unsigned int pa11 : 1; - unsigned int pa12 : 1; - unsigned int pa13 : 1; - unsigned int pa14 : 1; - unsigned int pa15 : 1; - unsigned int pa16 : 1; - unsigned int pa17 : 1; - unsigned int pa18 : 1; - unsigned int pa19 : 1; - unsigned int pa20 : 1; - unsigned int pa21 : 1; - unsigned int pa22 : 1; - unsigned int pa23 : 1; - unsigned int pa24 : 1; - unsigned int pa25 : 1; - unsigned int pa26 : 1; - unsigned int pa27 : 1; - unsigned int pa28 : 1; - unsigned int pa29 : 1; - unsigned int pa30 : 1; - unsigned int pa31 : 1; -} reg_pinmux_rw_gio_pa; -#define REG_RD_ADDR_pinmux_rw_gio_pa 4 -#define REG_WR_ADDR_pinmux_rw_gio_pa 4 - -/* Register rw_gio_pb, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int pb18 : 1; - unsigned int pb19 : 1; - unsigned int pb20 : 1; - unsigned int pb21 : 1; - unsigned int pb22 : 1; - unsigned int pb23 : 1; - unsigned int pb24 : 1; - unsigned int pb25 : 1; - unsigned int pb26 : 1; - unsigned int pb27 : 1; - unsigned int pb28 : 1; - unsigned int pb29 : 1; - unsigned int pb30 : 1; - unsigned int pb31 : 1; -} reg_pinmux_rw_gio_pb; -#define REG_RD_ADDR_pinmux_rw_gio_pb 8 -#define REG_WR_ADDR_pinmux_rw_gio_pb 8 - -/* Register rw_gio_pc, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_gio_pc; -#define REG_RD_ADDR_pinmux_rw_gio_pc 12 -#define REG_WR_ADDR_pinmux_rw_gio_pc 12 - -/* Register rw_iop_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int pa8 : 1; - unsigned int pa9 : 1; - unsigned int pa10 : 1; - unsigned int pa11 : 1; - unsigned int pa12 : 1; - unsigned int pa13 : 1; - unsigned int pa14 : 1; - unsigned int pa15 : 1; - unsigned int pa16 : 1; - unsigned int pa17 : 1; - unsigned int pa18 : 1; - unsigned int pa19 : 1; - unsigned int pa20 : 1; - unsigned int pa21 : 1; - unsigned int pa22 : 1; - unsigned int pa23 : 1; - unsigned int pa24 : 1; - unsigned int pa25 : 1; - unsigned int pa26 : 1; - unsigned int pa27 : 1; - unsigned int pa28 : 1; - unsigned int pa29 : 1; - unsigned int pa30 : 1; - unsigned int pa31 : 1; -} reg_pinmux_rw_iop_pa; -#define REG_RD_ADDR_pinmux_rw_iop_pa 16 -#define REG_WR_ADDR_pinmux_rw_iop_pa 16 - -/* Register rw_iop_pb, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int dummy1 : 24; -} reg_pinmux_rw_iop_pb; -#define REG_RD_ADDR_pinmux_rw_iop_pb 20 -#define REG_WR_ADDR_pinmux_rw_iop_pb 20 - -/* Register rw_iop_pio, scope pinmux, type rw */ -typedef struct { - unsigned int d0 : 1; - unsigned int d1 : 1; - unsigned int d2 : 1; - unsigned int d3 : 1; - unsigned int d4 : 1; - unsigned int d5 : 1; - unsigned int d6 : 1; - unsigned int d7 : 1; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_iop_pio; -#define REG_RD_ADDR_pinmux_rw_iop_pio 24 -#define REG_WR_ADDR_pinmux_rw_iop_pio 24 - -/* Register rw_iop_usb, scope pinmux, type rw */ -typedef struct { - unsigned int usb0 : 1; - unsigned int dummy1 : 31; -} reg_pinmux_rw_iop_usb; -#define REG_RD_ADDR_pinmux_rw_iop_usb 28 -#define REG_WR_ADDR_pinmux_rw_iop_usb 28 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_gio_pa_default = 0x00000000, - regk_pinmux_rw_gio_pb_default = 0x00000000, - regk_pinmux_rw_gio_pc_default = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_iop_pa_default = 0x00000000, - regk_pinmux_rw_iop_pb_default = 0x00000000, - regk_pinmux_rw_iop_pio_default = 0x00000000, - regk_pinmux_rw_iop_usb_default = 0x00000001, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h deleted file mode 100644 index 348e39f419e0..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h +++ /dev/null @@ -1,372 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pio_defs_h -#define __pio_defs_h - -/* - * This file is autogenerated from - * file: pio.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pio */ - -/* Register rw_data, scope pio, type rw */ -typedef unsigned int reg_pio_rw_data; -#define REG_RD_ADDR_pio_rw_data 64 -#define REG_WR_ADDR_pio_rw_data 64 - -/* Register rw_io_access0, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access0; -#define REG_RD_ADDR_pio_rw_io_access0 0 -#define REG_WR_ADDR_pio_rw_io_access0 0 - -/* Register rw_io_access1, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access1; -#define REG_RD_ADDR_pio_rw_io_access1 4 -#define REG_WR_ADDR_pio_rw_io_access1 4 - -/* Register rw_io_access2, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access2; -#define REG_RD_ADDR_pio_rw_io_access2 8 -#define REG_WR_ADDR_pio_rw_io_access2 8 - -/* Register rw_io_access3, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access3; -#define REG_RD_ADDR_pio_rw_io_access3 12 -#define REG_WR_ADDR_pio_rw_io_access3 12 - -/* Register rw_io_access4, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access4; -#define REG_RD_ADDR_pio_rw_io_access4 16 -#define REG_WR_ADDR_pio_rw_io_access4 16 - -/* Register rw_io_access5, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access5; -#define REG_RD_ADDR_pio_rw_io_access5 20 -#define REG_WR_ADDR_pio_rw_io_access5 20 - -/* Register rw_io_access6, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access6; -#define REG_RD_ADDR_pio_rw_io_access6 24 -#define REG_WR_ADDR_pio_rw_io_access6 24 - -/* Register rw_io_access7, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access7; -#define REG_RD_ADDR_pio_rw_io_access7 28 -#define REG_WR_ADDR_pio_rw_io_access7 28 - -/* Register rw_io_access8, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access8; -#define REG_RD_ADDR_pio_rw_io_access8 32 -#define REG_WR_ADDR_pio_rw_io_access8 32 - -/* Register rw_io_access9, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access9; -#define REG_RD_ADDR_pio_rw_io_access9 36 -#define REG_WR_ADDR_pio_rw_io_access9 36 - -/* Register rw_io_access10, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access10; -#define REG_RD_ADDR_pio_rw_io_access10 40 -#define REG_WR_ADDR_pio_rw_io_access10 40 - -/* Register rw_io_access11, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access11; -#define REG_RD_ADDR_pio_rw_io_access11 44 -#define REG_WR_ADDR_pio_rw_io_access11 44 - -/* Register rw_io_access12, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access12; -#define REG_RD_ADDR_pio_rw_io_access12 48 -#define REG_WR_ADDR_pio_rw_io_access12 48 - -/* Register rw_io_access13, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access13; -#define REG_RD_ADDR_pio_rw_io_access13 52 -#define REG_WR_ADDR_pio_rw_io_access13 52 - -/* Register rw_io_access14, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access14; -#define REG_RD_ADDR_pio_rw_io_access14 56 -#define REG_WR_ADDR_pio_rw_io_access14 56 - -/* Register rw_io_access15, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_pio_rw_io_access15; -#define REG_RD_ADDR_pio_rw_io_access15 60 -#define REG_WR_ADDR_pio_rw_io_access15 60 - -/* Register rw_ce0_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce0_cfg; -#define REG_RD_ADDR_pio_rw_ce0_cfg 68 -#define REG_WR_ADDR_pio_rw_ce0_cfg 68 - -/* Register rw_ce1_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce1_cfg; -#define REG_RD_ADDR_pio_rw_ce1_cfg 72 -#define REG_WR_ADDR_pio_rw_ce1_cfg 72 - -/* Register rw_ce2_cfg, scope pio, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int mode : 2; - unsigned int dummy1 : 16; -} reg_pio_rw_ce2_cfg; -#define REG_RD_ADDR_pio_rw_ce2_cfg 76 -#define REG_WR_ADDR_pio_rw_ce2_cfg 76 - -/* Register rw_dout, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_dout; -#define REG_RD_ADDR_pio_rw_dout 80 -#define REG_WR_ADDR_pio_rw_dout 80 - -/* Register rw_oe, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_oe; -#define REG_RD_ADDR_pio_rw_oe 84 -#define REG_WR_ADDR_pio_rw_oe 84 - -/* Register rw_man_ctrl, scope pio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_rw_man_ctrl; -#define REG_RD_ADDR_pio_rw_man_ctrl 88 -#define REG_WR_ADDR_pio_rw_man_ctrl 88 - -/* Register r_din, scope pio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int rd_n : 1; - unsigned int wr_n : 1; - unsigned int a0 : 1; - unsigned int a1 : 1; - unsigned int ce0_n : 1; - unsigned int ce1_n : 1; - unsigned int ce2_n : 1; - unsigned int rdy : 1; - unsigned int dummy1 : 16; -} reg_pio_r_din; -#define REG_RD_ADDR_pio_r_din 92 - -/* Register r_stat, scope pio, type r */ -typedef struct { - unsigned int busy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_stat; -#define REG_RD_ADDR_pio_r_stat 96 - -/* Register rw_intr_mask, scope pio, type rw */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_rw_intr_mask; -#define REG_RD_ADDR_pio_rw_intr_mask 100 -#define REG_WR_ADDR_pio_rw_intr_mask 100 - -/* Register rw_ack_intr, scope pio, type rw */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_rw_ack_intr; -#define REG_RD_ADDR_pio_rw_ack_intr 104 -#define REG_WR_ADDR_pio_rw_ack_intr 104 - -/* Register r_intr, scope pio, type r */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_intr; -#define REG_RD_ADDR_pio_r_intr 108 - -/* Register r_masked_intr, scope pio, type r */ -typedef struct { - unsigned int rdy : 1; - unsigned int dummy1 : 31; -} reg_pio_r_masked_intr; -#define REG_RD_ADDR_pio_r_masked_intr 112 - - -/* Constants */ -enum { - regk_pio_a2 = 0x00000003, - regk_pio_no = 0x00000000, - regk_pio_normal = 0x00000000, - regk_pio_rd = 0x00000001, - regk_pio_rw_ce0_cfg_default = 0x00000000, - regk_pio_rw_ce1_cfg_default = 0x00000000, - regk_pio_rw_ce2_cfg_default = 0x00000000, - regk_pio_rw_intr_mask_default = 0x00000000, - regk_pio_rw_man_ctrl_default = 0x00000000, - regk_pio_rw_oe_default = 0x00000000, - regk_pio_wr = 0x00000002, - regk_pio_wr_ce2 = 0x00000003, - regk_pio_yes = 0x00000001, - regk_pio_yes_all = 0x000000ff -}; -#endif /* __pio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h deleted file mode 100644 index 04ef87d42513..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: reg.rmap - * - * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ccd = 0xb0000000, - regi_ccd_top = 0xb0000000, - regi_ccd_dp = 0xb0000400, - regi_ccd_stat = 0xb0000800, - regi_ccd_tg = 0xb0001000, - regi_cfg = 0xb0002000, - regi_clkgen = 0xb0004000, - regi_ddr2_ctrl = 0xb0006000, - regi_dma0 = 0xb0008000, - regi_dma1 = 0xb000a000, - regi_dma11 = 0xb000c000, - regi_dma2 = 0xb000e000, - regi_dma3 = 0xb0010000, - regi_dma4 = 0xb0012000, - regi_dma5 = 0xb0014000, - regi_dma6 = 0xb0016000, - regi_dma7 = 0xb0018000, - regi_dma9 = 0xb001a000, - regi_eth = 0xb001c000, - regi_gio = 0xb0020000, - regi_h264 = 0xb0022000, - regi_hist = 0xb0026000, - regi_iop = 0xb0028000, - regi_iop_version = 0xb0028000, - regi_iop_fifo_in_extra = 0xb0028040, - regi_iop_fifo_out_extra = 0xb0028080, - regi_iop_trigger_grp0 = 0xb00280c0, - regi_iop_trigger_grp1 = 0xb0028100, - regi_iop_trigger_grp2 = 0xb0028140, - regi_iop_trigger_grp3 = 0xb0028180, - regi_iop_trigger_grp4 = 0xb00281c0, - regi_iop_trigger_grp5 = 0xb0028200, - regi_iop_trigger_grp6 = 0xb0028240, - regi_iop_trigger_grp7 = 0xb0028280, - regi_iop_crc_par = 0xb0028300, - regi_iop_dmc_in = 0xb0028380, - regi_iop_dmc_out = 0xb0028400, - regi_iop_fifo_in = 0xb0028480, - regi_iop_fifo_out = 0xb0028500, - regi_iop_scrc_in = 0xb0028580, - regi_iop_scrc_out = 0xb0028600, - regi_iop_timer_grp0 = 0xb0028680, - regi_iop_timer_grp1 = 0xb0028700, - regi_iop_sap_in = 0xb0028800, - regi_iop_sap_out = 0xb0028900, - regi_iop_spu = 0xb0028a00, - regi_iop_sw_cfg = 0xb0028b00, - regi_iop_sw_cpu = 0xb0028c00, - regi_iop_sw_mpu = 0xb0028d00, - regi_iop_sw_spu = 0xb0028e00, - regi_iop_mpu = 0xb0029000, - regi_irq = 0xb002a000, - regi_irq2 = 0xb006a000, - regi_jpeg = 0xb002c000, - regi_l2cache = 0xb0030000, - regi_marb_bar = 0xb0032000, - regi_marb_bar_bp0 = 0xb0032140, - regi_marb_bar_bp1 = 0xb0032180, - regi_marb_bar_bp2 = 0xb00321c0, - regi_marb_bar_bp3 = 0xb0032200, - regi_marb_foo = 0xb0034000, - regi_marb_foo_bp0 = 0xb0034280, - regi_marb_foo_bp1 = 0xb00342c0, - regi_marb_foo_bp2 = 0xb0034300, - regi_marb_foo_bp3 = 0xb0034340, - regi_pinmux = 0xb0038000, - regi_pio = 0xb0036000, - regi_sclr = 0xb003a000, - regi_sclr_fifo = 0xb003c000, - regi_ser0 = 0xb003e000, - regi_ser1 = 0xb0040000, - regi_ser2 = 0xb0042000, - regi_ser3 = 0xb0044000, - regi_ser4 = 0xb0046000, - regi_sser = 0xb0048000, - regi_strcop = 0xb004a000, - regi_strdma0 = 0xb004e000, - regi_strdma1 = 0xb0050000, - regi_strdma2 = 0xb0052000, - regi_strdma3 = 0xb0054000, - regi_strdma5 = 0xb0056000, - regi_strmux = 0xb004c000, - regi_timer0 = 0xb0058000, - regi_timer1 = 0xb005a000, - regi_timer2 = 0xb006e000, - regi_trace = 0xb005c000, - regi_vin = 0xb005e000, - regi_vout = 0xb0060000 -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h deleted file mode 100644 index a19955fa8d94..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: strmux.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 2; - unsigned int dma1 : 2; - unsigned int dma2 : 2; - unsigned int dma3 : 2; - unsigned int dma4 : 2; - unsigned int dma5 : 2; - unsigned int dma6 : 2; - unsigned int dma7 : 2; - unsigned int dummy1 : 2; - unsigned int dma9 : 2; - unsigned int dummy2 : 2; - unsigned int dma11 : 2; - unsigned int dummy3 : 8; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_eth = 0x00000001, - regk_strmux_h264 = 0x00000001, - regk_strmux_iop = 0x00000001, - regk_strmux_jpeg = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000002, - regk_strmux_ser3 = 0x00000002, - regk_strmux_ser4 = 0x00000002, - regk_strmux_sser = 0x00000001, - regk_strmux_strcop = 0x00000001 -}; -#endif /* __strmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h deleted file mode 100644 index de849a6362f6..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h +++ /dev/null @@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: timer.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_f90 = 0x00000003, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_vclk = 0x00000002, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h b/arch/cris/include/arch-v32/mach-a3/mach/memmap.h deleted file mode 100644 index 7b9a9a5699b2..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00018000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h b/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h deleted file mode 100644 index 35e3fc97d6a3..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_A 0 -#define PORT_B 1 -#define PORT_C 2 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_eth, - pinmux_geth, - pinmux_tg_ccd, - pinmux_tg_cmos, - pinmux_vout, - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_ser4, - pinmux_sser, - pinmux_pio, - pinmux_pwm0, - pinmux_pwm1, - pinmux_pwm2, - pinmux_i2c0, - pinmux_i2c1, - pinmux_i2c1_3wire, - pinmux_i2c1_sda1, - pinmux_i2c1_sda2, - pinmux_i2c1_sda3, -}; - -int crisv32_pinmux_init(void); -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); -void crisv32_pinmux_dump(void); - -#endif diff --git a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc deleted file mode 100644 index 2d52bcc96ed5..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef STARTUP_INC_INCLUDED -#define STARTUP_INC_INCLUDED - -#include -#include -#include -#include -#include - - .macro GIO_SET_P BITS, OUTREG - bmi 1f ; btstq: bit -> N flag - nop - or.d \BITS, \OUTREG -1: - .endm - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d 0xFFFFFFFF, $r0 - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 - move.d $r0, [$r1] - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 - move.d $r0, [$r1] - - ;; If eth_mdio, eth, geth bits are set in hwprot, don't - ;; set them to gpio, as this means they have been configured - ;; earlier and shouldn't be changed. - move.d 0xFC000000, $r2 ; pins 25..0 are eth_mdio, eth, geth - move.d REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1 - move.d [$r1], $r0 - btstq REG_BIT(pinmux, rw_hwprot, eth), $r0 - GIO_SET_P 0x00FFFF00, $r2 ;; pins 8..23 are eth - btstq REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0 - GIO_SET_P 0x03000000, $r2 ;; pins 24..25 are eth_mdio - btstq REG_BIT(pinmux, rw_hwprot, geth), $r0 - GIO_SET_P 0x000000FF, $r2 ;; pins 0..7 are geth - move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 - move.d $r2, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ - REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 - move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 - move.d $r1, [$r0] - .endm -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h b/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h deleted file mode 100644 index f9401a3de83c..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/arch/cris/include/arch-v32/mach-fs/mach/dma.h deleted file mode 100644 index 53a59944a48b..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/dma.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 10 - -#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ -#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ - -#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ -#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ - -#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ -#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ - -#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ -#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ - -#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ -#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ - -#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ -#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ - -#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ -#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ - -#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ -#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ - -#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ -#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ - -#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ -#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ - -#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ -#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ - -#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ -#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ - -#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ -#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ - -#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ -#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ - -enum dma_owner { - dma_eth0, - dma_eth1, - dma_iop0, - dma_iop1, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_sser0, - dma_sser1, - dma_ata, - dma_strp, - dma_ext0, - dma_ext1, - dma_ext2, - dma_ext3 -}; - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned bandwidth, - enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index 092cad384b86..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,320 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h deleted file mode 100644 index 5b38835b42f7..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 3d2056892832..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 99968cfa446a..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,633 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 412b8748e952..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 3eb17cfbdc75..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,230 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h deleted file mode 100644 index a9ffb7edaf91..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h +++ /dev/null @@ -1,285 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h deleted file mode 100644 index d1fa172f58f4..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,474 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h deleted file mode 100644 index a8d7cc528546..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h deleted file mode 100644 index cc8b20d17237..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h deleted file mode 100644 index da0b1103b66d..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h +++ /dev/null @@ -1,296 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h deleted file mode 100644 index ea752a2d8ee2..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define GIO_INTR_VECT GEN_IO_INTR_VECT -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define TIMER0_INTR_VECT TIMER_INTR_VECT -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f -#define NBR_INTR_VECT 0x50 -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h deleted file mode 100644 index 11ebd66585cd..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - -#define STRIDE_intr_vect_rw_mask 0 -/* Register rw_mask, scope intr_vect, type rw */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer0 : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_rw_mask; -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 - -#define STRIDE_intr_vect_r_vect 0 -/* Register r_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_vect; -#define REG_RD_ADDR_intr_vect_r_vect 4 - -#define STRIDE_intr_vect_r_masked_vect 0 -/* Register r_masked_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_masked_vect; -#define REG_RD_ADDR_intr_vect_r_masked_vect 8 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int ext : 1; - unsigned int watchdog : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 12 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 16 - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 20 -#define REG_WR_ADDR_intr_vect_rw_ipi 20 - -/* Constants */ -enum { - regk_intr_vect_off = 0x00000000, - regk_intr_vect_on = 0x00000001, - regk_intr_vect_rw_mask_default = 0x00000000 -}; -#endif /* __intr_vect_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h deleted file mode 100644 index fb7e20d77591..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h deleted file mode 100644 index 872a7942916a..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h +++ /dev/null @@ -1,476 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h deleted file mode 100644 index 0a316dc36a6b..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h deleted file mode 100644 index 1bfca2666158..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ata = 0xb0032000, - regi_bif_core = 0xb0014000, - regi_bif_dma = 0xb0016000, - regi_bif_slave = 0xb0018000, - regi_config = 0xb003c000, - regi_dma0 = 0xb0000000, - regi_dma1 = 0xb0002000, - regi_dma2 = 0xb0004000, - regi_dma3 = 0xb0006000, - regi_dma4 = 0xb0008000, - regi_dma5 = 0xb000a000, - regi_dma6 = 0xb000c000, - regi_dma7 = 0xb000e000, - regi_dma8 = 0xb0010000, - regi_dma9 = 0xb0012000, - regi_eth0 = 0xb0034000, - regi_eth1 = 0xb0036000, - regi_gio = 0xb001a000, - regi_iop = 0xb0020000, - regi_iop_version = 0xb0020000, - regi_iop_fifo_in0_extra = 0xb0020040, - regi_iop_fifo_in1_extra = 0xb0020080, - regi_iop_fifo_out0_extra = 0xb00200c0, - regi_iop_fifo_out1_extra = 0xb0020100, - regi_iop_trigger_grp0 = 0xb0020140, - regi_iop_trigger_grp1 = 0xb0020180, - regi_iop_trigger_grp2 = 0xb00201c0, - regi_iop_trigger_grp3 = 0xb0020200, - regi_iop_trigger_grp4 = 0xb0020240, - regi_iop_trigger_grp5 = 0xb0020280, - regi_iop_trigger_grp6 = 0xb00202c0, - regi_iop_trigger_grp7 = 0xb0020300, - regi_iop_crc_par0 = 0xb0020380, - regi_iop_crc_par1 = 0xb0020400, - regi_iop_dmc_in0 = 0xb0020480, - regi_iop_dmc_in1 = 0xb0020500, - regi_iop_dmc_out0 = 0xb0020580, - regi_iop_dmc_out1 = 0xb0020600, - regi_iop_fifo_in0 = 0xb0020680, - regi_iop_fifo_in1 = 0xb0020700, - regi_iop_fifo_out0 = 0xb0020780, - regi_iop_fifo_out1 = 0xb0020800, - regi_iop_scrc_in0 = 0xb0020880, - regi_iop_scrc_in1 = 0xb0020900, - regi_iop_scrc_out0 = 0xb0020980, - regi_iop_scrc_out1 = 0xb0020a00, - regi_iop_timer_grp0 = 0xb0020a80, - regi_iop_timer_grp1 = 0xb0020b00, - regi_iop_timer_grp2 = 0xb0020b80, - regi_iop_timer_grp3 = 0xb0020c00, - regi_iop_sap_in = 0xb0020d00, - regi_iop_sap_out = 0xb0020e00, - regi_iop_spu0 = 0xb0020f00, - regi_iop_spu1 = 0xb0021000, - regi_iop_sw_cfg = 0xb0021100, - regi_iop_sw_cpu = 0xb0021200, - regi_iop_sw_mpu = 0xb0021300, - regi_iop_sw_spu0 = 0xb0021400, - regi_iop_sw_spu1 = 0xb0021500, - regi_iop_mpu = 0xb0021600, - regi_irq = 0xb001c000, - regi_irq2 = 0xb005c000, - regi_marb = 0xb003e000, - regi_marb_bp0 = 0xb003e240, - regi_marb_bp1 = 0xb003e280, - regi_marb_bp2 = 0xb003e2c0, - regi_marb_bp3 = 0xb003e300, - regi_pinmux = 0xb0038000, - regi_ser0 = 0xb0026000, - regi_ser1 = 0xb0028000, - regi_ser2 = 0xb002a000, - regi_ser3 = 0xb002c000, - regi_sser0 = 0xb0022000, - regi_sser1 = 0xb0024000, - regi_strcop = 0xb0030000, - regi_strmux = 0xb003a000, - regi_timer = 0xb001e000, - regi_timer0 = 0xb001e000, - regi_timer2 = 0xb005e000, - regi_trace = 0xb0040000, -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h deleted file mode 100644 index 0ab49edb1c81..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h deleted file mode 100644 index 59c70ba9959b..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h deleted file mode 100644 index 94328936cc91..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00020000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h b/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h deleted file mode 100644 index 1d87f1392dc8..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); - -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc deleted file mode 100644 index 96c3b0fb62c1..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef STARTUP_INC_INCLUDED -#define STARTUP_INC_INCLUDED - -#include -#include -#include -#include - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 - move.d $r0, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - ;; Set up waitstates etc - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 - move.d $r1, [$r0] - .endm - -#endif diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild deleted file mode 100644 index 6a547fe8752b..000000000000 --- a/arch/cris/include/asm/Kbuild +++ /dev/null @@ -1,31 +0,0 @@ -generic-y += atomic.h -generic-y += barrier.h -generic-y += cmpxchg.h -generic-y += current.h -generic-y += device.h -generic-y += div64.h -generic-y += dma-mapping.h -generic-y += emergency-restart.h -generic-y += exec.h -generic-y += extable.h -generic-y += futex.h -generic-y += hardirq.h -generic-y += irq_regs.h -generic-y += irq_work.h -generic-y += kdebug.h -generic-y += kmap_types.h -generic-y += kprobes.h -generic-y += linkage.h -generic-y += local.h -generic-y += local64.h -generic-y += mcs_spinlock.h -generic-y += mm-arch-hooks.h -generic-y += module.h -generic-y += percpu.h -generic-y += preempt.h -generic-y += sections.h -generic-y += topology.h -generic-y += trace_clock.h -generic-y += vga.h -generic-y += word-at-a-time.h -generic-y += xor.h diff --git a/arch/cris/include/asm/asm-offsets.h b/arch/cris/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/arch/cris/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/axisflashmap.h b/arch/cris/include/asm/axisflashmap.h deleted file mode 100644 index 185596c2caab..000000000000 --- a/arch/cris/include/asm/axisflashmap.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_AXISFLASHMAP_H -#define __ASM_AXISFLASHMAP_H - -/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC - * as start, it ends with 0xFFFFFFFF */ -#define FLASH_BOOT_MAGIC 0xbeefcace -#define BOOTPARAM_OFFSET 0xc000 -/* apps/bootblocktool is used to read and write the parameters, - * and it has nothing to do with the partition table. - */ - -#define PARTITION_TABLE_OFFSET 10 -#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */ - -/* The partitiontable_head is located at offset +10: */ -struct partitiontable_head { - __u16 magic; /* PARTITION_TABLE_MAGIC */ - __u16 size; /* Length of ptable block (entries + end marker) */ - __u32 checksum; /* simple longword sum, over entries + end marker */ -}; - -/* And followed by partition table entries */ -struct partitiontable_entry { - __u32 offset; /* relative to the sector the ptable is in */ - __u32 size; /* in bytes */ - __u32 checksum; /* simple longword sum */ - __u16 type; /* see type codes below */ - __u16 flags; /* bit 0: ro/rw = 1/0 */ - __u32 future0; /* 16 bytes reserved for future use */ - __u32 future1; - __u32 future2; - __u32 future3; -}; -/* ended by an end marker: */ -#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF -#define PARTITIONTABLE_END_MARKER_SIZE 4 - -#define PARTITIONTABLE_END_PAD 10 - -/* Complete structure for whole partition table */ -/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting - * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER. - */ -struct partitiontable { - __u8 skip[PARTITION_TABLE_OFFSET]; - struct partitiontable_head head; - struct partitiontable_entry entries[]; -}; - -#define PARTITION_TYPE_PARAM 0x0001 -#define PARTITION_TYPE_KERNEL 0x0002 -#define PARTITION_TYPE_JFFS 0x0003 -#define PARTITION_TYPE_JFFS2 0x0000 - -#define PARTITION_FLAGS_READONLY_MASK 0x0001 -#define PARTITION_FLAGS_READONLY 0x0001 - -/* The master mtd for the entire flash. */ -extern struct mtd_info *axisflash_mtd; - -#endif diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h deleted file mode 100644 index 78f975ad42d9..000000000000 --- a/arch/cris/include/asm/bitops.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* asm/bitops.h for Linux/CRIS - * - * TODO: asm versions if speed is needed - * - * All bit operations return 0 if the bit was cleared before the - * operation and != 0 if it was not. - * - * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). - */ - -#ifndef _CRIS_BITOPS_H -#define _CRIS_BITOPS_H - -/* Currently this is unsuitable for consumption outside the kernel. */ -#ifdef __KERNEL__ - -#ifndef _LINUX_BITOPS_H -#error only can be included directly -#endif - -#include -#include -#include - -#include -#include - -/* - * Since we define it "external", it collides with the built-in - * definition, which doesn't have the same semantics. We don't want to - * use -fno-builtin, so just hide the name ffs. - */ -#define ffs(x) kernel_ffs(x) - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include - -#endif /* __KERNEL__ */ - -#endif /* _CRIS_BITOPS_H */ diff --git a/arch/cris/include/asm/bug.h b/arch/cris/include/asm/bug.h deleted file mode 100644 index f1fa72a426c2..000000000000 --- a/arch/cris/include/asm/bug.h +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_BUG_H -#define _CRIS_BUG_H -#include -#endif diff --git a/arch/cris/include/asm/bugs.h b/arch/cris/include/asm/bugs.h deleted file mode 100644 index c5907aac1007..000000000000 --- a/arch/cris/include/asm/bugs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $ - * - * include/asm-cris/bugs.h - * - * Copyright (C) 2001 Axis Communications AB - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -static void check_bugs(void) -{ -} - - - - diff --git a/arch/cris/include/asm/cache.h b/arch/cris/include/asm/cache.h deleted file mode 100644 index 8dac0922721c..000000000000 --- a/arch/cris/include/asm/cache.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include - -#endif /* _ASM_CACHE_H */ diff --git a/arch/cris/include/asm/cacheflush.h b/arch/cris/include/asm/cacheflush.h deleted file mode 100644 index 0da1c76a2bbc..000000000000 --- a/arch/cris/include/asm/cacheflush.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_CACHEFLUSH_H -#define _CRIS_CACHEFLUSH_H - -/* Keep includes the same across arches. */ -#include - -/* The cache doesn't need to be flushed when TLB entries change because - * the cache is mapped to physical memory, not virtual memory - */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start, end) do { } while (0) -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -int change_page_attr(struct page *page, int numpages, pgprot_t prot); - -#endif /* _CRIS_CACHEFLUSH_H */ diff --git a/arch/cris/include/asm/checksum.h b/arch/cris/include/asm/checksum.h deleted file mode 100644 index 61b6a4f6a002..000000000000 --- a/arch/cris/include/asm/checksum.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */ - -#ifndef _CRIS_CHECKSUM_H -#define _CRIS_CHECKSUM_H - -#include - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -__wsum csum_partial(const void *buff, int len, __wsum sum); - -/* - * the same as csum_partial, but copies from src while it - * checksums - * - * here even more important to align src and dst on a 32-bit (or even - * better 64-bit) boundary - */ - -__wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum); - -/* - * Fold a partial checksum into a word - */ - -static inline __sum16 csum_fold(__wsum csum) -{ - u32 sum = (__force u32)csum; - sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ - sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */ - return (__force __sum16)~sum; -} - -extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, - int len, __wsum sum, - int *errptr); - -/* - * This is a version of ip_compute_csum() optimized for IP headers, - * which always checksum on 4 octet boundaries. - * - */ - -static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) -{ - return csum_fold(csum_partial(iph, ihl * 4, 0)); -} - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ - -static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr, - __u32 len, __u8 proto, - __wsum sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); -} - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ - -static inline __sum16 ip_compute_csum(const void *buff, int len) -{ - return csum_fold (csum_partial(buff, len, 0)); -} - -#endif diff --git a/arch/cris/include/asm/delay.h b/arch/cris/include/asm/delay.h deleted file mode 100644 index 2dfdb13e1a9e..000000000000 --- a/arch/cris/include/asm/delay.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_DELAY_H -#define _CRIS_DELAY_H - -/* - * Copyright (C) 1998-2002 Axis Communications AB - * - * Delay routines, using a pre-computed "loops_per_second" value. - */ - -#include - -/* Use only for very small delays ( < 1 msec). */ - -extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */ - -/* May be defined by arch/delay.h. */ -#ifndef udelay -static inline void udelay(unsigned long usecs) -{ - __delay(usecs * loops_per_usec); -} -#endif - -#endif /* defined(_CRIS_DELAY_H) */ - - - diff --git a/arch/cris/include/asm/dma.h b/arch/cris/include/asm/dma.h deleted file mode 100644 index e1f7d6d9bfc2..000000000000 --- a/arch/cris/include/asm/dma.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */ - -#ifndef _ASM_DMA_H -#define _ASM_DMA_H - -#include - -/* it's useless on the Etrax, but unfortunately needed by the new - bootmem allocator (but this should do it for this) */ - -#define MAX_DMA_ADDRESS PAGE_OFFSET - -/* From PCI */ - -#ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) -#endif - -#endif /* _ASM_DMA_H */ diff --git a/arch/cris/include/asm/eshlibld.h b/arch/cris/include/asm/eshlibld.h deleted file mode 100644 index 88940556c2db..000000000000 --- a/arch/cris/include/asm/eshlibld.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/*!************************************************************************** -*! -*! FILE NAME : eshlibld.h -*! -*! DESCRIPTION: Prototypes for exported shared library functions -*! -*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit -*! (EXPORTED) -*! -*!--------------------------------------------------------------------------- -*! -*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN -*! -*!**************************************************************************/ -/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */ - -#ifndef _cris_relocate_h -#define _cris_relocate_h - -/* Please note that this file is also compiled into the xsim simulator. - Try to avoid breaking its double use (only works on a little-endian - 32-bit machine such as the i386 anyway). - - Use __KERNEL__ when you're about to use kernel functions, - (which you should not do here anyway, since this file is - used by glibc). - Use defined(__KERNEL__) || defined(__elinux__) when doing - things that only makes sense on an elinux system. - Use __CRIS__ when you're about to do (really) CRIS-specific code. -*/ - -/* We have dependencies all over the place for the host system - for xsim being a linux system, so let's not pretend anything - else with #ifdef:s here until fixed. */ -#include - -/* Maybe do sanity checking if file input. */ -#undef SANITYCHECK_RELOC - -/* Maybe output debug messages. */ -#undef RELOC_DEBUG - -/* Maybe we want to share core as well as disk space. - Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is - assumed that we want to share code when debugging (exposes more - trouble). */ -#ifndef SHARE_LIB_CORE -# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) -# define SHARE_LIB_CORE 0 -# else -# define SHARE_LIB_CORE 1 -# endif /* __KERNEL__ etc */ -#endif /* SHARE_LIB_CORE */ - - -/* Main exported function; supposed to be called when the program a.out - has been read in. */ -extern int -perform_cris_aout_relocations(unsigned long text, unsigned long tlength, - unsigned long data, unsigned long dlength, - unsigned long baddr, unsigned long blength, - - /* These may be zero when there's "perfect" - position-independent code. */ - unsigned char *trel, unsigned long tsrel, - unsigned long dsrel, - - /* These will be zero at a first try, to see - if code is statically linked. Else a - second try, with the symbol table and - string table nonzero should be done. */ - unsigned char *symbols, unsigned long symlength, - unsigned char *strings, unsigned long stringlength, - - /* These will only be used when symbol table - information is present. */ - char **env, int envc, - int euid, int is_suid); - - -#ifdef RELOC_DEBUG -/* Task-specific debug stuff. */ -struct task_reloc_debug { - struct memdebug *alloclast; - unsigned long alloc_total; - unsigned long export_total; -}; -#endif /* RELOC_DEBUG */ - -#if SHARE_LIB_CORE - -/* When code (and some very specific data) is shared and not just - dynamically linked, we need to export hooks for exec beginning and - end. */ - -struct shlibdep; - -extern void -shlibmod_exit(struct shlibdep **deps); - -/* Returns 0 if failure, nonzero for ok. */ -extern int -shlibmod_fork(struct shlibdep **deps); - -#else /* ! SHARE_LIB_CORE */ -# define shlibmod_exit(x) -# define shlibmod_fork(x) 1 -#endif /* ! SHARE_LIB_CORE */ - -#endif _cris_relocate_h -/********************** END OF FILE eshlibld.h *****************************/ - diff --git a/arch/cris/include/asm/etraxi2c.h b/arch/cris/include/asm/etraxi2c.h deleted file mode 100644 index 0fa6f03d93e7..000000000000 --- a/arch/cris/include/asm/etraxi2c.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */ - -#ifndef _LINUX_ETRAXI2C_H -#define _LINUX_ETRAXI2C_H - -/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */ - -#define ETRAXI2C_IOCTYPE 44 - -/* supported ioctl _IOC_NR's */ - -/* in write operations, the argument contains both i2c - * slave, register and value. - */ - -#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value)) -#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8)) - -#define I2C_ARGSLAVE(arg) ((arg) >> 16) -#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff) -#define I2C_ARGVALUE(arg) ((arg) & 0xff) - -#define I2C_WRITEREG 0x1 /* write to an i2c register */ -#define I2C_READREG 0x2 /* read from an i2c register */ - -/* -EXAMPLE usage: - - i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val); - ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg); - - i2c_arg = I2C_READARG(STA013_READ_ADDR, reg); - val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg); - -*/ -#endif diff --git a/arch/cris/include/asm/fasttimer.h b/arch/cris/include/asm/fasttimer.h deleted file mode 100644 index bc109f4a8377..000000000000 --- a/arch/cris/include/asm/fasttimer.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/include/asm-cris/fasttimer.h - * - * Fast timers for ETRAX100LX - * Copyright (C) 2000-2007 Axis Communications AB - */ -#include /* struct timeval */ -#include - -#ifdef CONFIG_ETRAX_FAST_TIMER - -typedef void fast_timer_function_type(unsigned long); - -struct fasttime_t { - unsigned long tv_jiff; /* jiffies */ - unsigned long tv_usec; /* microseconds */ -}; - -struct fast_timer{ /* Close to timer_list */ - struct fast_timer *next; - struct fast_timer *prev; - struct fasttime_t tv_set; - struct fasttime_t tv_expires; - unsigned long delay_us; - fast_timer_function_type *function; - unsigned long data; - const char *name; -}; - -extern struct fast_timer *fast_timer_list; - -void start_one_shot_timer(struct fast_timer *t, - fast_timer_function_type *function, - unsigned long data, - unsigned long delay_us, - const char *name); - -int del_fast_timer(struct fast_timer * t); -/* return 1 if deleted */ - - -void schedule_usleep(unsigned long us); - - -int fast_timer_init(void); - -#endif diff --git a/arch/cris/include/asm/fb.h b/arch/cris/include/asm/fb.h deleted file mode 100644 index e10150073c30..000000000000 --- a/arch/cris/include/asm/fb.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ -#include - -#define fb_pgprotect(...) do {} while (0) - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ diff --git a/arch/cris/include/asm/ftrace.h b/arch/cris/include/asm/ftrace.h deleted file mode 100644 index 40a8c178f10d..000000000000 --- a/arch/cris/include/asm/ftrace.h +++ /dev/null @@ -1 +0,0 @@ -/* empty */ diff --git a/arch/cris/include/asm/hw_irq.h b/arch/cris/include/asm/hw_irq.h deleted file mode 100644 index 298066020af2..000000000000 --- a/arch/cris/include/asm/hw_irq.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef _ASM_HW_IRQ_H -#define _ASM_HW_IRQ_H - -#endif - diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h deleted file mode 100644 index c92712d30f54..000000000000 --- a/arch/cris/include/asm/io.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_IO_H -#define _ASM_CRIS_IO_H - -#include /* for __va, __pa */ -#ifdef CONFIG_ETRAX_ARCH_V10 -#include -#endif -#include -#include - -extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); -extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot); - -static inline void __iomem * ioremap (unsigned long offset, unsigned long size) -{ - return __ioremap(offset, size, 0); -} - -extern void iounmap(volatile void * __iomem addr); - -extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size); - -#include - -#endif diff --git a/arch/cris/include/asm/irq.h b/arch/cris/include/asm/irq.h deleted file mode 100644 index 6a932f7db58e..000000000000 --- a/arch/cris/include/asm/irq.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_IRQ_H -#define _ASM_IRQ_H - -#include - -static inline int irq_canonicalize(int irq) -{ - return irq; -} - -#endif /* _ASM_IRQ_H */ - - diff --git a/arch/cris/include/asm/irqflags.h b/arch/cris/include/asm/irqflags.h deleted file mode 100644 index 943ba5ca6d2c..000000000000 --- a/arch/cris/include/asm/irqflags.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/mmu.h b/arch/cris/include/asm/mmu.h deleted file mode 100644 index 54da8f64b37a..000000000000 --- a/arch/cris/include/asm/mmu.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * CRIS MMU constants and PTE layout - */ - -#ifndef _CRIS_MMU_H -#define _CRIS_MMU_H - -#include - -#endif diff --git a/arch/cris/include/asm/mmu_context.h b/arch/cris/include/asm/mmu_context.h deleted file mode 100644 index 178f3b72e9e3..000000000000 --- a/arch/cris/include/asm/mmu_context.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __CRIS_MMU_CONTEXT_H -#define __CRIS_MMU_CONTEXT_H - -#include - -extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); -extern void get_mmu_context(struct mm_struct *mm); -extern void destroy_context(struct mm_struct *mm); -extern void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk); - -#define deactivate_mm(tsk,mm) do { } while (0) - -static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next) -{ - unsigned long flags; - - local_irq_save(flags); - switch_mm(prev, next, NULL); - local_irq_restore(flags); -} - -/* current active pgd - this is similar to other processors pgd - * registers like cr3 on the i386 - */ - -/* defined in arch/cris/mm/fault.c */ -DECLARE_PER_CPU(pgd_t *, current_pgd); - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -#endif diff --git a/arch/cris/include/asm/page.h b/arch/cris/include/asm/page.h deleted file mode 100644 index 5b5b3dad7484..000000000000 --- a/arch/cris/include/asm/page.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_PAGE_H -#define _CRIS_PAGE_H - -#include -#include - -/* PAGE_SHIFT determines the page size */ -#define PAGE_SHIFT 13 -#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE) - -#define clear_user_page(page, vaddr, pg) clear_page(page) -#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) - -#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ - alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) -#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE - -/* - * These are used to make use of C type-checking.. - */ -#ifndef __ASSEMBLY__ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; -#endif - -#define pte_val(x) ((x).pte) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */ -/* for that before indexing into the page table starting at mem_map */ -#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) -#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr) - -/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so - * we can let the map start there. notice that we subtract PAGE_OFFSET because - * we start our mem_map there - in other ports they map mem_map physically and - * use __pa instead. in our system both the physical and virtual address of DRAM - * is too high to let mem_map start at 0, so we do it this way instead (similar - * to arm and m68k I think) - */ - -#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT) - -/* convert a page (based on mem_map and forward) to a physical address - * do this by figuring out the virtual address and then use __pa - */ - -#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) - -#ifndef __ASSEMBLY__ - -#endif /* __ASSEMBLY__ */ - -#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) - -#include -#include - -#endif /* _CRIS_PAGE_H */ - diff --git a/arch/cris/include/asm/pci.h b/arch/cris/include/asm/pci.h deleted file mode 100644 index dcfef6407ae6..000000000000 --- a/arch/cris/include/asm/pci.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_PCI_H -#define __ASM_CRIS_PCI_H - - -#ifdef __KERNEL__ -#include /* for struct page */ - -/* Can be used to override the logic in pci_scan_bus for skipping - already-configured bus numbers - to be used for buggy BIOSes - or architectures with incomplete PCI setup by the loader */ - -#define pcibios_assign_all_busses(void) 1 - -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 - -#define PCIBIOS_MIN_CARDBUS_IO 0x4000 - -/* Dynamic DMA mapping stuff. - * i386 has everything mapped statically. - */ - -#include -#include -#include -#include -#include - -/* The PCI address space does equal the physical memory - * address space. The networking and block device layers use - * this boolean for bounce buffer decisions. - */ -#define PCI_DMA_BUS_IS_PHYS (1) - -#define HAVE_PCI_MMAP -#define ARCH_GENERIC_PCI_MMAP_RESOURCE - -#endif /* __KERNEL__ */ - -/* generic pci stuff */ -#include - -#endif /* __ASM_CRIS_PCI_H */ diff --git a/arch/cris/include/asm/pgalloc.h b/arch/cris/include/asm/pgalloc.h deleted file mode 100644 index d8dc1b834b7d..000000000000 --- a/arch/cris/include/asm/pgalloc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_PGALLOC_H -#define _CRIS_PGALLOC_H - -#include -#include - -#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte) -#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte)) -#define pmd_pgtable(pmd) pmd_page(pmd) - -/* - * Allocate and free page tables. - */ - -static inline pgd_t *pgd_alloc (struct mm_struct *mm) -{ - return (pgd_t *)get_zeroed_page(GFP_KERNEL); -} - -static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) -{ - free_page((unsigned long)pgd); -} - -static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) -{ - pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO); - return pte; -} - -static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) -{ - struct page *pte; - pte = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); - if (!pte) - return NULL; - if (!pgtable_page_ctor(pte)) { - __free_page(pte); - return NULL; - } - return pte; -} - -static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) -{ - free_page((unsigned long)pte); -} - -static inline void pte_free(struct mm_struct *mm, pgtable_t pte) -{ - pgtable_page_dtor(pte); - __free_page(pte); -} - -#define __pte_free_tlb(tlb,pte,address) \ -do { \ - pgtable_page_dtor(pte); \ - tlb_remove_page((tlb), pte); \ -} while (0) - -#define check_pgt_cache() do { } while (0) - -#endif diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h deleted file mode 100644 index 03fca401e23c..000000000000 --- a/arch/cris/include/asm/pgtable.h +++ /dev/null @@ -1,297 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * CRIS pgtable.h - macros and functions to manipulate page tables. - */ - -#ifndef _CRIS_PGTABLE_H -#define _CRIS_PGTABLE_H - -#include -#define __ARCH_USE_5LEVEL_HACK -#include - -#ifndef __ASSEMBLY__ -#include -#include -#endif -#include - -/* - * The Linux memory management assumes a three-level page table setup. On - * CRIS, we use that, but "fold" the mid level into the top-level page - * table. Since the MMU TLB is software loaded through an interrupt, it - * supports any page table structure, so we could have used a three-level - * setup, but for the amounts of memory we normally use, a two-level is - * probably more efficient. - * - * This file contains the functions and defines necessary to modify and use - * the CRIS page table tree. - */ -#ifndef __ASSEMBLY__ -extern void paging_init(void); -#endif - -/* Certain architectures need to do special things when pte's - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - -/* - * (pmds are folded into pgds so this doesn't get actually called, - * but the define is needed for a generic inline function.) - */ -#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) -#define set_pgu(pudptr, pudval) (*(pudptr) = pudval) - -/* PGDIR_SHIFT determines the size of the area a second-level page table can - * map. It is equal to the page size times the number of PTE's that fit in - * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. - */ - -#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * entries per page directory level: we use a two-level, so - * we don't really have any PMD directory physically. - * pointers are 4 bytes so we can use the page size and - * divide it by 4 (shift by 2). - */ -#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) -#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) - -/* calculate how many PGD entries a user-level program can use - * the first mappable virtual address is 0 - * (TASK_SIZE is the maximum virtual address space) - */ - -#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) -#define FIRST_USER_ADDRESS 0UL - -/* zero page used for uninitialized stuff */ -#ifndef __ASSEMBLY__ -extern unsigned long empty_zero_page; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) -#endif - -/* number of bits that fit into a memory pointer */ -#define BITS_PER_PTR (8*sizeof(unsigned long)) - -/* to align the pointer to a pointer address */ -#define PTR_MASK (~(sizeof(void*)-1)) - -/* sizeof(void*)==1<>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) - -/* to set the page-dir */ -#define SET_PAGE_DIR(tsk,pgdir) - -#define pte_none(x) (!pte_val(x)) -#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) -#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0) - -#define pmd_none(x) (!pmd_val(x)) -/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad - * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. - */ -#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) -#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) -#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) - -#ifndef __ASSEMBLY__ - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ - -static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } -static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } -static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } -static inline int pte_special(pte_t pte) { return 0; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); - return pte; -} - -static inline pte_t pte_mkold(pte_t pte) -{ - pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) |= _PAGE_WRITE; - if (pte_val(pte) & _PAGE_MODIFIED) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkdirty(pte_t pte) -{ - pte_val(pte) |= _PAGE_MODIFIED; - if (pte_val(pte) & _PAGE_WRITE) - pte_val(pte) |= _PAGE_SILENT_WRITE; - return pte; -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - { - pte_val(pte) |= _PAGE_SILENT_READ; - if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == - (_PAGE_WRITE | _PAGE_MODIFIED)) - pte_val(pte) |= _PAGE_SILENT_WRITE; - } - return pte; -} -static inline pte_t pte_mkspecial(pte_t pte) { return pte; } - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ - -/* What actually goes as arguments to the various functions is less than - * obvious, but a rule of thumb is that struct page's goes as struct page *, - * really physical DRAM addresses are unsigned long's, and DRAM "virtual" - * addresses (the 0xc0xxxxxx's) goes as void *'s. - */ - -static inline pte_t __mk_pte(void * page, pgprot_t pgprot) -{ - pte_t pte; - /* the PTE needs a physical address */ - pte_val(pte) = __pa(page) | pgprot_val(pgprot); - return pte; -} - -#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) - -#define mk_pte_phys(physpage, pgprot) \ -({ \ - pte_t __pte; \ - \ - pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ - __pte; \ -}) - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } - -#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE)) - - -/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval - * __pte_page(pte_val) refers to the "virtual" DRAM interval - * pte_pagenr refers to the page-number counted starting from the virtual DRAM start - */ - -static inline unsigned long __pte_page(pte_t pte) -{ - /* the PTE contains a physical address */ - return (unsigned long)__va(pte_val(pte) & PAGE_MASK); -} - -#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) - -/* permanent address of a page */ - -#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) -#define pte_page(pte) (mem_map+pte_pagenr(pte)) - -/* only the pte's themselves need to point to physical DRAM (see above) - * the pagetable links are purely handled within the kernel SW and thus - * don't need the __pa and __va transformations. - */ - -static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) -{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } - -#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)) -#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) - -/* to find an entry in a page-table-directory. */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) - -/* to find an entry in a page-table-directory */ -static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address) -{ - return mm->pgd + pgd_index(address); -} - -/* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(address) pgd_offset(&init_mm, address) - -/* Find an entry in the third-level page table.. */ -#define __pte_offset(address) \ - (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) -#define pte_offset_kernel(dir, address) \ - ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) -#define pte_offset_map(dir, address) \ - ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) - -#define pte_unmap(pte) do { } while (0) -#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) - -#define pte_ERROR(e) \ - printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) -#define pgd_ERROR(e) \ - printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) - - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ - -/* - * CRIS doesn't have any external MMU info: the kernel page - * tables contain all the necessary information. - * - * Actually I am not sure on what this could be used for. - */ -static inline void update_mmu_cache(struct vm_area_struct * vma, - unsigned long address, pte_t *ptep) -{ -} - -/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ -/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ - -#define __swp_type(x) (((x).val >> 5) & 0x7f) -#define __swp_offset(x) ((x).val >> 12) -#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -#define kern_addr_valid(addr) (1) - -#include - -/* - * No page table caches to initialise - */ -#define pgtable_cache_init() do { } while (0) - -typedef pte_t *pte_addr_t; - -#endif /* __ASSEMBLY__ */ -#endif /* _CRIS_PGTABLE_H */ diff --git a/arch/cris/include/asm/processor.h b/arch/cris/include/asm/processor.h deleted file mode 100644 index ee4d8b03d048..000000000000 --- a/arch/cris/include/asm/processor.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/asm-cris/processor.h - * - * Copyright (C) 2000, 2001 Axis Communications AB - * - * Authors: Bjorn Wesen Initial version - * - */ - -#ifndef __ASM_CRIS_PROCESSOR_H -#define __ASM_CRIS_PROCESSOR_H - -#include -#include -#include -#include - -struct task_struct; - -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX STACK_TOP - -/* This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) - -/* - * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack. - * This macro allows us to find those regs for a task. - * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while - * we're in the kernel, won't affect this - only the first user->kernel transition - * registers are reached by this. - */ - -#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1) - -/* - * Dito but for the currently running task - */ - -#define task_pt_regs(task) user_regs(task_thread_info(task)) - -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ - /* Nothing needs to be done. */ -} - -#define cpu_relax() barrier() - -void default_idle(void); - -#endif /* __ASM_CRIS_PROCESSOR_H */ diff --git a/arch/cris/include/asm/ptrace.h b/arch/cris/include/asm/ptrace.h deleted file mode 100644 index d69295f1a7c8..000000000000 --- a/arch/cris/include/asm/ptrace.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_PTRACE_H -#define _CRIS_PTRACE_H - -#include - - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 - -#define profile_pc(regs) instruction_pointer(regs) -#define current_user_stack_pointer() rdusp() - -#endif /* _CRIS_PTRACE_H */ diff --git a/arch/cris/include/asm/segment.h b/arch/cris/include/asm/segment.h deleted file mode 100644 index 6ac914b098bf..000000000000 --- a/arch/cris/include/asm/segment.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_SEGMENT_H -#define _ASM_SEGMENT_H - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#endif diff --git a/arch/cris/include/asm/serial.h b/arch/cris/include/asm/serial.h deleted file mode 100644 index f51e0e10faa7..000000000000 --- a/arch/cris/include/asm/serial.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_SERIAL_H -#define _ASM_SERIAL_H - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - */ -#define BASE_BAUD (1843200 / 16) - -#endif /* _ASM_SERIAL_H */ diff --git a/arch/cris/include/asm/shmparam.h b/arch/cris/include/asm/shmparam.h deleted file mode 100644 index 704a7257cb0d..000000000000 --- a/arch/cris/include/asm/shmparam.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_SHMPARAM_H -#define _ASM_CRIS_SHMPARAM_H - -/* same as asm-i386/ version.. */ - -#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ - -#endif /* _ASM_CRIS_SHMPARAM_H */ diff --git a/arch/cris/include/asm/signal.h b/arch/cris/include/asm/signal.h deleted file mode 100644 index 64b0943c0b00..000000000000 --- a/arch/cris/include/asm/signal.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_SIGNAL_H -#define _ASM_CRIS_SIGNAL_H - -#include - -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#define __ARCH_HAS_SA_RESTORER - -#include - -#endif diff --git a/arch/cris/include/asm/stacktrace.h b/arch/cris/include/asm/stacktrace.h deleted file mode 100644 index 154f0c90d0fa..000000000000 --- a/arch/cris/include/asm/stacktrace.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __CRIS_STACKTRACE_H -#define __CRIS_STACKTRACE_H - -void walk_stackframe(unsigned long sp, - int (*fn)(unsigned long addr, void *data), - void *data); - -#endif diff --git a/arch/cris/include/asm/string.h b/arch/cris/include/asm/string.h deleted file mode 100644 index bae5a0867785..000000000000 --- a/arch/cris/include/asm/string.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_STRING_H -#define _ASM_CRIS_STRING_H - -/* the optimized memcpy is in arch/cris/lib/string.c */ - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *, const void *, size_t); - -/* New and improved. In arch/cris/lib/memset.c */ - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, size_t); - -#ifdef CONFIG_ETRAX_ARCH_V32 -/* For v32 we provide strcmp. */ -#define __HAVE_ARCH_STRCMP -extern int strcmp(const char *s1, const char *s2); -#endif - -#endif diff --git a/arch/cris/include/asm/swab.h b/arch/cris/include/asm/swab.h deleted file mode 100644 index 5e1d8cf277fb..000000000000 --- a/arch/cris/include/asm/swab.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_SWAB_H -#define _CRIS_SWAB_H - -#include -#include - -#endif /* _CRIS_SWAB_H */ diff --git a/arch/cris/include/asm/switch_to.h b/arch/cris/include/asm/switch_to.h deleted file mode 100644 index dde4acf6e54d..000000000000 --- a/arch/cris/include/asm/switch_to.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_SWITCH_TO_H -#define __ASM_CRIS_SWITCH_TO_H - -/* the switch_to macro calls resume, an asm function in entry.S which does the actual - * task switching. - */ - -extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int); -#define switch_to(prev,next,last) last = resume(prev,next, \ - (int)&((struct task_struct *)0)->thread) - -#endif /* __ASM_CRIS_SWITCH_TO_H */ diff --git a/arch/cris/include/asm/termios.h b/arch/cris/include/asm/termios.h deleted file mode 100644 index 9832bf3221d0..000000000000 --- a/arch/cris/include/asm/termios.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_TERMIOS_H -#define _CRIS_TERMIOS_H - -#include - - -/* intr=^C quit=^\ erase=del kill=^U - eof=^D vtime=\0 vmin=\1 sxtc=\0 - start=^Q stop=^S susp=^Z eol=\0 - reprint=^R discard=^U werase=^W lnext=^V - eol2=\0 -*/ -#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" - -/* - * Translate a "termio" structure into a "termios". Ugh. - */ -#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ - unsigned short __tmp; \ - get_user(__tmp,&(termio)->x); \ - *(unsigned short *) &(termios)->x = __tmp; \ -} - -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ - SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) - -/* - * Translate a "termios" structure into a "termio". Ugh. - */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) - -#endif /* _CRIS_TERMIOS_H */ diff --git a/arch/cris/include/asm/thread_info.h b/arch/cris/include/asm/thread_info.h deleted file mode 100644 index 996fef3be1d5..000000000000 --- a/arch/cris/include/asm/thread_info.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* thread_info.h: CRIS low-level thread information - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - * - * CRIS port by Axis Communications - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -#include -#include -#include -#include -#endif - - -/* THREAD_SIZE is the size of the thread_info/kernel_stack combo. - * normally, the stack is found by doing something like p + THREAD_SIZE - * in CRIS, a page is 8192 bytes, which seems like a sane size - */ -#define THREAD_SIZE PAGE_SIZE -#define THREAD_SIZE_ORDER (0) - -/* - * low level task data that entry.S needs immediate access to - * - this struct should fit entirely inside of one cache line - * - this struct shares the supervisor stack pages - * - if the contents of this structure are changed, the assembly constants must also be changed - */ -#ifndef __ASSEMBLY__ -struct thread_info { - struct task_struct *task; /* main task structure */ - unsigned long flags; /* low level flags */ - __u32 cpu; /* current CPU */ - int preempt_count; /* 0 => preemptable, <0 => BUG */ - __u32 tls; /* TLS for this thread */ - - mm_segment_t addr_limit; /* thread address space: - 0-0xBFFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ - __u8 supervisor_stack[0]; -}; - -#endif - -/* - * macros/functions for gaining access to the thread information structure - */ -#ifndef __ASSEMBLY__ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ -} - -#endif /* !__ASSEMBLY__ */ - -/* - * thread information flags - * - these are process state flags that various assembly files may need to access - * - pending work-to-be-done flags are in LSW - * - other flags in MSW - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ -#define TIF_SIGPENDING 2 /* signal pending */ -#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ -#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ -#define TIF_MEMDIE 17 /* is terminating due to OOM killer */ - -#define _TIF_SYSCALL_TRACE (1< - -/* - * We don't have a cycle-counter.. but we do not support SMP anyway where this is - * used so it does not matter. - */ - -typedef unsigned long long cycles_t; - -static inline cycles_t get_cycles(void) -{ - return 0; -} - -#endif diff --git a/arch/cris/include/asm/tlb.h b/arch/cris/include/asm/tlb.h deleted file mode 100644 index 1f6a8a67cfda..000000000000 --- a/arch/cris/include/asm/tlb.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_TLB_H -#define _CRIS_TLB_H - -#include - -#include - -/* - * cris doesn't need any special per-pte or - * per-vma handling.. - */ -#define tlb_start_vma(tlb, vma) do { } while (0) -#define tlb_end_vma(tlb, vma) do { } while (0) -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) - -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) -#include - -#endif diff --git a/arch/cris/include/asm/tlbflush.h b/arch/cris/include/asm/tlbflush.h deleted file mode 100644 index e7cb964536d0..000000000000 --- a/arch/cris/include/asm/tlbflush.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _CRIS_TLBFLUSH_H -#define _CRIS_TLBFLUSH_H - -#include -#include -#include -#include - -/* - * TLB flushing (implemented in arch/cris/mm/tlb.c): - * - * - flush_tlb() flushes the current mm struct TLBs - * - flush_tlb_all() flushes all processes TLBs - * - flush_tlb_mm(mm) flushes the specified mm context TLB's - * - flush_tlb_page(vma, vmaddr) flushes one page - * - flush_tlb_range(mm, start, end) flushes a range of pages - * - */ - -extern void __flush_tlb_all(void); -extern void __flush_tlb_mm(struct mm_struct *mm); -extern void __flush_tlb_page(struct vm_area_struct *vma, - unsigned long addr); - -#define flush_tlb_all __flush_tlb_all -#define flush_tlb_mm __flush_tlb_mm -#define flush_tlb_page __flush_tlb_page - -static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) -{ - flush_tlb_mm(vma->vm_mm); -} - -static inline void flush_tlb(void) -{ - flush_tlb_mm(current->mm); -} - -#define flush_tlb_kernel_range(start, end) flush_tlb_all() - -#endif /* _CRIS_TLBFLUSH_H */ diff --git a/arch/cris/include/asm/uaccess.h b/arch/cris/include/asm/uaccess.h deleted file mode 100644 index 3b42ab0cae93..000000000000 --- a/arch/cris/include/asm/uaccess.h +++ /dev/null @@ -1,361 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Authors: Bjorn Wesen (bjornw@axis.com) - * Hans-Peter Nilsson (hp@axis.com) - */ - -/* Asm:s have been tweaked (within the domain of correctness) to give - satisfactory results for "gcc version 2.96 20000427 (experimental)". - - Check regularly... - - Register $r9 is chosen for temporaries, being a call-clobbered register - first in line to be used (notably for local blocks), not colliding with - parameter registers. */ - -#ifndef _CRIS_UACCESS_H -#define _CRIS_UACCESS_H - -#include -#include - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -/* addr_limit is the maximum accessible address for the task. we misuse - * the KERNEL_DS and USER_DS values to both assign and compare the - * addr_limit values through the equally misnamed get/set_fs macros. - * (see above) - */ - -#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) -#define USER_DS MAKE_MM_SEG(TASK_SIZE) - -#define get_ds() (KERNEL_DS) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define segment_eq(a, b) ((a).seg == (b).seg) - -#define __kernel_ok (uaccess_kernel()) -#define __user_ok(addr, size) \ - (((size) <= TASK_SIZE) && ((addr) <= TASK_SIZE-(size))) -#define __access_ok(addr, size) (__kernel_ok || __user_ok((addr), (size))) -#define access_ok(type, addr, size) __access_ok((unsigned long)(addr), (size)) - -#include -#include - -/* - * These are the main single-value transfer routines. They automatically - * use the right size if we just have the right pointer type. - * - * This gets kind of ugly. We want to return _two_ values in "get_user()" - * and yet we don't want to do any pointers, because that is too much - * of a performance impact. Thus we have a few rather ugly macros here, - * and hide all the ugliness from the user. - * - * The "__xxx" versions of the user access functions are versions that - * do not verify the address space, that must have been done previously - * with a separate "access_ok()" call (this is used when we do multiple - * accesses to the same area of user memory). - * - * As we use the same address space for kernel and user data on - * CRIS, we can just do these as direct assignments. (Of course, the - * exception handling means that it's no longer "just"...) - */ -#define get_user(x, ptr) \ - __get_user_check((x), (ptr), sizeof(*(ptr))) -#define put_user(x, ptr) \ - __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr))) - -#define __get_user(x, ptr) \ - __get_user_nocheck((x), (ptr), sizeof(*(ptr))) -#define __put_user(x, ptr) \ - __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr))) - -extern long __put_user_bad(void); - -#define __put_user_size(x, ptr, size, retval) \ -do { \ - retval = 0; \ - switch (size) { \ - case 1: \ - __put_user_asm(x, ptr, retval, "move.b"); \ - break; \ - case 2: \ - __put_user_asm(x, ptr, retval, "move.w"); \ - break; \ - case 4: \ - __put_user_asm(x, ptr, retval, "move.d"); \ - break; \ - case 8: \ - __put_user_asm_64(x, ptr, retval); \ - break; \ - default: \ - __put_user_bad(); \ - } \ -} while (0) - -#define __get_user_size(x, ptr, size, retval) \ -do { \ - retval = 0; \ - switch (size) { \ - case 1: \ - __get_user_asm(x, ptr, retval, "move.b"); \ - break; \ - case 2: \ - __get_user_asm(x, ptr, retval, "move.w"); \ - break; \ - case 4: \ - __get_user_asm(x, ptr, retval, "move.d"); \ - break; \ - case 8: \ - __get_user_asm_64(x, ptr, retval); \ - break; \ - default: \ - (x) = __get_user_bad(); \ - } \ -} while (0) - -#define __put_user_nocheck(x, ptr, size) \ -({ \ - long __pu_err; \ - __put_user_size((x), (ptr), (size), __pu_err); \ - __pu_err; \ -}) - -#define __put_user_check(x, ptr, size) \ -({ \ - long __pu_err = -EFAULT; \ - __typeof__(*(ptr)) *__pu_addr = (ptr); \ - if (access_ok(VERIFY_WRITE, __pu_addr, size)) \ - __put_user_size((x), __pu_addr, (size), __pu_err); \ - __pu_err; \ -}) - -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) - - - -#define __get_user_nocheck(x, ptr, size) \ -({ \ - long __gu_err, __gu_val; \ - __get_user_size(__gu_val, (ptr), (size), __gu_err); \ - (x) = (__force __typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -#define __get_user_check(x, ptr, size) \ -({ \ - long __gu_err = -EFAULT, __gu_val = 0; \ - const __typeof__(*(ptr)) *__gu_addr = (ptr); \ - if (access_ok(VERIFY_READ, __gu_addr, size)) \ - __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \ - (x) = (__force __typeof__(*(ptr)))__gu_val; \ - __gu_err; \ -}) - -extern long __get_user_bad(void); - -/* More complex functions. Most are inline, but some call functions that - live in lib/usercopy.c */ - -extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __copy_user_in(void *to, const void __user *from, unsigned long n); -extern unsigned long __do_clear_user(void __user *to, unsigned long n); - -static inline long -strncpy_from_user(char *dst, const char __user *src, long count) -{ - long res = -EFAULT; - - if (access_ok(VERIFY_READ, src, 1)) - res = __do_strncpy_from_user(dst, src, count); - return res; -} - - -/* Note that these expand awfully if made into switch constructs, so - don't do that. */ - -static inline unsigned long -__constant_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - unsigned long ret = 0; - - if (n == 0) - ; - else if (n == 1) - __asm_copy_from_user_1(to, from, ret); - else if (n == 2) - __asm_copy_from_user_2(to, from, ret); - else if (n == 3) - __asm_copy_from_user_3(to, from, ret); - else if (n == 4) - __asm_copy_from_user_4(to, from, ret); - else if (n == 5) - __asm_copy_from_user_5(to, from, ret); - else if (n == 6) - __asm_copy_from_user_6(to, from, ret); - else if (n == 7) - __asm_copy_from_user_7(to, from, ret); - else if (n == 8) - __asm_copy_from_user_8(to, from, ret); - else if (n == 9) - __asm_copy_from_user_9(to, from, ret); - else if (n == 10) - __asm_copy_from_user_10(to, from, ret); - else if (n == 11) - __asm_copy_from_user_11(to, from, ret); - else if (n == 12) - __asm_copy_from_user_12(to, from, ret); - else if (n == 13) - __asm_copy_from_user_13(to, from, ret); - else if (n == 14) - __asm_copy_from_user_14(to, from, ret); - else if (n == 15) - __asm_copy_from_user_15(to, from, ret); - else if (n == 16) - __asm_copy_from_user_16(to, from, ret); - else if (n == 20) - __asm_copy_from_user_20(to, from, ret); - else if (n == 24) - __asm_copy_from_user_24(to, from, ret); - else - ret = __copy_user_in(to, from, n); - - return ret; -} - -/* Ditto, don't make a switch out of this. */ - -static inline unsigned long -__constant_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - unsigned long ret = 0; - - if (n == 0) - ; - else if (n == 1) - __asm_copy_to_user_1(to, from, ret); - else if (n == 2) - __asm_copy_to_user_2(to, from, ret); - else if (n == 3) - __asm_copy_to_user_3(to, from, ret); - else if (n == 4) - __asm_copy_to_user_4(to, from, ret); - else if (n == 5) - __asm_copy_to_user_5(to, from, ret); - else if (n == 6) - __asm_copy_to_user_6(to, from, ret); - else if (n == 7) - __asm_copy_to_user_7(to, from, ret); - else if (n == 8) - __asm_copy_to_user_8(to, from, ret); - else if (n == 9) - __asm_copy_to_user_9(to, from, ret); - else if (n == 10) - __asm_copy_to_user_10(to, from, ret); - else if (n == 11) - __asm_copy_to_user_11(to, from, ret); - else if (n == 12) - __asm_copy_to_user_12(to, from, ret); - else if (n == 13) - __asm_copy_to_user_13(to, from, ret); - else if (n == 14) - __asm_copy_to_user_14(to, from, ret); - else if (n == 15) - __asm_copy_to_user_15(to, from, ret); - else if (n == 16) - __asm_copy_to_user_16(to, from, ret); - else if (n == 20) - __asm_copy_to_user_20(to, from, ret); - else if (n == 24) - __asm_copy_to_user_24(to, from, ret); - else - ret = __copy_user(to, from, n); - - return ret; -} - -/* No switch, please. */ - -static inline unsigned long -__constant_clear_user(void __user *to, unsigned long n) -{ - unsigned long ret = 0; - - if (n == 0) - ; - else if (n == 1) - __asm_clear_1(to, ret); - else if (n == 2) - __asm_clear_2(to, ret); - else if (n == 3) - __asm_clear_3(to, ret); - else if (n == 4) - __asm_clear_4(to, ret); - else if (n == 8) - __asm_clear_8(to, ret); - else if (n == 12) - __asm_clear_12(to, ret); - else if (n == 16) - __asm_clear_16(to, ret); - else if (n == 20) - __asm_clear_20(to, ret); - else if (n == 24) - __asm_clear_24(to, ret); - else - ret = __do_clear_user(to, n); - - return ret; -} - - -static inline size_t clear_user(void __user *to, size_t n) -{ - if (unlikely(!access_ok(VERIFY_WRITE, to, n))) - return n; - if (__builtin_constant_p(n)) - return __constant_clear_user(to, n); - else - return __do_clear_user(to, n); -} - -static inline unsigned long -raw_copy_from_user(void *to, const void __user *from, unsigned long n) -{ - if (__builtin_constant_p(n)) - return __constant_copy_from_user(to, from, n); - else - return __copy_user_in(to, from, n); -} - -static inline unsigned long -raw_copy_to_user(void __user *to, const void *from, unsigned long n) -{ - if (__builtin_constant_p(n)) - return __constant_copy_to_user(to, from, n); - else - return __copy_user(to, from, n); -} - -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - -static inline unsigned long -__clear_user(void __user *to, unsigned long n) -{ - return __do_clear_user(to, n); -} - -#endif /* _CRIS_UACCESS_H */ diff --git a/arch/cris/include/asm/ucontext.h b/arch/cris/include/asm/ucontext.h deleted file mode 100644 index 22f7e7cf59c8..000000000000 --- a/arch/cris/include/asm/ucontext.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_UCONTEXT_H -#define _ASM_CRIS_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* !_ASM_CRIS_UCONTEXT_H */ diff --git a/arch/cris/include/asm/unaligned.h b/arch/cris/include/asm/unaligned.h deleted file mode 100644 index 21772cf600dd..000000000000 --- a/arch/cris/include/asm/unaligned.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_UNALIGNED_H -#define _ASM_CRIS_UNALIGNED_H - -/* - * CRIS can do unaligned accesses itself. - */ -#include -#include - -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le - -#endif /* _ASM_CRIS_UNALIGNED_H */ diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h deleted file mode 100644 index 6a92c0505156..000000000000 --- a/arch/cris/include/asm/unistd.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_UNISTD_H_ -#define _ASM_CRIS_UNISTD_H_ - -#include - - -#define NR_syscalls 365 - -#include - -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_OLD_STAT -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_IPC -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SIGNAL -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_WAITPID -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLD_MMAP -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_FORK -#define __ARCH_WANT_SYS_VFORK -#define __ARCH_WANT_SYS_CLONE - -#endif /* _ASM_CRIS_UNISTD_H_ */ diff --git a/arch/cris/include/asm/user.h b/arch/cris/include/asm/user.h deleted file mode 100644 index a19c39547248..000000000000 --- a/arch/cris/include/asm/user.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_CRIS_USER_H -#define __ASM_CRIS_USER_H - -#include -#include -#include -#include - -/* - * Core file format: The core file is written in such a way that gdb - * can understand it and provide useful information to the user (under - * linux we use the `trad-core' bfd). The file contents are as follows: - * - * upage: 1 page consisting of a user struct that tells gdb - * what is present in the file. Directly after this is a - * copy of the task_struct, which is currently not used by gdb, - * but it may come in handy at some point. All of the registers - * are stored as part of the upage. The upage should always be - * only one page long. - * data: The data segment follows next. We use current->end_text to - * current->brk to pick up all of the user variables, plus any memory - * that may have been sbrk'ed. No attempt is made to determine if a - * page is demand-zero or if a page is totally unused, we just cover - * the entire range. All of the addresses are rounded in such a way - * that an integral number of pages is written. - * stack: We need the stack information in order to get a meaningful - * backtrace. We need to write the data from usp to - * current->start_stack, so we round each of these in order to be able - * to write an integer number of pages. - */ - -struct user { - struct user_regs_struct regs; /* entire machine state */ - size_t u_tsize; /* text size (pages) */ - size_t u_dsize; /* data size (pages) */ - size_t u_ssize; /* stack size (pages) */ - unsigned long start_code; /* text starting address */ - unsigned long start_data; /* data starting address */ - unsigned long start_stack; /* stack starting address */ - long int signal; /* signal causing core dump */ - unsigned long u_ar0; /* help gdb find registers */ - unsigned long magic; /* identifies a core file */ - char u_comm[32]; /* user command name */ -}; - -#define NBPG PAGE_SIZE -#define UPAGES 1 -#define HOST_TEXT_START_ADDR (u.start_code) -#define HOST_DATA_START_ADDR (u.start_data) -#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) - -#endif /* __ASM_CRIS_USER_H */ diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh b/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh deleted file mode 100644 index 6ac3a7bc9760..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh +++ /dev/null @@ -1,7306 +0,0 @@ -/* -!* This file was automatically generated by /n/asic/bin/reg_macro_gen -!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. -!* Editing within this file is thus not recommended, -!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. -!*/ - - -/* -!* Bus interface configuration registers -!*/ - -#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_zw__WIDTH 2 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_ew__WIDTH 2 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__sram_lw__WIDTH 4 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_zw__WIDTH 2 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_ew__WIDTH 2 -#define R_WAITSTATES__flash_lw__BITNR 0 -#define R_WAITSTATES__flash_lw__WIDTH 4 - -#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__sram_type__WIDTH 1 -#define R_BUS_CONFIG__sram_type__cwe 1 -#define R_BUS_CONFIG__sram_type__bwe 0 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__dma_burst__WIDTH 1 -#define R_BUS_CONFIG__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__sram_wr__WIDTH 1 -#define R_BUS_CONFIG__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__flash_wr__WIDTH 1 -#define R_BUS_CONFIG__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__sram_bw__WIDTH 1 -#define R_BUS_CONFIG__sram_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__BITNR 0 -#define R_BUS_CONFIG__flash_bw__WIDTH 1 -#define R_BUS_CONFIG__flash_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__bw16 0 - -#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 -#define R_BUS_STATUS__pll_lock_tm__expired 0 -#define R_BUS_STATUS__pll_lock_tm__counting 1 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__both_faults__WIDTH 1 -#define R_BUS_STATUS__both_faults__no 0 -#define R_BUS_STATUS__both_faults__yes 1 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__bsen___WIDTH 1 -#define R_BUS_STATUS__bsen___enable 0 -#define R_BUS_STATUS__bsen___disable 1 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__boot__WIDTH 2 -#define R_BUS_STATUS__boot__uncached 0 -#define R_BUS_STATUS__boot__serial 1 -#define R_BUS_STATUS__boot__network 2 -#define R_BUS_STATUS__boot__parallel 3 -#define R_BUS_STATUS__flashw__BITNR 0 -#define R_BUS_STATUS__flashw__WIDTH 1 -#define R_BUS_STATUS__flashw__bw32 1 -#define R_BUS_STATUS__flashw__bw16 0 - -#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__sdram__WIDTH 1 -#define R_DRAM_TIMING__sdram__enable 1 -#define R_DRAM_TIMING__sdram__disable 0 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__ref__WIDTH 2 -#define R_DRAM_TIMING__ref__e52us 0 -#define R_DRAM_TIMING__ref__e13us 1 -#define R_DRAM_TIMING__ref__e8700ns 2 -#define R_DRAM_TIMING__ref__disable 3 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rp__WIDTH 2 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rs__WIDTH 2 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__rh__WIDTH 2 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__w__WIDTH 1 -#define R_DRAM_TIMING__w__norm 0 -#define R_DRAM_TIMING__w__ext 1 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__c__WIDTH 1 -#define R_DRAM_TIMING__c__norm 0 -#define R_DRAM_TIMING__c__ext 1 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cz__WIDTH 2 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cp__WIDTH 2 -#define R_DRAM_TIMING__cw__BITNR 0 -#define R_DRAM_TIMING__cw__WIDTH 2 - -#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__sdram__WIDTH 1 -#define R_SDRAM_TIMING__sdram__enable 1 -#define R_SDRAM_TIMING__sdram__disable 0 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__mrs_data__WIDTH 15 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ref__WIDTH 2 -#define R_SDRAM_TIMING__ref__e52us 0 -#define R_SDRAM_TIMING__ref__e13us 1 -#define R_SDRAM_TIMING__ref__e6500ns 2 -#define R_SDRAM_TIMING__ref__disable 3 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__ddr__WIDTH 1 -#define R_SDRAM_TIMING__ddr__on 1 -#define R_SDRAM_TIMING__ddr__off 0 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__clk100__WIDTH 1 -#define R_SDRAM_TIMING__clk100__on 1 -#define R_SDRAM_TIMING__clk100__off 0 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__ps__WIDTH 1 -#define R_SDRAM_TIMING__ps__on 1 -#define R_SDRAM_TIMING__ps__off 0 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__cmd__WIDTH 2 -#define R_SDRAM_TIMING__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__ref 2 -#define R_SDRAM_TIMING__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__nop 0 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__pde__WIDTH 1 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rc__WIDTH 2 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rp__WIDTH 2 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__rcd__WIDTH 2 -#define R_SDRAM_TIMING__cl__BITNR 0 -#define R_SDRAM_TIMING__cl__WIDTH 2 - -#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm1__WIDTH 1 -#define R_DRAM_CONFIG__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__wmm0__WIDTH 1 -#define R_DRAM_CONFIG__wmm0__wmm 1 -#define R_DRAM_CONFIG__wmm0__norm 0 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh1__WIDTH 3 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__sh0__WIDTH 3 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__w__WIDTH 1 -#define R_DRAM_CONFIG__w__bw16 0 -#define R_DRAM_CONFIG__w__bw32 1 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__c__WIDTH 1 -#define R_DRAM_CONFIG__c__byte 0 -#define R_DRAM_CONFIG__c__bank 1 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__e__WIDTH 1 -#define R_DRAM_CONFIG__e__fast 0 -#define R_DRAM_CONFIG__e__edo 1 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__group_sel__WIDTH 5 -#define R_DRAM_CONFIG__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__grp1 1 -#define R_DRAM_CONFIG__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__bit29 29 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__ca1__WIDTH 3 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__bank23sel__WIDTH 5 -#define R_DRAM_CONFIG__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bit29 29 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__ca0__WIDTH 3 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 -#define R_DRAM_CONFIG__bank01sel__WIDTH 5 -#define R_DRAM_CONFIG__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bit29 29 - -#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm1__WIDTH 1 -#define R_SDRAM_CONFIG__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__wmm0__WIDTH 1 -#define R_SDRAM_CONFIG__wmm0__wmm 1 -#define R_SDRAM_CONFIG__wmm0__norm 0 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh1__WIDTH 3 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__sh0__WIDTH 3 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__w__WIDTH 1 -#define R_SDRAM_CONFIG__w__bw16 0 -#define R_SDRAM_CONFIG__w__bw32 1 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type1__WIDTH 1 -#define R_SDRAM_CONFIG__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__type0__WIDTH 1 -#define R_SDRAM_CONFIG__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__group_sel__WIDTH 5 -#define R_SDRAM_CONFIG__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__grp1 1 -#define R_SDRAM_CONFIG__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__bit29 29 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__ca1__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__ca0__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 -#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel0__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bit29 29 - -/* -!* External DMA registers -!*/ - -#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_0_CMD__cnt__enable 1 -#define R_EXT_DMA_0_CMD__cnt__disable 0 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__apol__WIDTH 1 -#define R_EXT_DMA_0_CMD__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_0_CMD__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__wid__WIDTH 2 -#define R_EXT_DMA_0_CMD__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__word 1 -#define R_EXT_DMA_0_CMD__wid__dword 2 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__dir__WIDTH 1 -#define R_EXT_DMA_0_CMD__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__output 1 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__run__WIDTH 1 -#define R_EXT_DMA_0_CMD__run__start 1 -#define R_EXT_DMA_0_CMD__run__stop 0 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__run__WIDTH 1 -#define R_EXT_DMA_0_STAT__run__start 1 -#define R_EXT_DMA_0_STAT__run__stop 0 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 - -#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_1_CMD__cnt__enable 1 -#define R_EXT_DMA_1_CMD__cnt__disable 0 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__apol__WIDTH 1 -#define R_EXT_DMA_1_CMD__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_1_CMD__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__wid__WIDTH 2 -#define R_EXT_DMA_1_CMD__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__word 1 -#define R_EXT_DMA_1_CMD__wid__dword 2 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__dir__WIDTH 1 -#define R_EXT_DMA_1_CMD__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__output 1 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__run__WIDTH 1 -#define R_EXT_DMA_1_CMD__run__start 1 -#define R_EXT_DMA_1_CMD__run__stop 0 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__run__WIDTH 1 -#define R_EXT_DMA_1_STAT__run__start 1 -#define R_EXT_DMA_1_STAT__run__stop 0 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 - -/* -!* Timer registers -!*/ - -#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv1__WIDTH 8 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__timerdiv0__WIDTH 8 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__presc_timer1__WIDTH 1 -#define R_TIMER_CTRL__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__i1__WIDTH 1 -#define R_TIMER_CTRL__i1__clr 1 -#define R_TIMER_CTRL__i1__nop 0 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__tm1__WIDTH 2 -#define R_TIMER_CTRL__tm1__stop_ld 0 -#define R_TIMER_CTRL__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__run 2 -#define R_TIMER_CTRL__tm1__reserved 3 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__clksel1__WIDTH 4 -#define R_TIMER_CTRL__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__presc_ext__WIDTH 1 -#define R_TIMER_CTRL__presc_ext__prescale 0 -#define R_TIMER_CTRL__presc_ext__external 1 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__i0__WIDTH 1 -#define R_TIMER_CTRL__i0__clr 1 -#define R_TIMER_CTRL__i0__nop 0 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__tm0__WIDTH 2 -#define R_TIMER_CTRL__tm0__stop_ld 0 -#define R_TIMER_CTRL__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__run 2 -#define R_TIMER_CTRL__tm0__reserved 3 -#define R_TIMER_CTRL__clksel0__BITNR 0 -#define R_TIMER_CTRL__clksel0__WIDTH 4 -#define R_TIMER_CTRL__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__flexible 15 - -#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer1__WIDTH 8 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__timer0__WIDTH 8 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_high__WIDTH 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 -#define R_TIMER_DATA__clkdiv_low__WIDTH 8 - -#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) -#define R_TIMER01_DATA__count__BITNR 0 -#define R_TIMER01_DATA__count__WIDTH 16 - -#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) -#define R_TIMER0_DATA__count__BITNR 0 -#define R_TIMER0_DATA__count__WIDTH 8 - -#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) -#define R_TIMER1_DATA__count__BITNR 0 -#define R_TIMER1_DATA__count__WIDTH 8 - -#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__key__WIDTH 3 -#define R_WATCHDOG__enable__BITNR 0 -#define R_WATCHDOG__enable__WIDTH 1 -#define R_WATCHDOG__enable__stop 0 -#define R_WATCHDOG__enable__start 1 - -#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 -#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 - -#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 -#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 - -#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 -#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 - -#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__ser_status__WIDTH 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 -#define R_PRESCALE_STATUS__tim_status__WIDTH 16 - -#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 -#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 - -#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 -#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 - -#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 - -/* -!* Shared RAM interface registers -!*/ - -#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__width__WIDTH 1 -#define R_SHARED_RAM_CONFIG__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 -#define R_SHARED_RAM_CONFIG__enable__yes 1 -#define R_SHARED_RAM_CONFIG__enable__no 0 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 -#define R_SHARED_RAM_CONFIG__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 -#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 -#define R_SHARED_RAM_CONFIG__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__nop 0 - -#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 -#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 - -/* -!* General config registers -!*/ - -#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__par_w__WIDTH 1 -#define R_GEN_CONFIG__par_w__select 1 -#define R_GEN_CONFIG__par_w__disable 0 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb2__WIDTH 1 -#define R_GEN_CONFIG__usb2__select 1 -#define R_GEN_CONFIG__usb2__disable 0 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__usb1__WIDTH 1 -#define R_GEN_CONFIG__usb1__select 1 -#define R_GEN_CONFIG__usb1__disable 0 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g24dir__WIDTH 1 -#define R_GEN_CONFIG__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_23dir__WIDTH 1 -#define R_GEN_CONFIG__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__out 1 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g8_15dir__WIDTH 1 -#define R_GEN_CONFIG__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__g0dir__WIDTH 1 -#define R_GEN_CONFIG__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__out 1 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma9__WIDTH 1 -#define R_GEN_CONFIG__dma9__usb 0 -#define R_GEN_CONFIG__dma9__serial1 1 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma8__WIDTH 1 -#define R_GEN_CONFIG__dma8__usb 0 -#define R_GEN_CONFIG__dma8__serial1 1 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma7__WIDTH 2 -#define R_GEN_CONFIG__dma7__unused 0 -#define R_GEN_CONFIG__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__intdma6 3 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma6__WIDTH 2 -#define R_GEN_CONFIG__dma6__unused 0 -#define R_GEN_CONFIG__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__intdma7 3 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma5__WIDTH 2 -#define R_GEN_CONFIG__dma5__par1 0 -#define R_GEN_CONFIG__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__serial3 2 -#define R_GEN_CONFIG__dma5__extdma0 3 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma4__WIDTH 2 -#define R_GEN_CONFIG__dma4__par1 0 -#define R_GEN_CONFIG__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__serial3 2 -#define R_GEN_CONFIG__dma4__extdma0 3 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma3__WIDTH 2 -#define R_GEN_CONFIG__dma3__par0 0 -#define R_GEN_CONFIG__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__serial2 2 -#define R_GEN_CONFIG__dma3__ata 3 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__dma2__WIDTH 2 -#define R_GEN_CONFIG__dma2__par0 0 -#define R_GEN_CONFIG__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__serial2 2 -#define R_GEN_CONFIG__dma2__ata 3 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__mio_w__WIDTH 1 -#define R_GEN_CONFIG__mio_w__select 1 -#define R_GEN_CONFIG__mio_w__disable 0 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__ser3__WIDTH 1 -#define R_GEN_CONFIG__ser3__select 1 -#define R_GEN_CONFIG__ser3__disable 0 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__par1__WIDTH 1 -#define R_GEN_CONFIG__par1__select 1 -#define R_GEN_CONFIG__par1__disable 0 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi0w__WIDTH 1 -#define R_GEN_CONFIG__scsi0w__select 1 -#define R_GEN_CONFIG__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__scsi1__WIDTH 1 -#define R_GEN_CONFIG__scsi1__select 1 -#define R_GEN_CONFIG__scsi1__disable 0 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__mio__WIDTH 1 -#define R_GEN_CONFIG__mio__select 1 -#define R_GEN_CONFIG__mio__disable 0 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__ser2__WIDTH 1 -#define R_GEN_CONFIG__ser2__select 1 -#define R_GEN_CONFIG__ser2__disable 0 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__par0__WIDTH 1 -#define R_GEN_CONFIG__par0__select 1 -#define R_GEN_CONFIG__par0__disable 0 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__ata__WIDTH 1 -#define R_GEN_CONFIG__ata__select 1 -#define R_GEN_CONFIG__ata__disable 0 -#define R_GEN_CONFIG__scsi0__BITNR 0 -#define R_GEN_CONFIG__scsi0__WIDTH 1 -#define R_GEN_CONFIG__scsi0__select 1 -#define R_GEN_CONFIG__scsi0__disable 0 - -#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode3__WIDTH 1 -#define R_GEN_CONFIG_II__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__sermode1__WIDTH 1 -#define R_GEN_CONFIG_II__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 -#define R_GEN_CONFIG_II__ext_clk__select 1 -#define R_GEN_CONFIG_II__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ser2__BITNR 1 -#define R_GEN_CONFIG_II__ser2__WIDTH 1 -#define R_GEN_CONFIG_II__ser2__select 1 -#define R_GEN_CONFIG_II__ser2__disable 0 -#define R_GEN_CONFIG_II__ser3__BITNR 0 -#define R_GEN_CONFIG_II__ser3__WIDTH 1 -#define R_GEN_CONFIG_II__ser3__select 1 -#define R_GEN_CONFIG_II__ser3__disable 0 - -#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__data__BITNR 0 -#define R_PORT_G_DATA__data__WIDTH 32 - -/* -!* General port configuration registers -!*/ - -#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir7__WIDTH 1 -#define R_PORT_PA_SET__dir7__input 0 -#define R_PORT_PA_SET__dir7__output 1 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir6__WIDTH 1 -#define R_PORT_PA_SET__dir6__input 0 -#define R_PORT_PA_SET__dir6__output 1 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir5__WIDTH 1 -#define R_PORT_PA_SET__dir5__input 0 -#define R_PORT_PA_SET__dir5__output 1 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir4__WIDTH 1 -#define R_PORT_PA_SET__dir4__input 0 -#define R_PORT_PA_SET__dir4__output 1 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir3__WIDTH 1 -#define R_PORT_PA_SET__dir3__input 0 -#define R_PORT_PA_SET__dir3__output 1 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir2__WIDTH 1 -#define R_PORT_PA_SET__dir2__input 0 -#define R_PORT_PA_SET__dir2__output 1 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir1__WIDTH 1 -#define R_PORT_PA_SET__dir1__input 0 -#define R_PORT_PA_SET__dir1__output 1 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__dir0__WIDTH 1 -#define R_PORT_PA_SET__dir0__input 0 -#define R_PORT_PA_SET__dir0__output 1 -#define R_PORT_PA_SET__data_out__BITNR 0 -#define R_PORT_PA_SET__data_out__WIDTH 8 - -#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) -#define R_PORT_PA_DATA__data_out__BITNR 0 -#define R_PORT_PA_DATA__data_out__WIDTH 8 - -#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir7__WIDTH 1 -#define R_PORT_PA_DIR__dir7__input 0 -#define R_PORT_PA_DIR__dir7__output 1 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir6__WIDTH 1 -#define R_PORT_PA_DIR__dir6__input 0 -#define R_PORT_PA_DIR__dir6__output 1 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir5__WIDTH 1 -#define R_PORT_PA_DIR__dir5__input 0 -#define R_PORT_PA_DIR__dir5__output 1 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir4__WIDTH 1 -#define R_PORT_PA_DIR__dir4__input 0 -#define R_PORT_PA_DIR__dir4__output 1 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir3__WIDTH 1 -#define R_PORT_PA_DIR__dir3__input 0 -#define R_PORT_PA_DIR__dir3__output 1 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir2__WIDTH 1 -#define R_PORT_PA_DIR__dir2__input 0 -#define R_PORT_PA_DIR__dir2__output 1 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir1__WIDTH 1 -#define R_PORT_PA_DIR__dir1__input 0 -#define R_PORT_PA_DIR__dir1__output 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 -#define R_PORT_PA_DIR__dir0__WIDTH 1 -#define R_PORT_PA_DIR__dir0__input 0 -#define R_PORT_PA_DIR__dir0__output 1 - -#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) -#define R_PORT_PA_READ__data_in__BITNR 0 -#define R_PORT_PA_READ__data_in__WIDTH 8 - -#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser3__WIDTH 1 -#define R_PORT_PB_SET__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__syncser1__WIDTH 1 -#define R_PORT_PB_SET__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_en__WIDTH 1 -#define R_PORT_PB_SET__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_d__WIDTH 1 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_clk__WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__i2c_oe___WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___enable 0 -#define R_PORT_PB_SET__i2c_oe___disable 1 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs7__WIDTH 1 -#define R_PORT_PB_SET__cs7__port 0 -#define R_PORT_PB_SET__cs7__cs 1 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs6__WIDTH 1 -#define R_PORT_PB_SET__cs6__port 0 -#define R_PORT_PB_SET__cs6__cs 1 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs5__WIDTH 1 -#define R_PORT_PB_SET__cs5__port 0 -#define R_PORT_PB_SET__cs5__cs 1 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs4__WIDTH 1 -#define R_PORT_PB_SET__cs4__port 0 -#define R_PORT_PB_SET__cs4__cs 1 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs3__WIDTH 1 -#define R_PORT_PB_SET__cs3__port 0 -#define R_PORT_PB_SET__cs3__cs 1 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__cs2__WIDTH 1 -#define R_PORT_PB_SET__cs2__port 0 -#define R_PORT_PB_SET__cs2__cs 1 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi1__WIDTH 1 -#define R_PORT_PB_SET__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi1__enph 1 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__scsi0__WIDTH 1 -#define R_PORT_PB_SET__scsi0__port_cs 0 -#define R_PORT_PB_SET__scsi0__enph 1 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir7__WIDTH 1 -#define R_PORT_PB_SET__dir7__input 0 -#define R_PORT_PB_SET__dir7__output 1 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir6__WIDTH 1 -#define R_PORT_PB_SET__dir6__input 0 -#define R_PORT_PB_SET__dir6__output 1 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir5__WIDTH 1 -#define R_PORT_PB_SET__dir5__input 0 -#define R_PORT_PB_SET__dir5__output 1 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir4__WIDTH 1 -#define R_PORT_PB_SET__dir4__input 0 -#define R_PORT_PB_SET__dir4__output 1 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir3__WIDTH 1 -#define R_PORT_PB_SET__dir3__input 0 -#define R_PORT_PB_SET__dir3__output 1 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir2__WIDTH 1 -#define R_PORT_PB_SET__dir2__input 0 -#define R_PORT_PB_SET__dir2__output 1 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir1__WIDTH 1 -#define R_PORT_PB_SET__dir1__input 0 -#define R_PORT_PB_SET__dir1__output 1 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__dir0__WIDTH 1 -#define R_PORT_PB_SET__dir0__input 0 -#define R_PORT_PB_SET__dir0__output 1 -#define R_PORT_PB_SET__data_out__BITNR 0 -#define R_PORT_PB_SET__data_out__WIDTH 8 - -#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) -#define R_PORT_PB_DATA__data_out__BITNR 0 -#define R_PORT_PB_DATA__data_out__WIDTH 8 - -#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir7__WIDTH 1 -#define R_PORT_PB_DIR__dir7__input 0 -#define R_PORT_PB_DIR__dir7__output 1 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir6__WIDTH 1 -#define R_PORT_PB_DIR__dir6__input 0 -#define R_PORT_PB_DIR__dir6__output 1 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir5__WIDTH 1 -#define R_PORT_PB_DIR__dir5__input 0 -#define R_PORT_PB_DIR__dir5__output 1 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir4__WIDTH 1 -#define R_PORT_PB_DIR__dir4__input 0 -#define R_PORT_PB_DIR__dir4__output 1 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir3__WIDTH 1 -#define R_PORT_PB_DIR__dir3__input 0 -#define R_PORT_PB_DIR__dir3__output 1 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir2__WIDTH 1 -#define R_PORT_PB_DIR__dir2__input 0 -#define R_PORT_PB_DIR__dir2__output 1 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir1__WIDTH 1 -#define R_PORT_PB_DIR__dir1__input 0 -#define R_PORT_PB_DIR__dir1__output 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 -#define R_PORT_PB_DIR__dir0__WIDTH 1 -#define R_PORT_PB_DIR__dir0__input 0 -#define R_PORT_PB_DIR__dir0__output 1 - -#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs7__WIDTH 1 -#define R_PORT_PB_CONFIG__cs7__port 0 -#define R_PORT_PB_CONFIG__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs6__WIDTH 1 -#define R_PORT_PB_CONFIG__cs6__port 0 -#define R_PORT_PB_CONFIG__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs5__WIDTH 1 -#define R_PORT_PB_CONFIG__cs5__port 0 -#define R_PORT_PB_CONFIG__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs4__WIDTH 1 -#define R_PORT_PB_CONFIG__cs4__port 0 -#define R_PORT_PB_CONFIG__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs3__WIDTH 1 -#define R_PORT_PB_CONFIG__cs3__port 0 -#define R_PORT_PB_CONFIG__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__cs2__WIDTH 1 -#define R_PORT_PB_CONFIG__cs2__port 0 -#define R_PORT_PB_CONFIG__cs2__cs 1 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 -#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi0__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__enph 1 - -#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser3__WIDTH 1 -#define R_PORT_PB_I2C__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__syncser1__WIDTH 1 -#define R_PORT_PB_I2C__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_en__WIDTH 1 -#define R_PORT_PB_I2C__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_d__WIDTH 1 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 -#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___enable 0 -#define R_PORT_PB_I2C__i2c_oe___disable 1 - -#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) -#define R_PORT_PB_READ__data_in__BITNR 0 -#define R_PORT_PB_READ__data_in__WIDTH 8 - -/* -!* Serial port registers -!*/ - -#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__reserved 15 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__reserved 15 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_CTRL__dma_err__stop 0 -#define R_SERIAL0_CTRL__dma_err__ignore 1 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_CTRL__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__rts___WIDTH 1 -#define R_SERIAL0_CTRL__rts___active 0 -#define R_SERIAL0_CTRL__rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_CTRL__sampling__middle 0 -#define R_SERIAL0_CTRL__sampling__majority 1 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__txd__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__auto_cts__active 1 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__data_out__BITNR 0 -#define R_SERIAL0_CTRL__data_out__WIDTH 8 - -#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__reserved 15 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 -#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__reserved 15 - -#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_REC_CTRL__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL0_REC_CTRL__rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_REC_CTRL__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 -#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__xoff_detect__WIDTH 1 -#define R_SERIAL0_READ__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__cts___WIDTH 1 -#define R_SERIAL0_READ__cts___active 0 -#define R_SERIAL0_READ__cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__tr_ready__WIDTH 1 -#define R_SERIAL0_READ__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__ready 1 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__rxd__WIDTH 1 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__overrun__WIDTH 1 -#define R_SERIAL0_READ__overrun__no 0 -#define R_SERIAL0_READ__overrun__yes 1 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__par_err__WIDTH 1 -#define R_SERIAL0_READ__par_err__no 0 -#define R_SERIAL0_READ__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__framing_err__WIDTH 1 -#define R_SERIAL0_READ__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_avail__WIDTH 1 -#define R_SERIAL0_READ__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__yes 1 -#define R_SERIAL0_READ__data_in__BITNR 0 -#define R_SERIAL0_READ__data_in__WIDTH 8 - -#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__cts___WIDTH 1 -#define R_SERIAL0_STATUS__cts___active 0 -#define R_SERIAL0_STATUS__cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL0_STATUS__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__ready 1 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__rxd__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__overrun__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__par_err__WIDTH 1 -#define R_SERIAL0_STATUS__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__framing_err__WIDTH 1 -#define R_SERIAL0_STATUS__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 -#define R_SERIAL0_STATUS__data_avail__WIDTH 1 -#define R_SERIAL0_STATUS__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__yes 1 - -#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 -#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL0_XOFF__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL0_XOFF__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__enable 1 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 -#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__reserved 15 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_CTRL__dma_err__stop 0 -#define R_SERIAL1_CTRL__dma_err__ignore 1 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__rts___WIDTH 1 -#define R_SERIAL1_CTRL__rts___active 0 -#define R_SERIAL1_CTRL__rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_CTRL__sampling__middle 0 -#define R_SERIAL1_CTRL__sampling__majority 1 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__txd__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__auto_cts__active 1 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__data_out__BITNR 0 -#define R_SERIAL1_CTRL__data_out__WIDTH 8 - -#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__reserved 15 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 -#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__reserved 15 - -#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_REC_CTRL__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL1_REC_CTRL__rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_REC_CTRL__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__xoff_detect__WIDTH 1 -#define R_SERIAL1_READ__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__cts___WIDTH 1 -#define R_SERIAL1_READ__cts___active 0 -#define R_SERIAL1_READ__cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__tr_ready__WIDTH 1 -#define R_SERIAL1_READ__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__ready 1 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__rxd__WIDTH 1 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__overrun__WIDTH 1 -#define R_SERIAL1_READ__overrun__no 0 -#define R_SERIAL1_READ__overrun__yes 1 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__par_err__WIDTH 1 -#define R_SERIAL1_READ__par_err__no 0 -#define R_SERIAL1_READ__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__framing_err__WIDTH 1 -#define R_SERIAL1_READ__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_avail__WIDTH 1 -#define R_SERIAL1_READ__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__yes 1 -#define R_SERIAL1_READ__data_in__BITNR 0 -#define R_SERIAL1_READ__data_in__WIDTH 8 - -#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__cts___WIDTH 1 -#define R_SERIAL1_STATUS__cts___active 0 -#define R_SERIAL1_STATUS__cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL1_STATUS__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__rxd__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__par_err__WIDTH 1 -#define R_SERIAL1_STATUS__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__framing_err__WIDTH 1 -#define R_SERIAL1_STATUS__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 -#define R_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SERIAL1_STATUS__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__yes 1 - -#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL1_XOFF__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL1_XOFF__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__enable 1 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 -#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__reserved 15 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__reserved 15 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_CTRL__dma_err__stop 0 -#define R_SERIAL2_CTRL__dma_err__ignore 1 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_CTRL__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__rts___WIDTH 1 -#define R_SERIAL2_CTRL__rts___active 0 -#define R_SERIAL2_CTRL__rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_CTRL__sampling__middle 0 -#define R_SERIAL2_CTRL__sampling__majority 1 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__txd__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__auto_cts__active 1 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__data_out__BITNR 0 -#define R_SERIAL2_CTRL__data_out__WIDTH 8 - -#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__reserved 15 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 -#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__reserved 15 - -#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_REC_CTRL__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL2_REC_CTRL__rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_REC_CTRL__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 -#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__xoff_detect__WIDTH 1 -#define R_SERIAL2_READ__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__cts___WIDTH 1 -#define R_SERIAL2_READ__cts___active 0 -#define R_SERIAL2_READ__cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__tr_ready__WIDTH 1 -#define R_SERIAL2_READ__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__ready 1 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__rxd__WIDTH 1 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__overrun__WIDTH 1 -#define R_SERIAL2_READ__overrun__no 0 -#define R_SERIAL2_READ__overrun__yes 1 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__par_err__WIDTH 1 -#define R_SERIAL2_READ__par_err__no 0 -#define R_SERIAL2_READ__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__framing_err__WIDTH 1 -#define R_SERIAL2_READ__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_avail__WIDTH 1 -#define R_SERIAL2_READ__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__yes 1 -#define R_SERIAL2_READ__data_in__BITNR 0 -#define R_SERIAL2_READ__data_in__WIDTH 8 - -#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__cts___WIDTH 1 -#define R_SERIAL2_STATUS__cts___active 0 -#define R_SERIAL2_STATUS__cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL2_STATUS__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__ready 1 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__rxd__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__overrun__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__par_err__WIDTH 1 -#define R_SERIAL2_STATUS__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__framing_err__WIDTH 1 -#define R_SERIAL2_STATUS__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 -#define R_SERIAL2_STATUS__data_avail__WIDTH 1 -#define R_SERIAL2_STATUS__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__yes 1 - -#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 -#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL2_XOFF__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL2_XOFF__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__enable 1 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 -#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__reserved 15 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_CTRL__dma_err__stop 0 -#define R_SERIAL3_CTRL__dma_err__ignore 1 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__rts___WIDTH 1 -#define R_SERIAL3_CTRL__rts___active 0 -#define R_SERIAL3_CTRL__rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_CTRL__sampling__middle 0 -#define R_SERIAL3_CTRL__sampling__majority 1 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__txd__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__auto_cts__active 1 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__data_out__BITNR 0 -#define R_SERIAL3_CTRL__data_out__WIDTH 8 - -#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__reserved 15 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 -#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__reserved 15 - -#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_REC_CTRL__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL3_REC_CTRL__rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_REC_CTRL__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__xoff_detect__WIDTH 1 -#define R_SERIAL3_READ__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__cts___WIDTH 1 -#define R_SERIAL3_READ__cts___active 0 -#define R_SERIAL3_READ__cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__tr_ready__WIDTH 1 -#define R_SERIAL3_READ__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__ready 1 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__rxd__WIDTH 1 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__overrun__WIDTH 1 -#define R_SERIAL3_READ__overrun__no 0 -#define R_SERIAL3_READ__overrun__yes 1 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__par_err__WIDTH 1 -#define R_SERIAL3_READ__par_err__no 0 -#define R_SERIAL3_READ__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__framing_err__WIDTH 1 -#define R_SERIAL3_READ__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_avail__WIDTH 1 -#define R_SERIAL3_READ__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__yes 1 -#define R_SERIAL3_READ__data_in__BITNR 0 -#define R_SERIAL3_READ__data_in__WIDTH 8 - -#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__cts___WIDTH 1 -#define R_SERIAL3_STATUS__cts___active 0 -#define R_SERIAL3_STATUS__cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL3_STATUS__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__rxd__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__par_err__WIDTH 1 -#define R_SERIAL3_STATUS__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__framing_err__WIDTH 1 -#define R_SERIAL3_STATUS__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 -#define R_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SERIAL3_STATUS__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__yes 1 - -#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL3_XOFF__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL3_XOFF__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__enable 1 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 -#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 - -#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 - -/* -!* Network interface registers -!*/ - -#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) -#define R_NETWORK_SA_0__ma0_low__BITNR 0 -#define R_NETWORK_SA_0__ma0_low__WIDTH 32 - -#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma1_low__WIDTH 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 -#define R_NETWORK_SA_1__ma0_high__WIDTH 16 - -#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) -#define R_NETWORK_SA_2__ma1_high__BITNR 0 -#define R_NETWORK_SA_2__ma1_high__WIDTH 32 - -#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) -#define R_NETWORK_GA_0__ga_low__BITNR 0 -#define R_NETWORK_GA_0__ga_low__WIDTH 32 - -#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) -#define R_NETWORK_GA_1__ga_high__BITNR 0 -#define R_NETWORK_GA_1__ga_high__WIDTH 32 - -#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 -#define R_NETWORK_REC_CONFIG__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 -#define R_NETWORK_REC_CONFIG__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 -#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 -#define R_NETWORK_REC_CONFIG__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 -#define R_NETWORK_REC_CONFIG__individual__receive 1 -#define R_NETWORK_REC_CONFIG__individual__discard 0 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 -#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma0__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__disable 0 - -#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__vg__on 1 -#define R_NETWORK_GEN_CONFIG__vg__off 0 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 -#define R_NETWORK_GEN_CONFIG__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 -#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__enable__on 1 -#define R_NETWORK_GEN_CONFIG__enable__off 0 - -#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 -#define R_NETWORK_TR_CTRL__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__delay__WIDTH 1 -#define R_NETWORK_TR_CTRL__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 -#define R_NETWORK_TR_CTRL__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__cd__WIDTH 1 -#define R_NETWORK_TR_CTRL__cd__enable 0 -#define R_NETWORK_TR_CTRL__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__retry__WIDTH 1 -#define R_NETWORK_TR_CTRL__retry__enable 0 -#define R_NETWORK_TR_CTRL__retry__disable 1 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__pad__WIDTH 1 -#define R_NETWORK_TR_CTRL__pad__enable 1 -#define R_NETWORK_TR_CTRL__pad__disable 0 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 -#define R_NETWORK_TR_CTRL__crc__WIDTH 1 -#define R_NETWORK_TR_CTRL__crc__enable 0 -#define R_NETWORK_TR_CTRL__crc__disable 1 - -#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__enable 1 -#define R_NETWORK_MGM_CTRL__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 -#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 - -#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxd_pins__WIDTH 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__rxer__WIDTH 1 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__underrun__WIDTH 1 -#define R_NETWORK_STAT__underrun__yes 1 -#define R_NETWORK_STAT__underrun__no 0 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__exc_col__WIDTH 1 -#define R_NETWORK_STAT__exc_col__yes 1 -#define R_NETWORK_STAT__exc_col__no 0 -#define R_NETWORK_STAT__mdio__BITNR 0 -#define R_NETWORK_STAT__mdio__WIDTH 1 - -#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__congestion__WIDTH 8 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__oversize__WIDTH 8 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__alignment_error__WIDTH 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 -#define R_REC_COUNTERS__crc_error__WIDTH 8 - -#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__deferred__WIDTH 8 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__late_col__WIDTH 8 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__multiple_col__WIDTH 8 -#define R_TR_COUNTERS__single_col__BITNR 0 -#define R_TR_COUNTERS__single_col__WIDTH 8 - -#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 -#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 - -/* -!* Parallel printer port registers -!*/ - -#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR0_CTRL_DATA__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__oe__WIDTH 1 -#define R_PAR0_CTRL_DATA__oe__enable 1 -#define R_PAR0_CTRL_DATA__oe__disable 0 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__seli__WIDTH 1 -#define R_PAR0_CTRL_DATA__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR0_CTRL_DATA__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__strb__WIDTH 1 -#define R_PAR0_CTRL_DATA__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__init__WIDTH 1 -#define R_PAR0_CTRL_DATA__init__active 1 -#define R_PAR0_CTRL_DATA__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR0_CTRL_DATA__data__BITNR 0 -#define R_PAR0_CTRL_DATA__data__WIDTH 8 - -#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) -#define R_PAR0_CTRL__ctrl__BITNR 0 -#define R_PAR0_CTRL__ctrl__WIDTH 5 - -#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__mode__WIDTH 3 -#define R_PAR0_STATUS_DATA__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__off 7 -#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__perr__WIDTH 1 -#define R_PAR0_STATUS_DATA__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__ack__WIDTH 1 -#define R_PAR0_STATUS_DATA__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__busy__WIDTH 1 -#define R_PAR0_STATUS_DATA__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__fault__WIDTH 1 -#define R_PAR0_STATUS_DATA__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__sel__WIDTH 1 -#define R_PAR0_STATUS_DATA__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR0_STATUS_DATA__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__dav__WIDTH 1 -#define R_PAR0_STATUS_DATA__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR0_STATUS_DATA__data__BITNR 0 -#define R_PAR0_STATUS_DATA__data__WIDTH 8 - -#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__mode__WIDTH 3 -#define R_PAR0_STATUS__mode__manual 0 -#define R_PAR0_STATUS__mode__centronics 1 -#define R_PAR0_STATUS__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__nibble 3 -#define R_PAR0_STATUS__mode__byte 4 -#define R_PAR0_STATUS__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__off 7 -#define R_PAR0_STATUS__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__epp_rd 0 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__perr__WIDTH 1 -#define R_PAR0_STATUS__perr__active 1 -#define R_PAR0_STATUS__perr__inactive 0 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__ack__WIDTH 1 -#define R_PAR0_STATUS__ack__active 0 -#define R_PAR0_STATUS__ack__inactive 1 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__busy__WIDTH 1 -#define R_PAR0_STATUS__busy__active 1 -#define R_PAR0_STATUS__busy__inactive 0 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__fault__WIDTH 1 -#define R_PAR0_STATUS__fault__active 0 -#define R_PAR0_STATUS__fault__inactive 1 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__sel__WIDTH 1 -#define R_PAR0_STATUS__sel__active 1 -#define R_PAR0_STATUS__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ext_mode__WIDTH 1 -#define R_PAR0_STATUS__ext_mode__enable 1 -#define R_PAR0_STATUS__ext_mode__disable 0 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__ecp_16__WIDTH 1 -#define R_PAR0_STATUS__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS__tr_rdy__ready 1 -#define R_PAR0_STATUS__tr_rdy__busy 0 -#define R_PAR0_STATUS__dav__BITNR 0 -#define R_PAR0_STATUS__dav__WIDTH 1 -#define R_PAR0_STATUS__dav__data 1 -#define R_PAR0_STATUS__dav__nodata 0 - -#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__data__BITNR 0 -#define R_PAR_ECP16_DATA__data__WIDTH 16 - -#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__ioe__WIDTH 1 -#define R_PAR0_CONFIG__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iseli__WIDTH 1 -#define R_PAR0_CONFIG__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__iautofd__WIDTH 1 -#define R_PAR0_CONFIG__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__istrb__WIDTH 1 -#define R_PAR0_CONFIG__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iinit__WIDTH 1 -#define R_PAR0_CONFIG__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iperr__WIDTH 1 -#define R_PAR0_CONFIG__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__iack__WIDTH 1 -#define R_PAR0_CONFIG__iack__inv 1 -#define R_PAR0_CONFIG__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ibusy__WIDTH 1 -#define R_PAR0_CONFIG__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__ifault__WIDTH 1 -#define R_PAR0_CONFIG__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__isel__WIDTH 1 -#define R_PAR0_CONFIG__isel__inv 1 -#define R_PAR0_CONFIG__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__ext_mode__WIDTH 1 -#define R_PAR0_CONFIG__ext_mode__enable 1 -#define R_PAR0_CONFIG__ext_mode__disable 0 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__wide__WIDTH 1 -#define R_PAR0_CONFIG__wide__enable 1 -#define R_PAR0_CONFIG__wide__disable 0 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__dma__WIDTH 1 -#define R_PAR0_CONFIG__dma__enable 1 -#define R_PAR0_CONFIG__dma__disable 0 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_in__WIDTH 1 -#define R_PAR0_CONFIG__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__rle_out__WIDTH 1 -#define R_PAR0_CONFIG__rle_out__enable 1 -#define R_PAR0_CONFIG__rle_out__disable 0 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__enable__WIDTH 1 -#define R_PAR0_CONFIG__enable__on 1 -#define R_PAR0_CONFIG__enable__reset 0 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__force__WIDTH 1 -#define R_PAR0_CONFIG__force__on 1 -#define R_PAR0_CONFIG__force__off 0 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__ign_ack__WIDTH 1 -#define R_PAR0_CONFIG__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__oe_ack__WIDTH 1 -#define R_PAR0_CONFIG__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__mode__BITNR 0 -#define R_PAR0_CONFIG__mode__WIDTH 3 -#define R_PAR0_CONFIG__mode__manual 0 -#define R_PAR0_CONFIG__mode__centronics 1 -#define R_PAR0_CONFIG__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__nibble 3 -#define R_PAR0_CONFIG__mode__byte 4 -#define R_PAR0_CONFIG__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__off 7 -#define R_PAR0_CONFIG__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__epp_rd 0 - -#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__fine_hold__WIDTH 3 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__hold__WIDTH 5 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__fine_strb__WIDTH 3 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__strobe__WIDTH 5 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__fine_setup__WIDTH 3 -#define R_PAR0_DELAY__setup__BITNR 0 -#define R_PAR0_DELAY__setup__WIDTH 5 - -#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR1_CTRL_DATA__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__oe__WIDTH 1 -#define R_PAR1_CTRL_DATA__oe__enable 1 -#define R_PAR1_CTRL_DATA__oe__disable 0 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__seli__WIDTH 1 -#define R_PAR1_CTRL_DATA__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR1_CTRL_DATA__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__strb__WIDTH 1 -#define R_PAR1_CTRL_DATA__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__init__WIDTH 1 -#define R_PAR1_CTRL_DATA__init__active 1 -#define R_PAR1_CTRL_DATA__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR1_CTRL_DATA__data__BITNR 0 -#define R_PAR1_CTRL_DATA__data__WIDTH 8 - -#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) -#define R_PAR1_CTRL__ctrl__BITNR 0 -#define R_PAR1_CTRL__ctrl__WIDTH 5 - -#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__mode__WIDTH 3 -#define R_PAR1_STATUS_DATA__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__off 7 -#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__perr__WIDTH 1 -#define R_PAR1_STATUS_DATA__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__ack__WIDTH 1 -#define R_PAR1_STATUS_DATA__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__busy__WIDTH 1 -#define R_PAR1_STATUS_DATA__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__fault__WIDTH 1 -#define R_PAR1_STATUS_DATA__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__sel__WIDTH 1 -#define R_PAR1_STATUS_DATA__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR1_STATUS_DATA__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__dav__WIDTH 1 -#define R_PAR1_STATUS_DATA__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR1_STATUS_DATA__data__BITNR 0 -#define R_PAR1_STATUS_DATA__data__WIDTH 8 - -#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__mode__WIDTH 3 -#define R_PAR1_STATUS__mode__manual 0 -#define R_PAR1_STATUS__mode__centronics 1 -#define R_PAR1_STATUS__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__nibble 3 -#define R_PAR1_STATUS__mode__byte 4 -#define R_PAR1_STATUS__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__off 7 -#define R_PAR1_STATUS__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__epp_rd 0 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__perr__WIDTH 1 -#define R_PAR1_STATUS__perr__active 1 -#define R_PAR1_STATUS__perr__inactive 0 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__ack__WIDTH 1 -#define R_PAR1_STATUS__ack__active 0 -#define R_PAR1_STATUS__ack__inactive 1 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__busy__WIDTH 1 -#define R_PAR1_STATUS__busy__active 1 -#define R_PAR1_STATUS__busy__inactive 0 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__fault__WIDTH 1 -#define R_PAR1_STATUS__fault__active 0 -#define R_PAR1_STATUS__fault__inactive 1 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__sel__WIDTH 1 -#define R_PAR1_STATUS__sel__active 1 -#define R_PAR1_STATUS__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__ext_mode__WIDTH 1 -#define R_PAR1_STATUS__ext_mode__enable 1 -#define R_PAR1_STATUS__ext_mode__disable 0 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS__tr_rdy__ready 1 -#define R_PAR1_STATUS__tr_rdy__busy 0 -#define R_PAR1_STATUS__dav__BITNR 0 -#define R_PAR1_STATUS__dav__WIDTH 1 -#define R_PAR1_STATUS__dav__data 1 -#define R_PAR1_STATUS__dav__nodata 0 - -#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__ioe__WIDTH 1 -#define R_PAR1_CONFIG__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iseli__WIDTH 1 -#define R_PAR1_CONFIG__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__iautofd__WIDTH 1 -#define R_PAR1_CONFIG__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__istrb__WIDTH 1 -#define R_PAR1_CONFIG__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iinit__WIDTH 1 -#define R_PAR1_CONFIG__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iperr__WIDTH 1 -#define R_PAR1_CONFIG__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__iack__WIDTH 1 -#define R_PAR1_CONFIG__iack__inv 1 -#define R_PAR1_CONFIG__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ibusy__WIDTH 1 -#define R_PAR1_CONFIG__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__ifault__WIDTH 1 -#define R_PAR1_CONFIG__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__isel__WIDTH 1 -#define R_PAR1_CONFIG__isel__inv 1 -#define R_PAR1_CONFIG__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__ext_mode__WIDTH 1 -#define R_PAR1_CONFIG__ext_mode__enable 1 -#define R_PAR1_CONFIG__ext_mode__disable 0 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__dma__WIDTH 1 -#define R_PAR1_CONFIG__dma__enable 1 -#define R_PAR1_CONFIG__dma__disable 0 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_in__WIDTH 1 -#define R_PAR1_CONFIG__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__rle_out__WIDTH 1 -#define R_PAR1_CONFIG__rle_out__enable 1 -#define R_PAR1_CONFIG__rle_out__disable 0 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__enable__WIDTH 1 -#define R_PAR1_CONFIG__enable__on 1 -#define R_PAR1_CONFIG__enable__reset 0 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__force__WIDTH 1 -#define R_PAR1_CONFIG__force__on 1 -#define R_PAR1_CONFIG__force__off 0 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__ign_ack__WIDTH 1 -#define R_PAR1_CONFIG__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__oe_ack__WIDTH 1 -#define R_PAR1_CONFIG__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__mode__BITNR 0 -#define R_PAR1_CONFIG__mode__WIDTH 3 -#define R_PAR1_CONFIG__mode__manual 0 -#define R_PAR1_CONFIG__mode__centronics 1 -#define R_PAR1_CONFIG__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__nibble 3 -#define R_PAR1_CONFIG__mode__byte 4 -#define R_PAR1_CONFIG__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__off 7 -#define R_PAR1_CONFIG__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__epp_rd 0 - -#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__fine_hold__WIDTH 3 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__hold__WIDTH 5 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__fine_strb__WIDTH 3 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__strobe__WIDTH 5 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__fine_setup__WIDTH 3 -#define R_PAR1_DELAY__setup__BITNR 0 -#define R_PAR1_DELAY__setup__WIDTH 5 - -/* -!* ATA interface registers -!*/ - -#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__sel__WIDTH 2 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs1__WIDTH 1 -#define R_ATA_CTRL_DATA__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__cs0__WIDTH 1 -#define R_ATA_CTRL_DATA__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__inactive 0 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__addr__WIDTH 3 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__rw__WIDTH 1 -#define R_ATA_CTRL_DATA__rw__read 1 -#define R_ATA_CTRL_DATA__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 -#define R_ATA_CTRL_DATA__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__handsh__WIDTH 1 -#define R_ATA_CTRL_DATA__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__multi__WIDTH 1 -#define R_ATA_CTRL_DATA__multi__on 1 -#define R_ATA_CTRL_DATA__multi__off 0 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 -#define R_ATA_CTRL_DATA__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__word 0 -#define R_ATA_CTRL_DATA__data__BITNR 0 -#define R_ATA_CTRL_DATA__data__WIDTH 16 - -#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__busy__WIDTH 1 -#define R_ATA_STATUS_DATA__busy__yes 1 -#define R_ATA_STATUS_DATA__busy__no 0 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_ATA_STATUS_DATA__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__dav__WIDTH 1 -#define R_ATA_STATUS_DATA__dav__data 1 -#define R_ATA_STATUS_DATA__dav__nodata 0 -#define R_ATA_STATUS_DATA__data__BITNR 0 -#define R_ATA_STATUS_DATA__data__WIDTH 16 - -#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__enable__WIDTH 1 -#define R_ATA_CONFIG__enable__on 1 -#define R_ATA_CONFIG__enable__off 0 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_strobe__WIDTH 5 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__dma_hold__WIDTH 5 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_setup__WIDTH 5 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_strobe__WIDTH 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 -#define R_ATA_CONFIG__pio_hold__WIDTH 5 - -#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__count__BITNR 0 -#define R_ATA_TRANSFER_CNT__count__WIDTH 17 - -/* -!* SCSI registers -!*/ - -#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__id_type__WIDTH 1 -#define R_SCSI0_CTRL__id_type__software 1 -#define R_SCSI0_CTRL__id_type__hardware 0 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__synch_per__WIDTH 8 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__rst__WIDTH 1 -#define R_SCSI0_CTRL__rst__yes 1 -#define R_SCSI0_CTRL__rst__no 0 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__atn__WIDTH 1 -#define R_SCSI0_CTRL__atn__yes 1 -#define R_SCSI0_CTRL__atn__no 0 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__my_id__WIDTH 4 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__target_id__WIDTH 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__fast_20__WIDTH 1 -#define R_SCSI0_CTRL__fast_20__yes 1 -#define R_SCSI0_CTRL__fast_20__no 0 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__bus_width__WIDTH 1 -#define R_SCSI0_CTRL__bus_width__wide 1 -#define R_SCSI0_CTRL__bus_width__narrow 0 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__synch__WIDTH 1 -#define R_SCSI0_CTRL__synch__synch 1 -#define R_SCSI0_CTRL__synch__asynch 0 -#define R_SCSI0_CTRL__enable__BITNR 0 -#define R_SCSI0_CTRL__enable__WIDTH 1 -#define R_SCSI0_CTRL__enable__on 1 -#define R_SCSI0_CTRL__enable__off 0 - -#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI0_CMD_DATA__parity_in__on 0 -#define R_SCSI0_CMD_DATA__parity_in__off 1 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__skip__WIDTH 1 -#define R_SCSI0_CMD_DATA__skip__on 1 -#define R_SCSI0_CMD_DATA__skip__off 0 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI0_CMD_DATA__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__command__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__resel_stat 5 -#define R_SCSI0_CMD_DATA__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__man_rat 13 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 -#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA__data_out__BITNR 0 -#define R_SCSI0_DATA__data_out__WIDTH 16 - -#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD__command__BITNR 0 -#define R_SCSI0_CMD__command__WIDTH 4 -#define R_SCSI0_CMD__command__full_din_1 0 -#define R_SCSI0_CMD__command__full_dout_1 1 -#define R_SCSI0_CMD__command__full_stat_1 2 -#define R_SCSI0_CMD__command__resel_din 3 -#define R_SCSI0_CMD__command__resel_dout 4 -#define R_SCSI0_CMD__command__resel_stat 5 -#define R_SCSI0_CMD__command__arb_only 6 -#define R_SCSI0_CMD__command__full_din_3 8 -#define R_SCSI0_CMD__command__full_dout_3 9 -#define R_SCSI0_CMD__command__full_stat_3 10 -#define R_SCSI0_CMD__command__man_data_in 11 -#define R_SCSI0_CMD__command__man_data_out 12 -#define R_SCSI0_CMD__command__man_rat 13 - -#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__skip__on 1 -#define R_SCSI0_STATUS_CTRL__skip__off 0 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__tst_resel__WIDTH 1 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__parity_error__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__bus_reset__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__yes 1 -#define R_SCSI0_STATUS__bus_reset__no 0 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel_target__WIDTH 4 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__resel__WIDTH 1 -#define R_SCSI0_STATUS__resel__yes 1 -#define R_SCSI0_STATUS__resel__no 0 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__curr_phase__WIDTH 3 -#define R_SCSI0_STATUS__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__valid_status__WIDTH 1 -#define R_SCSI0_STATUS__valid_status__yes 1 -#define R_SCSI0_STATUS__valid_status__no 0 -#define R_SCSI0_STATUS__seq_status__BITNR 0 -#define R_SCSI0_STATUS__seq_status__WIDTH 5 -#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__data_in__BITNR 0 -#define R_SCSI0_DATA_IN__data_in__WIDTH 16 - -#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__id_type__WIDTH 1 -#define R_SCSI1_CTRL__id_type__software 1 -#define R_SCSI1_CTRL__id_type__hardware 0 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__synch_per__WIDTH 8 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__rst__WIDTH 1 -#define R_SCSI1_CTRL__rst__yes 1 -#define R_SCSI1_CTRL__rst__no 0 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__atn__WIDTH 1 -#define R_SCSI1_CTRL__atn__yes 1 -#define R_SCSI1_CTRL__atn__no 0 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__my_id__WIDTH 4 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__target_id__WIDTH 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__fast_20__WIDTH 1 -#define R_SCSI1_CTRL__fast_20__yes 1 -#define R_SCSI1_CTRL__fast_20__no 0 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__bus_width__WIDTH 1 -#define R_SCSI1_CTRL__bus_width__wide 1 -#define R_SCSI1_CTRL__bus_width__narrow 0 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__synch__WIDTH 1 -#define R_SCSI1_CTRL__synch__synch 1 -#define R_SCSI1_CTRL__synch__asynch 0 -#define R_SCSI1_CTRL__enable__BITNR 0 -#define R_SCSI1_CTRL__enable__WIDTH 1 -#define R_SCSI1_CTRL__enable__on 1 -#define R_SCSI1_CTRL__enable__off 0 - -#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI1_CMD_DATA__parity_in__on 0 -#define R_SCSI1_CMD_DATA__parity_in__off 1 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__skip__WIDTH 1 -#define R_SCSI1_CMD_DATA__skip__on 1 -#define R_SCSI1_CMD_DATA__skip__off 0 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI1_CMD_DATA__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__command__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__resel_stat 5 -#define R_SCSI1_CMD_DATA__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__man_rat 13 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 -#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA__data_out__BITNR 0 -#define R_SCSI1_DATA__data_out__WIDTH 16 - -#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD__command__BITNR 0 -#define R_SCSI1_CMD__command__WIDTH 4 -#define R_SCSI1_CMD__command__full_din_1 0 -#define R_SCSI1_CMD__command__full_dout_1 1 -#define R_SCSI1_CMD__command__full_stat_1 2 -#define R_SCSI1_CMD__command__resel_din 3 -#define R_SCSI1_CMD__command__resel_dout 4 -#define R_SCSI1_CMD__command__resel_stat 5 -#define R_SCSI1_CMD__command__arb_only 6 -#define R_SCSI1_CMD__command__full_din_3 8 -#define R_SCSI1_CMD__command__full_dout_3 9 -#define R_SCSI1_CMD__command__full_stat_3 10 -#define R_SCSI1_CMD__command__man_data_in 11 -#define R_SCSI1_CMD__command__man_data_out 12 -#define R_SCSI1_CMD__command__man_rat 13 - -#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__skip__on 1 -#define R_SCSI1_STATUS_CTRL__skip__off 0 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__tst_resel__WIDTH 1 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__parity_error__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__bus_reset__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__yes 1 -#define R_SCSI1_STATUS__bus_reset__no 0 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel_target__WIDTH 4 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__resel__WIDTH 1 -#define R_SCSI1_STATUS__resel__yes 1 -#define R_SCSI1_STATUS__resel__no 0 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__curr_phase__WIDTH 3 -#define R_SCSI1_STATUS__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__valid_status__WIDTH 1 -#define R_SCSI1_STATUS__valid_status__yes 1 -#define R_SCSI1_STATUS__valid_status__no 0 -#define R_SCSI1_STATUS__seq_status__BITNR 0 -#define R_SCSI1_STATUS__seq_status__WIDTH 5 -#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__data_in__BITNR 0 -#define R_SCSI1_DATA_IN__data_in__WIDTH 16 - -/* -!* Interrupt mask and status registers -!*/ - -#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_RD__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_RD__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_RD__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__deferred__WIDTH 1 -#define R_IRQ_MASK0_RD__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__late_col__WIDTH 1 -#define R_IRQ_MASK0_RD__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_RD__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__single_col__WIDTH 1 -#define R_IRQ_MASK0_RD__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__congestion__WIDTH 1 -#define R_IRQ_MASK0_RD__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__oversize__WIDTH 1 -#define R_IRQ_MASK0_RD__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_RD__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 -#define R_IRQ_MASK0_RD__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__overrun__WIDTH 1 -#define R_IRQ_MASK0_RD__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__underrun__WIDTH 1 -#define R_IRQ_MASK0_RD__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_RD__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__mdio__WIDTH 1 -#define R_IRQ_MASK0_RD__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__mio__WIDTH 1 -#define R_IRQ_MASK0_RD__mio__active 1 -#define R_IRQ_MASK0_RD__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 -#define R_IRQ_MASK0_RD__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer1__WIDTH 1 -#define R_IRQ_MASK0_RD__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 -#define R_IRQ_MASK0_RD__timer0__WIDTH 1 -#define R_IRQ_MASK0_RD__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__inactive 0 - -#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 -#define R_IRQ_MASK0_CLR__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 -#define R_IRQ_MASK0_CLR__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 -#define R_IRQ_MASK0_CLR__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 -#define R_IRQ_MASK0_CLR__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 -#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__nop 0 - -#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__nmi_pin__WIDTH 1 -#define R_IRQ_READ0__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 -#define R_IRQ_READ0__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__sqe_test_error__WIDTH 1 -#define R_IRQ_READ0__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__carrier_loss__WIDTH 1 -#define R_IRQ_READ0__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__deferred__WIDTH 1 -#define R_IRQ_READ0__deferred__active 1 -#define R_IRQ_READ0__deferred__inactive 0 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__late_col__WIDTH 1 -#define R_IRQ_READ0__late_col__active 1 -#define R_IRQ_READ0__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__multiple_col__WIDTH 1 -#define R_IRQ_READ0__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__single_col__WIDTH 1 -#define R_IRQ_READ0__single_col__active 1 -#define R_IRQ_READ0__single_col__inactive 0 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__congestion__WIDTH 1 -#define R_IRQ_READ0__congestion__active 1 -#define R_IRQ_READ0__congestion__inactive 0 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__oversize__WIDTH 1 -#define R_IRQ_READ0__oversize__active 1 -#define R_IRQ_READ0__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__alignment_error__WIDTH 1 -#define R_IRQ_READ0__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__crc_error__WIDTH 1 -#define R_IRQ_READ0__crc_error__active 1 -#define R_IRQ_READ0__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__overrun__WIDTH 1 -#define R_IRQ_READ0__overrun__active 1 -#define R_IRQ_READ0__overrun__inactive 0 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__underrun__WIDTH 1 -#define R_IRQ_READ0__underrun__active 1 -#define R_IRQ_READ0__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__excessive_col__WIDTH 1 -#define R_IRQ_READ0__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__mdio__WIDTH 1 -#define R_IRQ_READ0__mdio__active 1 -#define R_IRQ_READ0__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq3__WIDTH 1 -#define R_IRQ_READ0__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq2__WIDTH 1 -#define R_IRQ_READ0__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq1__WIDTH 1 -#define R_IRQ_READ0__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__ata_drq0__WIDTH 1 -#define R_IRQ_READ0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_READ0__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__ata_irq3__WIDTH 1 -#define R_IRQ_READ0__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__par0_peri__WIDTH 1 -#define R_IRQ_READ0__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__ata_irq2__WIDTH 1 -#define R_IRQ_READ0__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__par0_data__WIDTH 1 -#define R_IRQ_READ0__par0_data__active 1 -#define R_IRQ_READ0__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__ata_irq1__WIDTH 1 -#define R_IRQ_READ0__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__par0_ready__WIDTH 1 -#define R_IRQ_READ0__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__ata_irq0__WIDTH 1 -#define R_IRQ_READ0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__mio__WIDTH 1 -#define R_IRQ_READ0__mio__active 1 -#define R_IRQ_READ0__mio__inactive 0 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__scsi0__WIDTH 1 -#define R_IRQ_READ0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__ata_dmaend__WIDTH 1 -#define R_IRQ_READ0__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma1__WIDTH 1 -#define R_IRQ_READ0__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__ext_dma0__WIDTH 1 -#define R_IRQ_READ0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer1__WIDTH 1 -#define R_IRQ_READ0__timer1__active 1 -#define R_IRQ_READ0__timer1__inactive 0 -#define R_IRQ_READ0__timer0__BITNR 0 -#define R_IRQ_READ0__timer0__WIDTH 1 -#define R_IRQ_READ0__timer0__active 1 -#define R_IRQ_READ0__timer0__inactive 0 - -#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_SET__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_SET__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_SET__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__deferred__WIDTH 1 -#define R_IRQ_MASK0_SET__deferred__set 1 -#define R_IRQ_MASK0_SET__deferred__nop 0 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__late_col__WIDTH 1 -#define R_IRQ_MASK0_SET__late_col__set 1 -#define R_IRQ_MASK0_SET__late_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_SET__multiple_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__single_col__WIDTH 1 -#define R_IRQ_MASK0_SET__single_col__set 1 -#define R_IRQ_MASK0_SET__single_col__nop 0 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__congestion__WIDTH 1 -#define R_IRQ_MASK0_SET__congestion__set 1 -#define R_IRQ_MASK0_SET__congestion__nop 0 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__oversize__WIDTH 1 -#define R_IRQ_MASK0_SET__oversize__set 1 -#define R_IRQ_MASK0_SET__oversize__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_SET__alignment_error__set 1 -#define R_IRQ_MASK0_SET__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 -#define R_IRQ_MASK0_SET__crc_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__nop 0 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__overrun__WIDTH 1 -#define R_IRQ_MASK0_SET__overrun__set 1 -#define R_IRQ_MASK0_SET__overrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__underrun__WIDTH 1 -#define R_IRQ_MASK0_SET__underrun__set 1 -#define R_IRQ_MASK0_SET__underrun__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_SET__excessive_col__set 1 -#define R_IRQ_MASK0_SET__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__mdio__WIDTH 1 -#define R_IRQ_MASK0_SET__mdio__set 1 -#define R_IRQ_MASK0_SET__mdio__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_peri__set 1 -#define R_IRQ_MASK0_SET__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_data__set 1 -#define R_IRQ_MASK0_SET__par0_data__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ready__set 1 -#define R_IRQ_MASK0_SET__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__mio__WIDTH 1 -#define R_IRQ_MASK0_SET__mio__set 1 -#define R_IRQ_MASK0_SET__mio__nop 0 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 -#define R_IRQ_MASK0_SET__scsi0__set 1 -#define R_IRQ_MASK0_SET__scsi0__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer1__WIDTH 1 -#define R_IRQ_MASK0_SET__timer1__set 1 -#define R_IRQ_MASK0_SET__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 -#define R_IRQ_MASK0_SET__timer0__WIDTH 1 -#define R_IRQ_MASK0_SET__timer0__set 1 -#define R_IRQ_MASK0_SET__timer0__nop 0 - -#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 -#define R_IRQ_MASK1_RD__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa7__WIDTH 1 -#define R_IRQ_MASK1_RD__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa6__WIDTH 1 -#define R_IRQ_MASK1_RD__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa5__WIDTH 1 -#define R_IRQ_MASK1_RD__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa4__WIDTH 1 -#define R_IRQ_MASK1_RD__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa3__WIDTH 1 -#define R_IRQ_MASK1_RD__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa2__WIDTH 1 -#define R_IRQ_MASK1_RD__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa1__WIDTH 1 -#define R_IRQ_MASK1_RD__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 -#define R_IRQ_MASK1_RD__pa0__WIDTH 1 -#define R_IRQ_MASK1_RD__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__inactive 0 - -#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 -#define R_IRQ_MASK1_CLR__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 -#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__nop 0 - -#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int7__WIDTH 1 -#define R_IRQ_READ1__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int6__WIDTH 1 -#define R_IRQ_READ1__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int5__WIDTH 1 -#define R_IRQ_READ1__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int4__WIDTH 1 -#define R_IRQ_READ1__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int3__WIDTH 1 -#define R_IRQ_READ1__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int2__WIDTH 1 -#define R_IRQ_READ1__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int1__WIDTH 1 -#define R_IRQ_READ1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__sw_int0__WIDTH 1 -#define R_IRQ_READ1__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_READ1__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_peri__WIDTH 1 -#define R_IRQ_READ1__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_data__WIDTH 1 -#define R_IRQ_READ1__par1_data__active 1 -#define R_IRQ_READ1__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__par1_ready__WIDTH 1 -#define R_IRQ_READ1__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__scsi1__WIDTH 1 -#define R_IRQ_READ1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_ready__WIDTH 1 -#define R_IRQ_READ1__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser3_data__WIDTH 1 -#define R_IRQ_READ1__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_ready__WIDTH 1 -#define R_IRQ_READ1__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser2_data__WIDTH 1 -#define R_IRQ_READ1__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_ready__WIDTH 1 -#define R_IRQ_READ1__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser1_data__WIDTH 1 -#define R_IRQ_READ1__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_ready__WIDTH 1 -#define R_IRQ_READ1__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__ser0_data__WIDTH 1 -#define R_IRQ_READ1__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa7__WIDTH 1 -#define R_IRQ_READ1__pa7__active 1 -#define R_IRQ_READ1__pa7__inactive 0 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa6__WIDTH 1 -#define R_IRQ_READ1__pa6__active 1 -#define R_IRQ_READ1__pa6__inactive 0 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa5__WIDTH 1 -#define R_IRQ_READ1__pa5__active 1 -#define R_IRQ_READ1__pa5__inactive 0 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa4__WIDTH 1 -#define R_IRQ_READ1__pa4__active 1 -#define R_IRQ_READ1__pa4__inactive 0 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa3__WIDTH 1 -#define R_IRQ_READ1__pa3__active 1 -#define R_IRQ_READ1__pa3__inactive 0 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa2__WIDTH 1 -#define R_IRQ_READ1__pa2__active 1 -#define R_IRQ_READ1__pa2__inactive 0 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa1__WIDTH 1 -#define R_IRQ_READ1__pa1__active 1 -#define R_IRQ_READ1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__BITNR 0 -#define R_IRQ_READ1__pa0__WIDTH 1 -#define R_IRQ_READ1__pa0__active 1 -#define R_IRQ_READ1__pa0__inactive 0 - -#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int0__set 1 -#define R_IRQ_MASK1_SET__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ready__set 1 -#define R_IRQ_MASK1_SET__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 -#define R_IRQ_MASK1_SET__scsi1__set 1 -#define R_IRQ_MASK1_SET__scsi1__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_data__set 1 -#define R_IRQ_MASK1_SET__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa7__WIDTH 1 -#define R_IRQ_MASK1_SET__pa7__set 1 -#define R_IRQ_MASK1_SET__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa6__WIDTH 1 -#define R_IRQ_MASK1_SET__pa6__set 1 -#define R_IRQ_MASK1_SET__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa5__WIDTH 1 -#define R_IRQ_MASK1_SET__pa5__set 1 -#define R_IRQ_MASK1_SET__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa4__WIDTH 1 -#define R_IRQ_MASK1_SET__pa4__set 1 -#define R_IRQ_MASK1_SET__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa3__WIDTH 1 -#define R_IRQ_MASK1_SET__pa3__set 1 -#define R_IRQ_MASK1_SET__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa2__WIDTH 1 -#define R_IRQ_MASK1_SET__pa2__set 1 -#define R_IRQ_MASK1_SET__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa1__WIDTH 1 -#define R_IRQ_MASK1_SET__pa1__set 1 -#define R_IRQ_MASK1_SET__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 -#define R_IRQ_MASK1_SET__pa0__WIDTH 1 -#define R_IRQ_MASK1_SET__pa0__set 1 -#define R_IRQ_MASK1_SET__pa0__nop 0 - -#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 - -#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_eop__WIDTH 1 -#define R_IRQ_READ2__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma9_descr__WIDTH 1 -#define R_IRQ_READ2__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_eop__WIDTH 1 -#define R_IRQ_READ2__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma8_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_eop__WIDTH 1 -#define R_IRQ_READ2__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma7_descr__WIDTH 1 -#define R_IRQ_READ2__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_eop__WIDTH 1 -#define R_IRQ_READ2__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma6_descr__WIDTH 1 -#define R_IRQ_READ2__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_eop__WIDTH 1 -#define R_IRQ_READ2__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma5_descr__WIDTH 1 -#define R_IRQ_READ2__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_eop__WIDTH 1 -#define R_IRQ_READ2__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma4_descr__WIDTH 1 -#define R_IRQ_READ2__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_eop__WIDTH 1 -#define R_IRQ_READ2__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma3_descr__WIDTH 1 -#define R_IRQ_READ2__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_eop__WIDTH 1 -#define R_IRQ_READ2__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma2_descr__WIDTH 1 -#define R_IRQ_READ2__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_eop__WIDTH 1 -#define R_IRQ_READ2__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma1_descr__WIDTH 1 -#define R_IRQ_READ2__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_eop__WIDTH 1 -#define R_IRQ_READ2__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__BITNR 0 -#define R_IRQ_READ2__dma0_descr__WIDTH 1 -#define R_IRQ_READ2__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__nop 0 - -#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__usb__WIDTH 1 -#define R_VECT_MASK_RD__usb__active 1 -#define R_VECT_MASK_RD__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma9__WIDTH 1 -#define R_VECT_MASK_RD__dma9__active 1 -#define R_VECT_MASK_RD__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma8__WIDTH 1 -#define R_VECT_MASK_RD__dma8__active 1 -#define R_VECT_MASK_RD__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma7__WIDTH 1 -#define R_VECT_MASK_RD__dma7__active 1 -#define R_VECT_MASK_RD__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma6__WIDTH 1 -#define R_VECT_MASK_RD__dma6__active 1 -#define R_VECT_MASK_RD__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma5__WIDTH 1 -#define R_VECT_MASK_RD__dma5__active 1 -#define R_VECT_MASK_RD__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma4__WIDTH 1 -#define R_VECT_MASK_RD__dma4__active 1 -#define R_VECT_MASK_RD__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma3__WIDTH 1 -#define R_VECT_MASK_RD__dma3__active 1 -#define R_VECT_MASK_RD__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma2__WIDTH 1 -#define R_VECT_MASK_RD__dma2__active 1 -#define R_VECT_MASK_RD__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma1__WIDTH 1 -#define R_VECT_MASK_RD__dma1__active 1 -#define R_VECT_MASK_RD__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__dma0__WIDTH 1 -#define R_VECT_MASK_RD__dma0__active 1 -#define R_VECT_MASK_RD__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__pa__WIDTH 1 -#define R_VECT_MASK_RD__pa__active 1 -#define R_VECT_MASK_RD__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 -#define R_VECT_MASK_RD__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__sw__WIDTH 1 -#define R_VECT_MASK_RD__sw__active 1 -#define R_VECT_MASK_RD__sw__inactive 0 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__serial__WIDTH 1 -#define R_VECT_MASK_RD__serial__active 1 -#define R_VECT_MASK_RD__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__snmp__WIDTH 1 -#define R_VECT_MASK_RD__snmp__active 1 -#define R_VECT_MASK_RD__snmp__inactive 0 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__network__WIDTH 1 -#define R_VECT_MASK_RD__network__active 1 -#define R_VECT_MASK_RD__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__scsi1__WIDTH 1 -#define R_VECT_MASK_RD__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__par1__WIDTH 1 -#define R_VECT_MASK_RD__par1__active 1 -#define R_VECT_MASK_RD__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__scsi0__WIDTH 1 -#define R_VECT_MASK_RD__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__par0__WIDTH 1 -#define R_VECT_MASK_RD__par0__active 1 -#define R_VECT_MASK_RD__par0__inactive 0 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__ata__WIDTH 1 -#define R_VECT_MASK_RD__ata__active 1 -#define R_VECT_MASK_RD__ata__inactive 0 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__mio__WIDTH 1 -#define R_VECT_MASK_RD__mio__active 1 -#define R_VECT_MASK_RD__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer1__WIDTH 1 -#define R_VECT_MASK_RD__timer1__active 1 -#define R_VECT_MASK_RD__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__timer0__WIDTH 1 -#define R_VECT_MASK_RD__timer0__active 1 -#define R_VECT_MASK_RD__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__nmi__WIDTH 1 -#define R_VECT_MASK_RD__nmi__active 1 -#define R_VECT_MASK_RD__nmi__inactive 0 -#define R_VECT_MASK_RD__some__BITNR 0 -#define R_VECT_MASK_RD__some__WIDTH 1 -#define R_VECT_MASK_RD__some__active 1 -#define R_VECT_MASK_RD__some__inactive 0 - -#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__usb__WIDTH 1 -#define R_VECT_MASK_CLR__usb__clr 1 -#define R_VECT_MASK_CLR__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma9__WIDTH 1 -#define R_VECT_MASK_CLR__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma8__WIDTH 1 -#define R_VECT_MASK_CLR__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma7__WIDTH 1 -#define R_VECT_MASK_CLR__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma6__WIDTH 1 -#define R_VECT_MASK_CLR__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma5__WIDTH 1 -#define R_VECT_MASK_CLR__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma4__WIDTH 1 -#define R_VECT_MASK_CLR__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma3__WIDTH 1 -#define R_VECT_MASK_CLR__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma2__WIDTH 1 -#define R_VECT_MASK_CLR__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma1__WIDTH 1 -#define R_VECT_MASK_CLR__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__dma0__WIDTH 1 -#define R_VECT_MASK_CLR__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__pa__WIDTH 1 -#define R_VECT_MASK_CLR__pa__clr 1 -#define R_VECT_MASK_CLR__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 -#define R_VECT_MASK_CLR__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__sw__WIDTH 1 -#define R_VECT_MASK_CLR__sw__clr 1 -#define R_VECT_MASK_CLR__sw__nop 0 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__serial__WIDTH 1 -#define R_VECT_MASK_CLR__serial__clr 1 -#define R_VECT_MASK_CLR__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__snmp__WIDTH 1 -#define R_VECT_MASK_CLR__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__nop 0 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__network__WIDTH 1 -#define R_VECT_MASK_CLR__network__clr 1 -#define R_VECT_MASK_CLR__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__scsi1__WIDTH 1 -#define R_VECT_MASK_CLR__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__par1__WIDTH 1 -#define R_VECT_MASK_CLR__par1__clr 1 -#define R_VECT_MASK_CLR__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__scsi0__WIDTH 1 -#define R_VECT_MASK_CLR__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__par0__WIDTH 1 -#define R_VECT_MASK_CLR__par0__clr 1 -#define R_VECT_MASK_CLR__par0__nop 0 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__ata__WIDTH 1 -#define R_VECT_MASK_CLR__ata__clr 1 -#define R_VECT_MASK_CLR__ata__nop 0 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__mio__WIDTH 1 -#define R_VECT_MASK_CLR__mio__clr 1 -#define R_VECT_MASK_CLR__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer1__WIDTH 1 -#define R_VECT_MASK_CLR__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__timer0__WIDTH 1 -#define R_VECT_MASK_CLR__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__nmi__WIDTH 1 -#define R_VECT_MASK_CLR__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nop 0 -#define R_VECT_MASK_CLR__some__BITNR 0 -#define R_VECT_MASK_CLR__some__WIDTH 1 -#define R_VECT_MASK_CLR__some__clr 1 -#define R_VECT_MASK_CLR__some__nop 0 - -#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__usb__WIDTH 1 -#define R_VECT_READ__usb__active 1 -#define R_VECT_READ__usb__inactive 0 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma9__WIDTH 1 -#define R_VECT_READ__dma9__active 1 -#define R_VECT_READ__dma9__inactive 0 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma8__WIDTH 1 -#define R_VECT_READ__dma8__active 1 -#define R_VECT_READ__dma8__inactive 0 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma7__WIDTH 1 -#define R_VECT_READ__dma7__active 1 -#define R_VECT_READ__dma7__inactive 0 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma6__WIDTH 1 -#define R_VECT_READ__dma6__active 1 -#define R_VECT_READ__dma6__inactive 0 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma5__WIDTH 1 -#define R_VECT_READ__dma5__active 1 -#define R_VECT_READ__dma5__inactive 0 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma4__WIDTH 1 -#define R_VECT_READ__dma4__active 1 -#define R_VECT_READ__dma4__inactive 0 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma3__WIDTH 1 -#define R_VECT_READ__dma3__active 1 -#define R_VECT_READ__dma3__inactive 0 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma2__WIDTH 1 -#define R_VECT_READ__dma2__active 1 -#define R_VECT_READ__dma2__inactive 0 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma1__WIDTH 1 -#define R_VECT_READ__dma1__active 1 -#define R_VECT_READ__dma1__inactive 0 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__dma0__WIDTH 1 -#define R_VECT_READ__dma0__active 1 -#define R_VECT_READ__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma1__WIDTH 1 -#define R_VECT_READ__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__ext_dma0__WIDTH 1 -#define R_VECT_READ__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__inactive 0 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__pa__WIDTH 1 -#define R_VECT_READ__pa__active 1 -#define R_VECT_READ__pa__inactive 0 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__irq_intnr__WIDTH 1 -#define R_VECT_READ__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__inactive 0 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__sw__WIDTH 1 -#define R_VECT_READ__sw__active 1 -#define R_VECT_READ__sw__inactive 0 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__serial__WIDTH 1 -#define R_VECT_READ__serial__active 1 -#define R_VECT_READ__serial__inactive 0 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__snmp__WIDTH 1 -#define R_VECT_READ__snmp__active 1 -#define R_VECT_READ__snmp__inactive 0 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__network__WIDTH 1 -#define R_VECT_READ__network__active 1 -#define R_VECT_READ__network__inactive 0 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__scsi1__WIDTH 1 -#define R_VECT_READ__scsi1__active 1 -#define R_VECT_READ__scsi1__inactive 0 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__par1__WIDTH 1 -#define R_VECT_READ__par1__active 1 -#define R_VECT_READ__par1__inactive 0 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__scsi0__WIDTH 1 -#define R_VECT_READ__scsi0__active 1 -#define R_VECT_READ__scsi0__inactive 0 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__par0__WIDTH 1 -#define R_VECT_READ__par0__active 1 -#define R_VECT_READ__par0__inactive 0 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__ata__WIDTH 1 -#define R_VECT_READ__ata__active 1 -#define R_VECT_READ__ata__inactive 0 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__mio__WIDTH 1 -#define R_VECT_READ__mio__active 1 -#define R_VECT_READ__mio__inactive 0 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer1__WIDTH 1 -#define R_VECT_READ__timer1__active 1 -#define R_VECT_READ__timer1__inactive 0 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__timer0__WIDTH 1 -#define R_VECT_READ__timer0__active 1 -#define R_VECT_READ__timer0__inactive 0 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__nmi__WIDTH 1 -#define R_VECT_READ__nmi__active 1 -#define R_VECT_READ__nmi__inactive 0 -#define R_VECT_READ__some__BITNR 0 -#define R_VECT_READ__some__WIDTH 1 -#define R_VECT_READ__some__active 1 -#define R_VECT_READ__some__inactive 0 - -#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__usb__WIDTH 1 -#define R_VECT_MASK_SET__usb__set 1 -#define R_VECT_MASK_SET__usb__nop 0 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma9__WIDTH 1 -#define R_VECT_MASK_SET__dma9__set 1 -#define R_VECT_MASK_SET__dma9__nop 0 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma8__WIDTH 1 -#define R_VECT_MASK_SET__dma8__set 1 -#define R_VECT_MASK_SET__dma8__nop 0 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma7__WIDTH 1 -#define R_VECT_MASK_SET__dma7__set 1 -#define R_VECT_MASK_SET__dma7__nop 0 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma6__WIDTH 1 -#define R_VECT_MASK_SET__dma6__set 1 -#define R_VECT_MASK_SET__dma6__nop 0 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma5__WIDTH 1 -#define R_VECT_MASK_SET__dma5__set 1 -#define R_VECT_MASK_SET__dma5__nop 0 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma4__WIDTH 1 -#define R_VECT_MASK_SET__dma4__set 1 -#define R_VECT_MASK_SET__dma4__nop 0 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma3__WIDTH 1 -#define R_VECT_MASK_SET__dma3__set 1 -#define R_VECT_MASK_SET__dma3__nop 0 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma2__WIDTH 1 -#define R_VECT_MASK_SET__dma2__set 1 -#define R_VECT_MASK_SET__dma2__nop 0 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma1__WIDTH 1 -#define R_VECT_MASK_SET__dma1__set 1 -#define R_VECT_MASK_SET__dma1__nop 0 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__dma0__WIDTH 1 -#define R_VECT_MASK_SET__dma0__set 1 -#define R_VECT_MASK_SET__dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma0__set 1 -#define R_VECT_MASK_SET__ext_dma0__nop 0 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__pa__WIDTH 1 -#define R_VECT_MASK_SET__pa__set 1 -#define R_VECT_MASK_SET__pa__nop 0 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 -#define R_VECT_MASK_SET__irq_intnr__set 1 -#define R_VECT_MASK_SET__irq_intnr__nop 0 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__sw__WIDTH 1 -#define R_VECT_MASK_SET__sw__set 1 -#define R_VECT_MASK_SET__sw__nop 0 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__serial__WIDTH 1 -#define R_VECT_MASK_SET__serial__set 1 -#define R_VECT_MASK_SET__serial__nop 0 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__snmp__WIDTH 1 -#define R_VECT_MASK_SET__snmp__set 1 -#define R_VECT_MASK_SET__snmp__nop 0 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__network__WIDTH 1 -#define R_VECT_MASK_SET__network__set 1 -#define R_VECT_MASK_SET__network__nop 0 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__scsi1__WIDTH 1 -#define R_VECT_MASK_SET__scsi1__set 1 -#define R_VECT_MASK_SET__scsi1__nop 0 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__par1__WIDTH 1 -#define R_VECT_MASK_SET__par1__set 1 -#define R_VECT_MASK_SET__par1__nop 0 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__scsi0__WIDTH 1 -#define R_VECT_MASK_SET__scsi0__set 1 -#define R_VECT_MASK_SET__scsi0__nop 0 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__par0__WIDTH 1 -#define R_VECT_MASK_SET__par0__set 1 -#define R_VECT_MASK_SET__par0__nop 0 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__ata__WIDTH 1 -#define R_VECT_MASK_SET__ata__set 1 -#define R_VECT_MASK_SET__ata__nop 0 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__mio__WIDTH 1 -#define R_VECT_MASK_SET__mio__set 1 -#define R_VECT_MASK_SET__mio__nop 0 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer1__WIDTH 1 -#define R_VECT_MASK_SET__timer1__set 1 -#define R_VECT_MASK_SET__timer1__nop 0 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__timer0__WIDTH 1 -#define R_VECT_MASK_SET__timer0__set 1 -#define R_VECT_MASK_SET__timer0__nop 0 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__nmi__WIDTH 1 -#define R_VECT_MASK_SET__nmi__set 1 -#define R_VECT_MASK_SET__nmi__nop 0 -#define R_VECT_MASK_SET__some__BITNR 0 -#define R_VECT_MASK_SET__some__WIDTH 1 -#define R_VECT_MASK_SET__some__set 1 -#define R_VECT_MASK_SET__some__nop 0 - -/* -!* DMA registers -!*/ - -#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch9_eop__WIDTH 1 -#define R_SET_EOP__ch9_eop__set 1 -#define R_SET_EOP__ch9_eop__nop 0 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch7_eop__WIDTH 1 -#define R_SET_EOP__ch7_eop__set 1 -#define R_SET_EOP__ch7_eop__nop 0 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch5_eop__WIDTH 1 -#define R_SET_EOP__ch5_eop__set 1 -#define R_SET_EOP__ch5_eop__nop 0 -#define R_SET_EOP__ch3_eop__BITNR 0 -#define R_SET_EOP__ch3_eop__WIDTH 1 -#define R_SET_EOP__ch3_eop__set 1 -#define R_SET_EOP__ch3_eop__nop 0 - -#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__hw__WIDTH 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 -#define R_DMA_CH0_HWSW__sw__WIDTH 16 - -#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__descr__BITNR 0 -#define R_DMA_CH0_DESCR__descr__WIDTH 32 - -#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__next__BITNR 0 -#define R_DMA_CH0_NEXT__next__WIDTH 32 - -#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__buf__BITNR 0 -#define R_DMA_CH0_BUF__buf__WIDTH 32 - -#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__first__BITNR 0 -#define R_DMA_CH0_FIRST__first__WIDTH 32 - -#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__cmd__BITNR 0 -#define R_DMA_CH0_CMD__cmd__WIDTH 3 -#define R_DMA_CH0_CMD__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__start 1 -#define R_DMA_CH0_CMD__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__reset 4 - -#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__avail__BITNR 0 -#define R_DMA_CH0_STATUS__avail__WIDTH 7 - -#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__hw__WIDTH 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 -#define R_DMA_CH1_HWSW__sw__WIDTH 16 - -#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__descr__BITNR 0 -#define R_DMA_CH1_DESCR__descr__WIDTH 32 - -#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__next__BITNR 0 -#define R_DMA_CH1_NEXT__next__WIDTH 32 - -#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__buf__BITNR 0 -#define R_DMA_CH1_BUF__buf__WIDTH 32 - -#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__first__BITNR 0 -#define R_DMA_CH1_FIRST__first__WIDTH 32 - -#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__cmd__BITNR 0 -#define R_DMA_CH1_CMD__cmd__WIDTH 3 -#define R_DMA_CH1_CMD__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__start 1 -#define R_DMA_CH1_CMD__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__reset 4 - -#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__avail__BITNR 0 -#define R_DMA_CH1_STATUS__avail__WIDTH 7 - -#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__hw__WIDTH 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 -#define R_DMA_CH2_HWSW__sw__WIDTH 16 - -#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__descr__BITNR 0 -#define R_DMA_CH2_DESCR__descr__WIDTH 32 - -#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__next__BITNR 0 -#define R_DMA_CH2_NEXT__next__WIDTH 32 - -#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__buf__BITNR 0 -#define R_DMA_CH2_BUF__buf__WIDTH 32 - -#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__first__BITNR 0 -#define R_DMA_CH2_FIRST__first__WIDTH 32 - -#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__cmd__BITNR 0 -#define R_DMA_CH2_CMD__cmd__WIDTH 3 -#define R_DMA_CH2_CMD__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__start 1 -#define R_DMA_CH2_CMD__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__reset 4 - -#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__avail__BITNR 0 -#define R_DMA_CH2_STATUS__avail__WIDTH 7 - -#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__hw__WIDTH 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 -#define R_DMA_CH3_HWSW__sw__WIDTH 16 - -#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__descr__BITNR 0 -#define R_DMA_CH3_DESCR__descr__WIDTH 32 - -#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__next__BITNR 0 -#define R_DMA_CH3_NEXT__next__WIDTH 32 - -#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__buf__BITNR 0 -#define R_DMA_CH3_BUF__buf__WIDTH 32 - -#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__first__BITNR 0 -#define R_DMA_CH3_FIRST__first__WIDTH 32 - -#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__cmd__BITNR 0 -#define R_DMA_CH3_CMD__cmd__WIDTH 3 -#define R_DMA_CH3_CMD__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__start 1 -#define R_DMA_CH3_CMD__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__reset 4 - -#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__avail__BITNR 0 -#define R_DMA_CH3_STATUS__avail__WIDTH 7 - -#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__hw__WIDTH 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 -#define R_DMA_CH4_HWSW__sw__WIDTH 16 - -#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__descr__BITNR 0 -#define R_DMA_CH4_DESCR__descr__WIDTH 32 - -#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__next__BITNR 0 -#define R_DMA_CH4_NEXT__next__WIDTH 32 - -#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__buf__BITNR 0 -#define R_DMA_CH4_BUF__buf__WIDTH 32 - -#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__first__BITNR 0 -#define R_DMA_CH4_FIRST__first__WIDTH 32 - -#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__cmd__BITNR 0 -#define R_DMA_CH4_CMD__cmd__WIDTH 3 -#define R_DMA_CH4_CMD__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__start 1 -#define R_DMA_CH4_CMD__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__reset 4 - -#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__avail__BITNR 0 -#define R_DMA_CH4_STATUS__avail__WIDTH 7 - -#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__hw__WIDTH 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 -#define R_DMA_CH5_HWSW__sw__WIDTH 16 - -#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__descr__BITNR 0 -#define R_DMA_CH5_DESCR__descr__WIDTH 32 - -#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__next__BITNR 0 -#define R_DMA_CH5_NEXT__next__WIDTH 32 - -#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__buf__BITNR 0 -#define R_DMA_CH5_BUF__buf__WIDTH 32 - -#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__first__BITNR 0 -#define R_DMA_CH5_FIRST__first__WIDTH 32 - -#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__cmd__BITNR 0 -#define R_DMA_CH5_CMD__cmd__WIDTH 3 -#define R_DMA_CH5_CMD__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__start 1 -#define R_DMA_CH5_CMD__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__reset 4 - -#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__avail__BITNR 0 -#define R_DMA_CH5_STATUS__avail__WIDTH 7 - -#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__hw__WIDTH 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 -#define R_DMA_CH6_HWSW__sw__WIDTH 16 - -#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__descr__BITNR 0 -#define R_DMA_CH6_DESCR__descr__WIDTH 32 - -#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__next__BITNR 0 -#define R_DMA_CH6_NEXT__next__WIDTH 32 - -#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__buf__BITNR 0 -#define R_DMA_CH6_BUF__buf__WIDTH 32 - -#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__first__BITNR 0 -#define R_DMA_CH6_FIRST__first__WIDTH 32 - -#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__cmd__BITNR 0 -#define R_DMA_CH6_CMD__cmd__WIDTH 3 -#define R_DMA_CH6_CMD__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__start 1 -#define R_DMA_CH6_CMD__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__reset 4 - -#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__avail__BITNR 0 -#define R_DMA_CH6_STATUS__avail__WIDTH 7 - -#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__hw__WIDTH 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 -#define R_DMA_CH7_HWSW__sw__WIDTH 16 - -#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__descr__BITNR 0 -#define R_DMA_CH7_DESCR__descr__WIDTH 32 - -#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__next__BITNR 0 -#define R_DMA_CH7_NEXT__next__WIDTH 32 - -#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__buf__BITNR 0 -#define R_DMA_CH7_BUF__buf__WIDTH 32 - -#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__first__BITNR 0 -#define R_DMA_CH7_FIRST__first__WIDTH 32 - -#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__cmd__BITNR 0 -#define R_DMA_CH7_CMD__cmd__WIDTH 3 -#define R_DMA_CH7_CMD__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__start 1 -#define R_DMA_CH7_CMD__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__reset 4 - -#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__avail__BITNR 0 -#define R_DMA_CH7_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__hw__WIDTH 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 -#define R_DMA_CH8_HWSW__sw__WIDTH 16 - -#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__descr__BITNR 0 -#define R_DMA_CH8_DESCR__descr__WIDTH 32 - -#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__next__BITNR 0 -#define R_DMA_CH8_NEXT__next__WIDTH 32 - -#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__buf__BITNR 0 -#define R_DMA_CH8_BUF__buf__WIDTH 32 - -#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__first__BITNR 0 -#define R_DMA_CH8_FIRST__first__WIDTH 32 - -#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__cmd__BITNR 0 -#define R_DMA_CH8_CMD__cmd__WIDTH 3 -#define R_DMA_CH8_CMD__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__start 1 -#define R_DMA_CH8_CMD__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__reset 4 - -#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__avail__BITNR 0 -#define R_DMA_CH8_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__sub__BITNR 0 -#define R_DMA_CH8_SUB__sub__WIDTH 32 - -#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__nep__BITNR 0 -#define R_DMA_CH8_NEP__nep__WIDTH 32 - -#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB0_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB1_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB2_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB3_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__hw__WIDTH 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 -#define R_DMA_CH9_HWSW__sw__WIDTH 16 - -#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__descr__BITNR 0 -#define R_DMA_CH9_DESCR__descr__WIDTH 32 - -#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__next__BITNR 0 -#define R_DMA_CH9_NEXT__next__WIDTH 32 - -#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__buf__BITNR 0 -#define R_DMA_CH9_BUF__buf__WIDTH 32 - -#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__first__BITNR 0 -#define R_DMA_CH9_FIRST__first__WIDTH 32 - -#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__cmd__BITNR 0 -#define R_DMA_CH9_CMD__cmd__WIDTH 3 -#define R_DMA_CH9_CMD__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__start 1 -#define R_DMA_CH9_CMD__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__reset 4 - -#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__avail__BITNR 0 -#define R_DMA_CH9_STATUS__avail__WIDTH 7 - -/* -!* Test mode registers -!*/ - -#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__single_step__WIDTH 1 -#define R_TEST_MODE__single_step__on 1 -#define R_TEST_MODE__single_step__off 0 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_wr__WIDTH 1 -#define R_TEST_MODE__step_wr__on 1 -#define R_TEST_MODE__step_wr__off 0 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_rd__WIDTH 1 -#define R_TEST_MODE__step_rd__on 1 -#define R_TEST_MODE__step_rd__off 0 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__step_fetch__WIDTH 1 -#define R_TEST_MODE__step_fetch__on 1 -#define R_TEST_MODE__step_fetch__off 0 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__mmu_test__WIDTH 1 -#define R_TEST_MODE__mmu_test__on 1 -#define R_TEST_MODE__mmu_test__off 0 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__usb_test__WIDTH 1 -#define R_TEST_MODE__usb_test__on 1 -#define R_TEST_MODE__usb_test__off 0 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__scsi_timer_test__WIDTH 1 -#define R_TEST_MODE__scsi_timer_test__on 1 -#define R_TEST_MODE__scsi_timer_test__off 0 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__backoff__WIDTH 1 -#define R_TEST_MODE__backoff__on 1 -#define R_TEST_MODE__backoff__off 0 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_test__WIDTH 1 -#define R_TEST_MODE__snmp_test__on 1 -#define R_TEST_MODE__snmp_test__off 0 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__snmp_inc__WIDTH 1 -#define R_TEST_MODE__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__ser_loop__WIDTH 1 -#define R_TEST_MODE__ser_loop__on 1 -#define R_TEST_MODE__ser_loop__off 0 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__baudrate__WIDTH 1 -#define R_TEST_MODE__baudrate__on 1 -#define R_TEST_MODE__baudrate__off 0 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__timer__WIDTH 2 -#define R_TEST_MODE__timer__off 0 -#define R_TEST_MODE__timer__even 1 -#define R_TEST_MODE__timer__odd 2 -#define R_TEST_MODE__timer__all 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__cache_test__WIDTH 1 -#define R_TEST_MODE__cache_test__normal 0 -#define R_TEST_MODE__cache_test__test 1 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__tag_test__WIDTH 1 -#define R_TEST_MODE__tag_test__normal 0 -#define R_TEST_MODE__tag_test__test 1 -#define R_TEST_MODE__cache_enable__BITNR 0 -#define R_TEST_MODE__cache_enable__WIDTH 1 -#define R_TEST_MODE__cache_enable__enable 1 -#define R_TEST_MODE__cache_enable__disable 0 - -#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__single_step__WIDTH 1 -#define R_SINGLE_STEP__single_step__on 1 -#define R_SINGLE_STEP__single_step__off 0 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_wr__WIDTH 1 -#define R_SINGLE_STEP__step_wr__on 1 -#define R_SINGLE_STEP__step_wr__off 0 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_rd__WIDTH 1 -#define R_SINGLE_STEP__step_rd__on 1 -#define R_SINGLE_STEP__step_rd__off 0 -#define R_SINGLE_STEP__step_fetch__BITNR 0 -#define R_SINGLE_STEP__step_fetch__WIDTH 1 -#define R_SINGLE_STEP__step_fetch__on 1 -#define R_SINGLE_STEP__step_fetch__off 0 - -/* -!* USB interface control registers -!*/ - -#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__major__WIDTH 4 -#define R_USB_REVISION__minor__BITNR 0 -#define R_USB_REVISION__minor__WIDTH 4 - -#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_sel__WIDTH 2 -#define R_USB_COMMAND__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port2 2 -#define R_USB_COMMAND__port_sel__both 3 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__port_cmd__WIDTH 2 -#define R_USB_COMMAND__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__suspend 2 -#define R_USB_COMMAND__port_cmd__resume 3 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__busy__WIDTH 1 -#define R_USB_COMMAND__busy__no 0 -#define R_USB_COMMAND__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__reset 1 -#define R_USB_COMMAND__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__host_stop 7 - -#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 -#define R_USB_COMMAND_DEV__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 -#define R_USB_COMMAND_DEV__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__busy__WIDTH 1 -#define R_USB_COMMAND_DEV__busy__no 0 -#define R_USB_COMMAND_DEV__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 - -#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__ourun__WIDTH 1 -#define R_USB_STATUS__ourun__no 0 -#define R_USB_STATUS__ourun__yes 1 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__perror__WIDTH 1 -#define R_USB_STATUS__perror__no 0 -#define R_USB_STATUS__perror__yes 1 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__device_mode__WIDTH 1 -#define R_USB_STATUS__device_mode__no 0 -#define R_USB_STATUS__device_mode__yes 1 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__host_mode__WIDTH 1 -#define R_USB_STATUS__host_mode__no 0 -#define R_USB_STATUS__host_mode__yes 1 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__started__WIDTH 1 -#define R_USB_STATUS__started__no 0 -#define R_USB_STATUS__started__yes 1 -#define R_USB_STATUS__running__BITNR 0 -#define R_USB_STATUS__running__WIDTH 1 -#define R_USB_STATUS__running__no 0 -#define R_USB_STATUS__running__yes 1 - -#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 - -#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__sof__WIDTH 1 -#define R_USB_IRQ_READ__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__pend 1 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__port_status__WIDTH 1 -#define R_USB_IRQ_READ__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 - -#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 - -#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__value__BITNR 0 -#define R_USB_FM_NUMBER__value__WIDTH 32 - -#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__fixed__WIDTH 8 -#define R_USB_FM_INTERVAL__adj__BITNR 0 -#define R_USB_FM_INTERVAL__adj__WIDTH 6 - -#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__value__BITNR 0 -#define R_USB_FM_REMAINING__value__WIDTH 14 - -#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__value__BITNR 0 -#define R_USB_FM_PSTART__value__WIDTH 14 - -#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble2__WIDTH 1 -#define R_USB_RH_STATUS__babble2__no 0 -#define R_USB_RH_STATUS__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__babble1__WIDTH 1 -#define R_USB_RH_STATUS__babble1__no 0 -#define R_USB_RH_STATUS__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus1__WIDTH 2 -#define R_USB_RH_STATUS__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__bus2__WIDTH 2 -#define R_USB_RH_STATUS__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__SE1 3 -#define R_USB_RH_STATUS__nports__BITNR 0 -#define R_USB_RH_STATUS__nports__WIDTH 2 - -#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__yes 1 - -#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__yes 1 - -#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__value__BITNR 0 -#define R_USB_EPT_INDEX__value__WIDTH 5 - -#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__valid__WIDTH 1 -#define R_USB_EPT_DATA__valid__no 0 -#define R_USB_EPT_DATA__valid__yes 1 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__hold__WIDTH 1 -#define R_USB_EPT_DATA__hold__no 0 -#define R_USB_EPT_DATA__hold__yes 1 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__error_count_in__WIDTH 2 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__t_in__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__low_speed__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__yes 1 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__port__WIDTH 2 -#define R_USB_EPT_DATA__port__any 0 -#define R_USB_EPT_DATA__port__p1 1 -#define R_USB_EPT_DATA__port__p2 2 -#define R_USB_EPT_DATA__port__undef 3 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__error_code__WIDTH 2 -#define R_USB_EPT_DATA__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__stall 1 -#define R_USB_EPT_DATA__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__buffer_error 3 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__t_out__WIDTH 1 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__error_count_out__WIDTH 2 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__max_len__WIDTH 7 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__ep__WIDTH 4 -#define R_USB_EPT_DATA__dev__BITNR 0 -#define R_USB_EPT_DATA__dev__WIDTH 7 - -#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 -#define R_USB_EPT_DATA_ISO__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__port__WIDTH 2 -#define R_USB_EPT_DATA_ISO__port__any 0 -#define R_USB_EPT_DATA_ISO__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 -#define R_USB_EPT_DATA_ISO__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__stall 1 -#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 -#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 - -#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 -#define R_USB_EPT_DATA_DEV__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 -#define R_USB_EPT_DATA_DEV__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 -#define R_USB_EPT_DATA_DEV__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 -#define R_USB_EPT_DATA_DEV__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__yes 1 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__port__WIDTH 2 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__t__WIDTH 1 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 -#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 - -#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__value__BITNR 0 -#define R_USB_SNMP_TERROR__value__WIDTH 32 - -#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__value__BITNR 0 -#define R_USB_EPID_ATTN__value__WIDTH 32 - -#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) -#define R_USB_PORT1_DISABLE__disable__BITNR 0 -#define R_USB_PORT1_DISABLE__disable__WIDTH 1 -#define R_USB_PORT1_DISABLE__disable__yes 0 -#define R_USB_PORT1_DISABLE__disable__no 1 - -#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) -#define R_USB_PORT2_DISABLE__disable__BITNR 0 -#define R_USB_PORT2_DISABLE__disable__WIDTH 1 -#define R_USB_PORT2_DISABLE__disable__yes 0 -#define R_USB_PORT2_DISABLE__disable__no 1 - -/* -!* MMU registers -!*/ - -#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__mmu_enable__WIDTH 1 -#define R_MMU_CONFIG__mmu_enable__enable 1 -#define R_MMU_CONFIG__mmu_enable__disable 0 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__inv_excp__WIDTH 1 -#define R_MMU_CONFIG__inv_excp__enable 1 -#define R_MMU_CONFIG__inv_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__acc_excp__WIDTH 1 -#define R_MMU_CONFIG__acc_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__disable 0 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__we_excp__WIDTH 1 -#define R_MMU_CONFIG__we_excp__enable 1 -#define R_MMU_CONFIG__we_excp__disable 0 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_f__WIDTH 1 -#define R_MMU_CONFIG__seg_f__seg 1 -#define R_MMU_CONFIG__seg_f__page 0 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_e__WIDTH 1 -#define R_MMU_CONFIG__seg_e__seg 1 -#define R_MMU_CONFIG__seg_e__page 0 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_d__WIDTH 1 -#define R_MMU_CONFIG__seg_d__seg 1 -#define R_MMU_CONFIG__seg_d__page 0 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_c__WIDTH 1 -#define R_MMU_CONFIG__seg_c__seg 1 -#define R_MMU_CONFIG__seg_c__page 0 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_b__WIDTH 1 -#define R_MMU_CONFIG__seg_b__seg 1 -#define R_MMU_CONFIG__seg_b__page 0 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_a__WIDTH 1 -#define R_MMU_CONFIG__seg_a__seg 1 -#define R_MMU_CONFIG__seg_a__page 0 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_9__WIDTH 1 -#define R_MMU_CONFIG__seg_9__seg 1 -#define R_MMU_CONFIG__seg_9__page 0 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_8__WIDTH 1 -#define R_MMU_CONFIG__seg_8__seg 1 -#define R_MMU_CONFIG__seg_8__page 0 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_7__WIDTH 1 -#define R_MMU_CONFIG__seg_7__seg 1 -#define R_MMU_CONFIG__seg_7__page 0 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_6__WIDTH 1 -#define R_MMU_CONFIG__seg_6__seg 1 -#define R_MMU_CONFIG__seg_6__page 0 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_5__WIDTH 1 -#define R_MMU_CONFIG__seg_5__seg 1 -#define R_MMU_CONFIG__seg_5__page 0 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_4__WIDTH 1 -#define R_MMU_CONFIG__seg_4__seg 1 -#define R_MMU_CONFIG__seg_4__page 0 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_3__WIDTH 1 -#define R_MMU_CONFIG__seg_3__seg 1 -#define R_MMU_CONFIG__seg_3__page 0 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_2__WIDTH 1 -#define R_MMU_CONFIG__seg_2__seg 1 -#define R_MMU_CONFIG__seg_2__page 0 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_1__WIDTH 1 -#define R_MMU_CONFIG__seg_1__seg 1 -#define R_MMU_CONFIG__seg_1__page 0 -#define R_MMU_CONFIG__seg_0__BITNR 0 -#define R_MMU_CONFIG__seg_0__WIDTH 1 -#define R_MMU_CONFIG__seg_0__seg 1 -#define R_MMU_CONFIG__seg_0__page 0 - -#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_f__WIDTH 1 -#define R_MMU_KSEG__seg_f__seg 1 -#define R_MMU_KSEG__seg_f__page 0 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_e__WIDTH 1 -#define R_MMU_KSEG__seg_e__seg 1 -#define R_MMU_KSEG__seg_e__page 0 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_d__WIDTH 1 -#define R_MMU_KSEG__seg_d__seg 1 -#define R_MMU_KSEG__seg_d__page 0 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_c__WIDTH 1 -#define R_MMU_KSEG__seg_c__seg 1 -#define R_MMU_KSEG__seg_c__page 0 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_b__WIDTH 1 -#define R_MMU_KSEG__seg_b__seg 1 -#define R_MMU_KSEG__seg_b__page 0 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_a__WIDTH 1 -#define R_MMU_KSEG__seg_a__seg 1 -#define R_MMU_KSEG__seg_a__page 0 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_9__WIDTH 1 -#define R_MMU_KSEG__seg_9__seg 1 -#define R_MMU_KSEG__seg_9__page 0 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_8__WIDTH 1 -#define R_MMU_KSEG__seg_8__seg 1 -#define R_MMU_KSEG__seg_8__page 0 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_7__WIDTH 1 -#define R_MMU_KSEG__seg_7__seg 1 -#define R_MMU_KSEG__seg_7__page 0 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_6__WIDTH 1 -#define R_MMU_KSEG__seg_6__seg 1 -#define R_MMU_KSEG__seg_6__page 0 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_5__WIDTH 1 -#define R_MMU_KSEG__seg_5__seg 1 -#define R_MMU_KSEG__seg_5__page 0 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_4__WIDTH 1 -#define R_MMU_KSEG__seg_4__seg 1 -#define R_MMU_KSEG__seg_4__page 0 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_3__WIDTH 1 -#define R_MMU_KSEG__seg_3__seg 1 -#define R_MMU_KSEG__seg_3__page 0 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_2__WIDTH 1 -#define R_MMU_KSEG__seg_2__seg 1 -#define R_MMU_KSEG__seg_2__page 0 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_1__WIDTH 1 -#define R_MMU_KSEG__seg_1__seg 1 -#define R_MMU_KSEG__seg_1__page 0 -#define R_MMU_KSEG__seg_0__BITNR 0 -#define R_MMU_KSEG__seg_0__WIDTH 1 -#define R_MMU_KSEG__seg_0__seg 1 -#define R_MMU_KSEG__seg_0__page 0 - -#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__inv_excp__WIDTH 1 -#define R_MMU_CTRL__inv_excp__enable 1 -#define R_MMU_CTRL__inv_excp__disable 0 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__acc_excp__WIDTH 1 -#define R_MMU_CTRL__acc_excp__enable 1 -#define R_MMU_CTRL__acc_excp__disable 0 -#define R_MMU_CTRL__we_excp__BITNR 0 -#define R_MMU_CTRL__we_excp__WIDTH 1 -#define R_MMU_CTRL__we_excp__enable 1 -#define R_MMU_CTRL__we_excp__disable 0 - -#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) -#define R_MMU_ENABLE__mmu_enable__BITNR 7 -#define R_MMU_ENABLE__mmu_enable__WIDTH 1 -#define R_MMU_ENABLE__mmu_enable__enable 1 -#define R_MMU_ENABLE__mmu_enable__disable 0 - -#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_7__WIDTH 4 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_6__WIDTH 4 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_5__WIDTH 4 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_4__WIDTH 4 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_3__WIDTH 4 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_2__WIDTH 4 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_1__WIDTH 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 -#define R_MMU_KBASE_LO__base_0__WIDTH 4 - -#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_f__WIDTH 4 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_e__WIDTH 4 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_d__WIDTH 4 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_c__WIDTH 4 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_b__WIDTH 4 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_a__WIDTH 4 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_9__WIDTH 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 -#define R_MMU_KBASE_HI__base_8__WIDTH 4 - -#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__page_id__BITNR 0 -#define R_MMU_CONTEXT__page_id__WIDTH 6 - -#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__vpn__WIDTH 19 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__miss_excp__WIDTH 1 -#define R_MMU_CAUSE__miss_excp__yes 1 -#define R_MMU_CAUSE__miss_excp__no 0 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__inv_excp__WIDTH 1 -#define R_MMU_CAUSE__inv_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__no 0 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__acc_excp__WIDTH 1 -#define R_MMU_CAUSE__acc_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__no 0 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__we_excp__WIDTH 1 -#define R_MMU_CAUSE__we_excp__yes 1 -#define R_MMU_CAUSE__we_excp__no 0 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__wr_rd__WIDTH 1 -#define R_MMU_CAUSE__wr_rd__write 1 -#define R_MMU_CAUSE__wr_rd__read 0 -#define R_MMU_CAUSE__page_id__BITNR 0 -#define R_MMU_CAUSE__page_id__WIDTH 6 - -#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__index__BITNR 0 -#define R_TLB_SELECT__index__WIDTH 6 - -#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__pfn__WIDTH 19 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__global__WIDTH 1 -#define R_TLB_LO__global__yes 1 -#define R_TLB_LO__global__no 0 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__valid__WIDTH 1 -#define R_TLB_LO__valid__yes 1 -#define R_TLB_LO__valid__no 0 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__kernel__WIDTH 1 -#define R_TLB_LO__kernel__yes 1 -#define R_TLB_LO__kernel__no 0 -#define R_TLB_LO__we__BITNR 0 -#define R_TLB_LO__we__WIDTH 1 -#define R_TLB_LO__we__yes 1 -#define R_TLB_LO__we__no 0 - -#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__vpn__WIDTH 19 -#define R_TLB_HI__page_id__BITNR 0 -#define R_TLB_HI__page_id__WIDTH 6 - -/* -!* Syncrounous serial port registers -!*/ - -#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 - -#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 - diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h deleted file mode 100644 index 2644bcbe4490..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/*!************************************************************************** -*! -*! MACROS: -*! IO_MASK(reg,field) -*! IO_STATE(reg,field,state) -*! IO_EXTRACT(reg,field,val) -*! IO_STATE_VALUE(reg,field,state) -*! IO_BITNR(reg,field) -*! IO_WIDTH(reg,field) -*! IO_FIELD(reg,field,val) -*! IO_RD(reg) -*! All moderegister addresses and fields of these. -*! -*!**************************************************************************/ - -#ifndef __sv_addr_ag_h__ -#define __sv_addr_ag_h__ - - -#define __test_sv_addr__ 0 - -/*------------------------------------------------------------ -!* General macros to manipulate moderegisters. -!*-----------------------------------------------------------*/ - -/* IO_MASK returns a mask for a specified bitfield in a register. - Note that this macro doesn't work when field width is 32 bits. */ -#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) -#define IO_MASK_(reg_, field_) \ - ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) - -/* IO_STATE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Shifted to correct position) */ -#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) -#define IO_STATE_(reg_, field_, _state) \ - ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) - -/* IO_EXTRACT returns the masked and shifted value corresponding to the - bitfield can have. */ -#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) -#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ - - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) - -/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Not shifted) */ -#define IO_STATE_VALUE(reg, field, state) \ - IO_STATE_VALUE_ (reg##_, field##_, _##state) -#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) - -/* IO_FIELD shifts the val parameter to be aligned with the bitfield - specified. */ -#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) -#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) - -/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is - LSB and the returned bitnumber is LSB of the field. */ -#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) -#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) - -/* IO_WIDTH returns the width, in bits, of a bitfield. */ -#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) -#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) - -/*--- Obsolete. Kept for backward compatibility. ---*/ -/* Reads (or writes) a byte/uword/udword from the specified mode - register. */ -#define IO_RD(reg) (*(volatile u32*)(reg)) -#define IO_RD_B(reg) (*(volatile u8*)(reg)) -#define IO_RD_W(reg) (*(volatile u16*)(reg)) -#define IO_RD_D(reg) (*(volatile u32*)(reg)) - -/*------------------------------------------------------------ -!* Start addresses of the different memory areas. -!*-----------------------------------------------------------*/ - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -/*------------------------------------------------------------ -!* Type casts used in mode register macros, making pointer -!* dereferencing possible. Empty in assembler. -!*-----------------------------------------------------------*/ - -#ifndef __ASSEMBLER__ -# define IO_TYPECAST_UDWORD (volatile u32*) -# define IO_TYPECAST_RO_UDWORD (const volatile u32*) -# define IO_TYPECAST_UWORD (volatile u16*) -# define IO_TYPECAST_RO_UWORD (const volatile u16*) -# define IO_TYPECAST_BYTE (volatile u8*) -# define IO_TYPECAST_RO_BYTE (const volatile u8*) -#else -# define IO_TYPECAST_UDWORD -# define IO_TYPECAST_RO_UDWORD -# define IO_TYPECAST_UWORD -# define IO_TYPECAST_RO_UWORD -# define IO_TYPECAST_BYTE -# define IO_TYPECAST_RO_BYTE -#endif - -/*------------------------------------------------------------*/ - -#include - -#if __test_sv_addr__ -/* IO_MASK( R_BUS_CONFIG , CE ) */ -IO_MASK( R_WAITSTATES , SRAM_WS ) -IO_MASK( R_TEST , W32 ) - -IO_STATE( R_BUS_CONFIG, CE, DISABLE ) -IO_STATE( R_BUS_CONFIG, CE, ENABLE ) - -IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) - -IO_MASK( R_DRAM_TIMING, REF ) - -IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) - -IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) - == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) -#endif - - -#endif /* ifndef __sv_addr_ag_h__ */ - diff --git a/arch/cris/include/uapi/arch-v10/arch/svinto.h b/arch/cris/include/uapi/arch-v10/arch/svinto.h deleted file mode 100644 index 793a4275d26a..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/svinto.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_CRIS_SVINTO_H -#define _ASM_CRIS_SVINTO_H - -#include - -extern unsigned int genconfig_shadow; /* defined and set in head.S */ - -/* dma stuff */ - -enum { /* Available in: */ - d_eol = (1 << 0), /* flags */ - d_eop = (1 << 1), /* flags & status */ - d_wait = (1 << 2), /* flags */ - d_int = (1 << 3), /* flags */ - d_txerr = (1 << 4), /* flags */ - d_stop = (1 << 4), /* status */ - d_ecp = (1 << 4), /* flags & status */ - d_pri = (1 << 5), /* flags & status */ - d_alignerr = (1 << 6), /* status */ - d_crcerr = (1 << 7) /* status */ -}; - -/* Do remember that DMA does not go through the MMU and needs - * a real physical address, not an address virtually mapped or - * paged. Therefore the buf/next ptrs below are unsigned long instead - * of void * to give a warning if you try to put a pointer directly - * to them instead of going through virt_to_phys/phys_to_virt. - */ - -typedef struct etrax_dma_descr { - unsigned short sw_len; /* 0-1 */ - unsigned short ctrl; /* 2-3 */ - unsigned long next; /* 4-7 */ - unsigned long buf; /* 8-11 */ - unsigned short hw_len; /* 12-13 */ - unsigned char status; /* 14 */ - unsigned char fifo_len; /* 15 */ -} etrax_dma_descr; - - -/* Use this for constant numbers only */ -#define RESET_DMA_NUM( n ) \ - *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) - -/* Use this for constant numbers or symbols, - * having two macros makes it possible to use constant expressions. - */ -#define RESET_DMA( n ) RESET_DMA_NUM( n ) - - -/* Use this for constant numbers only */ -#define WAIT_DMA_NUM( n ) \ - while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ - IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) - -/* Use this for constant numbers or symbols - * having two macros makes it possible to use constant expressions. - */ -#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) - -extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); -extern void flush_etrax_cache(void); - -#endif diff --git a/arch/cris/include/uapi/arch-v10/arch/user.h b/arch/cris/include/uapi/arch-v10/arch/user.h deleted file mode 100644 index 5b9288527b98..000000000000 --- a/arch/cris/include/uapi/arch-v10/arch/user.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ASM_CRIS_ARCH_USER_H -#define __ASM_CRIS_ARCH_USER_H - -/* User mode registers, used for core dumps. In order to keep ELF_NGREG - sensible we let all registers be 32 bits. The csr registers are included - for future use. */ -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* Stack pointer. */ - unsigned long pc; /* Program counter. */ - unsigned long p0; /* Constant zero (only 8 bits). */ - unsigned long vr; /* Version register (only 8 bits). */ - unsigned long p2; /* Reserved. */ - unsigned long p3; /* Reserved. */ - unsigned long p4; /* Constant zero (only 16 bits). */ - unsigned long ccr; /* Condition code register (only 16 bits). */ - unsigned long p6; /* Reserved. */ - unsigned long mof; /* Multiply overflow register. */ - unsigned long p8; /* Constant zero. */ - unsigned long ibr; /* Not accessible. */ - unsigned long irp; /* Not accessible. */ - unsigned long srp; /* Subroutine return pointer. */ - unsigned long bar; /* Not accessible. */ - unsigned long dccr; /* Dword condition code register. */ - unsigned long brp; /* Not accessible. */ - unsigned long usp; /* User-mode stack pointer. Same as sp when - in user mode. */ - unsigned long csrinstr; /* Internal status registers. */ - unsigned long csraddr; - unsigned long csrdata; -}; - -#endif diff --git a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h b/arch/cris/include/uapi/arch-v32/arch/cryptocop.h deleted file mode 100644 index 1072d5bf7d4f..000000000000 --- a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * The device /dev/cryptocop is accessible using this driver using - * CRYPTOCOP_MAJOR (254) and minor number 0. - */ - -#ifndef _UAPICRYPTOCOP_H -#define _UAPICRYPTOCOP_H - -#include - - -#define CRYPTOCOP_SESSION_ID_NONE (0) - -typedef unsigned long long int cryptocop_session_id; - -/* cryptocop ioctls */ -#define ETRAXCRYPTOCOP_IOCTYPE (250) - -#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) -#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) -#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) -#define CRYPTOCOP_IO_MAXNR (3) - -typedef enum { - cryptocop_cipher_des = 0, - cryptocop_cipher_3des = 1, - cryptocop_cipher_aes = 2, - cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ - cryptocop_cipher_none -} cryptocop_cipher_type; - -typedef enum { - cryptocop_digest_sha1 = 0, - cryptocop_digest_md5 = 1, - cryptocop_digest_none -} cryptocop_digest_type; - -typedef enum { - cryptocop_csum_le = 0, - cryptocop_csum_be = 1, - cryptocop_csum_none -} cryptocop_csum_type; - -typedef enum { - cryptocop_cipher_mode_ecb = 0, - cryptocop_cipher_mode_cbc, - cryptocop_cipher_mode_none -} cryptocop_cipher_mode; - -typedef enum { - cryptocop_3des_eee = 0, - cryptocop_3des_eed = 1, - cryptocop_3des_ede = 2, - cryptocop_3des_edd = 3, - cryptocop_3des_dee = 4, - cryptocop_3des_ded = 5, - cryptocop_3des_dde = 6, - cryptocop_3des_ddd = 7 -} cryptocop_3des_mode; - -/* Usermode accessible (ioctl) operations. */ -struct strcop_session_op{ - cryptocop_session_id ses_id; - - cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ - - cryptocop_cipher_mode cmode; /* ECB, CBC, none */ - cryptocop_3des_mode des3_mode; - - cryptocop_digest_type digest; /* MD5, SHA1, none */ - - cryptocop_csum_type csum; /* BE, LE, none */ - - unsigned char *key; - size_t keylen; -}; - -#define CRYPTOCOP_CSUM_LENGTH (2) -#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ -#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ -#define CRYPTOCOP_MAX_KEY_LENGTH (32) - -struct strcop_crypto_op{ - cryptocop_session_id ses_id; - - /* Indata. */ - unsigned char *indata; - size_t inlen; /* Total indata length. */ - - /* Cipher configuration. */ - unsigned char do_cipher:1; - unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ - unsigned char cipher_explicit:1; - size_t cipher_start; - size_t cipher_len; - /* cipher_iv is used if do_cipher and cipher_explicit and the cipher - mode is CBC. The length is controlled by the type of cipher, - e.g. DES/3DES 8 octets and AES 16 octets. */ - unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; - /* Outdata. */ - unsigned char *cipher_outdata; - size_t cipher_outlen; - - /* digest configuration. */ - unsigned char do_digest:1; - size_t digest_start; - size_t digest_len; - /* Outdata. The actual length is determined by the type of the digest. */ - unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; - - /* Checksum configuration. */ - unsigned char do_csum:1; - size_t csum_start; - size_t csum_len; - /* Outdata. */ - unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; -}; - - - - -#endif /* _UAPICRYPTOCOP_H */ diff --git a/arch/cris/include/uapi/arch-v32/arch/user.h b/arch/cris/include/uapi/arch-v32/arch/user.h deleted file mode 100644 index 3576b540ba78..000000000000 --- a/arch/cris/include/uapi/arch-v32/arch/user.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_CRIS_ARCH_USER_H -#define _ASM_CRIS_ARCH_USER_H - -/* User-mode register used for core dumps. */ - -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* R14, Stack pointer. */ - unsigned long acr; /* R15, Address calculation register. */ - unsigned long bz; /* P0, Constant zero (8-bits). */ - unsigned long vr; /* P1, Version register (8-bits). */ - unsigned long pid; /* P2, Process ID (8-bits). */ - unsigned long srs; /* P3, Support register select (8-bits). */ - unsigned long wz; /* P4, Constant zero (16-bits). */ - unsigned long exs; /* P5, Exception status. */ - unsigned long eda; /* P6, Exception data address. */ - unsigned long mof; /* P7, Multiply overflow regiter. */ - unsigned long dz; /* P8, Constant zero (32-bits). */ - unsigned long ebp; /* P9, Exception base pointer. */ - unsigned long erp; /* P10, Exception return pointer. */ - unsigned long srp; /* P11, Subroutine return pointer. */ - unsigned long nrp; /* P12, NMI return pointer. */ - unsigned long ccs; /* P13, Condition code stack. */ - unsigned long usp; /* P14, User mode stack pointer. */ - unsigned long spc; /* P15, Single step PC. */ -}; - -#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild deleted file mode 100644 index 3470c6e9c7b9..000000000000 --- a/arch/cris/include/uapi/asm/Kbuild +++ /dev/null @@ -1,22 +0,0 @@ -# UAPI Header export list -include include/uapi/asm-generic/Kbuild.asm - -generic-y += auxvec.h -generic-y += bitsperlong.h -generic-y += bpf_perf_event.h -generic-y += errno.h -generic-y += fcntl.h -generic-y += ioctl.h -generic-y += ipcbuf.h -generic-y += kvm_para.h -generic-y += mman.h -generic-y += msgbuf.h -generic-y += poll.h -generic-y += resource.h -generic-y += sembuf.h -generic-y += shmbuf.h -generic-y += siginfo.h -generic-y += socket.h -generic-y += sockios.h -generic-y += statfs.h -generic-y += types.h diff --git a/arch/cris/include/uapi/asm/byteorder.h b/arch/cris/include/uapi/asm/byteorder.h deleted file mode 100644 index 6e19891e06ee..000000000000 --- a/arch/cris/include/uapi/asm/byteorder.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_BYTEORDER_H -#define _CRIS_BYTEORDER_H - -#include - -#endif - - diff --git a/arch/cris/include/uapi/asm/elf.h b/arch/cris/include/uapi/asm/elf.h deleted file mode 100644 index ea4cbdafe885..000000000000 --- a/arch/cris/include/uapi/asm/elf.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ASMCRIS_ELF_H -#define __ASMCRIS_ELF_H - -/* - * ELF register definitions.. - */ - -#ifdef __arch_v32 -#include -#else -#include -#endif - -#define R_CRIS_NONE 0 -#define R_CRIS_8 1 -#define R_CRIS_16 2 -#define R_CRIS_32 3 -#define R_CRIS_8_PCREL 4 -#define R_CRIS_16_PCREL 5 -#define R_CRIS_32_PCREL 6 -#define R_CRIS_GNU_VTINHERIT 7 -#define R_CRIS_GNU_VTENTRY 8 -#define R_CRIS_COPY 9 -#define R_CRIS_GLOB_DAT 10 -#define R_CRIS_JUMP_SLOT 11 -#define R_CRIS_RELATIVE 12 -#define R_CRIS_16_GOT 13 -#define R_CRIS_32_GOT 14 -#define R_CRIS_16_GOTPLT 15 -#define R_CRIS_32_GOTPLT 16 -#define R_CRIS_32_GOTREL 17 -#define R_CRIS_32_PLT_GOTREL 18 -#define R_CRIS_32_PLT_PCREL 19 - -typedef unsigned long elf_greg_t; - -/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is - thus exposed to user-space. */ -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -/* A placeholder; CRIS does not have any fp regs. */ -typedef unsigned long elf_fpregset_t; - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2LSB -#define ELF_ARCH EM_CRIS - -/* The master for these definitions is {binutils}/include/elf/cris.h: */ -/* User symbols in this file have a leading underscore. */ -#define EF_CRIS_UNDERSCORE 0x00000001 - -/* This is a mask for different incompatible machine variants. */ -#define EF_CRIS_VARIANT_MASK 0x0000000e - -/* Variant 0; may contain v0..10 object. */ -#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000 - -/* Variant 1; contains v32 object. */ -#define EF_CRIS_VARIANT_V32 0x00000002 - -/* Variant 2; contains object compatible with v32 and v10. */ -#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 -/* End of excerpt from {binutils}/include/elf/cris.h. */ - -#define ELF_EXEC_PAGESIZE 8192 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) - -/* This yields a mask that user programs can use to figure out what - instruction set this CPU supports. This could be done in user space, - but it's not easy, and we've already done it here. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. -*/ - -#define ELF_PLATFORM (NULL) - -#endif diff --git a/arch/cris/include/uapi/asm/elf_v10.h b/arch/cris/include/uapi/asm/elf_v10.h deleted file mode 100644 index b1515f2684da..000000000000 --- a/arch/cris/include/uapi/asm/elf_v10.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ASMCRIS_ARCH_ELF_H -#define __ASMCRIS_ARCH_ELF_H - -#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10 - -/* Matches struct user_regs_struct */ -#define ELF_NGREG 35 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* - * ELF register definitions.. - */ - -#include - -/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program - starts (a register; assume first param register for CRIS) - contains a pointer to a function which might be - registered using `atexit'. This provides a mean for the - dynamic linker to call DT_FINI functions for shared libraries - that have been loaded before the code runs. - - A value of 0 tells we have no such handler. */ - -/* Explicitly set registers to 0 to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ -} while (0) - -/* The additional layer below is because the stack pointer is missing in - the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t, - and should be filled in according to the layout of the user_regs_struct - struct; regs is a pt_regs struct. We dump all registers, though several are - obviously unnecessary. That way there's less need for intelligence at - the receiving end (i.e. gdb). */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* sp */ \ - pr_reg[15] = regs->irp; /* pc */ \ - pr_reg[16] = 0; /* p0 */ \ - pr_reg[17] = rdvr(); /* vr */ \ - pr_reg[18] = 0; /* p2 */ \ - pr_reg[19] = 0; /* p3 */ \ - pr_reg[20] = 0; /* p4 */ \ - pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \ - pr_reg[22] = 0; /* p6 */ \ - pr_reg[23] = regs->mof; /* mof */ \ - pr_reg[24] = 0; /* p8 */ \ - pr_reg[25] = 0; /* ibr */ \ - pr_reg[26] = 0; /* irp */ \ - pr_reg[27] = regs->srp; /* srp */ \ - pr_reg[28] = 0; /* bar */ \ - pr_reg[29] = regs->dccr; /* dccr */ \ - pr_reg[30] = 0; /* brp */ \ - pr_reg[31] = rdusp(); /* usp */ \ - pr_reg[32] = 0; /* csrinstr */ \ - pr_reg[33] = 0; /* csraddr */ \ - pr_reg[34] = 0; /* csrdata */ - - -#endif diff --git a/arch/cris/include/uapi/asm/elf_v32.h b/arch/cris/include/uapi/asm/elf_v32.h deleted file mode 100644 index cc00ffdb7f9c..000000000000 --- a/arch/cris/include/uapi/asm/elf_v32.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASM_CRIS_ELF_H -#define _ASM_CRIS_ELF_H - -#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32 - -/* Matches struct user_regs_struct */ -#define ELF_NGREG 32 - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) \ - ((x)->e_machine == EM_CRIS \ - && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \ - || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32)))) - -/* CRISv32 ELF register definitions. */ - -#include - -/* Explicitly zero out registers to increase determinism. */ -#define ELF_PLAT_INIT(_r, load_addr) do { \ - (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \ - (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \ - (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \ - (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \ - (_r)->acr = 0; \ -} while (0) - -/* - * An executable for which elf_read_implies_exec() returns TRUE will - * have the READ_IMPLIES_EXEC personality flag set automatically. - */ -#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack)) - -/* - * This is basically a pt_regs with the additional definition - * of the stack pointer since it's needed in a core dump. - * pr_regs is a elf_gregset_t and should be filled according - * to the layout of user_regs_struct. - */ -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - pr_reg[0] = regs->r0; \ - pr_reg[1] = regs->r1; \ - pr_reg[2] = regs->r2; \ - pr_reg[3] = regs->r3; \ - pr_reg[4] = regs->r4; \ - pr_reg[5] = regs->r5; \ - pr_reg[6] = regs->r6; \ - pr_reg[7] = regs->r7; \ - pr_reg[8] = regs->r8; \ - pr_reg[9] = regs->r9; \ - pr_reg[10] = regs->r10; \ - pr_reg[11] = regs->r11; \ - pr_reg[12] = regs->r12; \ - pr_reg[13] = regs->r13; \ - pr_reg[14] = rdusp(); /* SP */ \ - pr_reg[15] = regs->acr; /* ACR */ \ - pr_reg[16] = 0; /* BZ */ \ - pr_reg[17] = rdvr(); /* VR */ \ - pr_reg[18] = 0; /* PID */ \ - pr_reg[19] = regs->srs; /* SRS */ \ - pr_reg[20] = 0; /* WZ */ \ - pr_reg[21] = regs->exs; /* EXS */ \ - pr_reg[22] = regs->eda; /* EDA */ \ - pr_reg[23] = regs->mof; /* MOF */ \ - pr_reg[24] = 0; /* DZ */ \ - pr_reg[25] = 0; /* EBP */ \ - pr_reg[26] = regs->erp; /* ERP */ \ - pr_reg[27] = regs->srp; /* SRP */ \ - pr_reg[28] = 0; /* NRP */ \ - pr_reg[29] = regs->ccs; /* CCS */ \ - pr_reg[30] = rdusp(); /* USP */ \ - pr_reg[31] = regs->spc; /* SPC */ \ - -#endif /* _ASM_CRIS_ELF_H */ diff --git a/arch/cris/include/uapi/asm/ethernet.h b/arch/cris/include/uapi/asm/ethernet.h deleted file mode 100644 index e0c1a6322824..000000000000 --- a/arch/cris/include/uapi/asm/ethernet.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * ioctl defines for ethernet driver - * - * Copyright (c) 2001 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef _CRIS_ETHERNET_H -#define _CRIS_ETHERNET_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ -#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ -#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ -#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 -#endif /* _CRIS_ETHERNET_H */ diff --git a/arch/cris/include/uapi/asm/etraxgpio.h b/arch/cris/include/uapi/asm/etraxgpio.h deleted file mode 100644 index 10ab0dd45bfe..000000000000 --- a/arch/cris/include/uapi/asm/etraxgpio.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * The following devices are accessible using this driver using - * GPIO_MAJOR (120) and a couple of minor numbers. - * - * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/gpiog minor 3 - * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG - * g1-g7 and g25-g31 is both input and outputs but on different pins - * Also note that some bits change pins depending on what interfaces - * are enabled. - */ -#ifndef _ASM_ETRAXGPIO_H -#define _ASM_ETRAXGPIO_H - -#define GPIO_MINOR_FIRST 0 - -#define ETRAXGPIO_IOCTYPE 43 - -/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_G 3 -#define GPIO_MINOR_LAST 3 -#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST - - -/* supported ioctl _IOC_NR's */ - -#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ -#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ -#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ - -/* the alarm is waited for by select() */ - -#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ -#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ -#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ - -/* LED ioctl */ -#define IO_LEDACTIVE_SET 0x7 /* set active led - * 0=off, 1=green, 2=red, 3=yellow */ - -/* GPIO direction ioctl's */ -#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ -#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, - returns mask with current inputs (obsolete) */ -#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, - returns mask with current outputs (obsolete)*/ - -/* LED ioctl extended */ -#define IO_LED_SETBIT 0xB -#define IO_LED_CLRBIT 0xC - -/* SHUTDOWN ioctl */ -#define IO_SHUTDOWN 0xD -#define IO_GET_PWR_BT 0xE - -/* Bit toggling in driver settings */ -/* bit set in low byte0 is CLK mask (0x00FF), - bit set in byte1 is DATA mask (0xFF00) - msb, data_mask[7:0] , clk_mask[7:0] - */ -#define IO_CFG_WRITE_MODE 0xF -#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ - ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) - -/* The following 4 ioctl's take a pointer as argument and handles - * 32 bit ports (port G) properly. - * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT - */ -#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ -#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ -#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ - /* *arg updated with current input pins. */ -#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ - /* *arg updated with current output pins. */ - -#endif diff --git a/arch/cris/include/uapi/asm/ioctls.h b/arch/cris/include/uapi/asm/ioctls.h deleted file mode 100644 index 92d654ce3d84..000000000000 --- a/arch/cris/include/uapi/asm/ioctls.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __ARCH_CRIS_IOCTLS_H__ -#define __ARCH_CRIS_IOCTLS_H__ - -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */ -#define TIOCSERWRRS485 0x5462 /* write rs-485 */ -#define TIOCSRS485 0x5463 /* enable rs-485 */ - -#include - -#endif diff --git a/arch/cris/include/uapi/asm/param.h b/arch/cris/include/uapi/asm/param.h deleted file mode 100644 index ae296115c7c9..000000000000 --- a/arch/cris/include/uapi/asm/param.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _ASMCRIS_PARAM_H -#define _ASMCRIS_PARAM_H - -/* Currently we assume that HZ=100 is good for CRIS. */ - -#define EXEC_PAGESIZE 8192 - -#include - -#endif /* _ASMCRIS_PARAM_H */ diff --git a/arch/cris/include/uapi/asm/posix_types.h b/arch/cris/include/uapi/asm/posix_types.h deleted file mode 100644 index c75d8b0acc99..000000000000 --- a/arch/cris/include/uapi/asm/posix_types.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ -/* I guess we should write these in assembler because they are used often. */ - -#ifndef __ARCH_CRIS_POSIX_TYPES_H -#define __ARCH_CRIS_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_mode_t; -#define __kernel_mode_t __kernel_mode_t - -typedef unsigned short __kernel_ipc_pid_t; -#define __kernel_ipc_pid_t __kernel_ipc_pid_t - -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -#define __kernel_uid_t __kernel_uid_t - -typedef unsigned short __kernel_old_dev_t; -#define __kernel_old_dev_t __kernel_old_dev_t - -#include - -#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/arch/cris/include/uapi/asm/ptrace.h b/arch/cris/include/uapi/asm/ptrace.h deleted file mode 100644 index 99de59e54613..000000000000 --- a/arch/cris/include/uapi/asm/ptrace.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifdef __arch_v32 -#include -#else -#include -#endif diff --git a/arch/cris/include/uapi/asm/ptrace_v10.h b/arch/cris/include/uapi/asm/ptrace_v10.h deleted file mode 100644 index 4ffffb7ab102..000000000000 --- a/arch/cris/include/uapi/asm/ptrace_v10.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Frame types */ - -#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */ -#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return - path */ - -/* Register numbers in the ptrace system call interface */ - -#define PT_FRAMETYPE 0 -#define PT_ORIG_R10 1 -#define PT_R13 2 -#define PT_R12 3 -#define PT_R11 4 -#define PT_R10 5 -#define PT_R9 6 -#define PT_R8 7 -#define PT_R7 8 -#define PT_R6 9 -#define PT_R5 10 -#define PT_R4 11 -#define PT_R3 12 -#define PT_R2 13 -#define PT_R1 14 -#define PT_R0 15 -#define PT_MOF 16 -#define PT_DCCR 17 -#define PT_SRP 18 -#define PT_IRP 19 /* This is actually the debugged process' PC */ -#define PT_CSRINSTR 20 /* CPU Status record remnants - - valid if frametype == busfault */ -#define PT_CSRADDR 21 -#define PT_CSRDATA 22 -#define PT_USP 23 /* special case - USP is not in the pt_regs */ -#define PT_MAX 23 - -/* Condition code bit numbers. The same numbers apply to CCR of course, - but we use DCCR everywhere else, so let's try and be consistent. */ -#define C_DCCR_BITNR 0 -#define V_DCCR_BITNR 1 -#define Z_DCCR_BITNR 2 -#define N_DCCR_BITNR 3 -#define X_DCCR_BITNR 4 -#define I_DCCR_BITNR 5 -#define B_DCCR_BITNR 6 -#define M_DCCR_BITNR 7 -#define U_DCCR_BITNR 8 -#define P_DCCR_BITNR 9 -#define F_DCCR_BITNR 10 - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long frametype; /* type of stackframe */ - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */ - unsigned long r13; - unsigned long r12; - unsigned long r11; - unsigned long r10; - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long mof; - unsigned long dccr; - unsigned long srp; - unsigned long irp; /* This is actually the debugged process' PC */ - unsigned long csrinstr; - unsigned long csraddr; - unsigned long csrdata; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r9; - unsigned long r8; - unsigned long r7; - unsigned long r6; - unsigned long r5; - unsigned long r4; - unsigned long r3; - unsigned long r2; - unsigned long r1; - unsigned long r0; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -/* bit 8 is user-mode flag */ -#define user_mode(regs) (((regs)->dccr & 0x100) != 0) -#define instruction_pointer(regs) ((regs)->irp) -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif diff --git a/arch/cris/include/uapi/asm/ptrace_v32.h b/arch/cris/include/uapi/asm/ptrace_v32.h deleted file mode 100644 index a91c4aacb14f..000000000000 --- a/arch/cris/include/uapi/asm/ptrace_v32.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_ARCH_PTRACE_H -#define _CRIS_ARCH_PTRACE_H - -/* Register numbers in the ptrace system call interface */ - -#define PT_ORIG_R10 0 -#define PT_R0 1 -#define PT_R1 2 -#define PT_R2 3 -#define PT_R3 4 -#define PT_R4 5 -#define PT_R5 6 -#define PT_R6 7 -#define PT_R7 8 -#define PT_R8 9 -#define PT_R9 10 -#define PT_R10 11 -#define PT_R11 12 -#define PT_R12 13 -#define PT_R13 14 -#define PT_ACR 15 -#define PT_SRS 16 -#define PT_MOF 17 -#define PT_SPC 18 -#define PT_CCS 19 -#define PT_SRP 20 -#define PT_ERP 21 /* This is actually the debugged process' PC */ -#define PT_EXS 22 -#define PT_EDA 23 -#define PT_USP 24 /* special case - USP is not in the pt_regs */ -#define PT_PPC 25 /* special case - pseudo PC */ -#define PT_BP 26 /* Base number for BP registers. */ -#define PT_BP_CTRL 26 /* BP control register. */ -#define PT_MAX 40 - -/* Condition code bit numbers. */ -#define C_CCS_BITNR 0 -#define V_CCS_BITNR 1 -#define Z_CCS_BITNR 2 -#define N_CCS_BITNR 3 -#define X_CCS_BITNR 4 -#define I_CCS_BITNR 5 -#define U_CCS_BITNR 6 -#define P_CCS_BITNR 7 -#define R_CCS_BITNR 8 -#define S_CCS_BITNR 9 -#define M_CCS_BITNR 30 -#define Q_CCS_BITNR 31 -#define CCS_SHIFT 10 /* Shift count for each level in CCS */ - -/* pt_regs not only specifices the format in the user-struct during - * ptrace but is also the frame format used in the kernel prologue/epilogues - * themselves - */ - -struct pt_regs { - unsigned long orig_r10; - /* pushed by movem r13, [sp] in SAVE_ALL. */ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long acr; - unsigned long srs; - unsigned long mof; - unsigned long spc; - unsigned long ccs; - unsigned long srp; - unsigned long erp; /* This is actually the debugged process' PC */ - /* For debugging purposes; saved only when needed. */ - unsigned long exs; - unsigned long eda; -}; - -/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S) - * when doing a context-switch. it is used (apart from in resume) when a new - * thread is made and we need to make _resume (which is starting it for the - * first time) realise what is going on. - * - * Actually, the use is very close to the thread struct (TSS) in that both the - * switch_stack and the TSS are used to keep thread stuff when switching in - * _resume. - */ - -struct switch_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long return_ip; /* ip that _resume will return to */ -}; - -#ifdef __KERNEL__ - -#define arch_has_single_step() (1) -#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0) -#define instruction_pointer(regs) ((regs)->erp) -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __KERNEL__ */ - -#endif diff --git a/arch/cris/include/uapi/asm/rs485.h b/arch/cris/include/uapi/asm/rs485.h deleted file mode 100644 index 041d31fa33d5..000000000000 --- a/arch/cris/include/uapi/asm/rs485.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* RS-485 structures */ - -/* Used with ioctl() TIOCSERSETRS485 for backward compatibility! - * XXX: Do not use it for new code! - */ -struct rs485_control { - unsigned short rts_on_send; - unsigned short rts_after_sent; - unsigned long delay_rts_before_send; - unsigned short enabled; -}; - -/* Used with ioctl() TIOCSERWRRS485 */ -struct rs485_write { - unsigned short outc_size; - unsigned char *outc; -}; - diff --git a/arch/cris/include/uapi/asm/setup.h b/arch/cris/include/uapi/asm/setup.h deleted file mode 100644 index 4854ace9db76..000000000000 --- a/arch/cris/include/uapi/asm/setup.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_SETUP_H -#define _CRIS_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -#endif diff --git a/arch/cris/include/uapi/asm/sigcontext.h b/arch/cris/include/uapi/asm/sigcontext.h deleted file mode 100644 index 97565ce3f0b9..000000000000 --- a/arch/cris/include/uapi/asm/sigcontext.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef _ASM_CRIS_SIGCONTEXT_H -#define _ASM_CRIS_SIGCONTEXT_H - -#include - -/* This struct is saved by setup_frame in signal.c, to keep the current context while - a signal handler is executed. It's restored by sys_sigreturn. - - To keep things simple, we use pt_regs here even though normally you just specify - the list of regs to save. Then we can use copy_from_user on the entire regs instead - of a bunch of get_user's as well... - -*/ - -struct sigcontext { - struct pt_regs regs; /* needs to be first */ - unsigned long oldmask; - unsigned long usp; /* usp before stacking this gunk on it */ -}; - -#endif - diff --git a/arch/cris/include/uapi/asm/signal.h b/arch/cris/include/uapi/asm/signal.h deleted file mode 100644 index e4ab00f00111..000000000000 --- a/arch/cris/include/uapi/asm/signal.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_ASM_CRIS_SIGNAL_H -#define _UAPI_ASM_CRIS_SIGNAL_H - -#include - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ - -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include - -#ifndef __KERNEL__ -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - - -#endif /* _UAPI_ASM_CRIS_SIGNAL_H */ diff --git a/arch/cris/include/uapi/asm/stat.h b/arch/cris/include/uapi/asm/stat.h deleted file mode 100644 index cdb74d5862e4..000000000000 --- a/arch/cris/include/uapi/asm/stat.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _CRIS_STAT_H -#define _CRIS_STAT_H - -/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in - the kernel if necessary. */ - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -#define STAT_HAVE_NSEC 1 - -struct stat { - unsigned long st_dev; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned long st_rdev; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* future possible st_blocks high bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ - - unsigned long long st_ino; -}; - -#endif diff --git a/arch/cris/include/uapi/asm/swab.h b/arch/cris/include/uapi/asm/swab.h deleted file mode 100644 index 4adf1e9f0b09..000000000000 --- a/arch/cris/include/uapi/asm/swab.h +++ /dev/null @@ -1,3 +0,0 @@ -/* - * CRIS byte swapping. - */ diff --git a/arch/cris/include/uapi/asm/sync_serial.h b/arch/cris/include/uapi/asm/sync_serial.h deleted file mode 100644 index f2d468889ba9..000000000000 --- a/arch/cris/include/uapi/asm/sync_serial.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* - * ioctl defines for synchronous serial port driver - * - * Copyright (c) 2001-2003 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef SYNC_SERIAL_H -#define SYNC_SERIAL_H - -#include - -#define SSP_SPEED _IOR('S', 0, unsigned int) -#define SSP_MODE _IOR('S', 1, unsigned int) -#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) -#define SSP_IPOLARITY _IOR('S', 3, unsigned int) -#define SSP_OPOLARITY _IOR('S', 4, unsigned int) -#define SSP_SPI _IOR('S', 5, unsigned int) -#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) -#define SSP_INPUT _IOR('S', 7, unsigned int) - -/* Values for SSP_SPEED */ -#define SSP150 0 -#define SSP300 1 -#define SSP600 2 -#define SSP1200 3 -#define SSP2400 4 -#define SSP4800 5 -#define SSP9600 6 -#define SSP19200 7 -#define SSP28800 8 -#define SSP57600 9 -#define SSP115200 10 -#define SSP230400 11 -#define SSP460800 12 -#define SSP921600 13 -#define SSP3125000 14 -#define CODEC 15 -#define CODEC_f32768 16 - -#define FREQ_4MHz 0 -#define FREQ_2MHz 1 -#define FREQ_1MHz 2 -#define FREQ_512kHz 3 -#define FREQ_256kHz 4 -#define FREQ_128kHz 5 -#define FREQ_64kHz 6 -#define FREQ_32kHz 7 -/* FREQ_* with values where bit (value & 0x10) is set are */ -/* used for CODEC_f32768 */ -#define FREQ_4096kHz 16 /* CODEC_f32768 */ - -/* Used by application to set CODEC divider, word rate and frame rate */ -#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \ - ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \ - (clk_per_sync << 16) | (sync_per_frame << 28)) - -/* Used by driver to extract speed */ -#define GET_SPEED(x) (x & 0xff) -#define GET_FREQ(x) ((x & 0xff00) >> 8) -#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) -#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) - -/* Values for SSP_MODE */ -#define MASTER_OUTPUT 0 -#define SLAVE_OUTPUT 1 -#define MASTER_INPUT 2 -#define SLAVE_INPUT 3 -#define MASTER_BIDIR 4 -#define SLAVE_BIDIR 5 - -/* Values for SSP_FRAME_SYNC */ -#define NORMAL_SYNC 1 -#define EARLY_SYNC 2 -#define SECOND_WORD_SYNC 0x40000 -#define LATE_SYNC 0x80000 - -#define BIT_SYNC 4 -#define WORD_SYNC 8 -#define EXTENDED_SYNC 0x10 - -#define SYNC_OFF 0x20 -#define SYNC_ON 0x40 -#define WORD_SIZE_8 0x80 -#define WORD_SIZE_12 0x100 -#define WORD_SIZE_16 0x200 -#define WORD_SIZE_24 0x400 -#define WORD_SIZE_32 0x800 -#define BIT_ORDER_LSB 0x1000 -#define BIT_ORDER_MSB 0x2000 -#define FLOW_CONTROL_ENABLE 0x4000 -#define FLOW_CONTROL_DISABLE 0x8000 -#define CLOCK_GATED 0x10000 -#define CLOCK_NOT_GATED 0x20000 - -/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ -#define CLOCK_NORMAL 1 -#define CLOCK_INVERT 2 -#define CLOCK_INEGEDGE CLOCK_NORMAL -#define CLOCK_IPOSEDGE CLOCK_INVERT -#define FRAME_NORMAL 4 -#define FRAME_INVERT 8 -#define STATUS_NORMAL 0x10 -#define STATUS_INVERT 0x20 - -/* Values for SSP_SPI */ -#define SPI_MASTER 0 -#define SPI_SLAVE 1 - -/* Values for SSP_INBUFCHUNK */ -/* plain integer with the size of DMA chunks */ - -/* To ensure that the timestamps are aligned with the data being read - * the read length MUST be a multiple of the length of the DMA buffers. - * - * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below. - */ -#define SSP_INPUT_CHUNK_SIZE 256 - -/* Request struct to pass through the ioctl interface to read - * data with timestamps. - */ -struct ssp_request { - char __user *buf; /* Where to put the data. */ - size_t len; /* Size of buf. MUST be a multiple of */ - /* SSP_INPUT_CHUNK_SIZE! */ - struct timespec ts; /* The time the data was sampled. */ -}; - -#endif diff --git a/arch/cris/include/uapi/asm/termbits.h b/arch/cris/include/uapi/asm/termbits.h deleted file mode 100644 index 86925dc1fcae..000000000000 --- a/arch/cris/include/uapi/asm/termbits.h +++ /dev/null @@ -1,236 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef __ARCH_ETRAX100_TERMBITS_H__ -#define __ARCH_ETRAX100_TERMBITS_H__ - -#include - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -/* - * 3 2 1 - * 10 987 654 321 098 765 432 109 876 543 210 - * | | ||| CBAUD - * obaud - * - * ||CSIZE - * - * |CSTOP - * |CREAD - * |CPARENB - * - * |CPARODD - * |HUPCL - * |CLOCAL - * |CBAUDEX - * 10 987 654 321 098 765 432 109 876 543 210 - * | || || CIBAUD, IBSHIFT=16 - * ibaud - * |CMSPAR - * | CRTSCTS - * x x xxx xxx x x xx Free bits - */ - -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 - -/* Unsupported rates, but needed to avoid compile error. */ -#define B500000 0010005 -#define B576000 0010006 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 - -/* etrax supports these additional three baud rates */ -#define B921600 0010005 -#define B1843200 0010006 -#define B6250000 0010007 -/* ETRAX FS supports this as well */ -#define B12500000 0010010 -#define CIBAUD 002003600000 /* input baud rate (used in v32) */ -/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX - * shifted left IBSHIFT bits. - */ -#define IBSHIFT 16 -#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ -#define CRTSCTS 020000000000 /* flow control */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 -#define EXTPROC 0200000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif diff --git a/arch/cris/include/uapi/asm/termios.h b/arch/cris/include/uapi/asm/termios.h deleted file mode 100644 index d87800a6d854..000000000000 --- a/arch/cris/include/uapi/asm/termios.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_CRIS_TERMIOS_H -#define _UAPI_CRIS_TERMIOS_H - -#include -#include -#include -#include - -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - - -#endif /* _UAPI_CRIS_TERMIOS_H */ diff --git a/arch/cris/include/uapi/asm/unistd.h b/arch/cris/include/uapi/asm/unistd.h deleted file mode 100644 index 7aba513b082d..000000000000 --- a/arch/cris/include/uapi/asm/unistd.h +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_ASM_CRIS_UNISTD_H_ -#define _UAPI_ASM_CRIS_UNISTD_H_ - -/* - * This file contains the system call numbers, and stub macros for libc. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_chown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_lchown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_chown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_mincore 218 -#define __NR_madvise 219 -#define __NR_getdents64 220 -#define __NR_fcntl64 221 -/* 223 is unused */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 -#define __NR_set_thread_area 243 -#define __NR_get_thread_area 244 -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 -#define __NR_fadvise64 250 -/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_epoll_create 254 -#define __NR_epoll_ctl 255 -#define __NR_epoll_wait 256 -#define __NR_remap_file_pages 257 -#define __NR_set_tid_address 258 -#define __NR_timer_create 259 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) -#define __NR_statfs64 268 -#define __NR_fstatfs64 269 -#define __NR_tgkill 270 -#define __NR_utimes 271 -#define __NR_fadvise64_64 272 -#define __NR_vserver 273 -#define __NR_mbind 274 -#define __NR_get_mempolicy 275 -#define __NR_set_mempolicy 276 -#define __NR_mq_open 277 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_kexec_load 283 -#define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 -#define __NR_migrate_pages 294 -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 -#define __NR_set_robust_list 311 -#define __NR_get_robust_list 312 -#define __NR_splice 313 -#define __NR_sync_file_range 314 -#define __NR_tee 315 -#define __NR_vmsplice 316 -#define __NR_move_pages 317 -#define __NR_getcpu 318 -#define __NR_epoll_pwait 319 -#define __NR_utimensat 320 -#define __NR_signalfd 321 -#define __NR_timerfd_create 322 -#define __NR_eventfd 323 -#define __NR_fallocate 324 -#define __NR_timerfd_settime 325 -#define __NR_timerfd_gettime 326 -#define __NR_signalfd4 327 -#define __NR_eventfd2 328 -#define __NR_epoll_create1 329 -#define __NR_dup3 330 -#define __NR_pipe2 331 -#define __NR_inotify_init1 332 -#define __NR_preadv 333 -#define __NR_pwritev 334 -#define __NR_setns 335 -#define __NR_name_to_handle_at 336 -#define __NR_open_by_handle_at 337 -#define __NR_rt_tgsigqueueinfo 338 -#define __NR_perf_event_open 339 -#define __NR_recvmmsg 340 -#define __NR_accept4 341 -#define __NR_fanotify_init 342 -#define __NR_fanotify_mark 343 -#define __NR_prlimit64 344 -#define __NR_clock_adjtime 345 -#define __NR_syncfs 346 -#define __NR_sendmmsg 347 -#define __NR_process_vm_readv 348 -#define __NR_process_vm_writev 349 -#define __NR_kcmp 350 -#define __NR_finit_module 351 -#define __NR_sched_setattr 352 -#define __NR_sched_getattr 353 -#define __NR_renameat2 354 -#define __NR_seccomp 355 -#define __NR_getrandom 356 -#define __NR_memfd_create 357 -#define __NR_bpf 358 -#define __NR_execveat 359 - -#endif /* _UAPI_ASM_CRIS_UNISTD_H_ */ diff --git a/arch/cris/kernel/Makefile b/arch/cris/kernel/Makefile deleted file mode 100644 index f6bfee6c8c1b..000000000000 --- a/arch/cris/kernel/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the CRIS port. -# - -CPPFLAGS_vmlinux.lds := -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE) -extra-y := vmlinux.lds - -obj-y := process.o traps.o irq.o ptrace.o setup.o time.o sys_cris.o -obj-y += stacktrace.o - -obj-$(CONFIG_MODULES) += crisksyms.o -obj-$(CONFIG_MODULES) += module.o -obj-$(CONFIG_SYSTEM_PROFILER) += profile.o - -clean: - diff --git a/arch/cris/kernel/asm-offsets.c b/arch/cris/kernel/asm-offsets.c deleted file mode 100644 index 0a5129941485..000000000000 --- a/arch/cris/kernel/asm-offsets.c +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -/* - * Generate definitions needed by assembly language modules. - * This code generates raw asm output which is post-processed to extract - * and format the required data. - */ - -#if !defined(CONFIG_ETRAX_ARCH_V10) && !defined(CONFIG_ETRAX_ARCH_V32) -#error One of ARCH v10 and ARCH v32 must be true! -#endif - -int main(void) -{ -#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry)) - ENTRY(orig_r10); - ENTRY(r13); - ENTRY(r12); - ENTRY(r11); - ENTRY(r10); - ENTRY(r9); -#ifdef CONFIG_ETRAX_ARCH_V32 - ENTRY(acr); - ENTRY(srs); -#endif - ENTRY(mof); -#ifdef CONFIG_ETRAX_ARCH_V10 - ENTRY(dccr); -#else - ENTRY(ccs); -#endif - ENTRY(srp); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry)) - ENTRY(task); - ENTRY(flags); - ENTRY(preempt_count); - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry)) - ENTRY(ksp); - ENTRY(usp); -#ifdef CONFIG_ETRAX_ARCH_V10 - ENTRY(dccr); -#else - ENTRY(ccs); -#endif - BLANK(); -#undef ENTRY -#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry)) - ENTRY(pid); - BLANK(); - DEFINE(LCLONE_VM, CLONE_VM); - DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED); - return 0; -} diff --git a/arch/cris/kernel/crisksyms.c b/arch/cris/kernel/crisksyms.c deleted file mode 100644 index 7024f7278c89..000000000000 --- a/arch/cris/kernel/crisksyms.c +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -extern void __Udiv(void); -extern void __Umod(void); -extern void __Div(void); -extern void __Mod(void); -extern void __ashldi3(void); -extern void __ashrdi3(void); -extern void __lshrdi3(void); -extern void __negdi2(void); -extern void iounmap(volatile void * __iomem); - -/* Platform dependent support */ -EXPORT_SYMBOL(loops_per_usec); - -/* Math functions */ -EXPORT_SYMBOL(__Udiv); -EXPORT_SYMBOL(__Umod); -EXPORT_SYMBOL(__Div); -EXPORT_SYMBOL(__Mod); -EXPORT_SYMBOL(__ashldi3); -EXPORT_SYMBOL(__ashrdi3); -EXPORT_SYMBOL(__lshrdi3); -EXPORT_SYMBOL(__negdi2); - -/* Memory functions */ -EXPORT_SYMBOL(__ioremap); -EXPORT_SYMBOL(iounmap); - -#undef memcpy -#undef memset -extern void * memset(void *, int, __kernel_size_t); -extern void * memcpy(void *, const void *, __kernel_size_t); -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memset); -#ifdef CONFIG_ETRAX_ARCH_V32 -#undef strcmp -EXPORT_SYMBOL(strcmp); -#endif - -#ifdef CONFIG_ETRAX_FAST_TIMER -/* Fast timer functions */ -EXPORT_SYMBOL(fast_timer_list); -EXPORT_SYMBOL(start_one_shot_timer); -EXPORT_SYMBOL(del_fast_timer); -EXPORT_SYMBOL(schedule_usleep); -#endif -EXPORT_SYMBOL(csum_partial); -EXPORT_SYMBOL(csum_partial_copy_from_user); -EXPORT_SYMBOL(csum_partial_copy_nocheck); diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c deleted file mode 100644 index 726cdf4bf2d8..000000000000 --- a/arch/cris/kernel/irq.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * - * linux/arch/cris/kernel/irq.c - * - * Copyright (c) 2000,2007 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - * This file contains the code used by various IRQ handling routines: - * asking for different IRQs should be done through these routines - * instead of just grabbing them. Thus setups with different IRQ numbers - * shouldn't result in any weird surprises, and installing new handlers - * should be easier. - * - */ - -/* - * IRQs are in fact implemented a bit like signal handlers for the kernel. - * Naturally it's not a 1:1 relation, but there are similarities. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -/* called by the assembler IRQ entry functions defined in irq.h - * to dispatch the interrupts to registered handlers - */ - -asmlinkage void do_IRQ(int irq, struct pt_regs * regs) -{ - unsigned long sp; - struct pt_regs *old_regs; - - trace_hardirqs_off(); - - old_regs = set_irq_regs(regs); - irq_enter(); - sp = rdsp(); - if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) { - printk("do_IRQ: stack overflow: %lX\n", sp); - show_stack(NULL, (unsigned long *)sp); - } - generic_handle_irq(irq); - irq_exit(); - set_irq_regs(old_regs); -} - -void weird_irq(void) -{ - local_irq_disable(); - printk("weird irq\n"); - while(1); -} - diff --git a/arch/cris/kernel/module.c b/arch/cris/kernel/module.c deleted file mode 100644 index af04cb6b6dc9..000000000000 --- a/arch/cris/kernel/module.c +++ /dev/null @@ -1,82 +0,0 @@ -/* Kernel module help for i386. - Copyright (C) 2001 Rusty Russell. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define DEBUGP printk -#else -#define DEBUGP(fmt , ...) -#endif - -#ifdef CONFIG_ETRAX_KMALLOCED_MODULES -void *module_alloc(unsigned long size) -{ - return kmalloc(size, GFP_KERNEL); -} - -/* Free memory returned from module_alloc */ -void module_memfree(void *module_region) -{ - kfree(module_region); -} -#endif - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr; - - DEBUGP ("Applying add relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - - for (i = 0; i < sechdrs[relsec].sh_size / sizeof (*rela); i++) { - /* This is where to make the change */ - uint32_t *loc - = ((void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rela[i].r_offset); - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - Elf32_Sym *sym - = ((Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM (rela[i].r_info)); - switch (ELF32_R_TYPE(rela[i].r_info)) { - case R_CRIS_32: - *loc = sym->st_value + rela[i].r_addend; - break; - case R_CRIS_32_PCREL: - *loc = sym->st_value - (unsigned)loc + rela[i].r_addend - 4; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rela[i].r_info)); - return -ENOEXEC; - } - } - - return 0; -} diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c deleted file mode 100644 index 50e5cf09841d..000000000000 --- a/arch/cris/kernel/process.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/process.c - * - * Copyright (C) 1995 Linus Torvalds - * Copyright (C) 2000-2002 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - */ - -/* - * This file handles the architecture-dependent parts of process handling.. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -//#define DEBUG - -extern void default_idle(void); - -void (*pm_power_off)(void); -EXPORT_SYMBOL(pm_power_off); - -void arch_cpu_idle(void) -{ - default_idle(); -} - -void hard_reset_now (void); - -void machine_restart(char *cmd) -{ - hard_reset_now(); -} - -/* - * Similar to machine_power_off, but don't shut off power. Add code - * here to freeze the system for e.g. post-mortem debug purpose when - * possible. This halt has nothing to do with the idle halt. - */ - -void machine_halt(void) -{ -} - -/* If or when software power-off is implemented, add code here. */ - -void machine_power_off(void) -{ -} - -/* - * When a process does an "exec", machine state like FPU and debug - * registers need to be reset. This is a hook function for that. - * Currently we don't have any such state to reset, so this is empty. - */ - -void flush_thread(void) -{ -} - -/* Fill in the fpu structure for a core dump. */ -int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu) -{ - return 0; -} diff --git a/arch/cris/kernel/profile.c b/arch/cris/kernel/profile.c deleted file mode 100644 index d2f978ad129a..000000000000 --- a/arch/cris/kernel/profile.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include - -#define SAMPLE_BUFFER_SIZE 8192 - -static char *sample_buffer; -static char *sample_buffer_pos; -static int prof_running = 0; - -void cris_profile_sample(struct pt_regs *regs) -{ - if (!prof_running) - return; - - if (user_mode(regs)) - *(unsigned int*)sample_buffer_pos = current->pid; - else - *(unsigned int*)sample_buffer_pos = 0; - - *(unsigned int *)(sample_buffer_pos + 4) = instruction_pointer(regs); - sample_buffer_pos += 8; - - if (sample_buffer_pos == sample_buffer + SAMPLE_BUFFER_SIZE) - sample_buffer_pos = sample_buffer; -} - -static ssize_t -read_cris_profile(struct file *file, char __user *buf, - size_t count, loff_t *ppos) -{ - unsigned long p = *ppos; - ssize_t ret; - - ret = simple_read_from_buffer(buf, count, ppos, sample_buffer, - SAMPLE_BUFFER_SIZE); - if (ret < 0) - return ret; - - memset(sample_buffer + p, 0, ret); - - return ret; -} - -static ssize_t -write_cris_profile(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) -{ - sample_buffer_pos = sample_buffer; - memset(sample_buffer, 0, SAMPLE_BUFFER_SIZE); - return count < SAMPLE_BUFFER_SIZE ? count : SAMPLE_BUFFER_SIZE; -} - -static const struct file_operations cris_proc_profile_operations = { - .read = read_cris_profile, - .write = write_cris_profile, - .llseek = default_llseek, -}; - -static int __init init_cris_profile(void) -{ - struct proc_dir_entry *entry; - - sample_buffer = kmalloc(SAMPLE_BUFFER_SIZE, GFP_KERNEL); - if (!sample_buffer) { - return -ENOMEM; - } - - sample_buffer_pos = sample_buffer; - - entry = proc_create("system_profile", S_IWUSR | S_IRUGO, NULL, - &cris_proc_profile_operations); - if (entry) { - proc_set_size(entry, SAMPLE_BUFFER_SIZE); - } - prof_running = 1; - - return 0; -} -__initcall(init_cris_profile); - diff --git a/arch/cris/kernel/ptrace.c b/arch/cris/kernel/ptrace.c deleted file mode 100644 index af42789a1544..000000000000 --- a/arch/cris/kernel/ptrace.c +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/ptrace.c - * - * Parts taken from the m68k port. - * - * Copyright (c) 2000, 2001, 2002 Axis Communications AB - * - * Authors: Bjorn Wesen - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - - -/* notification of userspace execution resumption - * - triggered by current->work.notify_resume - */ -extern int do_signal(int canrestart, struct pt_regs *regs); - - -void do_notify_resume(int canrestart, struct pt_regs *regs, - __u32 thread_info_flags) -{ - /* deal with pending signal delivery */ - if (thread_info_flags & _TIF_SIGPENDING) - do_signal(canrestart,regs); - - if (thread_info_flags & _TIF_NOTIFY_RESUME) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - } -} - -void do_work_pending(int syscall, struct pt_regs *regs, - unsigned int thread_flags) -{ - do { - if (likely(thread_flags & _TIF_NEED_RESCHED)) { - schedule(); - } else { - if (unlikely(!user_mode(regs))) - return; - local_irq_enable(); - if (thread_flags & _TIF_SIGPENDING) { - do_signal(syscall, regs); - syscall = 0; - } else { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - } - } - local_irq_disable(); - thread_flags = current_thread_info()->flags; - } while (thread_flags & _TIF_WORK_MASK); -} diff --git a/arch/cris/kernel/setup.c b/arch/cris/kernel/setup.c deleted file mode 100644 index 1b61a7207afb..000000000000 --- a/arch/cris/kernel/setup.c +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * - * linux/arch/cris/kernel/setup.c - * - * Copyright (C) 1995 Linus Torvalds - * Copyright (c) 2001 Axis Communications AB - */ - -/* - * This file handles the architecture-dependent parts of initialization - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Setup options - */ -struct screen_info screen_info; - -extern int root_mountflags; - -char __initdata cris_command_line[COMMAND_LINE_SIZE] = { 0, }; - -extern const unsigned long text_start, edata; /* set by the linker script */ -extern unsigned long dram_start, dram_end; - -extern unsigned long romfs_start, romfs_length, romfs_in_flash; /* from head.S */ - -static struct cpu cpu_devices[NR_CPUS]; - -extern void show_etrax_copyright(void); /* arch-vX/kernel/setup.c */ - -/* This mainly sets up the memory area, and can be really confusing. - * - * The physical DRAM is virtually mapped into dram_start to dram_end - * (usually c0000000 to c0000000 + DRAM size). The physical address is - * given by the macro __pa(). - * - * In this DRAM, the kernel code and data is loaded, in the beginning. - * It really starts at c0004000 to make room for some special pages - - * the start address is text_start. The kernel data ends at _end. After - * this the ROM filesystem is appended (if there is any). - * - * Between this address and dram_end, we have RAM pages usable to the - * boot code and the system. - * - */ - -void __init setup_arch(char **cmdline_p) -{ - extern void init_etrax_debug(void); - unsigned long bootmap_size; - unsigned long start_pfn, max_pfn; - unsigned long memory_start; - -#ifdef CONFIG_OF - early_init_dt_scan(__dtb_start); -#endif - - /* register an initial console printing routine for printk's */ - - init_etrax_debug(); - - /* we should really poll for DRAM size! */ - - high_memory = &dram_end; - - if(romfs_in_flash || !romfs_length) { - /* if we have the romfs in flash, or if there is no rom filesystem, - * our free area starts directly after the BSS - */ - memory_start = (unsigned long) &_end; - } else { - /* otherwise the free area starts after the ROM filesystem */ - printk("ROM fs in RAM, size %lu bytes\n", romfs_length); - memory_start = romfs_start + romfs_length; - } - - /* process 1's initial memory region is the kernel code/data */ - - init_mm.start_code = (unsigned long) &text_start; - init_mm.end_code = (unsigned long) &_etext; - init_mm.end_data = (unsigned long) &_edata; - init_mm.brk = (unsigned long) &_end; - - /* min_low_pfn points to the start of DRAM, start_pfn points - * to the first DRAM pages after the kernel, and max_low_pfn - * to the end of DRAM. - */ - - /* - * partially used pages are not usable - thus - * we are rounding upwards: - */ - - start_pfn = PFN_UP(memory_start); /* usually c0000000 + kernel + romfs */ - max_pfn = PFN_DOWN((unsigned long)high_memory); /* usually c0000000 + dram size */ - - /* - * Initialize the boot-time allocator (start, end) - * - * We give it access to all our DRAM, but we could as well just have - * given it a small slice. No point in doing that though, unless we - * have non-contiguous memory and want the boot-stuff to be in, say, - * the smallest area. - * - * It will put a bitmap of the allocated pages in the beginning - * of the range we give it, but it won't mark the bitmaps pages - * as reserved. We have to do that ourselves below. - * - * We need to use init_bootmem_node instead of init_bootmem - * because our map starts at a quite high address (min_low_pfn). - */ - - max_low_pfn = max_pfn; - min_low_pfn = PAGE_OFFSET >> PAGE_SHIFT; - - bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn, - min_low_pfn, - max_low_pfn); - - /* And free all memory not belonging to the kernel (addr, size) */ - - free_bootmem(PFN_PHYS(start_pfn), PFN_PHYS(max_pfn - start_pfn)); - - /* - * Reserve the bootmem bitmap itself as well. We do this in two - * steps (first step was init_bootmem()) because this catches - * the (very unlikely) case of us accidentally initializing the - * bootmem allocator with an invalid RAM area. - * - * Arguments are start, size - */ - - reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT); - - unflatten_and_copy_device_tree(); - - /* paging_init() sets up the MMU and marks all pages as reserved */ - - paging_init(); - - *cmdline_p = cris_command_line; - -#ifdef CONFIG_ETRAX_CMDLINE - if (!strcmp(cris_command_line, "")) { - strlcpy(cris_command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE); - cris_command_line[COMMAND_LINE_SIZE - 1] = '\0'; - } -#endif - - /* Save command line for future references. */ - memcpy(boot_command_line, cris_command_line, COMMAND_LINE_SIZE); - boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; - - /* give credit for the CRIS port */ - show_etrax_copyright(); - - /* Setup utsname */ - strcpy(init_utsname()->machine, cris_machine_name); -} - -#ifdef CONFIG_PROC_FS -static void *c_start(struct seq_file *m, loff_t *pos) -{ - return *pos < nr_cpu_ids ? (void *)(int)(*pos + 1) : NULL; -} - -static void *c_next(struct seq_file *m, void *v, loff_t *pos) -{ - ++*pos; - return c_start(m, pos); -} - -static void c_stop(struct seq_file *m, void *v) -{ -} - -extern int show_cpuinfo(struct seq_file *m, void *v); - -const struct seq_operations cpuinfo_op = { - .start = c_start, - .next = c_next, - .stop = c_stop, - .show = show_cpuinfo, -}; -#endif /* CONFIG_PROC_FS */ - -static int __init topology_init(void) -{ - int i; - - for_each_possible_cpu(i) { - return register_cpu(&cpu_devices[i], i); - } - - return 0; -} - -subsys_initcall(topology_init); diff --git a/arch/cris/kernel/stacktrace.c b/arch/cris/kernel/stacktrace.c deleted file mode 100644 index f1cc3aaacd8d..000000000000 --- a/arch/cris/kernel/stacktrace.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include -#include - -void walk_stackframe(unsigned long sp, - int (*fn)(unsigned long addr, void *data), - void *data) -{ - unsigned long high = ALIGN(sp, THREAD_SIZE); - - for (; sp <= high - 4; sp += 4) { - unsigned long addr = *(unsigned long *) sp; - - if (!kernel_text_address(addr)) - continue; - - if (fn(addr, data)) - break; - } -} - -struct stack_trace_data { - struct stack_trace *trace; - unsigned int no_sched_functions; - unsigned int skip; -}; - -#ifdef CONFIG_STACKTRACE - -static int save_trace(unsigned long addr, void *d) -{ - struct stack_trace_data *data = d; - struct stack_trace *trace = data->trace; - - if (data->no_sched_functions && in_sched_functions(addr)) - return 0; - - if (data->skip) { - data->skip--; - return 0; - } - - trace->entries[trace->nr_entries++] = addr; - - return trace->nr_entries >= trace->max_entries; -} - -void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) -{ - struct stack_trace_data data; - unsigned long sp; - - data.trace = trace; - data.skip = trace->skip; - - if (tsk != current) { - data.no_sched_functions = 1; - sp = tsk->thread.ksp; - } else { - data.no_sched_functions = 0; - sp = rdsp(); - } - - walk_stackframe(sp, save_trace, &data); - if (trace->nr_entries < trace->max_entries) - trace->entries[trace->nr_entries++] = ULONG_MAX; -} - -void save_stack_trace(struct stack_trace *trace) -{ - save_stack_trace_tsk(current, trace); -} -EXPORT_SYMBOL_GPL(save_stack_trace); - -#endif /* CONFIG_STACKTRACE */ diff --git a/arch/cris/kernel/sys_cris.c b/arch/cris/kernel/sys_cris.c deleted file mode 100644 index ecea13f1d760..000000000000 --- a/arch/cris/kernel/sys_cris.c +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* $Id: sys_cris.c,v 1.6 2004/03/11 11:38:40 starvik Exp $ - * - * linux/arch/cris/kernel/sys_cris.c - * - * This file contains various random system calls that - * have a non-standard calling sequence on some platforms. - * Since we don't have to do any backwards compatibility, our - * versions are done in the most "normal" way possible. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -asmlinkage long -sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, - unsigned long flags, unsigned long fd, unsigned long pgoff) -{ - /* bug(?): 8Kb pages here */ - return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff); -} diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c deleted file mode 100644 index 593239274f98..000000000000 --- a/arch/cris/kernel/time.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/kernel/time.c - * - * Copyright (C) 1991, 1992, 1995 Linus Torvalds - * Copyright (C) 1999, 2000, 2001 Axis Communications AB - * - * 1994-07-02 Alan Modra - * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime - * 1995-03-26 Markus Kuhn - * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887 - * precision CMOS clock update - * 1996-05-03 Ingo Molnar - * fixed time warps in do_[slow|fast]_gettimeoffset() - * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 - * "A Kernel Model for Precision Timekeeping" by Dave Mills - * - * Linux/CRIS specific code: - * - * Authors: Bjorn Wesen - * Johan Adolfsson - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -#define D(x) - -#define TICK_SIZE tick - -extern unsigned long loops_per_jiffy; /* init/main.c */ -unsigned long loops_per_usec; - -extern void cris_profile_sample(struct pt_regs* regs); - -void -cris_do_profile(struct pt_regs* regs) -{ - -#ifdef CONFIG_SYSTEM_PROFILER - cris_profile_sample(regs); -#endif - -#ifdef CONFIG_PROFILING - profile_tick(CPU_PROFILING); -#endif -} - -#ifndef CONFIG_GENERIC_SCHED_CLOCK -unsigned long long sched_clock(void) -{ - return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ) + - get_ns_in_jiffie(); -} -#endif - -static int -__init init_udelay(void) -{ - loops_per_usec = (loops_per_jiffy * HZ) / 1000000; - return 0; -} - -__initcall(init_udelay); diff --git a/arch/cris/kernel/traps.c b/arch/cris/kernel/traps.c deleted file mode 100644 index d4bc80469218..000000000000 --- a/arch/cris/kernel/traps.c +++ /dev/null @@ -1,241 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/traps.c - * - * Here we handle the break vectors not used by the system call - * mechanism, as well as some general stack/register dumping - * things. - * - * Copyright (C) 2000-2007 Axis Communications AB - * - * Authors: Bjorn Wesen - * Hans-Peter Nilsson - * - */ - -#include -#include -#include -#include -#ifdef CONFIG_KALLSYMS -#include -#endif - -#include -#include -#include - -extern void arch_enable_nmi(void); -extern void stop_watchdog(void); -extern void reset_watchdog(void); -extern void show_registers(struct pt_regs *regs); - -#ifdef CONFIG_DEBUG_BUGVERBOSE -extern void handle_BUG(struct pt_regs *regs); -#else -#define handle_BUG(regs) -#endif - -static int kstack_depth_to_print = 24; - -void (*nmi_handler)(struct pt_regs *); - -void show_trace(unsigned long *stack) -{ - unsigned long addr, module_start, module_end; - extern char _stext[], _etext[]; - int i; - - pr_err("\nCall Trace: "); - - i = 1; - module_start = VMALLOC_START; - module_end = VMALLOC_END; - - while (((long)stack & (THREAD_SIZE - 1)) != 0) { - if (__get_user(addr, stack)) { - /* This message matches "failing address" marked - s390 in ksymoops, so lines containing it will - not be filtered out by ksymoops. */ - pr_err("Failing address 0x%lx\n", (unsigned long)stack); - break; - } - stack++; - - /* - * If the address is either in the text segment of the - * kernel, or in the region which contains vmalloc'ed - * memory, it *may* be the address of a calling - * routine; if so, print it so that someone tracing - * down the cause of the crash will be able to figure - * out the call path that was taken. - */ - if (((addr >= (unsigned long)_stext) && - (addr <= (unsigned long)_etext)) || - ((addr >= module_start) && (addr <= module_end))) { -#ifdef CONFIG_KALLSYMS - print_ip_sym(addr); -#else - if (i && ((i % 8) == 0)) - pr_err("\n "); - pr_err("[<%08lx>] ", addr); - i++; -#endif - } - } -} - -/* - * These constants are for searching for possible module text - * segments. MODULE_RANGE is a guess of how much space is likely - * to be vmalloced. - */ - -#define MODULE_RANGE (8*1024*1024) - -/* - * The output (format, strings and order) is adjusted to be usable with - * ksymoops-2.4.1 with some necessary CRIS-specific patches. Please don't - * change it unless you're serious about adjusting ksymoops and syncing - * with the ksymoops maintainer. - */ - -void -show_stack(struct task_struct *task, unsigned long *sp) -{ - unsigned long *stack, addr; - int i; - - /* - * debugging aid: "show_stack(NULL);" prints a - * back trace. - */ - - if (sp == NULL) { - if (task) - sp = (unsigned long*)task->thread.ksp; - else - sp = (unsigned long*)rdsp(); - } - - stack = sp; - - pr_err("\nStack from %08lx:\n ", (unsigned long)stack); - for (i = 0; i < kstack_depth_to_print; i++) { - if (((long)stack & (THREAD_SIZE-1)) == 0) - break; - if (i && ((i % 8) == 0)) - pr_err("\n "); - if (__get_user(addr, stack)) { - /* This message matches "failing address" marked - s390 in ksymoops, so lines containing it will - not be filtered out by ksymoops. */ - pr_err("Failing address 0x%lx\n", (unsigned long)stack); - break; - } - stack++; - pr_err("%08lx ", addr); - } - show_trace(sp); -} - -#if 0 -/* displays a short stack trace */ - -int -show_stack(void) -{ - unsigned long *sp = (unsigned long *)rdusp(); - int i; - - pr_err("Stack dump [0x%08lx]:\n", (unsigned long)sp); - for (i = 0; i < 16; i++) - pr_err("sp + %d: 0x%08lx\n", i*4, sp[i]); - return 0; -} -#endif - -void set_nmi_handler(void (*handler)(struct pt_regs *)) -{ - nmi_handler = handler; - arch_enable_nmi(); -} - -#ifdef CONFIG_DEBUG_NMI_OOPS -void oops_nmi_handler(struct pt_regs *regs) -{ - stop_watchdog(); - oops_in_progress = 1; - pr_err("NMI!\n"); - show_registers(regs); - oops_in_progress = 0; - oops_exit(); - pr_err("\n"); /* Flush mtdoops. */ -} - -static int __init oops_nmi_register(void) -{ - set_nmi_handler(oops_nmi_handler); - return 0; -} - -__initcall(oops_nmi_register); - -#endif - -/* - * This gets called from entry.S when the watchdog has bitten. Show something - * similar to an Oops dump, and if the kernel is configured to be a nice - * doggy, then halt instead of reboot. - */ -void watchdog_bite_hook(struct pt_regs *regs) -{ -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - local_irq_disable(); - stop_watchdog(); - show_registers(regs); - - while (1) - ; /* Do nothing. */ -#else - show_registers(regs); -#endif -} - -/* This is normally the Oops function. */ -void die_if_kernel(const char *str, struct pt_regs *regs, long err) -{ - if (user_mode(regs)) - return; - -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - /* - * This printout might take too long and could trigger - * the watchdog normally. If NICE_DOGGY is set, simply - * stop the watchdog during the printout. - */ - stop_watchdog(); -#endif - - oops_enter(); - handle_BUG(regs); - - pr_err("Linux %s %s\n", utsname()->release, utsname()->version); - pr_err("%s: %04lx\n", str, err & 0xffff); - - show_registers(regs); - - oops_exit(); - oops_in_progress = 0; - pr_err("\n"); /* Flush mtdoops. */ - -#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY - reset_watchdog(); -#endif - do_exit(SIGSEGV); -} - -void __init trap_init(void) -{ - /* Nothing needs to be done */ -} diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S deleted file mode 100644 index 9b232e0f673e..000000000000 --- a/arch/cris/kernel/vmlinux.lds.S +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* ld script to make the Linux/CRIS kernel - * Authors: Bjorn Wesen (bjornw@axis.com) - * - * It is VERY DANGEROUS to fiddle around with the symbols in this - * script. It is for example quite vital that all generated sections - * that are used are actually named here, otherwise the linker will - * put them at the end, where the init stuff is which is FREED after - * the kernel has booted. - */ - -#include -#include -#include - -#ifdef CONFIG_ETRAX_VMEM_SIZE -#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE -#else -#define __CONFIG_ETRAX_VMEM_SIZE 0 -#endif - - -jiffies = jiffies_64; -SECTIONS -{ - . = DRAM_VIRTUAL_BASE; - dram_start = .; -#ifdef CONFIG_ETRAX_ARCH_V10 - ibr_start = .; -#else - ebp_start = .; - /* The boot section is only necessary until the VCS top */ - /* level testbench includes both flash and DRAM. */ - .boot : { *(.boot) } -#endif - - /* see head.S and pages reserved at the start */ - . = DRAM_VIRTUAL_BASE + 0x4000; - - _text = .; /* Text and read-only data. */ - text_start = .; /* Lots of aliases. */ - _stext = .; - __stext = .; - .text : { - HEAD_TEXT - TEXT_TEXT - SCHED_TEXT - CPUIDLE_TEXT - LOCK_TEXT - *(.fixup) - *(.text.__*) - } - - _etext = . ; /* End of text section. */ - __etext = .; - - EXCEPTION_TABLE(4) - - _sdata = .; - RODATA - - . = ALIGN (4); - ___data_start = . ; - __Sdata = . ; - .data : { /* Data */ - CACHELINE_ALIGNED_DATA(32) - READ_MOSTLY_DATA(32) - DATA_DATA - } - __edata = . ; /* End of data section. */ - _edata = . ; - - BUG_TABLE - - INIT_TASK_DATA_SECTION(PAGE_SIZE) - - . = ALIGN(PAGE_SIZE); /* Init code and data. */ - __init_begin = .; - INIT_TEXT_SECTION(PAGE_SIZE) - .init.data : { INIT_DATA } - .init.setup : { INIT_SETUP(16) } - .initcall.init : { - INIT_CALLS - } - - .con_initcall.init : { - CON_INITCALL - } - SECURITY_INIT - - /* .exit.text is discarded at runtime, not link time, - * to deal with references from __bug_table - */ - .exit.text : { - EXIT_TEXT - } - .exit.data : { - EXIT_DATA - } - -#ifdef CONFIG_ETRAX_ARCH_V10 -#ifdef CONFIG_BLK_DEV_INITRD - .init.ramfs : { - __initramfs_start = .; - *(.init.ramfs) - __initramfs_end = .; - } -#endif -#endif - __vmlinux_end = .; /* Last address of the physical file. */ -#ifdef CONFIG_ETRAX_ARCH_V32 - PERCPU_SECTION(32) - - .init.ramfs : { - INIT_RAM_FS - } -#endif - - /* - * We fill to the next page, so we can discard all init - * pages without needing to consider what payload might be - * appended to the kernel image. - */ - . = ALIGN(PAGE_SIZE); - - __init_end = .; - - __data_end = . ; /* Move to _edata ? */ - BSS_SECTION(1, 1, 1) - - . = ALIGN (0x20); - _end = .; - __end = .; - - dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024; - - DISCARDS -} diff --git a/arch/cris/mm/Makefile b/arch/cris/mm/Makefile deleted file mode 100644 index d3ae08c90b4e..000000000000 --- a/arch/cris/mm/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile for the linux cris-specific parts of the memory manager. -# - -obj-y := init.o fault.o tlb.o ioremap.o - diff --git a/arch/cris/mm/fault.c b/arch/cris/mm/fault.c deleted file mode 100644 index 29cc58038b98..000000000000 --- a/arch/cris/mm/fault.c +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * arch/cris/mm/fault.c - * - * Copyright (C) 2000-2010 Axis Communications AB - */ - -#include -#include -#include -#include -#include -#include -#include - -extern int find_fixup_code(struct pt_regs *); -extern void die_if_kernel(const char *, struct pt_regs *, long); -extern void show_registers(struct pt_regs *regs); - -/* debug of low-level TLB reload */ -#undef DEBUG - -#ifdef DEBUG -#define D(x) x -#else -#define D(x) -#endif - -/* debug of higher-level faults */ -#define DPG(x) - -/* current active page directory */ - -DEFINE_PER_CPU(pgd_t *, current_pgd); -unsigned long cris_signal_return_page; - -/* - * This routine handles page faults. It determines the address, - * and the problem, and then passes it off to one of the appropriate - * routines. - * - * Notice that the address we're given is aligned to the page the fault - * occurred in, since we only get the PFN in R_MMU_CAUSE not the complete - * address. - * - * error_code: - * bit 0 == 0 means no page found, 1 means protection fault - * bit 1 == 0 means read, 1 means write - * - * If this routine detects a bad access, it returns 1, otherwise it - * returns 0. - */ - -asmlinkage void -do_page_fault(unsigned long address, struct pt_regs *regs, - int protection, int writeaccess) -{ - struct task_struct *tsk; - struct mm_struct *mm; - struct vm_area_struct * vma; - siginfo_t info; - int fault; - unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; - - D(printk(KERN_DEBUG - "Page fault for %lX on %X at %lX, prot %d write %d\n", - address, smp_processor_id(), instruction_pointer(regs), - protection, writeaccess)); - - tsk = current; - - /* - * We fault-in kernel-space virtual memory on-demand. The - * 'reference' page table is init_mm.pgd. - * - * NOTE! We MUST NOT take any locks for this case. We may - * be in an interrupt or a critical region, and should - * only copy the information from the master page table, - * nothing more. - * - * NOTE2: This is done so that, when updating the vmalloc - * mappings we don't have to walk all processes pgdirs and - * add the high mappings all at once. Instead we do it as they - * are used. However vmalloc'ed page entries have the PAGE_GLOBAL - * bit set so sometimes the TLB can use a lingering entry. - * - * This verifies that the fault happens in kernel space - * and that the fault was not a protection error (error_code & 1). - */ - - if (address >= VMALLOC_START && - !protection && - !user_mode(regs)) - goto vmalloc_fault; - - /* When stack execution is not allowed we store the signal - * trampolines in the reserved cris_signal_return_page. - * Handle this in the exact same way as vmalloc (we know - * that the mapping is there and is valid so no need to - * call handle_mm_fault). - */ - if (cris_signal_return_page && - address == cris_signal_return_page && - !protection && user_mode(regs)) - goto vmalloc_fault; - - /* we can and should enable interrupts at this point */ - local_irq_enable(); - - mm = tsk->mm; - info.si_code = SEGV_MAPERR; - - /* - * If we're in an interrupt, have pagefaults disabled or have no - * user context, we must not take the fault. - */ - - if (faulthandler_disabled() || !mm) - goto no_context; - - if (user_mode(regs)) - flags |= FAULT_FLAG_USER; -retry: - down_read(&mm->mmap_sem); - vma = find_vma(mm, address); - if (!vma) - goto bad_area; - if (vma->vm_start <= address) - goto good_area; - if (!(vma->vm_flags & VM_GROWSDOWN)) - goto bad_area; - if (user_mode(regs)) { - /* - * accessing the stack below usp is always a bug. - * we get page-aligned addresses so we can only check - * if we're within a page from usp, but that might be - * enough to catch brutal errors at least. - */ - if (address + PAGE_SIZE < rdusp()) - goto bad_area; - } - if (expand_stack(vma, address)) - goto bad_area; - - /* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. - */ - - good_area: - info.si_code = SEGV_ACCERR; - - /* first do some preliminary protection checks */ - - if (writeaccess == 2){ - if (!(vma->vm_flags & VM_EXEC)) - goto bad_area; - } else if (writeaccess == 1) { - if (!(vma->vm_flags & VM_WRITE)) - goto bad_area; - flags |= FAULT_FLAG_WRITE; - } else { - if (!(vma->vm_flags & (VM_READ | VM_EXEC))) - goto bad_area; - } - - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ - - fault = handle_mm_fault(vma, address, flags); - - if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) - return; - - if (unlikely(fault & VM_FAULT_ERROR)) { - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGSEGV) - goto bad_area; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - BUG(); - } - - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_MAJOR) - tsk->maj_flt++; - else - tsk->min_flt++; - if (fault & VM_FAULT_RETRY) { - flags &= ~FAULT_FLAG_ALLOW_RETRY; - flags |= FAULT_FLAG_TRIED; - - /* - * No need to up_read(&mm->mmap_sem) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - - goto retry; - } - } - - up_read(&mm->mmap_sem); - return; - - /* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ - - bad_area: - up_read(&mm->mmap_sem); - - bad_area_nosemaphore: - DPG(show_registers(regs)); - - /* User mode accesses just cause a SIGSEGV */ - - if (user_mode(regs)) { -#ifdef CONFIG_NO_SEGFAULT_TERMINATION - DECLARE_WAIT_QUEUE_HEAD(wq); -#endif - printk(KERN_NOTICE "%s (pid %d) segfaults for page " - "address %08lx at pc %08lx\n", - tsk->comm, tsk->pid, - address, instruction_pointer(regs)); - - /* With DPG on, we've already dumped registers above. */ - DPG(if (0)) - show_registers(regs); - -#ifdef CONFIG_NO_SEGFAULT_TERMINATION - wait_event_interruptible(wq, 0 == 1); -#else - info.si_signo = SIGSEGV; - info.si_errno = 0; - /* info.si_code has been set above */ - info.si_addr = (void *)address; - force_sig_info(SIGSEGV, &info, tsk); -#endif - return; - } - - no_context: - - /* Are we prepared to handle this kernel fault? - * - * (The kernel has valid exception-points in the source - * when it accesses user-memory. When it fails in one - * of those points, we find it in a table and do a jump - * to some fixup code that loads an appropriate error - * code) - */ - - if (find_fixup_code(regs)) - return; - - /* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - */ - - if (!oops_in_progress) { - oops_in_progress = 1; - if ((unsigned long) (address) < PAGE_SIZE) - printk(KERN_ALERT "Unable to handle kernel NULL " - "pointer dereference"); - else - printk(KERN_ALERT "Unable to handle kernel access" - " at virtual address %08lx\n", address); - - die_if_kernel("Oops", regs, (writeaccess << 1) | protection); - oops_in_progress = 0; - } - - do_exit(SIGKILL); - - /* - * We ran out of memory, or some other thing happened to us that made - * us unable to handle the page fault gracefully. - */ - - out_of_memory: - up_read(&mm->mmap_sem); - if (!user_mode(regs)) - goto no_context; - pagefault_out_of_memory(); - return; - - do_sigbus: - up_read(&mm->mmap_sem); - - /* - * Send a sigbus, regardless of whether we were in kernel - * or user mode. - */ - info.si_signo = SIGBUS; - info.si_errno = 0; - info.si_code = BUS_ADRERR; - info.si_addr = (void *)address; - force_sig_info(SIGBUS, &info, tsk); - - /* Kernel mode? Handle exceptions or die */ - if (!user_mode(regs)) - goto no_context; - return; - -vmalloc_fault: - { - /* - * Synchronize this task's top level page-table - * with the 'reference' page table. - * - * Use current_pgd instead of tsk->active_mm->pgd - * since the latter might be unavailable if this - * code is executed in a misfortunately run irq - * (like inside schedule() between switch_mm and - * switch_to...). - */ - - int offset = pgd_index(address); - pgd_t *pgd, *pgd_k; - pud_t *pud, *pud_k; - pmd_t *pmd, *pmd_k; - pte_t *pte_k; - - pgd = (pgd_t *)per_cpu(current_pgd, smp_processor_id()) + offset; - pgd_k = init_mm.pgd + offset; - - /* Since we're two-level, we don't need to do both - * set_pgd and set_pmd (they do the same thing). If - * we go three-level at some point, do the right thing - * with pgd_present and set_pgd here. - * - * Also, since the vmalloc area is global, we don't - * need to copy individual PTE's, it is enough to - * copy the pgd pointer into the pte page of the - * root task. If that is there, we'll find our pte if - * it exists. - */ - - pud = pud_offset(pgd, address); - pud_k = pud_offset(pgd_k, address); - if (!pud_present(*pud_k)) - goto no_context; - - pmd = pmd_offset(pud, address); - pmd_k = pmd_offset(pud_k, address); - - if (!pmd_present(*pmd_k)) - goto bad_area_nosemaphore; - - set_pmd(pmd, *pmd_k); - - /* Make sure the actual PTE exists as well to - * catch kernel vmalloc-area accesses to non-mapped - * addresses. If we don't do this, this will just - * silently loop forever. - */ - - pte_k = pte_offset_kernel(pmd_k, address); - if (!pte_present(*pte_k)) - goto no_context; - - return; - } -} - -/* Find fixup code. */ -int -find_fixup_code(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - /* in case of delay slot fault (v32) */ - unsigned long ip = (instruction_pointer(regs) & ~0x1); - - fixup = search_exception_tables(ip); - if (fixup != 0) { - /* Adjust the instruction pointer in the stackframe. */ - instruction_pointer(regs) = fixup->fixup; - arch_fixup(regs); - return 1; - } - - return 0; -} diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c deleted file mode 100644 index e41d9c833e1c..000000000000 --- a/arch/cris/mm/init.c +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/mm/init.c - * - * Copyright (C) 1995 Linus Torvalds - * Copyright (C) 2000,2001 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - */ - -#include -#include -#include -#include -#include -#include -#include - -unsigned long empty_zero_page; -EXPORT_SYMBOL(empty_zero_page); - -void __init mem_init(void) -{ - BUG_ON(!mem_map); - - /* max/min_low_pfn was set by setup.c - * now we just copy it to some other necessary places... - * - * high_memory was also set in setup.c - */ - max_mapnr = max_low_pfn - min_low_pfn; - free_all_bootmem(); - mem_init_print_info(NULL); -} - -/* Free a range of init pages. Virtual addresses. */ - -void free_init_pages(const char *what, unsigned long begin, unsigned long end) -{ - unsigned long addr; - - for (addr = begin; addr < end; addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page(addr)); - init_page_count(virt_to_page(addr)); - free_page(addr); - totalram_pages++; - } - - printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); -} - -/* Free the pages occupied by initialization code. */ - -void free_initmem(void) -{ - free_initmem_default(-1); -} - -/* Free the pages occupied by initrd code. */ - -#ifdef CONFIG_BLK_DEV_INITRD -void free_initrd_mem(unsigned long start, unsigned long end) -{ - free_init_pages("initrd memory", - start, - end); -} -#endif diff --git a/arch/cris/mm/ioremap.c b/arch/cris/mm/ioremap.c deleted file mode 100644 index 350bd2a86ade..000000000000 --- a/arch/cris/mm/ioremap.c +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * arch/cris/mm/ioremap.c - * - * Re-map IO memory to kernel address space so that we can access it. - * Needed for memory-mapped I/O devices mapped outside our normal DRAM - * window (that is, all memory-mapped I/O devices). - * - * (C) Copyright 1995 1996 Linus Torvalds - * CRIS-port by Axis Communications AB - */ - -#include -#include -#include -#include - -/* - * Generic mapping function (not visible outside): - */ - -/* - * Remap an arbitrary physical address space into the kernel virtual - * address space. Needed when the kernel wants to access high addresses - * directly. - * - * NOTE! We need to allow non-page-aligned mappings too: we will obviously - * have to convert them into an offset in a page-aligned mapping, but the - * caller shouldn't need to know that small detail. - */ -void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot) -{ - void __iomem * addr; - struct vm_struct * area; - unsigned long offset, last_addr; - - /* Don't allow wraparound or zero size */ - last_addr = phys_addr + size - 1; - if (!size || last_addr < phys_addr) - return NULL; - - /* - * Mappings have to be page-aligned - */ - offset = phys_addr & ~PAGE_MASK; - phys_addr &= PAGE_MASK; - size = PAGE_ALIGN(last_addr+1) - phys_addr; - - /* - * Ok, go for it.. - */ - area = get_vm_area(size, VM_IOREMAP); - if (!area) - return NULL; - addr = (void __iomem *)area->addr; - if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size, - phys_addr, prot)) { - vfree((void __force *)addr); - return NULL; - } - return (void __iomem *) (offset + (char __iomem *)addr); -} - -void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) -{ - return __ioremap_prot(phys_addr, size, - __pgprot(_PAGE_PRESENT | __READABLE | - __WRITEABLE | _PAGE_GLOBAL | - _PAGE_KERNEL | flags)); -} - -/** - * ioremap_nocache - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - * - * Must be freed with iounmap. - */ - -void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size) -{ - return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0); -} -EXPORT_SYMBOL(ioremap_nocache); - -void iounmap(volatile void __iomem *addr) -{ - if (addr > high_memory) - return vfree((void *) (PAGE_MASK & (unsigned long) addr)); -} diff --git a/arch/cris/mm/tlb.c b/arch/cris/mm/tlb.c deleted file mode 100644 index e0dbea62cb81..000000000000 --- a/arch/cris/mm/tlb.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/cris/mm/tlb.c - * - * Copyright (C) 2000, 2001 Axis Communications AB - * - * Authors: Bjorn Wesen (bjornw@axis.com) - * - */ - -#include -#include -#include - -#include - -#define D(x) - -/* The TLB can host up to 64 different mm contexts at the same time. - * The running context is R_MMU_CONTEXT, and each TLB entry contains a - * page_id that has to match to give a hit. In page_id_map, we keep track - * of which mm we have assigned to which page_id, so that we know when - * to invalidate TLB entries. - * - * The last page_id is never running - it is used as an invalid page_id - * so we can make TLB entries that will never match. - * - * Notice that we need to make the flushes atomic, otherwise an interrupt - * handler that uses vmalloced memory might cause a TLB load in the middle - * of a flush causing. - */ - -struct mm_struct *page_id_map[NUM_PAGEID]; -static int map_replace_ptr = 1; /* which page_id_map entry to replace next */ - -/* the following functions are similar to those used in the PPC port */ - -static inline void -alloc_context(struct mm_struct *mm) -{ - struct mm_struct *old_mm; - - D(printk("tlb: alloc context %d (%p)\n", map_replace_ptr, mm)); - - /* did we replace an mm ? */ - - old_mm = page_id_map[map_replace_ptr]; - - if(old_mm) { - /* throw out any TLB entries belonging to the mm we replace - * in the map - */ - flush_tlb_mm(old_mm); - - old_mm->context.page_id = NO_CONTEXT; - } - - /* insert it into the page_id_map */ - - mm->context.page_id = map_replace_ptr; - page_id_map[map_replace_ptr] = mm; - - map_replace_ptr++; - - if(map_replace_ptr == INVALID_PAGEID) - map_replace_ptr = 0; /* wrap around */ -} - -/* - * if needed, get a new MMU context for the mm. otherwise nothing is done. - */ - -void -get_mmu_context(struct mm_struct *mm) -{ - if(mm->context.page_id == NO_CONTEXT) - alloc_context(mm); -} - -/* called by __exit_mm to destroy the used MMU context if any before - * destroying the mm itself. this is only called when the last user of the mm - * drops it. - * - * the only thing we really need to do here is mark the used PID slot - * as empty. - */ - -void -destroy_context(struct mm_struct *mm) -{ - if(mm->context.page_id != NO_CONTEXT) { - D(printk("destroy_context %d (%p)\n", mm->context.page_id, mm)); - flush_tlb_mm(mm); /* TODO this might be redundant ? */ - page_id_map[mm->context.page_id] = NULL; - } -} - -/* called once during VM initialization, from init.c */ - -void __init -tlb_init(void) -{ - int i; - - /* clear the page_id map */ - - for (i = 1; i < ARRAY_SIZE(page_id_map); i++) - page_id_map[i] = NULL; - - /* invalidate the entire TLB */ - - flush_tlb_all(); - - /* the init_mm has context 0 from the boot */ - - page_id_map[0] = &init_mm; -} -- cgit v1.2.3 From b1ba68f33c0caa937032615833e3321d03d877b4 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 5 Mar 2018 14:32:43 +0900 Subject: dt-bindings: rcar-gen3-phy-usb2: Add bindings for r8a77965 This patch adds support for r8a77965 (R-Car M3-N). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt index 99b651b33110..dbd137c079e2 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt @@ -8,6 +8,8 @@ Required properties: SoC. "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796 SoC. + "renesas,usb2-phy-r8a77965" if the device is a part of an + R8A77965 SoC. "renesas,usb2-phy-r8a77995" if the device is a part of an R8A77995 SoC. "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device. -- cgit v1.2.3 From 0147b57e731f128d68469d8032d53c0da89c8aae Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 5 Mar 2018 14:32:45 +0900 Subject: dt-bindings: rcar-gen3-phy-usb3: Add bindings for r8a77965 This patch adds bindings for r8a77965 (R-Car M3-N). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt index f94cea48f6b1..47dd296ecead 100644 --- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt +++ b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt @@ -11,6 +11,8 @@ Required properties: SoC. "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796 SoC. + "renesas,r8a77965-usb3-phy" if the device is a part of an + R8A77965 SoC. "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible device. -- cgit v1.2.3 From d581ba62f34be6a190116523521875a021109b02 Mon Sep 17 00:00:00 2001 From: Pengcheng Li Date: Fri, 9 Mar 2018 22:47:00 +0800 Subject: dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY It adds device tree bindings document for HiSilicon INNO USB2 PHY. Signed-off-by: Pengcheng Li Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt new file mode 100644 index 000000000000..0d70c8341095 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt @@ -0,0 +1,71 @@ +Device tree bindings for HiSilicon INNO USB2 PHY + +Required properties: +- compatible: Should be one of the following strings: + "hisilicon,inno-usb2-phy", + "hisilicon,hi3798cv200-usb2-phy". +- reg: Should be the address space for PHY configuration register in peripheral + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. +- clocks: The phandle and clock specifier pair for INNO USB2 PHY device + reference clock. +- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset + signal. +- #address-cells: Must be 1. +- #size-cells: Must be 0. + +The INNO USB2 PHY device should be a child node of peripheral controller that +contains the PHY configuration register, and each device suppports up to 2 PHY +ports which are represented as child nodes of INNO USB2 PHY device. + +Required properties for PHY port node: +- reg: The PHY port instance number. +- #phy-cells: Defined by generic PHY bindings. Must be 0. +- resets: The phandle and reset specifier pair for PHY port reset signal. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Example: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + usb2_phy1: usb2-phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy1_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 8>; + }; + + usb2_phy1_port1: phy@1 { + reg = <1>; + #phy-cells = <0>; + resets = <&crg 0xbc 9>; + }; + }; + + usb2_phy2: usb2-phy@124 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x124 0x4>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy2_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 10>; + }; + }; +}; -- cgit v1.2.3 From 5d1ebbda0318b1ba55eaa1fae3fd867af17b0774 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 8 Mar 2018 18:37:50 -0800 Subject: phy: mapphone-mdm6600: Add USB PHY driver for MDM6600 on Droid 4 Let's add support for the GPIO controlled USB PHY on the MDM6600 modem. It is used on some Motorola Mapphone series of phones and tablets such as Droid 4. The MDM6600 is hardwired to the first OHCI port in the Droid 4 case, and is controlled by several GPIOs. The USB PHY is integrated into the MDM6600 device it seems. We know this as we get L3 errors from omap-usb-host if trying to use the PHY before MDM6600 is configured. The GPIOs controlling MDM6600 are used to power device on and off, to configure the USB start-up mode (normal mode versus USB flashing), and they also tell the state of the MDM6600 device. The two start-up mode GPIOs are dual-purposed and used for out of band (OOB) wake-up for USB and TS 27.010 serial mux. But we need to configure the USB start-up mode first to get MDM6600 booted in the right mode to be usable in the first place. Note that the Motorola Mapphone Linux kernel tree has a "radio-ctrl" driver for modems. But it really does not control the radio at all, it just controls the modem power and start-up mode for USB. So I came to the conclusion that we're better off having this done in the USB PHY driver. For adding support for USB flashing mode, we can later on add a kernel module option for flash_mode=1 or something similar. Also note that currently there is no PM runtime support for the OHCI on omap variant SoCs. So for low(er) power idle states, currenty both ohci-platform and phy-mapphone-mdm6600 must be unloaded or unbound. For reference here is what I measured for total power consumption on an idle Droid 4 with and without USB related MDM6600 modules: idle lcd off phy-mapphone-mdm6600 ohci-platform 153mW 284mW 344mW So it seems that MDM6600 is currently not yet idling even with it's radio turned off, but that's something that is beyond the control of this USB PHY driver. This patch does get us to the point where modem data and GPS are usable with libqmi and ModemManager for example. Voice calls need more audio driver work. Cc: devicetree@vger.kernel.org Cc: Mark Rutland Cc: Marcel Partap Cc: Michael Scott Cc: Rob Herring Reviewed-by: Rob Herring Signed-off-by: Tony Lindgren Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-mapphone-mdm6600.txt | 29 ++ drivers/phy/motorola/Kconfig | 8 + drivers/phy/motorola/Makefile | 1 + drivers/phy/motorola/phy-mapphone-mdm6600.c | 542 +++++++++++++++++++++ 4 files changed, 580 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt create mode 100644 drivers/phy/motorola/phy-mapphone-mdm6600.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt b/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt new file mode 100644 index 000000000000..29427d4f047a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mapphone-mdm6600.txt @@ -0,0 +1,29 @@ +Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY + +Required properties: +- compatible Must be "motorola,mapphone-mdm6600" +- enable-gpios GPIO to enable the USB PHY +- power-gpios GPIO to power on the device +- reset-gpios GPIO to reset the device +- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for + normal mode versus USB flashing mode +- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600 +- motorola,status-gpios Three GPIOs to read the power state of the MDM6600 + +Example: + +usb-phy { + compatible = "motorola,mapphone-mdm6600"; + enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>, + <&gpio5 21 GPIO_ACTIVE_HIGH>; + motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>, + <&gpio4 8 GPIO_ACTIVE_HIGH>, + <&gpio5 14 GPIO_ACTIVE_HIGH>; + motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>, + <&gpio2 21 GPIO_ACTIVE_HIGH>, + <&gpio2 23 GPIO_ACTIVE_HIGH>; + #phy-cells = <0>; +}; diff --git a/drivers/phy/motorola/Kconfig b/drivers/phy/motorola/Kconfig index 6bb7d6bdf1bf..82651524ffb9 100644 --- a/drivers/phy/motorola/Kconfig +++ b/drivers/phy/motorola/Kconfig @@ -10,3 +10,11 @@ config PHY_CPCAP_USB help Enable this for USB to work on Motorola phones and tablets such as Droid 4. + +config PHY_MAPPHONE_MDM6600 + tristate "Motorola Mapphone MDM6600 modem USB PHY driver" + depends on OF && USB_SUPPORT + select GENERIC_PHY + help + Enable this for MDM6600 USB modem to work on Motorola phones + and tablets such as Droid 4. diff --git a/drivers/phy/motorola/Makefile b/drivers/phy/motorola/Makefile index b6cd618d671a..3514f985b355 100644 --- a/drivers/phy/motorola/Makefile +++ b/drivers/phy/motorola/Makefile @@ -3,3 +3,4 @@ # obj-$(CONFIG_PHY_CPCAP_USB) += phy-cpcap-usb.o +obj-$(CONFIG_PHY_MAPPHONE_MDM6600) += phy-mapphone-mdm6600.o diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c new file mode 100644 index 000000000000..5439dd90d0dd --- /dev/null +++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c @@ -0,0 +1,542 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Motorola Mapphone MDM6600 modem GPIO controlled USB PHY driver + * Copyright (C) 2018 Tony Lindgren + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */ +#define PHY_MDM6600_ENABLED_DELAY_MS 8000 /* 8s more total for MDM6600 */ + +enum phy_mdm6600_ctrl_lines { + PHY_MDM6600_ENABLE, /* USB PHY enable */ + PHY_MDM6600_POWER, /* Device power */ + PHY_MDM6600_RESET, /* Device reset */ + PHY_MDM6600_NR_CTRL_LINES, +}; + +enum phy_mdm6600_bootmode_lines { + PHY_MDM6600_MODE0, /* out USB mode0 and OOB wake */ + PHY_MDM6600_MODE1, /* out USB mode1, in OOB wake */ + PHY_MDM6600_NR_MODE_LINES, +}; + +enum phy_mdm6600_cmd_lines { + PHY_MDM6600_CMD0, + PHY_MDM6600_CMD1, + PHY_MDM6600_CMD2, + PHY_MDM6600_NR_CMD_LINES, +}; + +enum phy_mdm6600_status_lines { + PHY_MDM6600_STATUS0, + PHY_MDM6600_STATUS1, + PHY_MDM6600_STATUS2, + PHY_MDM6600_NR_STATUS_LINES, +}; + +/* + * MDM6600 command codes. These are based on Motorola Mapphone Linux + * kernel tree. + */ +enum phy_mdm6600_cmd { + PHY_MDM6600_CMD_BP_PANIC_ACK, + PHY_MDM6600_CMD_DATA_ONLY_BYPASS, /* Reroute USB to CPCAP PHY */ + PHY_MDM6600_CMD_FULL_BYPASS, /* Reroute USB to CPCAP PHY */ + PHY_MDM6600_CMD_NO_BYPASS, /* Request normal USB mode */ + PHY_MDM6600_CMD_BP_SHUTDOWN_REQ, /* Request device power off */ + PHY_MDM6600_CMD_BP_UNKNOWN_5, + PHY_MDM6600_CMD_BP_UNKNOWN_6, + PHY_MDM6600_CMD_UNDEFINED, +}; + +/* + * MDM6600 status codes. These are based on Motorola Mapphone Linux + * kernel tree. + */ +enum phy_mdm6600_status { + PHY_MDM6600_STATUS_PANIC, /* Seems to be really off */ + PHY_MDM6600_STATUS_PANIC_BUSY_WAIT, + PHY_MDM6600_STATUS_QC_DLOAD, + PHY_MDM6600_STATUS_RAM_DOWNLOADER, /* MDM6600 USB flashing mode */ + PHY_MDM6600_STATUS_PHONE_CODE_AWAKE, /* MDM6600 normal USB mode */ + PHY_MDM6600_STATUS_PHONE_CODE_ASLEEP, + PHY_MDM6600_STATUS_SHUTDOWN_ACK, + PHY_MDM6600_STATUS_UNDEFINED, +}; + +static const char * const +phy_mdm6600_status_name[] = { + "off", "busy", "qc_dl", "ram_dl", "awake", + "asleep", "shutdown", "undefined", +}; + +struct phy_mdm6600 { + struct device *dev; + struct phy *generic_phy; + struct phy_provider *phy_provider; + struct gpio_desc *ctrl_gpios[PHY_MDM6600_NR_CTRL_LINES]; + struct gpio_descs *mode_gpios; + struct gpio_descs *status_gpios; + struct gpio_descs *cmd_gpios; + struct delayed_work bootup_work; + struct delayed_work status_work; + struct completion ack; + bool enabled; /* mdm6600 phy enabled */ + bool running; /* mdm6600 boot done */ + int status; +}; + +static int phy_mdm6600_init(struct phy *x) +{ + struct phy_mdm6600 *ddata = phy_get_drvdata(x); + struct gpio_desc *enable_gpio = ddata->ctrl_gpios[PHY_MDM6600_ENABLE]; + + if (!ddata->enabled) + return -EPROBE_DEFER; + + gpiod_set_value_cansleep(enable_gpio, 0); + + return 0; +} + +static int phy_mdm6600_power_on(struct phy *x) +{ + struct phy_mdm6600 *ddata = phy_get_drvdata(x); + struct gpio_desc *enable_gpio = ddata->ctrl_gpios[PHY_MDM6600_ENABLE]; + + if (!ddata->enabled) + return -ENODEV; + + gpiod_set_value_cansleep(enable_gpio, 1); + + return 0; +} + +static int phy_mdm6600_power_off(struct phy *x) +{ + struct phy_mdm6600 *ddata = phy_get_drvdata(x); + struct gpio_desc *enable_gpio = ddata->ctrl_gpios[PHY_MDM6600_ENABLE]; + + if (!ddata->enabled) + return -ENODEV; + + gpiod_set_value_cansleep(enable_gpio, 0); + + return 0; +} + +static const struct phy_ops gpio_usb_ops = { + .init = phy_mdm6600_init, + .power_on = phy_mdm6600_power_on, + .power_off = phy_mdm6600_power_off, + .owner = THIS_MODULE, +}; + +/** + * phy_mdm6600_cmd() - send a command request to mdm6600 + * @ddata: device driver data + * + * Configures the three command request GPIOs to the specified value. + */ +static void phy_mdm6600_cmd(struct phy_mdm6600 *ddata, int val) +{ + int values[PHY_MDM6600_NR_CMD_LINES]; + int i; + + val &= (1 << PHY_MDM6600_NR_CMD_LINES) - 1; + for (i = 0; i < PHY_MDM6600_NR_CMD_LINES; i++) + values[i] = (val & BIT(i)) >> i; + + gpiod_set_array_value_cansleep(PHY_MDM6600_NR_CMD_LINES, + ddata->cmd_gpios->desc, values); +} + +/** + * phy_mdm6600_status() - read mdm6600 status lines + * @ddata: device driver data + */ +static void phy_mdm6600_status(struct work_struct *work) +{ + struct phy_mdm6600 *ddata; + struct device *dev; + int values[PHY_MDM6600_NR_STATUS_LINES]; + int error, i, val = 0; + + ddata = container_of(work, struct phy_mdm6600, status_work.work); + dev = ddata->dev; + + error = gpiod_get_array_value_cansleep(PHY_MDM6600_NR_CMD_LINES, + ddata->status_gpios->desc, + values); + if (error) + return; + + for (i = 0; i < PHY_MDM6600_NR_CMD_LINES; i++) { + val |= values[i] << i; + dev_dbg(ddata->dev, "XXX %s: i: %i values[i]: %i val: %i\n", + __func__, i, values[i], val); + } + ddata->status = val; + + dev_info(dev, "modem status: %i %s\n", + ddata->status, + phy_mdm6600_status_name[ddata->status & 7]); + complete(&ddata->ack); +} + +static irqreturn_t phy_mdm6600_irq_thread(int irq, void *data) +{ + struct phy_mdm6600 *ddata = data; + + schedule_delayed_work(&ddata->status_work, msecs_to_jiffies(10)); + + return IRQ_HANDLED; +} + +/** + * phy_mdm6600_wakeirq_thread - handle mode1 line OOB wake after booting + * @irq: interrupt + * @data: interrupt handler data + * + * GPIO mode1 is used initially as output to configure the USB boot + * mode for mdm6600. After booting it is used as input for OOB wake + * signal from mdm6600 to the SoC. Just use it for debug info only + * for now. + */ +static irqreturn_t phy_mdm6600_wakeirq_thread(int irq, void *data) +{ + struct phy_mdm6600 *ddata = data; + struct gpio_desc *mode_gpio1; + + mode_gpio1 = ddata->mode_gpios->desc[PHY_MDM6600_MODE1]; + dev_dbg(ddata->dev, "OOB wake on mode_gpio1: %i\n", + gpiod_get_value(mode_gpio1)); + + return IRQ_HANDLED; +} + +/** + * phy_mdm6600_init_irq() - initialize mdm6600 status IRQ lines + * @ddata: device driver data + */ +static void phy_mdm6600_init_irq(struct phy_mdm6600 *ddata) +{ + struct device *dev = ddata->dev; + int i, error, irq; + + for (i = PHY_MDM6600_STATUS0; + i <= PHY_MDM6600_STATUS2; i++) { + struct gpio_desc *gpio = ddata->status_gpios->desc[i]; + + irq = gpiod_to_irq(gpio); + if (irq <= 0) + continue; + + error = devm_request_threaded_irq(dev, irq, NULL, + phy_mdm6600_irq_thread, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + "mdm6600", + ddata); + if (error) + dev_warn(dev, "no modem status irq%i: %i\n", + irq, error); + } +} + +struct phy_mdm6600_map { + const char *name; + int direction; +}; + +static const struct phy_mdm6600_map +phy_mdm6600_ctrl_gpio_map[PHY_MDM6600_NR_CTRL_LINES] = { + { "enable", GPIOD_OUT_LOW, }, /* low = phy disabled */ + { "power", GPIOD_OUT_LOW, }, /* low = off */ + { "reset", GPIOD_OUT_HIGH, }, /* high = reset */ +}; + +/** + * phy_mdm6600_init_lines() - initialize mdm6600 GPIO lines + * @ddata: device driver data + */ +static int phy_mdm6600_init_lines(struct phy_mdm6600 *ddata) +{ + struct device *dev = ddata->dev; + int i; + + /* MDM6600 control lines */ + for (i = 0; i < ARRAY_SIZE(phy_mdm6600_ctrl_gpio_map); i++) { + const struct phy_mdm6600_map *map = + &phy_mdm6600_ctrl_gpio_map[i]; + struct gpio_desc **gpio = &ddata->ctrl_gpios[i]; + + *gpio = devm_gpiod_get(dev, map->name, map->direction); + if (IS_ERR(*gpio)) { + dev_info(dev, "gpio %s error %li\n", + map->name, PTR_ERR(*gpio)); + return PTR_ERR(*gpio); + } + } + + /* MDM6600 USB start-up mode output lines */ + ddata->mode_gpios = devm_gpiod_get_array(dev, "motorola,mode", + GPIOD_OUT_LOW); + if (IS_ERR(ddata->mode_gpios)) + return PTR_ERR(ddata->mode_gpios); + + if (ddata->mode_gpios->ndescs != PHY_MDM6600_NR_MODE_LINES) + return -EINVAL; + + /* MDM6600 status input lines */ + ddata->status_gpios = devm_gpiod_get_array(dev, "motorola,status", + GPIOD_IN); + if (IS_ERR(ddata->status_gpios)) + return PTR_ERR(ddata->status_gpios); + + if (ddata->status_gpios->ndescs != PHY_MDM6600_NR_STATUS_LINES) + return -EINVAL; + + /* MDM6600 cmd output lines */ + ddata->cmd_gpios = devm_gpiod_get_array(dev, "motorola,cmd", + GPIOD_OUT_LOW); + if (IS_ERR(ddata->cmd_gpios)) + return PTR_ERR(ddata->cmd_gpios); + + if (ddata->cmd_gpios->ndescs != PHY_MDM6600_NR_CMD_LINES) + return -EINVAL; + + return 0; +} + +/** + * phy_mdm6600_device_power_on() - power on mdm6600 device + * @ddata: device driver data + * + * To get the integrated USB phy in MDM6600 takes some hoops. We must ensure + * the shared USB bootmode GPIOs are configured, then request modem start-up, + * reset and power-up.. And then we need to recycle the shared USB bootmode + * GPIOs as they are also used for Out of Band (OOB) wake for the USB and + * TS 27.010 serial mux. + */ +static int phy_mdm6600_device_power_on(struct phy_mdm6600 *ddata) +{ + struct gpio_desc *mode_gpio0, *mode_gpio1, *reset_gpio, *power_gpio; + int error = 0, wakeirq; + + mode_gpio0 = ddata->mode_gpios->desc[PHY_MDM6600_MODE0]; + mode_gpio1 = ddata->mode_gpios->desc[PHY_MDM6600_MODE1]; + reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET]; + power_gpio = ddata->ctrl_gpios[PHY_MDM6600_POWER]; + + /* + * Shared GPIOs must be low for normal USB mode. After booting + * they are used for OOB wake signaling. These can be also used + * to configure USB flashing mode later on based on a module + * parameter. + */ + gpiod_set_value_cansleep(mode_gpio0, 0); + gpiod_set_value_cansleep(mode_gpio1, 0); + + /* Request start-up mode */ + phy_mdm6600_cmd(ddata, PHY_MDM6600_CMD_NO_BYPASS); + + /* Request a reset first */ + gpiod_set_value_cansleep(reset_gpio, 0); + msleep(100); + + /* Toggle power GPIO to request mdm6600 to start */ + gpiod_set_value_cansleep(power_gpio, 1); + msleep(100); + gpiod_set_value_cansleep(power_gpio, 0); + + /* + * Looks like the USB PHY needs between 2.2 to 4 seconds. + * If we try to use it before that, we will get L3 errors + * from omap-usb-host trying to access the PHY. See also + * phy_mdm6600_init() for -EPROBE_DEFER. + */ + msleep(PHY_MDM6600_PHY_DELAY_MS); + ddata->enabled = true; + + /* Booting up the rest of MDM6600 will take total about 8 seconds */ + dev_info(ddata->dev, "Waiting for power up request to complete..\n"); + if (wait_for_completion_timeout(&ddata->ack, + msecs_to_jiffies(PHY_MDM6600_ENABLED_DELAY_MS))) { + if (ddata->status > PHY_MDM6600_STATUS_PANIC && + ddata->status < PHY_MDM6600_STATUS_SHUTDOWN_ACK) + dev_info(ddata->dev, "Powered up OK\n"); + } else { + ddata->enabled = false; + error = -ETIMEDOUT; + dev_err(ddata->dev, "Timed out powering up\n"); + } + + /* Reconfigure mode1 GPIO as input for OOB wake */ + gpiod_direction_input(mode_gpio1); + + wakeirq = gpiod_to_irq(mode_gpio1); + if (wakeirq <= 0) + return wakeirq; + + error = devm_request_threaded_irq(ddata->dev, wakeirq, NULL, + phy_mdm6600_wakeirq_thread, + IRQF_TRIGGER_RISING | + IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, + "mdm6600-wake", + ddata); + if (error) + dev_warn(ddata->dev, "no modem wakeirq irq%i: %i\n", + wakeirq, error); + + ddata->running = true; + + return error; +} + +/** + * phy_mdm6600_device_power_off() - power off mdm6600 device + * @ddata: device driver data + */ +static void phy_mdm6600_device_power_off(struct phy_mdm6600 *ddata) +{ + struct gpio_desc *reset_gpio = + ddata->ctrl_gpios[PHY_MDM6600_RESET]; + + ddata->enabled = false; + phy_mdm6600_cmd(ddata, PHY_MDM6600_CMD_BP_SHUTDOWN_REQ); + msleep(100); + + gpiod_set_value_cansleep(reset_gpio, 1); + + dev_info(ddata->dev, "Waiting for power down request to complete.. "); + if (wait_for_completion_timeout(&ddata->ack, + msecs_to_jiffies(5000))) { + if (ddata->status == PHY_MDM6600_STATUS_PANIC) + dev_info(ddata->dev, "Powered down OK\n"); + } else { + dev_err(ddata->dev, "Timed out powering down\n"); + } +} + +static void phy_mdm6600_deferred_power_on(struct work_struct *work) +{ + struct phy_mdm6600 *ddata; + int error; + + ddata = container_of(work, struct phy_mdm6600, bootup_work.work); + + error = phy_mdm6600_device_power_on(ddata); + if (error) + dev_err(ddata->dev, "Device not functional\n"); +} + +static const struct of_device_id phy_mdm6600_id_table[] = { + { .compatible = "motorola,mapphone-mdm6600", }, + {}, +}; +MODULE_DEVICE_TABLE(of, phy_mdm6600_id_table); + +static int phy_mdm6600_probe(struct platform_device *pdev) +{ + struct phy_mdm6600 *ddata; + int error; + + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + INIT_DELAYED_WORK(&ddata->bootup_work, + phy_mdm6600_deferred_power_on); + INIT_DELAYED_WORK(&ddata->status_work, phy_mdm6600_status); + init_completion(&ddata->ack); + + ddata->dev = &pdev->dev; + platform_set_drvdata(pdev, ddata); + + error = phy_mdm6600_init_lines(ddata); + if (error) + return error; + + phy_mdm6600_init_irq(ddata); + + ddata->generic_phy = devm_phy_create(ddata->dev, NULL, &gpio_usb_ops); + if (IS_ERR(ddata->generic_phy)) { + error = PTR_ERR(ddata->generic_phy); + goto cleanup; + } + + phy_set_drvdata(ddata->generic_phy, ddata); + + ddata->phy_provider = + devm_of_phy_provider_register(ddata->dev, + of_phy_simple_xlate); + if (IS_ERR(ddata->phy_provider)) { + error = PTR_ERR(ddata->phy_provider); + goto cleanup; + } + + schedule_delayed_work(&ddata->bootup_work, 0); + + /* + * See phy_mdm6600_device_power_on(). We should be able + * to remove this eventually when ohci-platform can deal + * with -EPROBE_DEFER. + */ + msleep(PHY_MDM6600_PHY_DELAY_MS + 500); + + return 0; + +cleanup: + phy_mdm6600_device_power_off(ddata); + return error; +} + +static int phy_mdm6600_remove(struct platform_device *pdev) +{ + struct phy_mdm6600 *ddata = platform_get_drvdata(pdev); + struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET]; + + if (!ddata->running) + wait_for_completion_timeout(&ddata->ack, + msecs_to_jiffies(PHY_MDM6600_ENABLED_DELAY_MS)); + + gpiod_set_value_cansleep(reset_gpio, 1); + phy_mdm6600_device_power_off(ddata); + + cancel_delayed_work_sync(&ddata->bootup_work); + cancel_delayed_work_sync(&ddata->status_work); + + return 0; +} + +static struct platform_driver phy_mdm6600_driver = { + .probe = phy_mdm6600_probe, + .remove = phy_mdm6600_remove, + .driver = { + .name = "phy-mapphone-mdm6600", + .of_match_table = of_match_ptr(phy_mdm6600_id_table), + }, +}; + +module_platform_driver(phy_mdm6600_driver); + +MODULE_ALIAS("platform:gpio_usb"); +MODULE_AUTHOR("Tony Lindgren "); +MODULE_DESCRIPTION("mdm6600 gpio usb phy driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 6912d4f40bc7b8a40604f2fa02bb5545e39d1a35 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 16 Feb 2018 13:09:52 +0100 Subject: dt-bindings: phy-rockchip-typec: deprecate some register properties. As now the following register properties are in the driver, document as deprecated these properties and recommend to not use them on new bindings. The deprecated properties are: - rockchip,typec-conn-dir : the register of type-c connector direction - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable control. - rockchip,external-psm : the register of type-c phy external psm clock selection. - rockchip,pipe-status : the register of type-c phy pipe status. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Heiko Stuebner Reviewed-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/phy-rockchip-typec.txt | 33 +++++----------------- 1 file changed, 7 insertions(+), 26 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt index 6ea867e3176f..f95cd492d6fc 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -16,24 +16,6 @@ Required properties: "uphy", "uphy-pipe", "uphy-tcphy" - extcon : extcon specifier for the Power Delivery -Note, there are 2 type-c phys for RK3399, and they are almost identical, except -these registers(description below), every register node contains 3 sections: -offset, enable bit, write mask bit. - - rockchip,typec-conn-dir : the register of type-c connector direction, - for type-c phy0, it must be <0xe580 0 16>; - for type-c phy1, it must be <0xe58c 0 16>; - - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable - control. - for type-c phy0, it must be <0xe580 3 19>; - for type-c phy1, it must be <0xe58c 3 19>; - - rockchip,external-psm : the register of type-c phy external psm clock - selection. - for type-c phy0, it must be <0xe588 14 30>; - for type-c phy1, it must be <0xe594 14 30>; - - rockchip,pipe-status : the register of type-c phy pipe status. - for type-c phy0, it must be <0xe5c0 0 0>; - for type-c phy1, it must be <0xe5c0 16 16>; - Required nodes : a sub-node is required for each port the phy provides. The sub-node name is used to identify dp or usb3 port, and shall be the following entries: @@ -43,6 +25,13 @@ Required nodes : a sub-node is required for each port the phy provides. Required properties (port (child) node): - #phy-cells : must be 0, See ./phy-bindings.txt for details. +Deprecated properties, do not use in new device tree sources, these +properties are determined by the compatible value: + - rockchip,typec-conn-dir + - rockchip,usb3tousb2-en + - rockchip,external-psm + - rockchip,pipe-status + Example: tcphy0: phy@ff7c0000 { compatible = "rockchip,rk3399-typec-phy"; @@ -58,10 +47,6 @@ Example: <&cru SRST_UPHY0_PIPE_L00>, <&cru SRST_P_UPHY0_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - rockchip,typec-conn-dir = <0xe580 0 16>; - rockchip,usb3tousb2-en = <0xe580 3 19>; - rockchip,external-psm = <0xe588 14 30>; - rockchip,pipe-status = <0xe5c0 0 0>; tcphy0_dp: dp-port { #phy-cells = <0>; @@ -86,10 +71,6 @@ Example: <&cru SRST_UPHY1_PIPE_L00>, <&cru SRST_P_UPHY1_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; - rockchip,typec-conn-dir = <0xe58c 0 16>; - rockchip,usb3tousb2-en = <0xe58c 3 19>; - rockchip,external-psm = <0xe594 14 30>; - rockchip,pipe-status = <0xe5c0 16 16>; tcphy1_dp: dp-port { #phy-cells = <0>; -- cgit v1.2.3 From 21bf9bc2a99e7b519b0035155209aeea2bc90696 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 1 Mar 2018 16:25:11 +0100 Subject: dt-bindings: phy-rockchip-typec: move extcon property to be optional. The extcon property is used to detect the cable-state but some boards just connect the type-c phy to a regular USB-A connector without any power-delivery and thus no controller reporting the cable-state. So the extcon property is not really a required property, move it to be optional instead. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Heiko Stuebner Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt index f95cd492d6fc..960da7fcaa9e 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -14,6 +14,8 @@ Required properties: - resets : a list of phandle + reset specifier pairs - reset-names : string reset name, must be: "uphy", "uphy-pipe", "uphy-tcphy" + +Optional properties: - extcon : extcon specifier for the Power Delivery Required nodes : a sub-node is required for each port the phy provides. -- cgit v1.2.3 From f3b249e652792290cea1db45fa58e51c69cdd68e Mon Sep 17 00:00:00 2001 From: Brad Mouring Date: Tue, 13 Mar 2018 16:32:16 -0500 Subject: Documentation: macb: Document phy-handle binding Document the existence of the optional binding, directing to the general ethernet document that describes this binding. Signed-off-by: Brad Mouring Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/macb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 27966ae741e0..457d5ae16f23 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -29,6 +29,7 @@ Optional properties for PHY child node: - reset-gpios : Should specify the gpio for phy reset - magic-packet : If present, indicates that the hardware supports waking up via magic packet. +- phy-handle : see ethernet.txt file in the same directory Examples: -- cgit v1.2.3 From 9885b1bd953640abb7c1de158a2475f23ee13fc8 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 6 Mar 2018 00:20:59 +0200 Subject: dt-bindings: rng: Document Freescale i.MX21 and i.MX31 RNGA compatibles Freescale i.MX21 and i.MX31 SoCs contain a Random Number Generator Accelerator module (RNGA), which is replaced by RNGB and RNGC modules on later i.MX SoC series, the change adds a new compatible property to describe the controller. Since all versions of Freescale RNG modules are legacy, apparently the documentation file has no more potential for further extensions, nevertheless generalize it by removing explicit RNGC specifics. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Rob Herring Reviewed-by: Fabio Estevam Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/imx-rng.txt | 20 ++++++++++++++++++++ Documentation/devicetree/bindings/rng/imx-rngc.txt | 21 --------------------- 2 files changed, 20 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/rng/imx-rng.txt delete mode 100644 Documentation/devicetree/bindings/rng/imx-rngc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/imx-rng.txt b/Documentation/devicetree/bindings/rng/imx-rng.txt new file mode 100644 index 000000000000..405c2b00ccb0 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/imx-rng.txt @@ -0,0 +1,20 @@ +Freescale RNGA/RNGB/RNGC (Random Number Generator Versions A, B and C) + +Required properties: +- compatible : should be one of + "fsl,imx21-rnga" + "fsl,imx31-rnga" (backward compatible with "fsl,imx21-rnga") + "fsl,imx25-rngb" + "fsl,imx35-rngc" +- reg : offset and length of the register set of this block +- interrupts : the interrupt number for the RNG block +- clocks : the RNG clk source + +Example: + +rng@53fb0000 { + compatible = "fsl,imx25-rngb"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&trng_clk>; +}; diff --git a/Documentation/devicetree/bindings/rng/imx-rngc.txt b/Documentation/devicetree/bindings/rng/imx-rngc.txt deleted file mode 100644 index 93c7174a7bed..000000000000 --- a/Documentation/devicetree/bindings/rng/imx-rngc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Freescale RNGC (Random Number Generator Version C) - -The driver also supports version B, which is mostly compatible -to version C. - -Required properties: -- compatible : should be one of - "fsl,imx25-rngb" - "fsl,imx35-rngc" -- reg : offset and length of the register set of this block -- interrupts : the interrupt number for the RNGC block -- clocks : the RNGC clk source - -Example: - -rng@53fb0000 { - compatible = "fsl,imx25-rngb"; - reg = <0x53fb0000 0x4000>; - interrupts = <22>; - clocks = <&trng_clk>; -}; -- cgit v1.2.3 From 4731a43169b799a9b4337579793a24fcc85943f5 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 22 Feb 2018 12:04:32 -0800 Subject: rtc: isl12026: new driver. The ISL12026 is a combination RTC and EEPROM device with I2C interface. The standard RTC driver interface is provided. The EEPROM is accessed via the NVMEM interface. Reviewed-by: Rob Herring Reviewed-by: Andy Shevchenko Signed-off-by: David Daney Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/isil,isl12026.txt | 28 ++ drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-isl12026.c | 505 +++++++++++++++++++++ 4 files changed, 544 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt create mode 100644 drivers/rtc/rtc-isl12026.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rtc/isil,isl12026.txt b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt new file mode 100644 index 000000000000..2e0be45193bb --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/isil,isl12026.txt @@ -0,0 +1,28 @@ +ISL12026 I2C RTC/EEPROM + +ISL12026 is an I2C RTC/EEPROM combination device. The RTC and control +registers respond at bus address 0x6f, and the EEPROM array responds +at bus address 0x57. The canonical "reg" value will be for the RTC portion. + +Required properties supported by the device: + + - "compatible": must be "isil,isl12026" + - "reg": I2C bus address of the device (always 0x6f) + +Optional properties: + + - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified + value for proper operation. + + - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified + value for proper operation. + + +Example: + + rtc@6f { + compatible = "isil,isl12026"; + reg = <0x6f>; + isil,pwr-bsw = <0>; + isil,pwr-sbib = <1>; + } diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index f6d7e490e714..3bf649cd7b83 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -407,6 +407,16 @@ config RTC_DRV_ISL12022 This driver can also be built as a module. If so, the module will be called rtc-isl12022. +config RTC_DRV_ISL12026 + tristate "Intersil ISL12026" + depends on OF || COMPILE_TEST + help + If you say yes here you get support for the + Intersil ISL12026 RTC chip. + + This driver can also be built as a module. If so, the module + will be called rtc-isl12026. + config RTC_DRV_X1205 tristate "Xicor/Intersil X1205" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 4fbf87e45a7c..f481661a6eae 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o obj-$(CONFIG_RTC_DRV_HYM8563) += rtc-hym8563.o obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o +obj-$(CONFIG_RTC_DRV_ISL12026) += rtc-isl12026.o obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o obj-$(CONFIG_RTC_DRV_LP8788) += rtc-lp8788.o diff --git a/drivers/rtc/rtc-isl12026.c b/drivers/rtc/rtc-isl12026.c new file mode 100644 index 000000000000..ada9849d8d97 --- /dev/null +++ b/drivers/rtc/rtc-isl12026.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * An I2C driver for the Intersil ISL 12026 + * + * Copyright (c) 2018 Cavium, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* register offsets */ +#define ISL12026_REG_PWR 0x14 +# define ISL12026_REG_PWR_BSW BIT(6) +# define ISL12026_REG_PWR_SBIB BIT(7) +#define ISL12026_REG_SC 0x30 +#define ISL12026_REG_HR 0x32 +# define ISL12026_REG_HR_MIL BIT(7) /* military or 24 hour time */ +#define ISL12026_REG_SR 0x3f +# define ISL12026_REG_SR_RTCF BIT(0) +# define ISL12026_REG_SR_WEL BIT(1) +# define ISL12026_REG_SR_RWEL BIT(2) +# define ISL12026_REG_SR_MBZ BIT(3) +# define ISL12026_REG_SR_OSCF BIT(4) + +/* The EEPROM array responds at i2c address 0x57 */ +#define ISL12026_EEPROM_ADDR 0x57 + +#define ISL12026_PAGESIZE 16 +#define ISL12026_NVMEM_WRITE_TIME 20 + +struct isl12026 { + struct rtc_device *rtc; + struct i2c_client *nvm_client; +}; + +static int isl12026_read_reg(struct i2c_client *client, int reg) +{ + u8 addr[] = {0, reg}; + u8 val; + int ret; + + struct i2c_msg msgs[] = { + { + .addr = client->addr, + .flags = 0, + .len = sizeof(addr), + .buf = addr + }, { + .addr = client->addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &val + } + }; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, "read reg error, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + } else { + ret = val; + } + + return ret; +} + +static int isl12026_arm_write(struct i2c_client *client) +{ + int ret; + u8 op[3]; + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = op + }; + + /* Set SR.WEL */ + op[0] = 0; + op[1] = ISL12026_REG_SR; + op[2] = ISL12026_REG_SR_WEL; + msg.len = 3; + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, "write error SR.WEL, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + goto out; + } + + /* Set SR.WEL and SR.RWEL */ + op[2] = ISL12026_REG_SR_WEL | ISL12026_REG_SR_RWEL; + msg.len = 3; + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, + "write error SR.WEL|SR.RWEL, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + goto out; + } else { + ret = 0; + } +out: + return ret; +} + +static int isl12026_disarm_write(struct i2c_client *client) +{ + int ret; + u8 op[3] = {0, ISL12026_REG_SR, 0}; + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + .len = sizeof(op), + .buf = op + }; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, + "write error SR, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + } else { + ret = 0; + } + + return ret; +} + +static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val) +{ + int ret; + u8 op[3] = {0, reg, val}; + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + .len = sizeof(op), + .buf = op + }; + + ret = isl12026_arm_write(client); + if (ret) + return ret; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, "write error CCR, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + goto out; + } + + msleep(ISL12026_NVMEM_WRITE_TIME); + + ret = isl12026_disarm_write(client); +out: + return ret; +} + +static int isl12026_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + int ret; + u8 op[10]; + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + .len = sizeof(op), + .buf = op + }; + + ret = isl12026_arm_write(client); + if (ret) + return ret; + + /* Set the CCR registers */ + op[0] = 0; + op[1] = ISL12026_REG_SC; + op[2] = bin2bcd(tm->tm_sec); /* SC */ + op[3] = bin2bcd(tm->tm_min); /* MN */ + op[4] = bin2bcd(tm->tm_hour) | ISL12026_REG_HR_MIL; /* HR */ + op[5] = bin2bcd(tm->tm_mday); /* DT */ + op[6] = bin2bcd(tm->tm_mon + 1); /* MO */ + op[7] = bin2bcd(tm->tm_year % 100); /* YR */ + op[8] = bin2bcd(tm->tm_wday & 7); /* DW */ + op[9] = bin2bcd(tm->tm_year >= 100 ? 20 : 19); /* Y2K */ + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, "write error CCR, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + goto out; + } + + ret = isl12026_disarm_write(client); +out: + return ret; +} + +static int isl12026_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct i2c_client *client = to_i2c_client(dev); + u8 ccr[8]; + u8 addr[2]; + u8 sr; + int ret; + struct i2c_msg msgs[] = { + { + .addr = client->addr, + .flags = 0, + .len = sizeof(addr), + .buf = addr + }, { + .addr = client->addr, + .flags = I2C_M_RD, + } + }; + + /* First, read SR */ + addr[0] = 0; + addr[1] = ISL12026_REG_SR; + msgs[1].len = 1; + msgs[1].buf = &sr; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, "read error, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + goto out; + } + + if (sr & ISL12026_REG_SR_RTCF) + dev_warn(&client->dev, "Real-Time Clock Failure on read\n"); + if (sr & ISL12026_REG_SR_OSCF) + dev_warn(&client->dev, "Oscillator Failure on read\n"); + + /* Second, CCR regs */ + addr[0] = 0; + addr[1] = ISL12026_REG_SC; + msgs[1].len = sizeof(ccr); + msgs[1].buf = ccr; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&client->dev, "read error, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + goto out; + } + + tm->tm_sec = bcd2bin(ccr[0] & 0x7F); + tm->tm_min = bcd2bin(ccr[1] & 0x7F); + if (ccr[2] & ISL12026_REG_HR_MIL) + tm->tm_hour = bcd2bin(ccr[2] & 0x3F); + else + tm->tm_hour = bcd2bin(ccr[2] & 0x1F) + + ((ccr[2] & 0x20) ? 12 : 0); + tm->tm_mday = bcd2bin(ccr[3] & 0x3F); + tm->tm_mon = bcd2bin(ccr[4] & 0x1F) - 1; + tm->tm_year = bcd2bin(ccr[5]); + if (bcd2bin(ccr[7]) == 20) + tm->tm_year += 100; + tm->tm_wday = ccr[6] & 0x07; + + ret = 0; +out: + return ret; +} + +static const struct rtc_class_ops isl12026_rtc_ops = { + .read_time = isl12026_rtc_read_time, + .set_time = isl12026_rtc_set_time, +}; + +static int isl12026_nvm_read(void *p, unsigned int offset, + void *val, size_t bytes) +{ + struct isl12026 *priv = p; + int ret; + u8 addr[2]; + struct i2c_msg msgs[] = { + { + .addr = priv->nvm_client->addr, + .flags = 0, + .len = sizeof(addr), + .buf = addr + }, { + .addr = priv->nvm_client->addr, + .flags = I2C_M_RD, + .buf = val + } + }; + + /* + * offset and bytes checked and limited by nvmem core, so + * proceed without further checks. + */ + ret = mutex_lock_interruptible(&priv->rtc->ops_lock); + if (ret) + return ret; + + /* 2 bytes of address, most significant first */ + addr[0] = offset >> 8; + addr[1] = offset; + msgs[1].len = bytes; + ret = i2c_transfer(priv->nvm_client->adapter, msgs, ARRAY_SIZE(msgs)); + + mutex_unlock(&priv->rtc->ops_lock); + + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&priv->nvm_client->dev, + "nvmem read error, ret=%d\n", ret); + return ret < 0 ? ret : -EIO; + } + + return 0; +} + +static int isl12026_nvm_write(void *p, unsigned int offset, + void *val, size_t bytes) +{ + struct isl12026 *priv = p; + int ret; + u8 *v = val; + size_t chunk_size, num_written; + u8 payload[ISL12026_PAGESIZE + 2]; /* page + 2 address bytes */ + struct i2c_msg msgs[] = { + { + .addr = priv->nvm_client->addr, + .flags = 0, + .buf = payload + } + }; + + /* + * offset and bytes checked and limited by nvmem core, so + * proceed without further checks. + */ + ret = mutex_lock_interruptible(&priv->rtc->ops_lock); + if (ret) + return ret; + + num_written = 0; + while (bytes) { + chunk_size = round_down(offset, ISL12026_PAGESIZE) + + ISL12026_PAGESIZE - offset; + chunk_size = min(bytes, chunk_size); + /* + * 2 bytes of address, most significant first, followed + * by page data bytes + */ + memcpy(payload + 2, v + num_written, chunk_size); + payload[0] = offset >> 8; + payload[1] = offset; + msgs[0].len = chunk_size + 2; + ret = i2c_transfer(priv->nvm_client->adapter, + msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + dev_err(&priv->nvm_client->dev, + "nvmem write error, ret=%d\n", ret); + ret = ret < 0 ? ret : -EIO; + break; + } + ret = 0; + bytes -= chunk_size; + offset += chunk_size; + num_written += chunk_size; + msleep(ISL12026_NVMEM_WRITE_TIME); + } + + mutex_unlock(&priv->rtc->ops_lock); + + return ret; +} + +static void isl12026_force_power_modes(struct i2c_client *client) +{ + int ret; + int pwr, requested_pwr; + u32 bsw_val, sbib_val; + bool set_bsw, set_sbib; + + /* + * If we can read the of_property, set the specified value. + * If there is an error reading the of_property (likely + * because it does not exist), keep the current value. + */ + ret = of_property_read_u32(client->dev.of_node, + "isil,pwr-bsw", &bsw_val); + set_bsw = (ret == 0); + + ret = of_property_read_u32(client->dev.of_node, + "isil,pwr-sbib", &sbib_val); + set_sbib = (ret == 0); + + /* Check if PWR.BSW and/or PWR.SBIB need specified values */ + if (!set_bsw && !set_sbib) + return; + + pwr = isl12026_read_reg(client, ISL12026_REG_PWR); + if (pwr < 0) { + dev_warn(&client->dev, "Error: Failed to read PWR %d\n", pwr); + return; + } + + requested_pwr = pwr; + + if (set_bsw) { + if (bsw_val) + requested_pwr |= ISL12026_REG_PWR_BSW; + else + requested_pwr &= ~ISL12026_REG_PWR_BSW; + } /* else keep current BSW */ + + if (set_sbib) { + if (sbib_val) + requested_pwr |= ISL12026_REG_PWR_SBIB; + else + requested_pwr &= ~ISL12026_REG_PWR_SBIB; + } /* else keep current SBIB */ + + if (pwr >= 0 && pwr != requested_pwr) { + dev_dbg(&client->dev, "PWR: %02x\n", pwr); + dev_dbg(&client->dev, "Updating PWR to: %02x\n", requested_pwr); + isl12026_write_reg(client, ISL12026_REG_PWR, requested_pwr); + } +} + +static int isl12026_probe_new(struct i2c_client *client) +{ + struct isl12026 *priv; + int ret; + struct nvmem_config nvm_cfg; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) + return -ENODEV; + + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + i2c_set_clientdata(client, priv); + + isl12026_force_power_modes(client); + + priv->nvm_client = i2c_new_dummy(client->adapter, ISL12026_EEPROM_ADDR); + if (!priv->nvm_client) + return -ENOMEM; + + priv->rtc = devm_rtc_allocate_device(&client->dev); + ret = PTR_ERR_OR_ZERO(priv->rtc); + if (ret) + return ret; + + priv->rtc->ops = &isl12026_rtc_ops; + priv->rtc->nvram_old_abi = false; + ret = rtc_register_device(priv->rtc); + if (ret) + return ret; + + memset(&nvm_cfg, 0, sizeof(nvm_cfg)); + nvm_cfg.name = "eeprom"; + nvm_cfg.read_only = false; + nvm_cfg.root_only = true; + nvm_cfg.base_dev = &client->dev; + nvm_cfg.priv = priv; + nvm_cfg.stride = 1; + nvm_cfg.word_size = 1; + nvm_cfg.size = 512; + nvm_cfg.reg_read = isl12026_nvm_read; + nvm_cfg.reg_write = isl12026_nvm_write; + + return rtc_nvmem_register(priv->rtc, &nvm_cfg); +} + +static int isl12026_remove(struct i2c_client *client) +{ + struct isl12026 *priv = i2c_get_clientdata(client); + + i2c_unregister_device(priv->nvm_client); + return 0; +} + +static const struct of_device_id isl12026_dt_match[] = { + { .compatible = "isil,isl12026" }, + { } +}; +MODULE_DEVICE_TABLE(of, isl12026_dt_match); + +static struct i2c_driver isl12026_driver = { + .driver = { + .name = "rtc-isl12026", + .of_match_table = isl12026_dt_match, + }, + .probe_new = isl12026_probe_new, + .remove = isl12026_remove, +}; + +module_i2c_driver(isl12026_driver); + +MODULE_DESCRIPTION("ISL 12026 RTC driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From d0843e61690c1d107b92234ee5c1cf6a65293d9d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Mar 2018 11:44:46 +0100 Subject: of: Documentation: Fix forgotten reference to of_overlay_apply() Fixes: 93a6039000b5acab ("of: Documentation: of_overlay_apply() replaced by of_overlay_fdt_apply()") Signed-off-by: Geert Uytterhoeven Signed-off-by: Rob Herring --- Documentation/devicetree/overlay-notes.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt index 5175a24d387e..a4feb6dde8cd 100644 --- a/Documentation/devicetree/overlay-notes.txt +++ b/Documentation/devicetree/overlay-notes.txt @@ -91,8 +91,8 @@ The API is quite easy to use. return value is an error or a cookie identifying this overlay. 2. Call of_overlay_remove() to remove and cleanup the overlay changeset -previously created via the call to of_overlay_apply(). Removal of an overlay -changeset that is stacked by another will not be permitted. +previously created via the call to of_overlay_fdt_apply(). Removal of an +overlay changeset that is stacked by another will not be permitted. Finally, if you need to remove all overlays in one-go, just call of_overlay_remove_all() which will remove every single one in the correct -- cgit v1.2.3 From 2e08e4d2ff488424919d69dd211ac860a019ac1d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 16 Mar 2018 22:02:12 +0800 Subject: dt-bindings: add device tree binding for Allwinner H6 main CCU The Allwinner H6 main CCU uses the internal oscillator of the SoC, which is different with old SoCs' main CCU. Add device tree binding for the Allwinner H6 main CCU. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index 4ca21c3a6fc9..460ef27b1008 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -20,6 +20,7 @@ Required properties : - "allwinner,sun50i-a64-ccu" - "allwinner,sun50i-a64-r-ccu" - "allwinner,sun50i-h5-ccu" + - "allwinner,sun50i-h6-ccu" - "nextthing,gr8-ccu" - reg: Must contain the registers base address and length @@ -31,6 +32,9 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 +For the main CCU on H6, one more clock is needed: +- "iosc": the SoC's internal frequency oscillator + For the PRCM CCUs on A83T/H3/A64, two more clocks are needed: - "pll-periph": the SoC's peripheral PLL from the main CCU - "iosc": the SoC's internal frequency oscillator -- cgit v1.2.3 From 2c97fa22daa1f9bdbdebb9880f44a50c703a9d35 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Sun, 18 Feb 2018 03:54:36 +0800 Subject: dt-bindings: clock: mediatek: add missing required #reset-cells All ethsys, pciesys and ssusbsys internally include reset controller, so explicitly add back these missing cell definitions to related bindings and examples. Signed-off-by: Sean Wang Cc: Rob Herring Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger Acked-by: Stephen Boyd Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ 3 files changed, 5 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt index 6cc7840ff37a..8f5335b480ac 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt @@ -9,6 +9,7 @@ Required Properties: - "mediatek,mt2701-ethsys", "syscon" - "mediatek,mt7622-ethsys", "syscon" - #clock-cells: Must be 1 +- #reset-cells: Must be 1 The ethsys controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt index d5d5f1227665..7fe5dc6097a6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-pciesys", "syscon" - #clock-cells: Must be 1 +- #reset-cells: Must be 1 The PCIESYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { compatible = "mediatek,mt7622-pciesys", "syscon"; reg = <0 0x1a100800 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt index 00760019da00..b8184da2508c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be: - "mediatek,mt7622-ssusbsys", "syscon" - #clock-cells: Must be 1 +- #reset-cells: Must be 1 The SSUSBSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; -- cgit v1.2.3 From c235edcb34651023c9eb1c5c4a7cdcaf7250d02c Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Tue, 13 Mar 2018 11:16:45 +0100 Subject: ARM: dts: sun8i-h3: Add Mali node The H3 has an ARM Mali 400 GPU, so add binding to our DT. Signed-off-by: Giulio Benetti Reviewed-by: Rob Herring Signed-off-by: Maxime Ripard --- .../devicetree/bindings/gpu/arm,mali-utgard.txt | 1 + arch/arm/boot/dts/sun8i-h3.dtsi | 27 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index ad876548ab5d..c1f65d1dac1d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -10,6 +10,7 @@ Required properties: * And, optionally, one of the vendor specific compatible: + allwinner,sun4i-a10-mali + allwinner,sun7i-a20-mali + + allwinner,sun8i-h3-mali + allwinner,sun50i-h5-mali + amlogic,meson-gxbb-mali + amlogic,meson-gxl-mali diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 8495deecedad..10da8ed7db81 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -79,6 +79,33 @@ , ; }; + + soc { + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-h3-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + }; }; &ccu { -- cgit v1.2.3 From 8bde8fd64d1b8f8bc1577e28ff412553597b6adb Mon Sep 17 00:00:00 2001 From: Katsuhiro Suzuki Date: Fri, 16 Mar 2018 16:08:12 +0900 Subject: ASoC: uniphier: add syscon property to binding document This patch adds syscon property for specifying soc-glue core into DT binding documentation. Currently, soc-glue core is used for changing the state of S/PDIF signal output pin to signal output state or Hi-Z state. If you don't need to use features on soc-glue described above you can ommit this property. Signed-off-by: Katsuhiro Suzuki Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/uniphier,aio.txt | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/uniphier,aio.txt b/Documentation/devicetree/bindings/sound/uniphier,aio.txt index 65d71cf6ef0f..4ce68ed6f2f2 100644 --- a/Documentation/devicetree/bindings/sound/uniphier,aio.txt +++ b/Documentation/devicetree/bindings/sound/uniphier,aio.txt @@ -22,6 +22,12 @@ Required properties: entry in reset-names. - #sound-dai-cells: should be 1. +Optional properties: +- socionext,syscon: a phandle, should contain soc-glue. + The soc-glue is used for changing mode of S/PDIF signal pin + to Output from Hi-Z. This property is optional if you use + I2S signal pins only. + Example: audio { compatible = "socionext,uniphier-ld20-aio"; @@ -34,4 +40,6 @@ Example: reset-names = "aio"; resets = <&sys_rst 40>; #sound-dai-cells = <1>; + + socionext,syscon = <&sg>; }; -- cgit v1.2.3 From 3b84574d95c020f01410ff2ca0a38dd8fd7b644b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Mar 2018 16:35:12 +0100 Subject: ASoC: samsung: Mark unused Odroid compatibles as deprecated Compatible for XU4 audio is not being used. Instead the board uses the same compatible as XU3. The devices are now just compatible so they should use the same value. Mark "hardkernel,odroid-xu4-audio" as being deprecated so in this future could be removed to limit useless properties. Additionally add older compatibles appearing in the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/samsung,odroid.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.txt b/Documentation/devicetree/bindings/sound/samsung,odroid.txt index f35a2694eb04..e9da2200e173 100644 --- a/Documentation/devicetree/bindings/sound/samsung,odroid.txt +++ b/Documentation/devicetree/bindings/sound/samsung,odroid.txt @@ -3,7 +3,9 @@ Samsung Exynos Odroid XU3/XU4 audio complex with MAX98090 codec Required properties: - compatible - "hardkernel,odroid-xu3-audio" - for Odroid XU3 board, - "hardkernel,odroid-xu4-audio" - for Odroid XU4 board + "hardkernel,odroid-xu4-audio" - for Odroid XU4 board (deprecated), + "samsung,odroid-xu3-audio" - for Odroid XU3 board (deprecated), + "samsung,odroid-xu4-audio" - for Odroid XU4 board (deprecated) - model - the user-visible name of this sound complex - clocks - should contain entries matching clock names in the clock-names property -- cgit v1.2.3 From da263026c013412110da464537e1c5532f0714ee Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 Mar 2018 14:59:45 +0100 Subject: ASoC: rsnd: Document R-Car M3-W support Document support for the sound modules in the Renesas M3-W (r8a7796) SoC. No driver update is needed. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/renesas,rsnd.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index 5bed9a595772..b86d790f630f 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt @@ -351,6 +351,7 @@ Required properties: - "renesas,rcar_sound-r8a7793" (R-Car M2-N) - "renesas,rcar_sound-r8a7794" (R-Car E2) - "renesas,rcar_sound-r8a7795" (R-Car H3) + - "renesas,rcar_sound-r8a7796" (R-Car M3-W) - reg : Should contain the register physical address. required register is SRU/ADG/SSI if generation1 -- cgit v1.2.3 From e4fe156ae8ec5227e6cbdbca61a0f72e77a67c8b Mon Sep 17 00:00:00 2001 From: Mylène Josserand Date: Thu, 15 Mar 2018 17:18:25 +0100 Subject: ASoC: Add bindings for PCM1789 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a device-tree binding for Texas Instrument's PCM1789 codec. For the moment, only I2C bus is supported but SPI could be added in future. Signed-off-by: Mylène Josserand Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/pcm1789.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/pcm1789.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/pcm1789.txt b/Documentation/devicetree/bindings/sound/pcm1789.txt new file mode 100644 index 000000000000..3c74ed220ac2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/pcm1789.txt @@ -0,0 +1,22 @@ +Texas Instruments pcm1789 DT bindings + +PCM1789 is a simple audio codec that can be connected via +I2C or SPI. Currently, only I2C bus is supported. + +Required properties: + + - compatible: "ti,pcm1789" + +Required properties on I2C: + + - reg: the I2C address + - reset-gpios: GPIO to control the RESET pin + +Examples: + + audio-codec@4c { + compatible = "ti,pcm1789"; + reg = <0x4c>; + reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + }; -- cgit v1.2.3 From 050a0e1f539448474250f441332c0a7d9714d3b5 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Sun, 18 Mar 2018 13:22:37 -0400 Subject: ASoC: add tda7419 audio processor binding DeviceTree binding for the tda7419 audio processor. Signed-off-by: Matt Porter Signed-off-by: Mark Brown --- .../devicetree/bindings/sound/tda7419.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/tda7419.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/tda7419.txt b/Documentation/devicetree/bindings/sound/tda7419.txt new file mode 100644 index 000000000000..6b85ec38dd56 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tda7419.txt @@ -0,0 +1,38 @@ +TDA7419 audio processor + +This device supports I2C only. + +Required properties: + +- compatible : "st,tda7419" +- reg : the I2C address of the device. +- vdd-supply : a regulator spec for the common power supply (8-10V) + +Optional properties: + +- st,mute-gpios : a GPIO spec for the MUTE pin. + +Pins on the device (for linking into audio routes): + + * SE3L + * SE3R + * SE2L + * SE2R + * SE1L + * SE1R + * DIFFL + * DIFFR + * MIX + * OUTLF + * OUTRF + * OUTLR + * OUTRR + * OUTSW + +Example: + +ap: tda7419@44 { + compatible = "st,tda7419"; + reg = <0x44>; + vdd-supply = <&vdd_9v0_reg>; +}; -- cgit v1.2.3 From 274ce5e24170d20160d1ebc2e5e83b371646bf60 Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev Date: Tue, 6 Mar 2018 14:46:15 +0300 Subject: dt-bindings: Document the Synopsys DW AXI DMA bindings This patch adds documentation of device tree bindings for the Synopsys DesignWare AXI DMA controller. Signed-off-by: Eugeniy Paltsev Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt new file mode 100644 index 000000000000..f237b7928283 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt @@ -0,0 +1,41 @@ +Synopsys DesignWare AXI DMA Controller + +Required properties: +- compatible: "snps,axi-dma-1.01a" +- reg: Address range of the DMAC registers. This should include + all of the per-channel registers. +- interrupt: Should contain the DMAC interrupt number. +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device. +- dma-channels: Number of channels supported by hardware. +- snps,dma-masters: Number of AXI masters supported by the hardware. +- snps,data-width: Maximum AXI data width supported by hardware. + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) +- snps,priority: Priority of channel. Array size is equal to the number of + dma-channels. Priority value must be programmed within [0:dma-channels-1] + range. (0 - minimum priority) +- snps,block-size: Maximum block size supported by the controller channel. + Array size is equal to the number of dma-channels. + +Optional properties: +- snps,axi-max-burst-len: Restrict master AXI burst length by value specified + in this property. If this property is missing the maximum AXI burst length + supported by DMAC is used. [1:256] + +Example: + +dmac: dma-controller@80000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x80000 0x400>; + clocks = <&core_clk>, <&cfgr_clk>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <27>; + + dma-channels = <4>; + snps,dma-masters = <2>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; +}; -- cgit v1.2.3 From e5878732a521dd31ea6377875e49adc424503e5b Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Mon, 19 Mar 2018 10:02:18 +0800 Subject: ahci: imx: add the imx6qp ahci sata support - Regarding to imx6q ahci sata, imx6qp ahci sata has the reset mechanism. Add the imx6qp ahci sata support in this commit. - Use the specific reset callback for imx53 sata, and use the default ahci_ops.softreset for the others. Signed-off-by: Richard Zhu Signed-off-by: Tejun Heo --- Documentation/devicetree/bindings/ata/imx-sata.txt | 1 + drivers/ata/ahci_imx.c | 36 +++++++++++++++++++--- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 2 ++ 3 files changed, 35 insertions(+), 4 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt index a3d14719e478..781f88751762 100644 --- a/Documentation/devicetree/bindings/ata/imx-sata.txt +++ b/Documentation/devicetree/bindings/ata/imx-sata.txt @@ -7,6 +7,7 @@ Required properties: - compatible : should be one of the following: - "fsl,imx53-ahci" for i.MX53 SATA controller - "fsl,imx6q-ahci" for i.MX6Q SATA controller + - "fsl,imx6qp-ahci" for i.MX6QP SATA controller - interrupts : interrupt mapping for SATA IRQ - reg : registers mapping - clocks : list of clock specifiers, must contain an entry for each diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index a58bcc069c54..577458fe4aa9 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -58,6 +58,7 @@ enum { enum ahci_imx_type { AHCI_IMX53, AHCI_IMX6Q, + AHCI_IMX6QP, }; struct imx_ahci_priv { @@ -188,11 +189,26 @@ static int imx_phy_reg_read(u16 *val, void __iomem *mmio) static int imx_sata_phy_reset(struct ahci_host_priv *hpriv) { + struct imx_ahci_priv *imxpriv = hpriv->plat_data; void __iomem *mmio = hpriv->mmio; int timeout = 10; u16 val; int ret; + if (imxpriv->type == AHCI_IMX6QP) { + /* 6qp adds the sata reset mechanism, use it for 6qp sata */ + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_PD, 0); + + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_RST, 0); + udelay(50); + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_RST, + IMX6Q_GPR5_SATA_SW_RST); + return 0; + } + /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); if (ret) @@ -408,7 +424,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) if (ret < 0) goto disable_regulator; - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { /* * set PHY Paremeters, two steps to configure the GPR13, * one write for rest of parameters, mask of first write @@ -459,10 +475,21 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv) if (imxpriv->no_device) return; - if (imxpriv->type == AHCI_IMX6Q) { + switch (imxpriv->type) { + case AHCI_IMX6QP: + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5, + IMX6Q_GPR5_SATA_SW_PD, + IMX6Q_GPR5_SATA_SW_PD); regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, IMX6Q_GPR13_SATA_MPLL_CLK_EN, !IMX6Q_GPR13_SATA_MPLL_CLK_EN); + break; + + case AHCI_IMX6Q: + regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, + IMX6Q_GPR13_SATA_MPLL_CLK_EN, + !IMX6Q_GPR13_SATA_MPLL_CLK_EN); + break; } clk_disable_unprepare(imxpriv->sata_ref_clk); @@ -513,7 +540,7 @@ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class, if (imxpriv->type == AHCI_IMX53) ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); - else if (imxpriv->type == AHCI_IMX6Q) + else ret = ahci_ops.softreset(link, class, deadline); return ret; @@ -536,6 +563,7 @@ static const struct ata_port_info ahci_imx_port_info = { static const struct of_device_id imx_ahci_of_match[] = { { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, + { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP }, {}, }; MODULE_DEVICE_TABLE(of, imx_ahci_of_match); @@ -743,7 +771,7 @@ static int imx_ahci_probe(struct platform_device *pdev) return PTR_ERR(imxpriv->ahb_clk); } - if (imxpriv->type == AHCI_IMX6Q) { + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { u32 reg_value; imxpriv->gpr = syscon_regmap_lookup_by_compatible( diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c8e0164c5423..e06f5f79eaef 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -243,6 +243,8 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_SATA_SW_PD BIT(10) +#define IMX6Q_GPR5_SATA_SW_RST BIT(11) #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) -- cgit v1.2.3 From 2817a92dd90ab8c53f2c03b7c4d5f8590ee36940 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 6 Mar 2018 17:09:29 +0800 Subject: dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device The MediaTek audio hardware block that exposes functionalities that are handled by separate subsystems in the kernel. These functions are all mapped somewhere at 0x112xxxxx, and there are some control bits are mixed up with other functions within the same registers. This patch modifies example to illustrate child nodes. Signed-off-by: Ryder Lee Signed-off-by: Stephen Boyd --- .../bindings/arm/mediatek/mediatek,audsys.txt | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index 9b8f578d5e19..97b304eaa47c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -13,10 +13,19 @@ The AUDSYS controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. +Required sub-nodes: +------- +For common binding part and usage, refer to +../sonud/mt2701-afe-pcm.txt. + Example: -audsys: audsys@11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x1000>; - #clock-cells = <1>; -}; + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7622-audsys", "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + ... + }; + }; -- cgit v1.2.3 From 9cb12501f38f924567ea7ba10041d32ecd7bf809 Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 6 Mar 2018 17:09:30 +0800 Subject: dt-bindings: clock: mediatek: add audsys support for MT2701 This patch adds a compatible string for MT2701. Signed-off-by: Ryder Lee Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index 97b304eaa47c..34a69ba67f13 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system. Required Properties: - compatible: Should be one of: + - "mediatek,mt2701-audsys", "syscon" - "mediatek,mt7622-audsys", "syscon" - #clock-cells: Must be 1 -- cgit v1.2.3 From d41850437c364ef7aba9bc25c1c701699d0240e0 Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Thu, 15 Mar 2018 16:25:07 +0000 Subject: arm64: dts: allwinner: a64: Add watchdog Add a watchdog node for the A64, automatically enabled on all boards. Since the device is compatible with an existing driver, we only reserve a new compatible string to be used together with the fall back. Tested on Olimex Teres-I. Signed-off-by: Harald Geyer Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 6 ++++-- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 +++++++ 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index 62dd5baad70e..04fc368d828f 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer Required properties: -- compatible : should be either "allwinner,sun4i-a10-wdt" or - "allwinner,sun6i-a31-wdt" +- compatible : should be one of + "allwinner,sun4i-a10-wdt" + "allwinner,sun6i-a31-wdt" + "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt" - reg : Specifies base physical address and size of the registers. Example: diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 64e452a758fa..8401e7f887ff 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -665,5 +665,12 @@ #address-cells = <1>; #size-cells = <0>; }; + + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun50i-a64-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = ; + }; }; }; -- cgit v1.2.3 From 648d1382d422076364a874b8b92b9ec3ff37874e Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 28 Feb 2018 12:54:53 +0800 Subject: dt-bindings: mailbox: Introduce Hi3660 controller binding Introduce a binding for the Hi3660 mailbox controller, the mailbox is used within application processor (AP), communication processor (CP), HIFI and MCU, etc. Acked-by: Rob Herring Signed-off-by: Leo Yan Signed-off-by: Jassi Brar --- .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt new file mode 100644 index 000000000000..3e5b4537407d --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt @@ -0,0 +1,51 @@ +Hisilicon Hi3660 Mailbox Controller + +Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages +are passed between processors, including application & communication +processors, MCU, HIFI, etc. Each channel is unidirectional and accessed +by using MMIO registers; it supports maximum to 8 words message. + +Controller +---------- + +Required properties: +- compatible: : Shall be "hisilicon,hi3660-mbox" +- reg: : Offset and length of the device's register set +- #mbox-cells: : Must be 3 + <&phandle channel dst_irq ack_irq> + phandle : Label name of controller + channel : Channel number + dst_irq : Remote interrupt vector + ack_irq : Local interrupt vector + +- interrupts: : Contains the two IRQ lines for mailbox. + +Example: + +mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = <0x0 0xc0 0x4>, + <0x0 0xc1 0x4>; + #mbox-cells = <3>; +}; + +Client +------ + +Required properties: +- compatible : See the client docs +- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) + Cells must match 'mbox-cells' (See Controller docs above) + +Optional properties +- mbox-names : Name given to channels seen in the 'mboxes' property. + +Example: + +stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; +}; -- cgit v1.2.3 From 418dbeb618a07a18f0389a482cdfea1bae181671 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 14 Mar 2018 15:53:11 +0200 Subject: dt-bindings: omap5: ctrl: Support for control module wkup pad config The pad configuration area under control module wkup has some miscellaneous config registers, that are not pinmux related. Add new compatible string for this section of control module. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/arm/omap/ctrl.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt index ce8dabf8c0f9..f35b77920786 100644 --- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt +++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt @@ -25,6 +25,7 @@ Required properties: "ti,omap4-scm-padconf-wkup" "ti,omap5-scm-core" "ti,omap5-scm-padconf-core" + "ti,omap5-scm-wkup-pad-conf" "ti,dra7-scm-core" - reg: Contains Control Module register address range (base address and length) -- cgit v1.2.3 From b6e37ce2371dac0d696332d8e74c110030ab47c3 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:17 -0500 Subject: dt-bindings: clock: Add new bindings for TI Davinci PLL clocks This adds a new binding for the PLL IP blocks in the mach-davinci family of processors. Currently, only da850 has device tree support but these bindings can also work for other SoCs in this family just by adding new compatible strings. Note: Although these PLL controllers are very similar to the TI Keystone SoCs, we are not re-using those bindings. The Keystone bindings use a legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs have a slightly different PLL register layout and a number of quirks that can't be handled by the existing bindings, so the keystone bindings could not be used as-is anyway. Signed-off-by: David Lechner Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/ti/davinci/pll.txt | 96 ++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt new file mode 100644 index 000000000000..36998e184821 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt @@ -0,0 +1,96 @@ +Binding for TI DaVinci PLL Controllers + +The PLL provides clocks to most of the components on the SoC. In addition +to the PLL itself, this controller also contains bypasses, gates, dividers, +an multiplexers for various clock signals. + +Required properties: +- compatible: shall be one of: + - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX + - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX +- reg: physical base address and size of the controller's register area. +- clocks: phandles corresponding to the clock names +- clock-names: names of the clock sources - depends on compatible string + - for "ti,da850-pll0", shall be "clksrc", "extclksrc" + - for "ti,da850-pll1", shall be "clksrc" + +Optional properties: +- ti,clkmode-square-wave: Indicates that the the board is supplying a square + wave input on the OSCIN pin instead of using a crystal oscillator. + This property is only valid when compatible = "ti,da850-pll0". + + +Optional child nodes: + +pllout + Describes the main PLL clock output (before POSTDIV). The node name must + be "pllout". + + Required properties: + - #clock-cells: shall be 0 + +sysclk + Describes the PLLDIVn divider clocks that provide the SYSCLKn clock + domains. The node name must be "sysclk". Consumers of this node should + use "n" in "SYSCLKn" as the index parameter for the clock cell. + + Required properties: + - #clock-cells: shall be 1 + +auxclk + Describes the AUXCLK output of the PLL. The node name must be "auxclk". + This child node is only valid when compatible = "ti,da850-pll0". + + Required properties: + - #clock-cells: shall be 0 + +obsclk + Describes the OBSCLK output of the PLL. The node name must be "obsclk". + + Required properties: + - #clock-cells: shall be 0 + + +Examples: + + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>, <&pll1_sysclk 3>; + clock-names = "clksrc", "extclksrc"; + ti,clkmode-square-wave; + + pll0_pllout: pllout { + #clock-cells = <0>; + }; + + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + + pll0_auxclk: auxclk { + #clock-cells = <0>; + }; + + pll0_obsclk: obsclk { + #clock-cells = <0>; + }; + }; + + pll1: clock-controller@21a000 { + compatible = "ti,da850-pll1"; + reg = <0x21a000 0x1000>; + clocks = <&ref_clk>; + clock-names = "clksrc"; + + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + + pll0_obsclk: obsclk { + #clock-cells = <0>; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt -- cgit v1.2.3 From 21cdf7269f9dcd8dc22d152fbfee85e4ea57289f Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:25 -0500 Subject: dt-bindings: clock: New bindings for TI Davinci PSC This adds a new binding for the Power Sleep Controller (PSC) for the mach-davinci family of processors. Note: Although TI Keystone has a very similar PSC, we are not using the existing bindings. Keystone is using a legacy one-node-per-clock binding (actually two nodes if you count the separate reset binding for the same IP block). Also, some davinci LPSCs have quirks that aren't handled by the keystone bindings, so we would be adding one compatible string per clock with quirks instead of just a new compatible string for each controller. Signed-off-by: David Lechner Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/ti/davinci/psc.txt | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/psc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt new file mode 100644 index 000000000000..dae4ad8e198c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt @@ -0,0 +1,71 @@ +Binding for TI DaVinci Power Sleep Controller (PSC) + +The PSC provides power management, clock gating and reset functionality. It is +primarily used for clocking. + +Required properties: +- compatible: shall be one of: + - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX + - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX +- reg: physical base address and size of the controller's register area +- #clock-cells: from common clock binding; shall be set to 1 +- #power-domain-cells: from generic power domain binding; shall be set to 1. +- clocks: phandles to clocks corresponding to the clock-names property +- clock-names: list of parent clock names - depends on compatible value + - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2", + "pll0_sysclk4", "pll0_sysclk6", "async1" + - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3" + +Optional properties: +- #reset-cells: from reset binding; shall be set to 1 - only applicable when + at least one local domain provides a local reset. + +Consumers: + + Clock, power domain and reset consumers shall use the local power domain + module ID (LPSC) as the index corresponding to the clock cell. Refer to + the device-specific datasheet to find these numbers. NB: Most local + domains only provide a clock/power domain and not a reset. + +Examples: + + psc0: clock-controller@10000 { + compatible = "ti,da850-psc0"; + reg = <0x10000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, + <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>; + clock_names = "pll0_sysclk1", "pll0_sysclk2", + "pll0_sysclk4", "pll0_sysclk6", "async1"; + }; + psc1: clock-controller@227000 { + compatible = "ti,da850-psc1"; + reg = <0x227000 0x1000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>; + clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3"; + }; + + /* consumer */ + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + clocks = <&psc0 15>; + power-domains = <&psc0 15>; + resets = <&psc0 15>; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt +- Documentation/devicetree/bindings/power/power_domain.txt +- Documentation/devicetree/bindings/reset/reset.txt -- cgit v1.2.3 From 0c92c71770457df9c5459190ba72350459785f37 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Thu, 15 Mar 2018 21:52:33 -0500 Subject: dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks This adds a new binding for the clocks present in the CFGCHIP syscon registers in TI DA8XX SoCs. Signed-off-by: David Lechner Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../bindings/clock/ti/davinci/da8xx-cfgchip.txt | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt new file mode 100644 index 000000000000..1e03dce99a8f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt @@ -0,0 +1,93 @@ +Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks + +TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of +registers call CFGCHIPn. Some of these registers function as clock +gates. This document describes the bindings for those clocks. + +All of the clock nodes described below must be child nodes of a CFGCHIP node +(compatible = "ti,da830-cfgchip"). + +USB PHY clocks +-------------- +Required properties: +- compatible: shall be "ti,da830-usb-phy-clocks". +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: phandles to the parent clocks corresponding to clock-names +- clock-names: shall be "fck", "usb_refclkin", "auxclk" + +This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz +clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock. + +eHRPWM Time Base Clock (TBCLK) +------------------------------ +Required properties: +- compatible: shall be "ti,da830-tbclksync". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle to the parent clock +- clock-names: shall be "fck" + +PLL DIV4.5 divider +------------------ +Required properties: +- compatible: shall be "ti,da830-div4p5ena". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle to the parent clock +- clock-names: shall be "pll0_pllout" + +EMIFA clock source (ASYNC1) +--------------------------- +Required properties: +- compatible: shall be "ti,da850-async1-clksrc". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandles to the parent clocks corresponding to clock-names +- clock-names: shall be "pll0_sysclk3", "div4.5" + +ASYNC3 clock source +------------------- +Required properties: +- compatible: shall be "ti,da850-async3-clksrc". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandles to the parent clocks corresponding to clock-names +- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2" + +Examples: + + cfgchip: syscon@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + usb_phy_clk: usb-phy-clocks { + compatible = "ti,da830-usb-phy-clocks"; + #clock-cells = <1>; + clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>; + clock-names = "fck", "usb_refclkin", "auxclk"; + }; + ehrpwm_tbclk: ehrpwm_tbclk { + compatible = "ti,da830-tbclksync"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-names = "fck"; + }; + div4p5_clk: div4.5 { + compatible = "ti,da830-div4p5ena"; + #clock-cells = <0>; + clocks = <&pll0_pllout>; + clock-names = "pll0_pllout"; + }; + async1_clk: async1 { + compatible = "ti,da850-async1-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 3>, <&div4p5_clk>; + clock-names = "pll0_sysclk3", "div4.5"; + }; + async3_clk: async3 { + compatible = "ti,da850-async3-clksrc"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt + -- cgit v1.2.3 From 9fe77e0166ae453d61954e8200b90ac7000242de Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 24 Jan 2018 15:42:00 +0000 Subject: dt-bindings: iommu: ipmmu-vmsa: Add device tree support for r8a774[35] Document r8a774[35] specific compatible strings. The Renesas RZ/G1[ME] (r8a774[35]) IPMMU are identical to the R-Car Gen2 family. Signed-off-by: Biju Das Reviewed-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Joerg Roedel --- Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt index 1fd5d69647ca..ffadb7c6f1f3 100644 --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt @@ -11,6 +11,8 @@ Required Properties: the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU. - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU. + - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU. + - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU. - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU. - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU. - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. @@ -19,7 +21,8 @@ Required Properties: - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU. - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU. - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU. - - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU. + - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible + IPMMU. - reg: Base address and size of the IPMMU registers. - interrupts: Specifiers for the MMU fault interrupts. For instances that -- cgit v1.2.3 From 279df1917d3e7817983bf5b3476643ec6dfd6f22 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 20 Mar 2018 13:03:32 -0300 Subject: ASoC: rockchip: Fix compatible string in example Use the correct compatible string in the example devicetree snippet, which was probably overlooked. Signed-off-by: Ezequiel Garcia Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt index 2539e1d68107..e5430d1d34e4 100644 --- a/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt +++ b/Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt @@ -22,7 +22,7 @@ Optionnal properties: Example: sound { - compatible = "rockchip,rockchip-audio-es8388"; + compatible = "rockchip,rk3288-hdmi-analog"; rockchip,model = "Analog audio output"; rockchip,i2s-controller = <&i2s>; rockchip,audio-codec = <&es8388>; -- cgit v1.2.3 From c0a2676c911c73cf7c753083fdd8f775063d324b Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Tue, 16 Jan 2018 17:06:16 +0100 Subject: dt-bindings: at24: add compatible for nxp,se97b The datasheet talks about the chip being an spd, but the chip is writable so atmel,24c02 is more appropriate as fallback. Signed-off-by: Peter Rosin Reviewed-by: Rob Herring Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/eeprom/at24.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index abfae1beca2b..edf9247613f6 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -46,6 +46,7 @@ Required properties: Some vendors use different model names for chips which are just variants of the above. Known such exceptions are listed below: + "nxp,se97b" - the fallback is "atmel,24c02", "renesas,r1ex24002" - the fallback is "atmel,24c02" - reg: The I2C address of the EEPROM. -- cgit v1.2.3 From 3644784caa017cc3cf4188fb0bfbf3421e8aa7ad Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 2 Mar 2018 11:14:16 +0100 Subject: dt-bindings: at24: add bindings for Rohm BR24T01 Both manufacturer and name variant. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Reviewed-by: Rob Herring Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index edf9247613f6..a201a1183118 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -41,6 +41,7 @@ Required properties: "nxp", "ramtron", "renesas", + "rohm", "st", Some vendors use different model names for chips which are just @@ -48,6 +49,7 @@ Required properties: "nxp,se97b" - the fallback is "atmel,24c02", "renesas,r1ex24002" - the fallback is "atmel,24c02" + "rohm,br24t01" - the fallback is "atmel,24c01" - reg: The I2C address of the EEPROM. -- cgit v1.2.3 From 84e10623c0b9c81557918804f309d66aec86a233 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 2 Mar 2018 17:56:37 +0100 Subject: dt-bindings: at24: add Renesas R1EX24128 Document the compatible value for the Renesas R1EX24128ASAS0A two-wire serial interface EEPROM, so it can be used in DTS files without causing checkpatch warnings. Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Acked-by: Wolfram Sang Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/eeprom/at24.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt index a201a1183118..61d833abafbf 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.txt +++ b/Documentation/devicetree/bindings/eeprom/at24.txt @@ -49,6 +49,7 @@ Required properties: "nxp,se97b" - the fallback is "atmel,24c02", "renesas,r1ex24002" - the fallback is "atmel,24c02" + "renesas,r1ex24128" - the fallback is "atmel,24c128" "rohm,br24t01" - the fallback is "atmel,24c01" - reg: The I2C address of the EEPROM. -- cgit v1.2.3 From d60f6e3713ecf56408c38d761ef7fc0ce9510f16 Mon Sep 17 00:00:00 2001 From: Philipp Rossak Date: Tue, 13 Feb 2018 07:29:48 -0500 Subject: media: dt: bindings: Update binding documentation for sunxi IR controller This patch updates documentation for Device-Tree bindings for sunxi IR controller and adds the new optional property for the base clock frequency. Signed-off-by: Philipp Rossak Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt index 91648c569b1e..278098987edb 100644 --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt @@ -11,6 +11,8 @@ Required properties: Optional properties: - linux,rc-map-name: see rc.txt file in the same directory. - resets : phandle + reset specifier pair +- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz + if missing. Example: @@ -18,6 +20,7 @@ ir0: ir@1c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; + clock-frequency = <3000000>; resets = <&apb0_rst 1>; interrupts = <0 5 1>; reg = <0x01C21800 0x40>; -- cgit v1.2.3 From 9feb786876c711a11002dd35cae6c814abe354e9 Mon Sep 17 00:00:00 2001 From: Jean-Michel Hautbois Date: Tue, 13 Feb 2018 12:48:53 -0500 Subject: media: dt-bindings: media: adv7604: Extend bindings to allow specifying slave map addresses The ADV7604 has thirteen 256-byte maps that can be accessed via the main I2C ports. Each map has it own I2C address and acts as a standard slave device on the I2C bus. Extend the device tree node bindings to be able to override the default addresses so that address conflicts with other devices on the same bus may be resolved at the board description level. [Kieran: Re-adapted for mainline] Signed-off-by: Jean-Michel Hautbois Signed-off-by: Kieran Bingham Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/i2c/adv7604.txt | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.txt b/Documentation/devicetree/bindings/media/i2c/adv7604.txt index 9cbd92eb5d05..dcf57e7c60eb 100644 --- a/Documentation/devicetree/bindings/media/i2c/adv7604.txt +++ b/Documentation/devicetree/bindings/media/i2c/adv7604.txt @@ -13,7 +13,11 @@ Required Properties: - "adi,adv7611" for the ADV7611 - "adi,adv7612" for the ADV7612 - - reg: I2C slave address + - reg: I2C slave addresses + The ADV76xx has up to thirteen 256-byte maps that can be accessed via the + main I2C ports. Each map has it own I2C address and acts as a standard + slave device on the I2C bus. The main address is mandatory, others are + optional and revert to defaults if not specified. - hpd-gpios: References to the GPIOs that control the HDMI hot-plug detection pins, one per HDMI input. The active flag indicates the GPIO @@ -35,6 +39,11 @@ Optional Properties: - reset-gpios: Reference to the GPIO connected to the device's reset pin. - default-input: Select which input is selected after reset. + - reg-names : Names of maps with programmable addresses. + It can contain any map needing a non-default address. + Possible maps names are : + "main", "avlink", "cec", "infoframe", "esdp", "dpp", "afe", + "rep", "edid", "hdmi", "test", "cp", "vdp" Optional Endpoint Properties: @@ -52,7 +61,12 @@ Example: hdmi_receiver@4c { compatible = "adi,adv7611"; - reg = <0x4c>; + /* + * The edid page will be accessible @ 0x66 on the I2C bus. All + * other maps will retain their default addresses. + */ + reg = <0x4c>, <0x66>; + reg-names "main", "edid"; reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>; hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From b3fd27e9150f7ac2a2bd3f61aa71aadb4db499b2 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 20 Mar 2018 14:07:56 +0100 Subject: dt-bindings: Add vendor prefix for Microsemi Corporation Microsemi Corporation provides semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Signed-off-by: Alexandre Belloni Acked-by: Rob Herring Cc: Ralf Baechle Cc: Allan Nielsen Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18853/ Signed-off-by: James Hogan --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index ae850d6c0ad3..ffc959ef53e9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -224,6 +224,7 @@ motorola Motorola, Inc. moxa Moxa Inc. mpl MPL AG mqmaker mqmaker Inc. +mscc Microsemi Corporation msi Micro-Star International Co. Ltd. mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) multi-inno Multi-Inno Technology Co.,Ltd -- cgit v1.2.3 From 2707177e86ec9b25c0988c2cc827acbae409b376 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 20 Mar 2018 14:07:57 +0100 Subject: dt-bindings: mips: Add bindings for Microsemi SoCs Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Signed-off-by: Alexandre Belloni Reviewed-by: Rob Herring Cc: Ralf Baechle Cc: Allan Nielsen Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18854/ Signed-off-by: James Hogan --- Documentation/devicetree/bindings/mips/mscc.txt | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt new file mode 100644 index 000000000000..ae15ec333542 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -0,0 +1,43 @@ +* Microsemi MIPS CPUs + +Boards with a SoC of the Microsemi MIPS family shall have the following +properties: + +Required properties: +- compatible: "mscc,ocelot" + + +* Other peripherals: + +o CPU chip regs: + +The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous +functionalities: chip ID, general purpose register for software use, reset +controller, hardware status and configuration, efuses. + +Required properties: +- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@71070000 { + compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + }; + + +o CPU system control: + +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU +endianness, CPU bus control, CPU status. + +Required properties: +- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@70000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x70000000 0x2c>; + }; -- cgit v1.2.3 From 48f80609e536bc9be12c64e4c6c69625baee7b02 Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Fri, 16 Mar 2018 15:35:38 -0700 Subject: usb: dwc3: Make TX/RX threshold configurable DWC_usb31 periodic transfer at 48K+ bytes per interval may need modification to the TX/RX packet threshold to achieve optimal result. Add properties to make it configurable. By default, periodic ESS TX and RX threshold are not enabled. To enable TX or RX threshold (host mode only), both packet threshold count and max burst size properties must be set to a valid non-zero value 1-16. DWC_usb31 programming guide section 1.2.3 and 1.2.4. Cc: John Youn Reviewed-by: Rob Herring Signed-off-by: Thinh Nguyen Signed-off-by: Felipe Balbi --- Documentation/devicetree/bindings/usb/dwc3.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 44e8bab159ad..0dbd3083e7dd 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -57,6 +57,22 @@ Optional properties: - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame length adjustment when the fladj_30mhz_sdbnd signal is invalid or incorrect. + - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode + only. Set this and rx-max-burst-prd to a valid, + non-zero value 1-16 (DWC_usb31 programming guide + section 1.2.4) to enable periodic ESS RX threshold. + - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set + this and rx-thr-num-pkt-prd to a valid, non-zero value + 1-16 (DWC_usb31 programming guide section 1.2.4) to + enable periodic ESS RX threshold. + - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode + only. Set this and tx-max-burst-prd to a valid, + non-zero value 1-16 (DWC_usb31 programming guide + section 1.2.3) to enable periodic ESS TX threshold. + - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set + this and tx-thr-num-pkt-prd to a valid, non-zero value + 1-16 (DWC_usb31 programming guide section 1.2.3) to + enable periodic ESS TX threshold. - tx-fifo-resize: determines if the FIFO *has* to be reallocated. -- cgit v1.2.3 From 1dd5e986a9b9794a314ee59aca3fbbbf209c2076 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 9 Mar 2018 04:34:40 -0500 Subject: media: dt-bindings: media: rcar_vin: Use status "okay" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the Devicetree Specification, "ok" is not a valid status. Fixes: 47c71bd61b772cd7 ("[media] rcar_vin: add devicetree support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/media/rcar_vin.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index 19357d0bbe65..1ce7ff9449c5 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt @@ -56,7 +56,7 @@ Board setup example (vin1 composite video input) ------------------------------------------------ &i2c2 { - status = "ok"; + status = "okay"; pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -79,7 +79,7 @@ Board setup example (vin1 composite video input) pinctrl-0 = <&vin1_pins>; pinctrl-names = "default"; - status = "ok"; + status = "okay"; port { #address-cells = <1>; -- cgit v1.2.3 From b1394dc151cba4c50316ea43136b28de541c043b Mon Sep 17 00:00:00 2001 From: Smitha T Murthy Date: Fri, 2 Feb 2018 07:25:38 -0500 Subject: media: s5p-mfc: Adding initial support for MFC v10.10 Adding the support for MFC v10.10, with new register file and necessary hw control, decoder, encoder and structural changes. Signed-off-by: Smitha T Murthy Reviewed-by: Andrzej Hajda Acked-by: Rob Herring Acked-by: Hans Verkuil Signed-off-by: Sylwester Nawrocki Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/media/s5p-mfc.txt | 1 + drivers/media/platform/s5p-mfc/regs-mfc-v10.h | 35 ++++++++++++++++++++++ drivers/media/platform/s5p-mfc/s5p_mfc.c | 25 ++++++++++++++++ drivers/media/platform/s5p-mfc/s5p_mfc_common.h | 9 +++++- drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c | 4 +++ drivers/media/platform/s5p-mfc/s5p_mfc_dec.c | 32 ++++++++------------ drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 16 ++++------ drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 9 ++++-- drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h | 2 ++ 9 files changed, 100 insertions(+), 33 deletions(-) create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index d3404b5d4d17..aa54c8159d9f 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -13,6 +13,7 @@ Required properties: (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC + (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC - reg : Physical base address of the IP registers and length of memory mapped region. diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h new file mode 100644 index 000000000000..4422a75db727 --- /dev/null +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Register definition file for Samsung MFC V10.x Interface (FIMV) driver + * + */ + +#ifndef _REGS_MFC_V10_H +#define _REGS_MFC_V10_H + +#include +#include "regs-mfc-v8.h" + +/* MFCv10 register definitions*/ +#define S5P_FIMV_MFC_CLOCK_OFF_V10 0x7120 +#define S5P_FIMV_MFC_STATE_V10 0x7124 + +/* MFCv10 Context buffer sizes */ +#define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K) +#define MFC_H264_DEC_CTX_BUF_SIZE_V10 (2 * SZ_1M) +#define MFC_OTHER_DEC_CTX_BUF_SIZE_V10 (20 * SZ_1K) +#define MFC_H264_ENC_CTX_BUF_SIZE_V10 (100 * SZ_1K) +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10 (15 * SZ_1K) + +/* MFCv10 variant defines */ +#define MAX_FW_SIZE_V10 (SZ_1M) +#define MAX_CPB_SIZE_V10 (3 * SZ_1M) +#define MFC_VERSION_V10 0xA0 +#define MFC_NUM_PORTS_V10 1 + +#endif /*_REGS_MFC_V10_H*/ + diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index d5b94fc0040e..a653e3a9197a 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -1607,6 +1607,28 @@ static struct s5p_mfc_variant mfc_drvdata_v8_5433 = { .num_clocks = 3, }; +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = { + .dev_ctx = MFC_CTX_BUF_SIZE_V10, + .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V10, + .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V10, + .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V10, + .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V10, +}; + +static struct s5p_mfc_buf_size buf_size_v10 = { + .fw = MAX_FW_SIZE_V10, + .cpb = MAX_CPB_SIZE_V10, + .priv = &mfc_buf_size_v10, +}; + +static struct s5p_mfc_variant mfc_drvdata_v10 = { + .version = MFC_VERSION_V10, + .version_bit = MFC_V10_BIT, + .port_num = MFC_NUM_PORTS_V10, + .buf_size = &buf_size_v10, + .fw_name[0] = "s5p-mfc-v10.fw", +}; + static const struct of_device_id exynos_mfc_match[] = { { .compatible = "samsung,mfc-v5", @@ -1623,6 +1645,9 @@ static const struct of_device_id exynos_mfc_match[] = { }, { .compatible = "samsung,exynos5433-mfc", .data = &mfc_drvdata_v8_5433, + }, { + .compatible = "samsung,mfc-v10", + .data = &mfc_drvdata_v10, }, {}, }; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index 91090fc5a551..c4f0968534b5 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -23,7 +23,7 @@ #include #include #include "regs-mfc.h" -#include "regs-mfc-v8.h" +#include "regs-mfc-v10.h" #define S5P_MFC_NAME "s5p-mfc" @@ -715,11 +715,18 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); #define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0) #define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0) #define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0) +#define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0) #define MFC_V5_BIT BIT(0) #define MFC_V6_BIT BIT(1) #define MFC_V7_BIT BIT(2) #define MFC_V8_BIT BIT(3) +#define MFC_V10_BIT BIT(5) +#define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \ + MFC_V8_BIT | MFC_V10_BIT) +#define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \ + MFC_V10_BIT) +#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT) #endif /* S5P_MFC_COMMON_H_ */ diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c index a1c729c197d3..76405f5b4f7e 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c @@ -239,6 +239,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) } else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); + + if (IS_MFCV10(dev)) + mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10); + mfc_debug(2, "Will now wait for completion of firmware transfer\n"); if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) { mfc_err("Failed to load firmware\n"); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c index 42e9351303a2..81de3029f76c 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c @@ -54,7 +54,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_NONE, .type = MFC_FMT_RAW, .num_planes = 2, - .versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT, + .versions = MFC_V6PLUS_BITS, }, { .name = "4:2:0 2 Planes Y/CrCb", @@ -62,7 +62,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_NONE, .type = MFC_FMT_RAW, .num_planes = 2, - .versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT, + .versions = MFC_V6PLUS_BITS, }, { .name = "H264 Encoded Stream", @@ -70,8 +70,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_H264_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "H264/MVC Encoded Stream", @@ -79,7 +78,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_H264_MVC_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT, + .versions = MFC_V6PLUS_BITS, }, { .name = "H263 Encoded Stream", @@ -87,8 +86,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_H263_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "MPEG1 Encoded Stream", @@ -96,8 +94,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_MPEG2_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "MPEG2 Encoded Stream", @@ -105,8 +102,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_MPEG2_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "MPEG4 Encoded Stream", @@ -114,8 +110,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_MPEG4_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "XviD Encoded Stream", @@ -123,8 +118,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_MPEG4_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "VC1 Encoded Stream", @@ -132,8 +126,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_VC1_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "VC1 RCV Encoded Stream", @@ -141,8 +134,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_VC1RCV_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "VP8 Encoded Stream", @@ -150,7 +142,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_VP8_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT, + .versions = MFC_V6PLUS_BITS, }, }; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c index 0d5d465561be..9a21e8c34112 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c @@ -57,8 +57,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_NONE, .type = MFC_FMT_RAW, .num_planes = 2, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "4:2:0 2 Planes Y/CrCb", @@ -66,7 +65,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_NONE, .type = MFC_FMT_RAW, .num_planes = 2, - .versions = MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT, + .versions = MFC_V6PLUS_BITS, }, { .name = "H264 Encoded Stream", @@ -74,8 +73,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_H264_ENC, .type = MFC_FMT_ENC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "MPEG4 Encoded Stream", @@ -83,8 +81,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_MPEG4_ENC, .type = MFC_FMT_ENC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "H263 Encoded Stream", @@ -92,8 +89,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_H263_ENC, .type = MFC_FMT_ENC, .num_planes = 1, - .versions = MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | - MFC_V8_BIT, + .versions = MFC_V5PLUS_BITS, }, { .name = "VP8 Encoded Stream", @@ -101,7 +97,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_MFC_CODEC_VP8_ENC, .type = MFC_FMT_ENC, .num_planes = 1, - .versions = MFC_V7_BIT | MFC_V8_BIT, + .versions = MFC_V7PLUS_BITS, }, }; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index fe144799e304..2041d8138c5f 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -356,6 +356,7 @@ static int calc_plane(int width, int height) static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) { + struct s5p_mfc_dev *dev = ctx->dev; ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6); ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6); mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n" @@ -372,8 +373,12 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { - ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, - ctx->img_height); + if (IS_MFCV10(dev)) + ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width, + ctx->img_height); + else + ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, + ctx->img_height); ctx->mv_size = ALIGN(ctx->mv_size, 16); } else { ctx->mv_size = 0; diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h index 80558484bb40..021b8dbe2244 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h @@ -24,6 +24,8 @@ #define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, 16) #define S5P_MFC_DEC_MV_SIZE_V6(x, y) (MB_WIDTH(x) * \ (((MB_HEIGHT(y)+1)/2)*2) * 64 + 128) +#define S5P_MFC_DEC_MV_SIZE_V10(x, y) (MB_WIDTH(x) * \ + (((MB_HEIGHT(y)+1)/2)*2) * 64 + 512) /* Definition */ #define ENC_MULTI_SLICE_MB_MAX ((1 << 30) - 1) -- cgit v1.2.3 From c927d74ec0319abb0b232adf9dbe4e7be3791328 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Thu, 22 Mar 2018 16:15:23 +0100 Subject: dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Add the Device Tree binding documentation for the Microsemi Ocelot interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Acked-by: Rob Herring Signed-off-by: Alexandre Belloni Signed-off-by: Marc Zyngier --- .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt new file mode 100644 index 000000000000..b47a8a02b17b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -0,0 +1,22 @@ +Microsemi Ocelot SoC ICPU Interrupt Controller + +Required properties: + +- compatible : should be "mscc,ocelot-icpu-intr" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; -- cgit v1.2.3 From 72fd9bc8f54fa54d56adc892385d6315cf7b3494 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Mon, 19 Mar 2018 15:16:38 +0800 Subject: dt-bindings: imx: update pinctrl doc for imx6sll Add pinctrl binding doc update for imx6sll. Signed-off-by: Bai Ping Acked-by: Shawn Guo Acked-by: Dong Aisheng Signed-off-by: Linus Walleij --- .../bindings/pinctrl/fsl,imx6sll-pinctrl.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt new file mode 100644 index 000000000000..175e8939a301 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt @@ -0,0 +1,40 @@ +* Freescale i.MX6 SLL IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx6sll-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in + imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX6SLL + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_LVE (1 << 22) +PAD_CTL_HYS (1 << 16) +PAD_CTL_PUS_100K_DOWN (0 << 14) +PAD_CTL_PUS_47K_UP (1 << 14) +PAD_CTL_PUS_100K_UP (2 << 14) +PAD_CTL_PUS_22K_UP (3 << 14) +PAD_CTL_PUE (1 << 13) +PAD_CTL_PKE (1 << 12) +PAD_CTL_ODE (1 << 11) +PAD_CTL_SPEED_LOW (0 << 6) +PAD_CTL_SPEED_MED (1 << 6) +PAD_CTL_SPEED_HIGH (3 << 6) +PAD_CTL_DSE_DISABLE (0 << 3) +PAD_CTL_DSE_260ohm (1 << 3) +PAD_CTL_DSE_130ohm (2 << 3) +PAD_CTL_DSE_87ohm (3 << 3) +PAD_CTL_DSE_65ohm (4 << 3) +PAD_CTL_DSE_52ohm (5 << 3) +PAD_CTL_DSE_43ohm (6 << 3) +PAD_CTL_DSE_37ohm (7 << 3) +PAD_CTL_SRE_FAST (1 << 0) +PAD_CTL_SRE_SLOW (0 << 0) + +Refer to imx6sll-pinfunc.h in device tree source folder for all available +imx6sll PIN_FUNC_ID. -- cgit v1.2.3 From 1d17cbfbb55cd80890312dd8c64d0008b25b05c0 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 13 Mar 2018 17:48:42 +0100 Subject: crypto: inside-secure - fix clock resource by adding a register clock On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updated accordingly. Signed-off-by: Gregory CLEMENT Signed-off-by: Herbert Xu --- .../bindings/crypto/inside-secure-safexcel.txt | 6 +++- drivers/crypto/inside-secure/safexcel.c | 34 ++++++++++++++++------ drivers/crypto/inside-secure/safexcel.h | 1 + 3 files changed, 31 insertions(+), 10 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt index 30c3ce6b502e..5dba55cdfa63 100644 --- a/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt +++ b/Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt @@ -8,7 +8,11 @@ Required properties: - interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem". Optional properties: -- clocks: Reference to the crypto engine clock. +- clocks: Reference to the crypto engine clocks, the second clock is + needed for the Armada 7K/8K SoCs. +- clock-names: mandatory if there is a second clock, in this case the + name must be "core" for the first clock and "reg" for + the second one. Example: diff --git a/drivers/crypto/inside-secure/safexcel.c b/drivers/crypto/inside-secure/safexcel.c index cbcb5d9f17bd..2f68b4ed5500 100644 --- a/drivers/crypto/inside-secure/safexcel.c +++ b/drivers/crypto/inside-secure/safexcel.c @@ -895,16 +895,30 @@ static int safexcel_probe(struct platform_device *pdev) } } + priv->reg_clk = devm_clk_get(&pdev->dev, "reg"); + ret = PTR_ERR_OR_ZERO(priv->reg_clk); + /* The clock isn't mandatory */ + if (ret != -ENOENT) { + if (ret) + goto err_core_clk; + + ret = clk_prepare_enable(priv->reg_clk); + if (ret) { + dev_err(dev, "unable to enable reg clk (%d)\n", ret); + goto err_core_clk; + } + } + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); if (ret) - goto err_clk; + goto err_reg_clk; priv->context_pool = dmam_pool_create("safexcel-context", dev, sizeof(struct safexcel_context_record), 1, 0); if (!priv->context_pool) { ret = -ENOMEM; - goto err_clk; + goto err_reg_clk; } safexcel_configure(priv); @@ -919,12 +933,12 @@ static int safexcel_probe(struct platform_device *pdev) &priv->ring[i].cdr, &priv->ring[i].rdr); if (ret) - goto err_clk; + goto err_reg_clk; ring_irq = devm_kzalloc(dev, sizeof(*ring_irq), GFP_KERNEL); if (!ring_irq) { ret = -ENOMEM; - goto err_clk; + goto err_reg_clk; } ring_irq->priv = priv; @@ -936,7 +950,7 @@ static int safexcel_probe(struct platform_device *pdev) ring_irq); if (irq < 0) { ret = irq; - goto err_clk; + goto err_reg_clk; } priv->ring[i].work_data.priv = priv; @@ -947,7 +961,7 @@ static int safexcel_probe(struct platform_device *pdev) priv->ring[i].workqueue = create_singlethread_workqueue(wq_name); if (!priv->ring[i].workqueue) { ret = -ENOMEM; - goto err_clk; + goto err_reg_clk; } priv->ring[i].requests = 0; @@ -968,18 +982,20 @@ static int safexcel_probe(struct platform_device *pdev) ret = safexcel_hw_init(priv); if (ret) { dev_err(dev, "EIP h/w init failed (%d)\n", ret); - goto err_clk; + goto err_reg_clk; } ret = safexcel_register_algorithms(priv); if (ret) { dev_err(dev, "Failed to register algorithms (%d)\n", ret); - goto err_clk; + goto err_reg_clk; } return 0; -err_clk: +err_reg_clk: + clk_disable_unprepare(priv->reg_clk); +err_core_clk: clk_disable_unprepare(priv->clk); return ret; } diff --git a/drivers/crypto/inside-secure/safexcel.h b/drivers/crypto/inside-secure/safexcel.h index d8dff65fc311..4efeb0251daf 100644 --- a/drivers/crypto/inside-secure/safexcel.h +++ b/drivers/crypto/inside-secure/safexcel.h @@ -525,6 +525,7 @@ struct safexcel_crypto_priv { void __iomem *base; struct device *dev; struct clk *clk; + struct clk *reg_clk; struct safexcel_config config; enum safexcel_eip_version version; -- cgit v1.2.3 From 2805894c1ee0e598d59f055b8225ce4d0d6b2a19 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Tue, 13 Mar 2018 13:33:30 -0400 Subject: dt-bindings: rng: add bindings doc for Keystone SA HWRNG driver The Keystone SA module has a hardware random generator module. This commit adds binding doc for the KS2 SA HWRNG driver. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Reviewed-by: Rob Herring Signed-off-by: Herbert Xu --- Documentation/devicetree/bindings/rng/ks-sa-rng.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/rng/ks-sa-rng.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/rng/ks-sa-rng.txt b/Documentation/devicetree/bindings/rng/ks-sa-rng.txt new file mode 100644 index 000000000000..b7a65b487901 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/ks-sa-rng.txt @@ -0,0 +1,21 @@ +Keystone SoC Hardware Random Number Generator(HWRNG) Module + +On Keystone SoCs HWRNG module is a submodule of the Security Accelerator. + +- compatible: should be "ti,keystone-rng" +- ti,syscon-sa-cfg: phandle to syscon node of the SA configuration registers. + This registers are shared between hwrng and crypto drivers. +- clocks: phandle to the reference clocks for the subsystem +- clock-names: functional clock name. Should be set to "fck" +- reg: HWRNG module register space + +Example: +/* K2HK */ + +rng@24000 { + compatible = "ti,keystone-rng"; + ti,syscon-sa-cfg = <&sa_config>; + clocks = <&clksa>; + clock-names = "fck"; + reg = <0x24000 0x1000>; +}; -- cgit v1.2.3 From 953cc3e8117013bd39a3b94e28361ce94ad63075 Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Tue, 20 Mar 2018 09:15:41 +0100 Subject: clk: Add driver for the si544 clock generator chip This patch adds the driver and devicetree documentation for the Silicon Labs SI544 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 200kHz to 1500MHz. Signed-off-by: Mike Looijmans [sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning] Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/silabs,si544.txt | 25 ++ drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-si544.c | 411 +++++++++++++++++++++ 4 files changed, 446 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/silabs,si544.txt create mode 100644 drivers/clk/clk-si544.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.txt b/Documentation/devicetree/bindings/clock/silabs,si544.txt new file mode 100644 index 000000000000..b86535b80920 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si544.txt @@ -0,0 +1,25 @@ +Binding for Silicon Labs 544 programmable I2C clock generator. + +Reference +This binding uses the common clock binding[1]. Details about the device can be +found in the datasheet[2]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Si544 datasheet + https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf + +Required properties: + - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according + to the speed grade of the chip. + - reg: I2C device address. + - #clock-cells: From common clock bindings: Shall be 0. + +Optional properties: + - clock-output-names: From common clock bindings. Recommended to be "si544". + +Example: + si544: clock-controller@55 { + reg = <0x55>; + #clock-cells = <0>; + compatible = "silabs,si544b"; + }; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 98ce9fc6e6c0..580fc04a96c4 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -91,6 +91,15 @@ config COMMON_CLK_SI514 This driver supports the Silicon Labs 514 programmable clock generator. +config COMMON_CLK_SI544 + tristate "Clock driver for SiLabs 544 devices" + depends on I2C + select REGMAP_I2C + help + ---help--- + This driver supports the Silicon Labs 544 programmable clock + generator. + config COMMON_CLK_SI570 tristate "Clock driver for SiLabs 570 and compatible devices" depends on I2C diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..bde614ab82e0 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o +obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o obj-$(CONFIG_ARCH_STM32) += clk-stm32h7.o diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c new file mode 100644 index 000000000000..1c96a9f6c022 --- /dev/null +++ b/drivers/clk/clk-si544.c @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Silicon Labs Si544 Programmable Oscillator + * Copyright (C) 2018 Topic Embedded Products + * Author: Mike Looijmans + */ + +#include +#include +#include +#include +#include +#include + +/* I2C registers (decimal as in datasheet) */ +#define SI544_REG_CONTROL 7 +#define SI544_REG_OE_STATE 17 +#define SI544_REG_HS_DIV 23 +#define SI544_REG_LS_HS_DIV 24 +#define SI544_REG_FBDIV0 26 +#define SI544_REG_FBDIV8 27 +#define SI544_REG_FBDIV16 28 +#define SI544_REG_FBDIV24 29 +#define SI544_REG_FBDIV32 30 +#define SI544_REG_FBDIV40 31 +#define SI544_REG_FCAL_OVR 69 +#define SI544_REG_ADPLL_DELTA_M0 231 +#define SI544_REG_ADPLL_DELTA_M8 232 +#define SI544_REG_ADPLL_DELTA_M16 233 +#define SI544_REG_PAGE_SELECT 255 + +/* Register values */ +#define SI544_CONTROL_RESET BIT(7) +#define SI544_CONTROL_MS_ICAL2 BIT(3) + +#define SI544_OE_STATE_ODC_OE BIT(0) + +/* Max freq depends on speed grade */ +#define SI544_MIN_FREQ 200000U + +/* Si544 Internal oscilator runs at 55.05 MHz */ +#define FXO 55050000U + +/* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */ +#define FVCO_MIN 10800000000ULL + +#define HS_DIV_MAX 2046 +#define HS_DIV_MAX_ODD 33 + +/* Lowest frequency synthesizeable using only the HS divider */ +#define MIN_HSDIV_FREQ (FVCO_MIN / HS_DIV_MAX) + +enum si544_speed_grade { + si544a, + si544b, + si544c, +}; + +struct clk_si544 { + struct clk_hw hw; + struct regmap *regmap; + struct i2c_client *i2c_client; + enum si544_speed_grade speed_grade; +}; +#define to_clk_si544(_hw) container_of(_hw, struct clk_si544, hw) + +/** + * struct clk_si544_muldiv - Multiplier/divider settings + * @fb_div_frac: integer part of feedback divider (32 bits) + * @fb_div_int: fractional part of feedback divider (11 bits) + * @hs_div: 1st divider, 5..2046, must be even when >33 + * @ls_div_bits: 2nd divider, as 2^x, range 0..5 + * If ls_div_bits is non-zero, hs_div must be even + */ +struct clk_si544_muldiv { + u32 fb_div_frac; + u16 fb_div_int; + u16 hs_div; + u8 ls_div_bits; +}; + +/* Enables or disables the output driver */ +static int si544_enable_output(struct clk_si544 *data, bool enable) +{ + return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, + SI544_OE_STATE_ODC_OE, enable ? SI544_OE_STATE_ODC_OE : 0); +} + +/* Retrieve clock multiplier and dividers from hardware */ +static int si544_get_muldiv(struct clk_si544 *data, + struct clk_si544_muldiv *settings) +{ + int err; + u8 reg[6]; + + err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); + if (err) + return err; + + settings->ls_div_bits = (reg[1] >> 4) & 0x07; + settings->hs_div = (reg[1] & 0x07) << 8 | reg[0]; + + err = regmap_bulk_read(data->regmap, SI544_REG_FBDIV0, reg, 6); + if (err) + return err; + + settings->fb_div_int = reg[4] | (reg[5] & 0x07) << 8; + settings->fb_div_frac = reg[0] | reg[1] << 8 | reg[2] << 16 | + reg[3] << 24; + return 0; +} + +static int si544_set_muldiv(struct clk_si544 *data, + struct clk_si544_muldiv *settings) +{ + int err; + u8 reg[6]; + + reg[0] = settings->hs_div; + reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4; + + err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2); + if (err < 0) + return err; + + reg[0] = settings->fb_div_frac; + reg[1] = settings->fb_div_frac >> 8; + reg[2] = settings->fb_div_frac >> 16; + reg[3] = settings->fb_div_frac >> 24; + reg[4] = settings->fb_div_int; + reg[5] = settings->fb_div_int >> 8; + + /* + * Writing to SI544_REG_FBDIV40 triggers the clock change, so that + * must be written last + */ + return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6); +} + +static bool is_valid_frequency(const struct clk_si544 *data, + unsigned long frequency) +{ + unsigned long max_freq = 0; + + if (frequency < SI544_MIN_FREQ) + return false; + + switch (data->speed_grade) { + case si544a: + max_freq = 1500000000; + break; + case si544b: + max_freq = 800000000; + break; + case si544c: + max_freq = 350000000; + break; + } + + return frequency <= max_freq; +} + +/* Calculate divider settings for a given frequency */ +static int si544_calc_muldiv(struct clk_si544_muldiv *settings, + unsigned long frequency) +{ + u64 vco; + u32 ls_freq; + u32 tmp; + u8 res; + + /* Determine the minimum value of LS_DIV and resulting target freq. */ + ls_freq = frequency; + settings->ls_div_bits = 0; + + if (frequency >= MIN_HSDIV_FREQ) { + settings->ls_div_bits = 0; + } else { + res = 1; + tmp = 2 * HS_DIV_MAX; + while (tmp <= (HS_DIV_MAX * 32)) { + if (((u64)frequency * tmp) >= FVCO_MIN) + break; + ++res; + tmp <<= 1; + } + settings->ls_div_bits = res; + ls_freq = frequency << res; + } + + /* Determine minimum HS_DIV by rounding up */ + vco = FVCO_MIN + ls_freq - 1; + do_div(vco, ls_freq); + settings->hs_div = vco; + + /* round up to even number when required */ + if ((settings->hs_div & 1) && + (settings->hs_div > HS_DIV_MAX_ODD || settings->ls_div_bits)) + ++settings->hs_div; + + /* Calculate VCO frequency (in 10..12GHz range) */ + vco = (u64)ls_freq * settings->hs_div; + + /* Calculate the integer part of the feedback divider */ + tmp = do_div(vco, FXO); + settings->fb_div_int = vco; + + /* And the fractional bits using the remainder */ + vco = (u64)tmp << 32; + do_div(vco, FXO); + settings->fb_div_frac = vco; + + return 0; +} + +/* Calculate resulting frequency given the register settings */ +static unsigned long si544_calc_rate(struct clk_si544_muldiv *settings) +{ + u32 d = settings->hs_div * BIT(settings->ls_div_bits); + u64 vco; + + /* Calculate VCO from the fractional part */ + vco = (u64)settings->fb_div_frac * FXO; + vco += (FXO / 2); + vco >>= 32; + + /* Add the integer part of the VCO frequency */ + vco += (u64)settings->fb_div_int * FXO; + + /* Apply divider to obtain the generated frequency */ + do_div(vco, d); + + return vco; +} + +static unsigned long si544_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_si544 *data = to_clk_si544(hw); + struct clk_si544_muldiv settings; + int err; + + err = si544_get_muldiv(data, &settings); + if (err) + return 0; + + return si544_calc_rate(&settings); +} + +static long si544_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_si544 *data = to_clk_si544(hw); + struct clk_si544_muldiv settings; + int err; + + if (!is_valid_frequency(data, rate)) + return -EINVAL; + + err = si544_calc_muldiv(&settings, rate); + if (err) + return err; + + return si544_calc_rate(&settings); +} + +/* + * Update output frequency for "big" frequency changes + */ +static int si544_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_si544 *data = to_clk_si544(hw); + struct clk_si544_muldiv settings; + int err; + + if (!is_valid_frequency(data, rate)) + return -EINVAL; + + err = si544_calc_muldiv(&settings, rate); + if (err) + return err; + + si544_enable_output(data, false); + + /* Allow FCAL for this frequency update */ + err = regmap_write(data->regmap, SI544_REG_FCAL_OVR, 0); + if (err < 0) + return err; + + + err = si544_set_muldiv(data, &settings); + if (err < 0) + return err; /* Undefined state now, best to leave disabled */ + + /* Trigger calibration */ + err = regmap_write(data->regmap, SI544_REG_CONTROL, + SI544_CONTROL_MS_ICAL2); + if (err < 0) + return err; + + /* Applying a new frequency can take up to 10ms */ + usleep_range(10000, 12000); + + si544_enable_output(data, true); + + return err; +} + +static const struct clk_ops si544_clk_ops = { + .recalc_rate = si544_recalc_rate, + .round_rate = si544_round_rate, + .set_rate = si544_set_rate, +}; + +static bool si544_regmap_is_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SI544_REG_CONTROL: + case SI544_REG_FCAL_OVR: + return true; + default: + return false; + } +} + +static const struct regmap_config si544_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .max_register = SI544_REG_PAGE_SELECT, + .volatile_reg = si544_regmap_is_volatile, +}; + +static int si544_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct clk_si544 *data; + struct clk_init_data init; + int err; + + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + init.ops = &si544_clk_ops; + init.flags = 0; + init.num_parents = 0; + data->hw.init = &init; + data->i2c_client = client; + data->speed_grade = id->driver_data; + + if (of_property_read_string(client->dev.of_node, "clock-output-names", + &init.name)) + init.name = client->dev.of_node->name; + + data->regmap = devm_regmap_init_i2c(client, &si544_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + i2c_set_clientdata(client, data); + + /* Select page 0, just to be sure, there appear to be no more */ + err = regmap_write(data->regmap, SI544_REG_PAGE_SELECT, 0); + if (err < 0) + return err; + + err = devm_clk_hw_register(&client->dev, &data->hw); + if (err) { + dev_err(&client->dev, "clock registration failed\n"); + return err; + } + err = devm_of_clk_add_hw_provider(&client->dev, of_clk_hw_simple_get, + &data->hw); + if (err) { + dev_err(&client->dev, "unable to add clk provider\n"); + return err; + } + + return 0; +} + +static const struct i2c_device_id si544_id[] = { + { "si544a", si544a }, + { "si544b", si544b }, + { "si544c", si544c }, + { } +}; +MODULE_DEVICE_TABLE(i2c, si544_id); + +static const struct of_device_id clk_si544_of_match[] = { + { .compatible = "silabs,si544a" }, + { .compatible = "silabs,si544b" }, + { .compatible = "silabs,si544c" }, + { }, +}; +MODULE_DEVICE_TABLE(of, clk_si544_of_match); + +static struct i2c_driver si544_driver = { + .driver = { + .name = "si544", + .of_match_table = clk_si544_of_match, + }, + .probe = si544_probe, + .id_table = si544_id, +}; +module_i2c_driver(si544_driver); + +MODULE_AUTHOR("Mike Looijmans "); +MODULE_DESCRIPTION("Si544 driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 1daa85d13f39144e43508fdd364ecbbaffbf35dc Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 13 Mar 2018 16:47:25 +1030 Subject: dt-bindings: watchdog: Add Nuvoton NPCM description These bindings describe the watchdog IP as used by the Nuvoton NPCM750 (Poleg) BMC SoC. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley Reviewed-by: Guenter Roeck Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck --- .../bindings/watchdog/nuvoton,npcm-wdt.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt new file mode 100644 index 000000000000..6d593003c933 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt @@ -0,0 +1,28 @@ +Nuvoton NPCM Watchdog + +Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. +The watchdog supports a pre-timeout interrupt that fires 10ms before the +expiry. + +Required properties: +- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg). +- reg : Offset and length of the register set for the device. +- interrupts : Contain the timer interrupt with flags for + falling edge. + +Required clocking property, have to be one of: +- clocks : phandle of timer reference clock. +- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx + timer (usually 25000000). + +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + +Example: + +timer@f000801c { + compatible = "nuvoton,npcm750-wdt"; + interrupts = ; + reg = <0xf000801c 0x4>; + clocks = <&clk NPCM7XX_CLK_TIMER>; +}; -- cgit v1.2.3 From 9d952aa2c8a46ba577b77619cc53e3df95507095 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 20 Mar 2018 22:53:20 +0100 Subject: dt-bindings: i2c: document R8A77965 bindings R-Car M3-N (R8A77965) SoC has a R-Car Gen3-compatible I2C controller. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang --- Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt index e91dbafe71e5..4a7811ecd954 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt @@ -13,6 +13,7 @@ Required properties: "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC. "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC. "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC. + "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC. "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC. "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC. "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device. -- cgit v1.2.3 From 7f2e85840871f199057e65232ebde846192ed989 Mon Sep 17 00:00:00 2001 From: Ivan Gorinov Date: Thu, 22 Mar 2018 14:35:33 -0700 Subject: of/Documentation: Specify local APIC ID in "reg" Use the "reg" property to specify the processor's local APIC ID instead of setting it to the CPU node index in Device Tree. Local APIC ID is assigned by hardware and visible in the APIC ID register. Some processor models allow APIC ID to be changed by software, but CPUID instruction executed with %eax = 0x0b always returns the initial ID in %edx. Local APIC ID does not match the node index in many systems. Signed-off-by: Ivan Gorinov Signed-off-by: Thomas Gleixner Reviewed-by: Andy Shevchenko Reviewed-by: Rob Herring Cc: Mark Rutland Cc: Rob Herring Cc: Frank Rowand Link: https://lkml.kernel.org/r/4b1a471a56ac0ebd7510f4759afce9104595d6da.1521753738.git.ivan.gorinov@intel.com --- Documentation/devicetree/bindings/x86/ce4100.txt | 37 ++++++++++++++++++------ 1 file changed, 28 insertions(+), 9 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/x86/ce4100.txt b/Documentation/devicetree/bindings/x86/ce4100.txt index b49ae593a60b..cd1221bfb539 100644 --- a/Documentation/devicetree/bindings/x86/ce4100.txt +++ b/Documentation/devicetree/bindings/x86/ce4100.txt @@ -7,17 +7,36 @@ Many of the "generic" devices like HPET or IO APIC have the ce4100 name in their compatible property because they first appeared in this SoC. -The CPU node ------------- - cpu@0 { - device_type = "cpu"; - compatible = "intel,ce4100"; - reg = <0>; - lapic = <&lapic0>; +The CPU nodes +------------- + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,ce4100"; + reg = <0x00>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,ce4100"; + reg = <0x02>; + }; }; -The reg property describes the CPU number. The lapic property points to -the local APIC timer. +A "cpu" node describes one logical processor (hardware thread). + +Required properties: + +- device_type + Device type, must be "cpu". + +- reg + Local APIC ID, the unique number assigned to each processor by + system hardware. The SoC node ------------ -- cgit v1.2.3 From 9a95e8d25a140ba95654b34b44f531d0c485c7a7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 17:46:54 +0100 Subject: gpio: remove etraxfs driver The cris architecture is getting removed, so we no longer need the etraxfs driver. Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/gpio/gpio-etraxfs.txt | 22 - drivers/gpio/Kconfig | 9 - drivers/gpio/Makefile | 1 - drivers/gpio/gpio-etraxfs.c | 475 --------------------- 4 files changed, 507 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt delete mode 100644 drivers/gpio/gpio-etraxfs.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt b/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt deleted file mode 100644 index 170194af3027..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt +++ /dev/null @@ -1,22 +0,0 @@ -Axis ETRAX FS General I/O controller bindings - -Required properties: - -- compatible: one of: - - "axis,etraxfs-gio" - - "axis,artpec3-gio" -- reg: Physical base address and length of the controller's registers. -- #gpio-cells: Should be 3 - - The first cell is the gpio offset number. - - The second cell is reserved and is currently unused. - - The third cell is the port number (hex). -- gpio-controller: Marks the device node as a GPIO controller. - -Example: - - gio: gpio@b001a000 { - compatible = "axis,etraxfs-gio"; - reg = <0xb001a000 0x1000>; - gpio-controller; - #gpio-cells = <3>; - }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8dbb2280538d..68d812b38be7 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -170,15 +170,6 @@ config GPIO_EP93XX depends on ARCH_EP93XX select GPIO_GENERIC -config GPIO_ETRAXFS - bool "Axis ETRAX FS General I/O" - depends on CRIS || COMPILE_TEST - depends on OF_GPIO - select GPIO_GENERIC - select GPIOLIB_IRQCHIP - help - Say yes here to support the GPIO controller on Axis ETRAX FS SoCs. - config GPIO_EXAR tristate "Support for GPIO pins on XR17V352/354/358" depends on SERIAL_8250_EXAR diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index cccb0d40846c..db8c9d4ea2ef 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,7 +46,6 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o obj-$(CONFIG_GPIO_EM) += gpio-em.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o -obj-$(CONFIG_GPIO_ETRAXFS) += gpio-etraxfs.o obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o diff --git a/drivers/gpio/gpio-etraxfs.c b/drivers/gpio/gpio-etraxfs.c deleted file mode 100644 index 94db1bf4bfdb..000000000000 --- a/drivers/gpio/gpio-etraxfs.c +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include - -#define ETRAX_FS_rw_pa_dout 0 -#define ETRAX_FS_r_pa_din 4 -#define ETRAX_FS_rw_pa_oe 8 -#define ETRAX_FS_rw_intr_cfg 12 -#define ETRAX_FS_rw_intr_mask 16 -#define ETRAX_FS_rw_ack_intr 20 -#define ETRAX_FS_r_intr 24 -#define ETRAX_FS_r_masked_intr 28 -#define ETRAX_FS_rw_pb_dout 32 -#define ETRAX_FS_r_pb_din 36 -#define ETRAX_FS_rw_pb_oe 40 -#define ETRAX_FS_rw_pc_dout 48 -#define ETRAX_FS_r_pc_din 52 -#define ETRAX_FS_rw_pc_oe 56 -#define ETRAX_FS_rw_pd_dout 64 -#define ETRAX_FS_r_pd_din 68 -#define ETRAX_FS_rw_pd_oe 72 -#define ETRAX_FS_rw_pe_dout 80 -#define ETRAX_FS_r_pe_din 84 -#define ETRAX_FS_rw_pe_oe 88 - -#define ARTPEC3_r_pa_din 0 -#define ARTPEC3_rw_pa_dout 4 -#define ARTPEC3_rw_pa_oe 8 -#define ARTPEC3_r_pb_din 44 -#define ARTPEC3_rw_pb_dout 48 -#define ARTPEC3_rw_pb_oe 52 -#define ARTPEC3_r_pc_din 88 -#define ARTPEC3_rw_pc_dout 92 -#define ARTPEC3_rw_pc_oe 96 -#define ARTPEC3_r_pd_din 116 -#define ARTPEC3_rw_intr_cfg 120 -#define ARTPEC3_rw_intr_pins 124 -#define ARTPEC3_rw_intr_mask 128 -#define ARTPEC3_rw_ack_intr 132 -#define ARTPEC3_r_masked_intr 140 - -#define GIO_CFG_OFF 0 -#define GIO_CFG_HI 1 -#define GIO_CFG_LO 2 -#define GIO_CFG_SET 3 -#define GIO_CFG_POSEDGE 5 -#define GIO_CFG_NEGEDGE 6 -#define GIO_CFG_ANYEDGE 7 - -struct etraxfs_gpio_info; - -struct etraxfs_gpio_block { - raw_spinlock_t lock; - u32 mask; - u32 cfg; - u32 pins; - unsigned int group[8]; - - void __iomem *regs; - const struct etraxfs_gpio_info *info; -}; - -struct etraxfs_gpio_chip { - struct gpio_chip gc; - struct etraxfs_gpio_block *block; -}; - -struct etraxfs_gpio_port { - const char *label; - unsigned int oe; - unsigned int dout; - unsigned int din; - unsigned int ngpio; -}; - -struct etraxfs_gpio_info { - unsigned int num_ports; - const struct etraxfs_gpio_port *ports; - - unsigned int rw_ack_intr; - unsigned int rw_intr_mask; - unsigned int rw_intr_cfg; - unsigned int rw_intr_pins; - unsigned int r_masked_intr; -}; - -static const struct etraxfs_gpio_port etraxfs_gpio_etraxfs_ports[] = { - { - .label = "A", - .ngpio = 8, - .oe = ETRAX_FS_rw_pa_oe, - .dout = ETRAX_FS_rw_pa_dout, - .din = ETRAX_FS_r_pa_din, - }, - { - .label = "B", - .ngpio = 18, - .oe = ETRAX_FS_rw_pb_oe, - .dout = ETRAX_FS_rw_pb_dout, - .din = ETRAX_FS_r_pb_din, - }, - { - .label = "C", - .ngpio = 18, - .oe = ETRAX_FS_rw_pc_oe, - .dout = ETRAX_FS_rw_pc_dout, - .din = ETRAX_FS_r_pc_din, - }, - { - .label = "D", - .ngpio = 18, - .oe = ETRAX_FS_rw_pd_oe, - .dout = ETRAX_FS_rw_pd_dout, - .din = ETRAX_FS_r_pd_din, - }, - { - .label = "E", - .ngpio = 18, - .oe = ETRAX_FS_rw_pe_oe, - .dout = ETRAX_FS_rw_pe_dout, - .din = ETRAX_FS_r_pe_din, - }, -}; - -static const struct etraxfs_gpio_info etraxfs_gpio_etraxfs = { - .num_ports = ARRAY_SIZE(etraxfs_gpio_etraxfs_ports), - .ports = etraxfs_gpio_etraxfs_ports, - .rw_ack_intr = ETRAX_FS_rw_ack_intr, - .rw_intr_mask = ETRAX_FS_rw_intr_mask, - .rw_intr_cfg = ETRAX_FS_rw_intr_cfg, - .r_masked_intr = ETRAX_FS_r_masked_intr, -}; - -static const struct etraxfs_gpio_port etraxfs_gpio_artpec3_ports[] = { - { - .label = "A", - .ngpio = 32, - .oe = ARTPEC3_rw_pa_oe, - .dout = ARTPEC3_rw_pa_dout, - .din = ARTPEC3_r_pa_din, - }, - { - .label = "B", - .ngpio = 32, - .oe = ARTPEC3_rw_pb_oe, - .dout = ARTPEC3_rw_pb_dout, - .din = ARTPEC3_r_pb_din, - }, - { - .label = "C", - .ngpio = 16, - .oe = ARTPEC3_rw_pc_oe, - .dout = ARTPEC3_rw_pc_dout, - .din = ARTPEC3_r_pc_din, - }, - { - .label = "D", - .ngpio = 32, - .din = ARTPEC3_r_pd_din, - }, -}; - -static const struct etraxfs_gpio_info etraxfs_gpio_artpec3 = { - .num_ports = ARRAY_SIZE(etraxfs_gpio_artpec3_ports), - .ports = etraxfs_gpio_artpec3_ports, - .rw_ack_intr = ARTPEC3_rw_ack_intr, - .rw_intr_mask = ARTPEC3_rw_intr_mask, - .rw_intr_cfg = ARTPEC3_rw_intr_cfg, - .r_masked_intr = ARTPEC3_r_masked_intr, - .rw_intr_pins = ARTPEC3_rw_intr_pins, -}; - -static unsigned int etraxfs_gpio_chip_to_port(struct gpio_chip *gc) -{ - return gc->label[0] - 'A'; -} - -static int etraxfs_gpio_of_xlate(struct gpio_chip *gc, - const struct of_phandle_args *gpiospec, - u32 *flags) -{ - /* - * Port numbers are A to E, and the properties are integers, so we - * specify them as 0xA - 0xE. - */ - if (etraxfs_gpio_chip_to_port(gc) + 0xA != gpiospec->args[2]) - return -EINVAL; - - return of_gpio_simple_xlate(gc, gpiospec, flags); -} - -static const struct of_device_id etraxfs_gpio_of_table[] = { - { - .compatible = "axis,etraxfs-gio", - .data = &etraxfs_gpio_etraxfs, - }, - { - .compatible = "axis,artpec3-gio", - .data = &etraxfs_gpio_artpec3, - }, - {}, -}; - -static unsigned int etraxfs_gpio_to_group_irq(unsigned int gpio) -{ - return gpio % 8; -} - -static unsigned int etraxfs_gpio_to_group_pin(struct etraxfs_gpio_chip *chip, - unsigned int gpio) -{ - return 4 * etraxfs_gpio_chip_to_port(&chip->gc) + gpio / 8; -} - -static void etraxfs_gpio_irq_ack(struct irq_data *d) -{ - struct etraxfs_gpio_chip *chip = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - struct etraxfs_gpio_block *block = chip->block; - unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq); - - writel(BIT(grpirq), block->regs + block->info->rw_ack_intr); -} - -static void etraxfs_gpio_irq_mask(struct irq_data *d) -{ - struct etraxfs_gpio_chip *chip = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - struct etraxfs_gpio_block *block = chip->block; - unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq); - - raw_spin_lock(&block->lock); - block->mask &= ~BIT(grpirq); - writel(block->mask, block->regs + block->info->rw_intr_mask); - raw_spin_unlock(&block->lock); -} - -static void etraxfs_gpio_irq_unmask(struct irq_data *d) -{ - struct etraxfs_gpio_chip *chip = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - struct etraxfs_gpio_block *block = chip->block; - unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq); - - raw_spin_lock(&block->lock); - block->mask |= BIT(grpirq); - writel(block->mask, block->regs + block->info->rw_intr_mask); - raw_spin_unlock(&block->lock); -} - -static int etraxfs_gpio_irq_set_type(struct irq_data *d, u32 type) -{ - struct etraxfs_gpio_chip *chip = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - struct etraxfs_gpio_block *block = chip->block; - unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq); - u32 cfg; - - switch (type) { - case IRQ_TYPE_EDGE_RISING: - cfg = GIO_CFG_POSEDGE; - break; - case IRQ_TYPE_EDGE_FALLING: - cfg = GIO_CFG_NEGEDGE; - break; - case IRQ_TYPE_EDGE_BOTH: - cfg = GIO_CFG_ANYEDGE; - break; - case IRQ_TYPE_LEVEL_LOW: - cfg = GIO_CFG_LO; - break; - case IRQ_TYPE_LEVEL_HIGH: - cfg = GIO_CFG_HI; - break; - default: - return -EINVAL; - } - - raw_spin_lock(&block->lock); - block->cfg &= ~(0x7 << (grpirq * 3)); - block->cfg |= (cfg << (grpirq * 3)); - writel(block->cfg, block->regs + block->info->rw_intr_cfg); - raw_spin_unlock(&block->lock); - - return 0; -} - -static int etraxfs_gpio_irq_request_resources(struct irq_data *d) -{ - struct etraxfs_gpio_chip *chip = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - struct etraxfs_gpio_block *block = chip->block; - unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq); - int ret = -EBUSY; - - raw_spin_lock(&block->lock); - if (block->group[grpirq]) - goto out; - - ret = gpiochip_lock_as_irq(&chip->gc, d->hwirq); - if (ret) - goto out; - - block->group[grpirq] = d->irq; - if (block->info->rw_intr_pins) { - unsigned int pin = etraxfs_gpio_to_group_pin(chip, d->hwirq); - - block->pins &= ~(0xf << (grpirq * 4)); - block->pins |= (pin << (grpirq * 4)); - - writel(block->pins, block->regs + block->info->rw_intr_pins); - } - -out: - raw_spin_unlock(&block->lock); - return ret; -} - -static void etraxfs_gpio_irq_release_resources(struct irq_data *d) -{ - struct etraxfs_gpio_chip *chip = - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - struct etraxfs_gpio_block *block = chip->block; - unsigned int grpirq = etraxfs_gpio_to_group_irq(d->hwirq); - - raw_spin_lock(&block->lock); - block->group[grpirq] = 0; - gpiochip_unlock_as_irq(&chip->gc, d->hwirq); - raw_spin_unlock(&block->lock); -} - -static struct irq_chip etraxfs_gpio_irq_chip = { - .name = "gpio-etraxfs", - .irq_ack = etraxfs_gpio_irq_ack, - .irq_mask = etraxfs_gpio_irq_mask, - .irq_unmask = etraxfs_gpio_irq_unmask, - .irq_set_type = etraxfs_gpio_irq_set_type, - .irq_request_resources = etraxfs_gpio_irq_request_resources, - .irq_release_resources = etraxfs_gpio_irq_release_resources, -}; - -static irqreturn_t etraxfs_gpio_interrupt(int irq, void *dev_id) -{ - struct etraxfs_gpio_block *block = dev_id; - unsigned long intr = readl(block->regs + block->info->r_masked_intr); - int bit; - - for_each_set_bit(bit, &intr, 8) - generic_handle_irq(block->group[bit]); - - return IRQ_RETVAL(intr & 0xff); -} - -static int etraxfs_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct etraxfs_gpio_info *info; - const struct of_device_id *match; - struct etraxfs_gpio_block *block; - struct etraxfs_gpio_chip *chips; - struct resource *res, *irq; - bool allportsirq = false; - void __iomem *regs; - int ret; - int i; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - regs = devm_ioremap_resource(dev, res); - if (IS_ERR(regs)) - return PTR_ERR(regs); - - match = of_match_node(etraxfs_gpio_of_table, dev->of_node); - if (!match) - return -EINVAL; - - info = match->data; - - chips = devm_kzalloc(dev, sizeof(*chips) * info->num_ports, GFP_KERNEL); - if (!chips) - return -ENOMEM; - - irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!irq) - return -EINVAL; - - block = devm_kzalloc(dev, sizeof(*block), GFP_KERNEL); - if (!block) - return -ENOMEM; - - raw_spin_lock_init(&block->lock); - - block->regs = regs; - block->info = info; - - writel(0, block->regs + info->rw_intr_mask); - writel(0, block->regs + info->rw_intr_cfg); - if (info->rw_intr_pins) { - allportsirq = true; - writel(0, block->regs + info->rw_intr_pins); - } - - ret = devm_request_irq(dev, irq->start, etraxfs_gpio_interrupt, - IRQF_SHARED, dev_name(dev), block); - if (ret) { - dev_err(dev, "Unable to request irq %d\n", ret); - return ret; - } - - for (i = 0; i < info->num_ports; i++) { - struct etraxfs_gpio_chip *chip = &chips[i]; - struct gpio_chip *gc = &chip->gc; - const struct etraxfs_gpio_port *port = &info->ports[i]; - unsigned long flags = BGPIOF_READ_OUTPUT_REG_SET; - void __iomem *dat = regs + port->din; - void __iomem *set = regs + port->dout; - void __iomem *dirout = regs + port->oe; - - chip->block = block; - - if (dirout == set) { - dirout = set = NULL; - flags = BGPIOF_NO_OUTPUT; - } - - ret = bgpio_init(gc, dev, 4, - dat, set, NULL, dirout, NULL, - flags); - if (ret) { - dev_err(dev, "Unable to init port %s\n", - port->label); - continue; - } - - gc->ngpio = port->ngpio; - gc->label = port->label; - - gc->of_node = dev->of_node; - gc->of_gpio_n_cells = 3; - gc->of_xlate = etraxfs_gpio_of_xlate; - - ret = gpiochip_add_data(gc, chip); - if (ret) { - dev_err(dev, "Unable to register port %s\n", - gc->label); - continue; - } - - if (i > 0 && !allportsirq) - continue; - - ret = gpiochip_irqchip_add(gc, &etraxfs_gpio_irq_chip, 0, - handle_level_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(dev, "Unable to add irqchip to port %s\n", - gc->label); - } - } - - return 0; -} - -static struct platform_driver etraxfs_gpio_driver = { - .driver = { - .name = "etraxfs-gpio", - .of_match_table = of_match_ptr(etraxfs_gpio_of_table), - }, - .probe = etraxfs_gpio_probe, -}; - -builtin_platform_driver(etraxfs_gpio_driver); -- cgit v1.2.3 From aa4afa2cddf069405fa9dc326074071fb475fbac Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 9 Mar 2018 17:45:30 +0100 Subject: serial: remove cris/etrax uart drivers The cris architecture is getting removed, so we don't need the uart driver any more. Acked-by: Greg Kroah-Hartman Acked-by: Jesper Nilsson Signed-off-by: Arnd Bergmann --- .../bindings/serial/axis,etraxfs-uart.txt | 22 - drivers/tty/serial/Kconfig | 11 - drivers/tty/serial/Makefile | 2 - drivers/tty/serial/crisv10.c | 4248 -------------------- drivers/tty/serial/crisv10.h | 133 - drivers/tty/serial/etraxfs-uart.c | 960 ----- 6 files changed, 5376 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt delete mode 100644 drivers/tty/serial/crisv10.c delete mode 100644 drivers/tty/serial/crisv10.h delete mode 100644 drivers/tty/serial/etraxfs-uart.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt b/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt deleted file mode 100644 index 048c3818c826..000000000000 --- a/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt +++ /dev/null @@ -1,22 +0,0 @@ -ETRAX FS UART - -Required properties: -- compatible : "axis,etraxfs-uart" -- reg: offset and length of the register set for the device. -- interrupts: device interrupt - -Optional properties: -- {dtr,dsr,rng,dcd}-gpios: specify a GPIO for DTR/DSR/RI/DCD - line respectively. - -Example: - -serial@b00260000 { - compatible = "axis,etraxfs-uart"; - reg = <0xb0026000 0x1000>; - interrupts = <68>; - dtr-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; - dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; - rng-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; - dcd-gpios = <&sysgpio 3 GPIO_ACTIVE_LOW>; -}; diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 3682fd3e960c..f6e09326042d 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1114,17 +1114,6 @@ config SERIAL_VT8500_CONSOLE depends on SERIAL_VT8500=y select SERIAL_CORE_CONSOLE -config SERIAL_ETRAXFS - bool "ETRAX FS serial port support" - depends on ETRAX_ARCH_V32 && OF - select SERIAL_CORE - select SERIAL_MCTRL_GPIO if GPIOLIB - -config SERIAL_ETRAXFS_CONSOLE - bool "ETRAX FS serial console support" - depends on SERIAL_ETRAXFS - select SERIAL_CORE_CONSOLE - config SERIAL_NETX tristate "NetX serial port support" depends on ARCH_NETX diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 842d185d697e..c21835dc16b2 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -51,8 +51,6 @@ obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o obj-$(CONFIG_SERIAL_MPSC) += mpsc.o obj-$(CONFIG_SERIAL_MESON) += meson_uart.o obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o -obj-$(CONFIG_ETRAX_SERIAL) += crisv10.o -obj-$(CONFIG_SERIAL_ETRAXFS) += etraxfs-uart.o obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o obj-$(CONFIG_SERIAL_SC16IS7XX_CORE) += sc16is7xx.o obj-$(CONFIG_SERIAL_JSM) += jsm/ diff --git a/drivers/tty/serial/crisv10.c b/drivers/tty/serial/crisv10.c deleted file mode 100644 index c9458a033e3c..000000000000 --- a/drivers/tty/serial/crisv10.c +++ /dev/null @@ -1,4248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Serial port driver for the ETRAX 100LX chip - * - * Copyright (C) 1998-2007 Axis Communications AB - * - * Many, many authors. Based once upon a time on serial.c for 16x50. - * - */ - -static char *serial_version = "$Revision: 1.25 $"; - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -/* non-arch dependent serial structures are in linux/serial.h */ -#include -/* while we keep our own stuff (struct e100_serial) in a local .h file */ -#include "crisv10.h" -#include -#include - -#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER -#ifndef CONFIG_ETRAX_FAST_TIMER -#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER" -#endif -#endif - -#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \ - (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0) -#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1" -#endif - -/* - * All of the compatibilty code so we can compile serial.c against - * older kernels is hidden in serial_compat.h - */ -#if defined(LOCAL_HEADERS) -#include "serial_compat.h" -#endif - -struct tty_driver *serial_driver; - -/* number of characters left in xmit buffer before we ask for more */ -#define WAKEUP_CHARS 256 - -//#define SERIAL_DEBUG_INTR -//#define SERIAL_DEBUG_OPEN -//#define SERIAL_DEBUG_FLOW -//#define SERIAL_DEBUG_DATA -//#define SERIAL_DEBUG_THROTTLE -//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */ -//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */ - -/* Enable this to use serial interrupts to handle when you - expect the first received event on the serial port to - be an error, break or similar. Used to be able to flash IRMA - from eLinux */ -#define SERIAL_HANDLE_EARLY_ERRORS - -/* Currently 16 descriptors x 128 bytes = 2048 bytes */ -#define SERIAL_DESCR_BUF_SIZE 256 - -#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */ -#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE - -/* We don't want to load the system with massive fast timer interrupt - * on high baudrates so limit it to 250 us (4kHz) */ -#define MIN_FLUSH_TIME_USEC 250 - -/* Add an x here to log a lot of timer stuff */ -#define TIMERD(x) -/* Debug details of interrupt handling */ -#define DINTR1(x) /* irq on/off, errors */ -#define DINTR2(x) /* tx and rx */ -/* Debug flip buffer stuff */ -#define DFLIP(x) -/* Debug flow control and overview of data flow */ -#define DFLOW(x) -#define DBAUD(x) -#define DLOG_INT_TRIG(x) - -//#define DEBUG_LOG_INCLUDED -#ifndef DEBUG_LOG_INCLUDED -#define DEBUG_LOG(line, string, value) -#else -struct debug_log_info -{ - unsigned long time; - unsigned long timer_data; -// int line; - const char *string; - int value; -}; -#define DEBUG_LOG_SIZE 4096 - -struct debug_log_info debug_log[DEBUG_LOG_SIZE]; -int debug_log_pos = 0; - -#define DEBUG_LOG(_line, _string, _value) do { \ - if ((_line) == SERIAL_DEBUG_LINE) {\ - debug_log_func(_line, _string, _value); \ - }\ -}while(0) - -void debug_log_func(int line, const char *string, int value) -{ - if (debug_log_pos < DEBUG_LOG_SIZE) { - debug_log[debug_log_pos].time = jiffies; - debug_log[debug_log_pos].timer_data = *R_TIMER_DATA; -// debug_log[debug_log_pos].line = line; - debug_log[debug_log_pos].string = string; - debug_log[debug_log_pos].value = value; - debug_log_pos++; - } - /*printk(string, value);*/ -} -#endif - -#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS -/* Default number of timer ticks before flushing rx fifo - * When using "little data, low latency applications: use 0 - * When using "much data applications (PPP)" use ~5 - */ -#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5 -#endif - -unsigned long timer_data_to_ns(unsigned long timer_data); - -static void change_speed(struct e100_serial *info); -static void rs_throttle(struct tty_struct * tty); -static void rs_wait_until_sent(struct tty_struct *tty, int timeout); -static int rs_write(struct tty_struct *tty, - const unsigned char *buf, int count); -#ifdef CONFIG_ETRAX_RS485 -static int e100_write_rs485(struct tty_struct *tty, - const unsigned char *buf, int count); -#endif -static int get_lsr_info(struct e100_serial *info, unsigned int *value); - - -#define DEF_BAUD 115200 /* 115.2 kbit/s */ -#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */ -/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */ -#define DEF_TX 0x80 /* or SERIAL_CTRL_B */ - -/* offsets from R_SERIALx_CTRL */ - -#define REG_DATA 0 -#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */ -#define REG_TR_DATA 0 -#define REG_STATUS 1 -#define REG_TR_CTRL 1 -#define REG_REC_CTRL 2 -#define REG_BAUD 3 -#define REG_XOFF 4 /* this is a 32 bit register */ - -/* The bitfields are the same for all serial ports */ -#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd) -#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail) -#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err) -#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err) -#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun) - -#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK) - -/* Values for info->errorcode */ -#define ERRCODE_SET_BREAK (TTY_BREAK) -#define ERRCODE_INSERT 0x100 -#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK) - -#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop; - -/* - * General note regarding the use of IO_* macros in this file: - * - * We will use the bits defined for DMA channel 6 when using various - * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are - * the same for all channels (which of course they are). - * - * We will also use the bits defined for serial port 0 when writing commands - * to the different ports, as these bits too are the same for all ports. - */ - - -/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */ -static const unsigned long e100_ser_int_mask = 0 -#ifdef CONFIG_ETRAX_SERIAL_PORT0 -| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready) -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT1 -| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready) -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT2 -| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready) -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT3 -| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready) -#endif -; -unsigned long r_alt_ser_baudrate_shadow = 0; - -/* this is the data for the four serial ports in the etrax100 */ -/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */ -/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */ - -static struct e100_serial rs_table[] = { - { .baud = DEF_BAUD, - .ioport = (unsigned char *)R_SERIAL0_CTRL, - .irq = 1U << 12, /* uses DMA 6 and 7 */ - .oclrintradr = R_DMA_CH6_CLR_INTR, - .ofirstadr = R_DMA_CH6_FIRST, - .ocmdadr = R_DMA_CH6_CMD, - .ostatusadr = R_DMA_CH6_STATUS, - .iclrintradr = R_DMA_CH7_CLR_INTR, - .ifirstadr = R_DMA_CH7_FIRST, - .icmdadr = R_DMA_CH7_CMD, - .idescradr = R_DMA_CH7_DESCR, - .rx_ctrl = DEF_RX, - .tx_ctrl = DEF_TX, - .iseteop = 2, - .dma_owner = dma_ser0, - .io_if = if_serial_0, -#ifdef CONFIG_ETRAX_SERIAL_PORT0 - .enabled = 1, -#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT - .dma_out_enabled = 1, - .dma_out_nbr = SER0_TX_DMA_NBR, - .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR, - .dma_out_irq_flags = 0, - .dma_out_irq_description = "serial 0 dma tr", -#else - .dma_out_enabled = 0, - .dma_out_nbr = UINT_MAX, - .dma_out_irq_nbr = 0, - .dma_out_irq_flags = 0, - .dma_out_irq_description = NULL, -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN - .dma_in_enabled = 1, - .dma_in_nbr = SER0_RX_DMA_NBR, - .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR, - .dma_in_irq_flags = 0, - .dma_in_irq_description = "serial 0 dma rec", -#else - .dma_in_enabled = 0, - .dma_in_nbr = UINT_MAX, - .dma_in_irq_nbr = 0, - .dma_in_irq_flags = 0, - .dma_in_irq_description = NULL, -#endif -#else - .enabled = 0, - .io_if_description = NULL, - .dma_out_enabled = 0, - .dma_in_enabled = 0 -#endif - -}, /* ttyS0 */ - { .baud = DEF_BAUD, - .ioport = (unsigned char *)R_SERIAL1_CTRL, - .irq = 1U << 16, /* uses DMA 8 and 9 */ - .oclrintradr = R_DMA_CH8_CLR_INTR, - .ofirstadr = R_DMA_CH8_FIRST, - .ocmdadr = R_DMA_CH8_CMD, - .ostatusadr = R_DMA_CH8_STATUS, - .iclrintradr = R_DMA_CH9_CLR_INTR, - .ifirstadr = R_DMA_CH9_FIRST, - .icmdadr = R_DMA_CH9_CMD, - .idescradr = R_DMA_CH9_DESCR, - .rx_ctrl = DEF_RX, - .tx_ctrl = DEF_TX, - .iseteop = 3, - .dma_owner = dma_ser1, - .io_if = if_serial_1, -#ifdef CONFIG_ETRAX_SERIAL_PORT1 - .enabled = 1, - .io_if_description = "ser1", -#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT - .dma_out_enabled = 1, - .dma_out_nbr = SER1_TX_DMA_NBR, - .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR, - .dma_out_irq_flags = 0, - .dma_out_irq_description = "serial 1 dma tr", -#else - .dma_out_enabled = 0, - .dma_out_nbr = UINT_MAX, - .dma_out_irq_nbr = 0, - .dma_out_irq_flags = 0, - .dma_out_irq_description = NULL, -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN - .dma_in_enabled = 1, - .dma_in_nbr = SER1_RX_DMA_NBR, - .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR, - .dma_in_irq_flags = 0, - .dma_in_irq_description = "serial 1 dma rec", -#else - .dma_in_enabled = 0, - .dma_in_enabled = 0, - .dma_in_nbr = UINT_MAX, - .dma_in_irq_nbr = 0, - .dma_in_irq_flags = 0, - .dma_in_irq_description = NULL, -#endif -#else - .enabled = 0, - .io_if_description = NULL, - .dma_in_irq_nbr = 0, - .dma_out_enabled = 0, - .dma_in_enabled = 0 -#endif -}, /* ttyS1 */ - - { .baud = DEF_BAUD, - .ioport = (unsigned char *)R_SERIAL2_CTRL, - .irq = 1U << 4, /* uses DMA 2 and 3 */ - .oclrintradr = R_DMA_CH2_CLR_INTR, - .ofirstadr = R_DMA_CH2_FIRST, - .ocmdadr = R_DMA_CH2_CMD, - .ostatusadr = R_DMA_CH2_STATUS, - .iclrintradr = R_DMA_CH3_CLR_INTR, - .ifirstadr = R_DMA_CH3_FIRST, - .icmdadr = R_DMA_CH3_CMD, - .idescradr = R_DMA_CH3_DESCR, - .rx_ctrl = DEF_RX, - .tx_ctrl = DEF_TX, - .iseteop = 0, - .dma_owner = dma_ser2, - .io_if = if_serial_2, -#ifdef CONFIG_ETRAX_SERIAL_PORT2 - .enabled = 1, - .io_if_description = "ser2", -#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT - .dma_out_enabled = 1, - .dma_out_nbr = SER2_TX_DMA_NBR, - .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR, - .dma_out_irq_flags = 0, - .dma_out_irq_description = "serial 2 dma tr", -#else - .dma_out_enabled = 0, - .dma_out_nbr = UINT_MAX, - .dma_out_irq_nbr = 0, - .dma_out_irq_flags = 0, - .dma_out_irq_description = NULL, -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN - .dma_in_enabled = 1, - .dma_in_nbr = SER2_RX_DMA_NBR, - .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR, - .dma_in_irq_flags = 0, - .dma_in_irq_description = "serial 2 dma rec", -#else - .dma_in_enabled = 0, - .dma_in_nbr = UINT_MAX, - .dma_in_irq_nbr = 0, - .dma_in_irq_flags = 0, - .dma_in_irq_description = NULL, -#endif -#else - .enabled = 0, - .io_if_description = NULL, - .dma_out_enabled = 0, - .dma_in_enabled = 0 -#endif - }, /* ttyS2 */ - - { .baud = DEF_BAUD, - .ioport = (unsigned char *)R_SERIAL3_CTRL, - .irq = 1U << 8, /* uses DMA 4 and 5 */ - .oclrintradr = R_DMA_CH4_CLR_INTR, - .ofirstadr = R_DMA_CH4_FIRST, - .ocmdadr = R_DMA_CH4_CMD, - .ostatusadr = R_DMA_CH4_STATUS, - .iclrintradr = R_DMA_CH5_CLR_INTR, - .ifirstadr = R_DMA_CH5_FIRST, - .icmdadr = R_DMA_CH5_CMD, - .idescradr = R_DMA_CH5_DESCR, - .rx_ctrl = DEF_RX, - .tx_ctrl = DEF_TX, - .iseteop = 1, - .dma_owner = dma_ser3, - .io_if = if_serial_3, -#ifdef CONFIG_ETRAX_SERIAL_PORT3 - .enabled = 1, - .io_if_description = "ser3", -#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT - .dma_out_enabled = 1, - .dma_out_nbr = SER3_TX_DMA_NBR, - .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR, - .dma_out_irq_flags = 0, - .dma_out_irq_description = "serial 3 dma tr", -#else - .dma_out_enabled = 0, - .dma_out_nbr = UINT_MAX, - .dma_out_irq_nbr = 0, - .dma_out_irq_flags = 0, - .dma_out_irq_description = NULL, -#endif -#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN - .dma_in_enabled = 1, - .dma_in_nbr = SER3_RX_DMA_NBR, - .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR, - .dma_in_irq_flags = 0, - .dma_in_irq_description = "serial 3 dma rec", -#else - .dma_in_enabled = 0, - .dma_in_nbr = UINT_MAX, - .dma_in_irq_nbr = 0, - .dma_in_irq_flags = 0, - .dma_in_irq_description = NULL -#endif -#else - .enabled = 0, - .io_if_description = NULL, - .dma_out_enabled = 0, - .dma_in_enabled = 0 -#endif - } /* ttyS3 */ -}; - - -#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial)) - -#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER -static struct fast_timer fast_timers[NR_PORTS]; -#endif - -/* RS-485 */ -#if defined(CONFIG_ETRAX_RS485) -#ifdef CONFIG_ETRAX_FAST_TIMER -static struct fast_timer fast_timers_rs485[NR_PORTS]; -#endif -#if defined(CONFIG_ETRAX_RS485_ON_PA) -static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT; -#endif -#endif - -/* Info and macros needed for each ports extra control/status signals. */ -#define E100_STRUCT_PORT(line, pinname) \ - ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \ - (R_PORT_PA_DATA): ( \ - (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \ - (R_PORT_PB_DATA):&dummy_ser[line])) - -#define E100_STRUCT_SHADOW(line, pinname) \ - ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \ - (&port_pa_data_shadow): ( \ - (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \ - (&port_pb_data_shadow):&dummy_ser[line])) -#define E100_STRUCT_MASK(line, pinname) \ - ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \ - (1<= 0)? \ - (1< 3.3V to RS-232 driver -> -12V on RS-232 level - * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level - * - * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip - */ - -/* Output */ -#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK) -/* Input */ -#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK) - -/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */ -/* Is an output */ -#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask) - -/* Normally inputs */ -#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask) -#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask) - -/* Input */ -#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask) - -/* Calculate the chartime depending on baudrate, numbor of bits etc. */ -static void update_char_time(struct e100_serial * info) -{ - tcflag_t cflags = info->port.tty->termios.c_cflag; - int bits; - - /* calc. number of bits / data byte */ - /* databits + startbit and 1 stopbit */ - if ((cflags & CSIZE) == CS7) - bits = 9; - else - bits = 10; - - if (cflags & CSTOPB) /* 2 stopbits ? */ - bits++; - - if (cflags & PARENB) /* parity bit ? */ - bits++; - - /* calc timeout */ - info->char_time_usec = ((bits * 1000000) / info->baud) + 1; - info->flush_time_usec = 4*info->char_time_usec; - if (info->flush_time_usec < MIN_FLUSH_TIME_USEC) - info->flush_time_usec = MIN_FLUSH_TIME_USEC; - -} - -/* - * This function maps from the Bxxxx defines in asm/termbits.h into real - * baud rates. - */ - -static int -cflag_to_baud(unsigned int cflag) -{ - static int baud_table[] = { - 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, - 4800, 9600, 19200, 38400 }; - - static int ext_baud_table[] = { - 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000, - 0, 0, 0, 0, 0, 0, 0, 0 }; - - if (cflag & CBAUDEX) - return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX]; - else - return baud_table[cflag & CBAUD]; -} - -/* and this maps to an etrax100 hardware baud constant */ - -static unsigned char -cflag_to_etrax_baud(unsigned int cflag) -{ - char retval; - - static char baud_table[] = { - -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 }; - - static char ext_baud_table[] = { - -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 }; - - if (cflag & CBAUDEX) - retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX]; - else - retval = baud_table[cflag & CBAUD]; - - if (retval < 0) { - printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag); - retval = 5; /* choose default 9600 instead */ - } - - return retval | (retval << 4); /* choose same for both TX and RX */ -} - - -/* Various static support functions */ - -/* Functions to set or clear DTR/RTS on the requested line */ -/* It is complicated by the fact that RTS is a serial port register, while - * DTR might not be implemented in the HW at all, and if it is, it can be on - * any general port. - */ - - -static inline void -e100_dtr(struct e100_serial *info, int set) -{ - unsigned char mask = e100_modem_pins[info->line].dtr_mask; - -#ifdef SERIAL_DEBUG_IO - printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask); - printk("ser%i shadow before 0x%02X get: %i\n", - info->line, *e100_modem_pins[info->line].dtr_shadow, - E100_DTR_GET(info)); -#endif - /* DTR is active low */ - { - unsigned long flags; - - local_irq_save(flags); - *e100_modem_pins[info->line].dtr_shadow &= ~mask; - *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask); - *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow; - local_irq_restore(flags); - } - -#ifdef SERIAL_DEBUG_IO - printk("ser%i shadow after 0x%02X get: %i\n", - info->line, *e100_modem_pins[info->line].dtr_shadow, - E100_DTR_GET(info)); -#endif -} - -/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive - * 0=0V , 1=3.3V - */ -static inline void -e100_rts(struct e100_serial *info, int set) -{ - unsigned long flags; - local_irq_save(flags); - info->rx_ctrl &= ~E100_RTS_MASK; - info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */ - info->ioport[REG_REC_CTRL] = info->rx_ctrl; - local_irq_restore(flags); -#ifdef SERIAL_DEBUG_IO - printk("ser%i rts %i\n", info->line, set); -#endif -} - - -/* If this behaves as a modem, RI and CD is an output */ -static inline void -e100_ri_out(struct e100_serial *info, int set) -{ - /* RI is active low */ - { - unsigned char mask = e100_modem_pins[info->line].ri_mask; - unsigned long flags; - - local_irq_save(flags); - *e100_modem_pins[info->line].ri_shadow &= ~mask; - *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask); - *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow; - local_irq_restore(flags); - } -} -static inline void -e100_cd_out(struct e100_serial *info, int set) -{ - /* CD is active low */ - { - unsigned char mask = e100_modem_pins[info->line].cd_mask; - unsigned long flags; - - local_irq_save(flags); - *e100_modem_pins[info->line].cd_shadow &= ~mask; - *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask); - *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow; - local_irq_restore(flags); - } -} - -static inline void -e100_disable_rx(struct e100_serial *info) -{ - /* disable the receiver */ - info->ioport[REG_REC_CTRL] = - (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable)); -} - -static inline void -e100_enable_rx(struct e100_serial *info) -{ - /* enable the receiver */ - info->ioport[REG_REC_CTRL] = - (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable)); -} - -/* the rx DMA uses both the dma_descr and the dma_eop interrupts */ - -static inline void -e100_disable_rxdma_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("rxdma_irq(%d): 0\n",info->line); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line)); - *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3); -} - -static inline void -e100_enable_rxdma_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("rxdma_irq(%d): 1\n",info->line); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line)); - *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3); -} - -/* the tx DMA uses only dma_descr interrupt */ - -static void e100_disable_txdma_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("txdma_irq(%d): 0\n",info->line); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line)); - *R_IRQ_MASK2_CLR = info->irq; -} - -static void e100_enable_txdma_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("txdma_irq(%d): 1\n",info->line); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line)); - *R_IRQ_MASK2_SET = info->irq; -} - -static void e100_disable_txdma_channel(struct e100_serial *info) -{ - unsigned long flags; - - /* Disable output DMA channel for the serial port in question - * ( set to something other than serialX) - */ - local_irq_save(flags); - DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line)); - if (info->line == 0) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) == - IO_STATE(R_GEN_CONFIG, dma6, serial0)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); - } - } else if (info->line == 1) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) == - IO_STATE(R_GEN_CONFIG, dma8, serial1)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); - } - } else if (info->line == 2) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) == - IO_STATE(R_GEN_CONFIG, dma2, serial2)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); - } - } else if (info->line == 3) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) == - IO_STATE(R_GEN_CONFIG, dma4, serial3)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); - } - } - *R_GEN_CONFIG = genconfig_shadow; - local_irq_restore(flags); -} - - -static void e100_enable_txdma_channel(struct e100_serial *info) -{ - unsigned long flags; - - local_irq_save(flags); - DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line)); - /* Enable output DMA channel for the serial port in question */ - if (info->line == 0) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0); - } else if (info->line == 1) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1); - } else if (info->line == 2) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2); - } else if (info->line == 3) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3); - } - *R_GEN_CONFIG = genconfig_shadow; - local_irq_restore(flags); -} - -static void e100_disable_rxdma_channel(struct e100_serial *info) -{ - unsigned long flags; - - /* Disable input DMA channel for the serial port in question - * ( set to something other than serialX) - */ - local_irq_save(flags); - if (info->line == 0) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) == - IO_STATE(R_GEN_CONFIG, dma7, serial0)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused); - } - } else if (info->line == 1) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) == - IO_STATE(R_GEN_CONFIG, dma9, serial1)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb); - } - } else if (info->line == 2) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) == - IO_STATE(R_GEN_CONFIG, dma3, serial2)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); - } - } else if (info->line == 3) { - if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) == - IO_STATE(R_GEN_CONFIG, dma5, serial3)) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); - } - } - *R_GEN_CONFIG = genconfig_shadow; - local_irq_restore(flags); -} - - -static void e100_enable_rxdma_channel(struct e100_serial *info) -{ - unsigned long flags; - - local_irq_save(flags); - /* Enable input DMA channel for the serial port in question */ - if (info->line == 0) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0); - } else if (info->line == 1) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1); - } else if (info->line == 2) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2); - } else if (info->line == 3) { - genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5); - genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3); - } - *R_GEN_CONFIG = genconfig_shadow; - local_irq_restore(flags); -} - -#ifdef SERIAL_HANDLE_EARLY_ERRORS -/* in order to detect and fix errors on the first byte - we have to use the serial interrupts as well. */ - -static inline void -e100_disable_serial_data_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("ser_irq(%d): 0\n",info->line); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line)); - *R_IRQ_MASK1_CLR = (1U << (8+2*info->line)); -} - -static inline void -e100_enable_serial_data_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("ser_irq(%d): 1\n",info->line); - printk("**** %d = %d\n", - (8+2*info->line), - (1U << (8+2*info->line))); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line)); - *R_IRQ_MASK1_SET = (1U << (8+2*info->line)); -} -#endif - -static inline void -e100_disable_serial_tx_ready_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("ser_tx_irq(%d): 0\n",info->line); -#endif - DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line)); - *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line)); -} - -static inline void -e100_enable_serial_tx_ready_irq(struct e100_serial *info) -{ -#ifdef SERIAL_DEBUG_INTR - printk("ser_tx_irq(%d): 1\n",info->line); - printk("**** %d = %d\n", - (8+1+2*info->line), - (1U << (8+1+2*info->line))); -#endif - DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line)); - *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line)); -} - -static inline void e100_enable_rx_irq(struct e100_serial *info) -{ - if (info->uses_dma_in) - e100_enable_rxdma_irq(info); - else - e100_enable_serial_data_irq(info); -} -static inline void e100_disable_rx_irq(struct e100_serial *info) -{ - if (info->uses_dma_in) - e100_disable_rxdma_irq(info); - else - e100_disable_serial_data_irq(info); -} - -#if defined(CONFIG_ETRAX_RS485) -/* Enable RS-485 mode on selected port. This is UGLY. */ -static int -e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r) -{ - struct e100_serial * info = (struct e100_serial *)tty->driver_data; - -#if defined(CONFIG_ETRAX_RS485_ON_PA) - *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit); -#endif - - info->rs485 = *r; - - /* Maximum delay before RTS equal to 1000 */ - if (info->rs485.delay_rts_before_send >= 1000) - info->rs485.delay_rts_before_send = 1000; - -/* printk("rts: on send = %i, after = %i, enabled = %i", - info->rs485.rts_on_send, - info->rs485.rts_after_sent, - info->rs485.enabled - ); -*/ - return 0; -} - -static int -e100_write_rs485(struct tty_struct *tty, - const unsigned char *buf, int count) -{ - struct e100_serial * info = (struct e100_serial *)tty->driver_data; - int old_value = (info->rs485.flags) & SER_RS485_ENABLED; - - /* rs485 is always implicitly enabled if we're using the ioctl() - * but it doesn't have to be set in the serial_rs485 - * (to be backward compatible with old apps) - * So we store, set and restore it. - */ - info->rs485.flags |= SER_RS485_ENABLED; - /* rs_write now deals with RS485 if enabled */ - count = rs_write(tty, buf, count); - if (!old_value) - info->rs485.flags &= ~(SER_RS485_ENABLED); - return count; -} - -#ifdef CONFIG_ETRAX_FAST_TIMER -/* Timer function to toggle RTS when using FAST_TIMER */ -static void rs485_toggle_rts_timer_function(unsigned long data) -{ - struct e100_serial *info = (struct e100_serial *)data; - - fast_timers_rs485[info->line].function = NULL; - e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND)); -#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) - e100_enable_rx(info); - e100_enable_rx_irq(info); -#endif -} -#endif -#endif /* CONFIG_ETRAX_RS485 */ - -/* - * ------------------------------------------------------------ - * rs_stop() and rs_start() - * - * This routines are called before setting or resetting tty->stopped. - * They enable or disable transmitter using the XOFF registers, as necessary. - * ------------------------------------------------------------ - */ - -static void -rs_stop(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - if (info) { - unsigned long flags; - unsigned long xoff; - - local_irq_save(flags); - DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n", - CIRC_CNT(info->xmit.head, - info->xmit.tail,SERIAL_XMIT_SIZE))); - - xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, - STOP_CHAR(info->port.tty)); - xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop); - if (I_IXON(tty)) - xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); - - *((unsigned long *)&info->ioport[REG_XOFF]) = xoff; - local_irq_restore(flags); - } -} - -static void -rs_start(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - if (info) { - unsigned long flags; - unsigned long xoff; - - local_irq_save(flags); - DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n", - CIRC_CNT(info->xmit.head, - info->xmit.tail,SERIAL_XMIT_SIZE))); - xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty)); - xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); - if (I_IXON(tty)) - xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); - - *((unsigned long *)&info->ioport[REG_XOFF]) = xoff; - if (!info->uses_dma_out && - info->xmit.head != info->xmit.tail && info->xmit.buf) - e100_enable_serial_tx_ready_irq(info); - - local_irq_restore(flags); - } -} - -/* - * ---------------------------------------------------------------------- - * - * Here starts the interrupt handling routines. All of the following - * subroutines are declared as inline and are folded into - * rs_interrupt(). They were separated out for readability's sake. - * - * Note: rs_interrupt() is a "fast" interrupt, which means that it - * runs with interrupts turned off. People who may want to modify - * rs_interrupt() should try to keep the interrupt handler as fast as - * possible. After you are done making modifications, it is not a bad - * idea to do: - * - * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c - * - * and look at the resulting assemble code in serial.s. - * - * - Ted Ts'o (tytso@mit.edu), 7-Mar-93 - * ----------------------------------------------------------------------- - */ - -/* - * This routine is used by the interrupt handler to schedule - * processing in the software interrupt portion of the driver. - */ -static void rs_sched_event(struct e100_serial *info, int event) -{ - if (info->event & (1 << event)) - return; - info->event |= 1 << event; - schedule_work(&info->work); -} - -/* The output DMA channel is free - use it to send as many chars as possible - * NOTES: - * We don't pay attention to info->x_char, which means if the TTY wants to - * use XON/XOFF it will set info->x_char but we won't send any X char! - * - * To implement this, we'd just start a DMA send of 1 byte pointing at a - * buffer containing the X char, and skip updating xmit. We'd also have to - * check if the last sent char was the X char when we enter this function - * the next time, to avoid updating xmit with the sent X value. - */ - -static void -transmit_chars_dma(struct e100_serial *info) -{ - unsigned int c, sentl; - struct etrax_dma_descr *descr; - - /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */ - *info->oclrintradr = - IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | - IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); - -#ifdef SERIAL_DEBUG_INTR - if (info->line == SERIAL_DEBUG_LINE) - printk("tc\n"); -#endif - if (!info->tr_running) { - /* weirdo... we shouldn't get here! */ - printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n"); - return; - } - - descr = &info->tr_descr; - - /* first get the amount of bytes sent during the last DMA transfer, - and update xmit accordingly */ - - /* if the stop bit was not set, all data has been sent */ - if (!(descr->status & d_stop)) { - sentl = descr->sw_len; - } else - /* otherwise we find the amount of data sent here */ - sentl = descr->hw_len; - - DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl)); - - /* update stats */ - info->icount.tx += sentl; - - /* update xmit buffer */ - info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1); - - /* if there is only a few chars left in the buf, wake up the blocked - write if any */ - if (CIRC_CNT(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE) < WAKEUP_CHARS) - rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); - - /* find out the largest amount of consecutive bytes we want to send now */ - - c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); - - /* Don't send all in one DMA transfer - divide it so we wake up - * application before all is sent - */ - - if (c >= 4*WAKEUP_CHARS) - c = c/2; - - if (c <= 0) { - /* our job here is done, don't schedule any new DMA transfer */ - info->tr_running = 0; - -#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER) - if (info->rs485.flags & SER_RS485_ENABLED) { - /* Set a short timer to toggle RTS */ - start_one_shot_timer(&fast_timers_rs485[info->line], - rs485_toggle_rts_timer_function, - (unsigned long)info, - info->char_time_usec*2, - "RS-485"); - } -#endif /* RS485 */ - return; - } - - /* ok we can schedule a dma send of c chars starting at info->xmit.tail */ - /* set up the descriptor correctly for output */ - DFLOW(DEBUG_LOG(info->line, "TX %i\n", c)); - descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */ - descr->sw_len = c; - descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail); - descr->status = 0; - - *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */ - *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start); - - /* DMA is now running (hopefully) */ -} /* transmit_chars_dma */ - -static void -start_transmit(struct e100_serial *info) -{ -#if 0 - if (info->line == SERIAL_DEBUG_LINE) - printk("x\n"); -#endif - - info->tr_descr.sw_len = 0; - info->tr_descr.hw_len = 0; - info->tr_descr.status = 0; - info->tr_running = 1; - if (info->uses_dma_out) - transmit_chars_dma(info); - else - e100_enable_serial_tx_ready_irq(info); -} /* start_transmit */ - -#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER -static int serial_fast_timer_started = 0; -static int serial_fast_timer_expired = 0; -static void flush_timeout_function(unsigned long data); -#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\ - unsigned long timer_flags; \ - local_irq_save(timer_flags); \ - if (fast_timers[info->line].function == NULL) { \ - serial_fast_timer_started++; \ - TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \ - TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \ - start_one_shot_timer(&fast_timers[info->line], \ - flush_timeout_function, \ - (unsigned long)info, \ - (usec), \ - string); \ - } \ - else { \ - TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \ - } \ - local_irq_restore(timer_flags); \ -} -#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec) - -#else -#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) -#define START_FLUSH_FAST_TIMER(info, string) -#endif - -static struct etrax_recv_buffer * -alloc_recv_buffer(unsigned int size) -{ - struct etrax_recv_buffer *buffer; - - buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC); - if (!buffer) - return NULL; - - buffer->next = NULL; - buffer->length = 0; - buffer->error = TTY_NORMAL; - - return buffer; -} - -static void -append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer) -{ - unsigned long flags; - - local_irq_save(flags); - - if (!info->first_recv_buffer) - info->first_recv_buffer = buffer; - else - info->last_recv_buffer->next = buffer; - - info->last_recv_buffer = buffer; - - info->recv_cnt += buffer->length; - if (info->recv_cnt > info->max_recv_cnt) - info->max_recv_cnt = info->recv_cnt; - - local_irq_restore(flags); -} - -static int -add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag) -{ - struct etrax_recv_buffer *buffer; - if (info->uses_dma_in) { - buffer = alloc_recv_buffer(4); - if (!buffer) - return 0; - - buffer->length = 1; - buffer->error = flag; - buffer->buffer[0] = data; - - append_recv_buffer(info, buffer); - - info->icount.rx++; - } else { - tty_insert_flip_char(&info->port, data, flag); - info->icount.rx++; - } - - return 1; -} - -static unsigned int handle_descr_data(struct e100_serial *info, - struct etrax_dma_descr *descr, - unsigned int recvl) -{ - struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer; - - if (info->recv_cnt + recvl > 65536) { - printk(KERN_WARNING - "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl); - return 0; - } - - buffer->length = recvl; - - if (info->errorcode == ERRCODE_SET_BREAK) - buffer->error = TTY_BREAK; - info->errorcode = 0; - - append_recv_buffer(info, buffer); - - buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE); - if (!buffer) - panic("%s: Failed to allocate memory for receive buffer!\n", __func__); - - descr->buf = virt_to_phys(buffer->buffer); - - return recvl; -} - -static unsigned int handle_all_descr_data(struct e100_serial *info) -{ - struct etrax_dma_descr *descr; - unsigned int recvl; - unsigned int ret = 0; - - while (1) - { - descr = &info->rec_descr[info->cur_rec_descr]; - - if (descr == phys_to_virt(*info->idescradr)) - break; - - if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS) - info->cur_rec_descr = 0; - - /* find out how many bytes were read */ - - /* if the eop bit was not set, all data has been received */ - if (!(descr->status & d_eop)) { - recvl = descr->sw_len; - } else { - /* otherwise we find the amount of data received here */ - recvl = descr->hw_len; - } - - /* Reset the status information */ - descr->status = 0; - - DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl); - if (info->port.tty->stopped) { - unsigned char *buf = phys_to_virt(descr->buf); - DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]); - DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]); - DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]); - } - ); - - /* update stats */ - info->icount.rx += recvl; - - ret += handle_descr_data(info, descr, recvl); - } - - return ret; -} - -static void receive_chars_dma(struct e100_serial *info) -{ - struct tty_struct *tty; - unsigned char rstat; - - /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */ - *info->iclrintradr = - IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | - IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); - - tty = info->port.tty; - if (!tty) /* Something wrong... */ - return; - -#ifdef SERIAL_HANDLE_EARLY_ERRORS - if (info->uses_dma_in) - e100_enable_serial_data_irq(info); -#endif - - if (info->errorcode == ERRCODE_INSERT_BREAK) - add_char_and_flag(info, '\0', TTY_BREAK); - - handle_all_descr_data(info); - - /* Read the status register to detect errors */ - rstat = info->ioport[REG_STATUS]; - if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) { - DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat)); - } - - if (rstat & SER_ERROR_MASK) { - /* If we got an error, we must reset it by reading the - * data_in field - */ - unsigned char data = info->ioport[REG_DATA]; - - DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n", - ((rstat & SER_ERROR_MASK) << 8) | data); - - if (rstat & SER_PAR_ERR_MASK) - add_char_and_flag(info, data, TTY_PARITY); - else if (rstat & SER_OVERRUN_MASK) - add_char_and_flag(info, data, TTY_OVERRUN); - else if (rstat & SER_FRAMING_ERR_MASK) - add_char_and_flag(info, data, TTY_FRAME); - } - - START_FLUSH_FAST_TIMER(info, "receive_chars"); - - /* Restart the receiving DMA */ - *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart); -} - -static int start_recv_dma(struct e100_serial *info) -{ - struct etrax_dma_descr *descr = info->rec_descr; - struct etrax_recv_buffer *buffer; - int i; - - /* Set up the receiving descriptors */ - for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) { - buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE); - if (!buffer) - panic("%s: Failed to allocate memory for receive buffer!\n", __func__); - - descr[i].ctrl = d_int; - descr[i].buf = virt_to_phys(buffer->buffer); - descr[i].sw_len = SERIAL_DESCR_BUF_SIZE; - descr[i].hw_len = 0; - descr[i].status = 0; - descr[i].next = virt_to_phys(&descr[i+1]); - } - - /* Link the last descriptor to the first */ - descr[i-1].next = virt_to_phys(&descr[0]); - - /* Start with the first descriptor in the list */ - info->cur_rec_descr = 0; - - /* Start the DMA */ - *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]); - *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start); - - /* Input DMA should be running now */ - return 1; -} - -static void -start_receive(struct e100_serial *info) -{ - if (info->uses_dma_in) { - /* reset the input dma channel to be sure it works */ - - *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) == - IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); - - start_recv_dma(info); - } -} - - -/* the bits in the MASK2 register are laid out like this: - DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR - where I is the input channel and O is the output channel for the port. - info->irq is the bit number for the DMAO_DESCR so to check the others we - shift info->irq to the left. -*/ - -/* dma output channel interrupt handler - this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or - DMA8(ser1) when they have finished a descriptor with the intr flag set. -*/ - -static irqreturn_t -tr_interrupt(int irq, void *dev_id) -{ - struct e100_serial *info; - unsigned long ireg; - int i; - int handled = 0; - - /* find out the line that caused this irq and get it from rs_table */ - - ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */ - - for (i = 0; i < NR_PORTS; i++) { - info = rs_table + i; - if (!info->enabled || !info->uses_dma_out) - continue; - /* check for dma_descr (don't need to check for dma_eop in output dma for serial */ - if (ireg & info->irq) { - handled = 1; - /* we can send a new dma bunch. make it so. */ - DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i)); - /* Read jiffies_usec first, - * we want this time to be as late as possible - */ - info->last_tx_active_usec = GET_JIFFIES_USEC(); - info->last_tx_active = jiffies; - transmit_chars_dma(info); - } - - /* FIXME: here we should really check for a change in the - status lines and if so call status_handle(info) */ - } - return IRQ_RETVAL(handled); -} /* tr_interrupt */ - -/* dma input channel interrupt handler */ - -static irqreturn_t -rec_interrupt(int irq, void *dev_id) -{ - struct e100_serial *info; - unsigned long ireg; - int i; - int handled = 0; - - /* find out the line that caused this irq and get it from rs_table */ - - ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */ - - for (i = 0; i < NR_PORTS; i++) { - info = rs_table + i; - if (!info->enabled || !info->uses_dma_in) - continue; - /* check for both dma_eop and dma_descr for the input dma channel */ - if (ireg & ((info->irq << 2) | (info->irq << 3))) { - handled = 1; - /* we have received something */ - receive_chars_dma(info); - } - - /* FIXME: here we should really check for a change in the - status lines and if so call status_handle(info) */ - } - return IRQ_RETVAL(handled); -} /* rec_interrupt */ - -static int force_eop_if_needed(struct e100_serial *info) -{ - /* We check data_avail bit to determine if data has - * arrived since last time - */ - unsigned char rstat = info->ioport[REG_STATUS]; - - /* error or datavail? */ - if (rstat & SER_ERROR_MASK) { - /* Some error has occurred. If there has been valid data, an - * EOP interrupt will be made automatically. If no data, the - * normal ser_interrupt should be enabled and handle it. - * So do nothing! - */ - DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n", - rstat | (info->line << 8)); - return 0; - } - - if (rstat & SER_DATA_AVAIL_MASK) { - /* Ok data, no error, count it */ - TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n", - rstat | (info->line << 8))); - /* Read data to clear status flags */ - (void)info->ioport[REG_DATA]; - - info->forced_eop = 0; - START_FLUSH_FAST_TIMER(info, "magic"); - return 0; - } - - /* hit the timeout, force an EOP for the input - * dma channel if we haven't already - */ - if (!info->forced_eop) { - info->forced_eop = 1; - TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line)); - FORCE_EOP(info); - } - - return 1; -} - -static void flush_to_flip_buffer(struct e100_serial *info) -{ - struct etrax_recv_buffer *buffer; - unsigned long flags; - - local_irq_save(flags); - - while ((buffer = info->first_recv_buffer) != NULL) { - unsigned int count = buffer->length; - - tty_insert_flip_string(&info->port, buffer->buffer, count); - info->recv_cnt -= count; - - if (count == buffer->length) { - info->first_recv_buffer = buffer->next; - kfree(buffer); - } else { - buffer->length -= count; - memmove(buffer->buffer, buffer->buffer + count, buffer->length); - buffer->error = TTY_NORMAL; - } - } - - if (!info->first_recv_buffer) - info->last_recv_buffer = NULL; - - local_irq_restore(flags); - - /* This includes a check for low-latency */ - tty_flip_buffer_push(&info->port); -} - -static void check_flush_timeout(struct e100_serial *info) -{ - /* Flip what we've got (if we can) */ - flush_to_flip_buffer(info); - - /* We might need to flip later, but not to fast - * since the system is busy processing input... */ - if (info->first_recv_buffer) - START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000); - - /* Force eop last, since data might have come while we're processing - * and if we started the slow timer above, we won't start a fast - * below. - */ - force_eop_if_needed(info); -} - -#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER -static void flush_timeout_function(unsigned long data) -{ - struct e100_serial *info = (struct e100_serial *)data; - - fast_timers[info->line].function = NULL; - serial_fast_timer_expired++; - TIMERD(DEBUG_LOG(info->line, "flush_timeout %i ", info->line)); - TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired)); - check_flush_timeout(info); -} - -#else - -/* dma fifo/buffer timeout handler - forces an end-of-packet for the dma input channel if no chars - have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s. -*/ - -static struct timer_list flush_timer; - -static void -timed_flush_handler(struct timer_list *unused) -{ - struct e100_serial *info; - int i; - - for (i = 0; i < NR_PORTS; i++) { - info = rs_table + i; - if (info->uses_dma_in) - check_flush_timeout(info); - } - - /* restart flush timer */ - mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS); -} -#endif - -#ifdef SERIAL_HANDLE_EARLY_ERRORS - -/* If there is an error (ie break) when the DMA is running and - * there are no bytes in the fifo the DMA is stopped and we get no - * eop interrupt. Thus we have to monitor the first bytes on a DMA - * transfer, and if it is without error we can turn the serial - * interrupts off. - */ - -/* -BREAK handling on ETRAX 100: -ETRAX will generate interrupt although there is no stop bit between the -characters. - -Depending on how long the break sequence is, the end of the breaksequence -will look differently: -| indicates start/end of a character. - -B= Break character (0x00) with framing error. -E= Error byte with parity error received after B characters. -F= "Faked" valid byte received immediately after B characters. -V= Valid byte - -1. - B BL ___________________________ V -.._|__________|__________| |valid data | - -Multiple frame errors with data == 0x00 (B), -the timing matches up "perfectly" so no extra ending char is detected. -The RXD pin is 1 in the last interrupt, in that case -we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really -know if another byte will come and this really is case 2. below -(e.g F=0xFF or 0xFE) -If RXD pin is 0 we can expect another character (see 2. below). - - -2. - - B B E or F__________________..__ V -.._|__________|__________|______ | |valid data - "valid" or - parity error - -Multiple frame errors with data == 0x00 (B), -but the part of the break trigs is interpreted as a start bit (and possibly -some 0 bits followed by a number of 1 bits and a stop bit). -Depending on parity settings etc. this last character can be either -a fake "valid" char (F) or have a parity error (E). - -If the character is valid it will be put in the buffer, -we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt -will set the flags so the tty will handle it, -if it's an error byte it will not be put in the buffer -and we set info->errorcode = ERRCODE_INSERT_BREAK. - -To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp -of the last faulty char (B) and compares it with the current time: -If the time elapsed time is less then 2*char_time_usec we will assume -it's a faked F char and not a Valid char and set -info->errorcode = ERRCODE_SET_BREAK. - -Flaws in the above solution: -~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -We use the timer to distinguish a F character from a V character, -if a V character is to close after the break we might make the wrong decision. - -TODO: The break will be delayed until an F or V character is received. - -*/ - -static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info) -{ - unsigned long data_read; - - /* Read data and status at the same time */ - data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]); -more_data: - if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) { - DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0)); - } - DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read))); - - if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) | - IO_MASK(R_SERIAL0_READ, par_err) | - IO_MASK(R_SERIAL0_READ, overrun) )) { - /* An error */ - info->last_rx_active_usec = GET_JIFFIES_USEC(); - info->last_rx_active = jiffies; - DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read)); - DLOG_INT_TRIG( - if (!log_int_trig1_pos) { - log_int_trig1_pos = log_int_pos; - log_int(rdpc(), 0, 0); - } - ); - - - if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) && - (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) { - /* Most likely a break, but we get interrupts over and - * over again. - */ - - if (!info->break_detected_cnt) { - DEBUG_LOG(info->line, "#BRK start\n", 0); - } - if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) { - /* The RX pin is high now, so the break - * must be over, but.... - * we can't really know if we will get another - * last byte ending the break or not. - * And we don't know if the byte (if any) will - * have an error or look valid. - */ - DEBUG_LOG(info->line, "# BL BRK\n", 0); - info->errorcode = ERRCODE_INSERT_BREAK; - } - info->break_detected_cnt++; - } else { - /* The error does not look like a break, but could be - * the end of one - */ - if (info->break_detected_cnt) { - DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt); - info->errorcode = ERRCODE_INSERT_BREAK; - } else { - unsigned char data = IO_EXTRACT(R_SERIAL0_READ, - data_in, data_read); - char flag = TTY_NORMAL; - if (info->errorcode == ERRCODE_INSERT_BREAK) { - tty_insert_flip_char(&info->port, 0, flag); - info->icount.rx++; - } - - if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) { - info->icount.parity++; - flag = TTY_PARITY; - } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) { - info->icount.overrun++; - flag = TTY_OVERRUN; - } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) { - info->icount.frame++; - flag = TTY_FRAME; - } - tty_insert_flip_char(&info->port, data, flag); - info->errorcode = 0; - } - info->break_detected_cnt = 0; - } - } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) { - /* No error */ - DLOG_INT_TRIG( - if (!log_int_trig1_pos) { - if (log_int_pos >= log_int_size) { - log_int_pos = 0; - } - log_int_trig0_pos = log_int_pos; - log_int(rdpc(), 0, 0); - } - ); - tty_insert_flip_char(&info->port, - IO_EXTRACT(R_SERIAL0_READ, data_in, data_read), - TTY_NORMAL); - } else { - DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read); - } - - - info->icount.rx++; - data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]); - if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) { - DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)); - goto more_data; - } - - tty_flip_buffer_push(&info->port); -} - -static void handle_ser_rx_interrupt(struct e100_serial *info) -{ - unsigned char rstat; - -#ifdef SERIAL_DEBUG_INTR - printk("Interrupt from serport %d\n", i); -#endif -/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */ - if (!info->uses_dma_in) { - handle_ser_rx_interrupt_no_dma(info); - return; - } - /* DMA is used */ - rstat = info->ioport[REG_STATUS]; - if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) { - DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0)); - } - - if (rstat & SER_ERROR_MASK) { - unsigned char data; - - info->last_rx_active_usec = GET_JIFFIES_USEC(); - info->last_rx_active = jiffies; - /* If we got an error, we must reset it by reading the - * data_in field - */ - data = info->ioport[REG_DATA]; - DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data)); - DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat)); - if (!data && (rstat & SER_FRAMING_ERR_MASK)) { - /* Most likely a break, but we get interrupts over and - * over again. - */ - - if (!info->break_detected_cnt) { - DEBUG_LOG(info->line, "#BRK start\n", 0); - } - if (rstat & SER_RXD_MASK) { - /* The RX pin is high now, so the break - * must be over, but.... - * we can't really know if we will get another - * last byte ending the break or not. - * And we don't know if the byte (if any) will - * have an error or look valid. - */ - DEBUG_LOG(info->line, "# BL BRK\n", 0); - info->errorcode = ERRCODE_INSERT_BREAK; - } - info->break_detected_cnt++; - } else { - /* The error does not look like a break, but could be - * the end of one - */ - if (info->break_detected_cnt) { - DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt); - info->errorcode = ERRCODE_INSERT_BREAK; - } else { - if (info->errorcode == ERRCODE_INSERT_BREAK) { - info->icount.brk++; - add_char_and_flag(info, '\0', TTY_BREAK); - } - - if (rstat & SER_PAR_ERR_MASK) { - info->icount.parity++; - add_char_and_flag(info, data, TTY_PARITY); - } else if (rstat & SER_OVERRUN_MASK) { - info->icount.overrun++; - add_char_and_flag(info, data, TTY_OVERRUN); - } else if (rstat & SER_FRAMING_ERR_MASK) { - info->icount.frame++; - add_char_and_flag(info, data, TTY_FRAME); - } - - info->errorcode = 0; - } - info->break_detected_cnt = 0; - DEBUG_LOG(info->line, "#iERR s d %04X\n", - ((rstat & SER_ERROR_MASK) << 8) | data); - } - } else { /* It was a valid byte, now let the DMA do the rest */ - unsigned long curr_time_u = GET_JIFFIES_USEC(); - unsigned long curr_time = jiffies; - - if (info->break_detected_cnt) { - /* Detect if this character is a new valid char or the - * last char in a break sequence: If LSBits are 0 and - * MSBits are high AND the time is close to the - * previous interrupt we should discard it. - */ - long elapsed_usec = - (curr_time - info->last_rx_active) * (1000000/HZ) + - curr_time_u - info->last_rx_active_usec; - if (elapsed_usec < 2*info->char_time_usec) { - DEBUG_LOG(info->line, "FBRK %i\n", info->line); - /* Report as BREAK (error) and let - * receive_chars_dma() handle it - */ - info->errorcode = ERRCODE_SET_BREAK; - } else { - DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line); - } - DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt); - } - -#ifdef SERIAL_DEBUG_INTR - printk("** OK, disabling ser_interrupts\n"); -#endif - e100_disable_serial_data_irq(info); - DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line)); - info->break_detected_cnt = 0; - - } - /* Restarting the DMA never hurts */ - *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart); - START_FLUSH_FAST_TIMER(info, "ser_int"); -} /* handle_ser_rx_interrupt */ - -static void handle_ser_tx_interrupt(struct e100_serial *info) -{ - unsigned long flags; - - if (info->x_char) { - unsigned char rstat; - DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char)); - local_irq_save(flags); - rstat = info->ioport[REG_STATUS]; - DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat)); - - info->ioport[REG_TR_DATA] = info->x_char; - info->icount.tx++; - info->x_char = 0; - /* We must enable since it is disabled in ser_interrupt */ - e100_enable_serial_tx_ready_irq(info); - local_irq_restore(flags); - return; - } - if (info->uses_dma_out) { - unsigned char rstat; - int i; - /* We only use normal tx interrupt when sending x_char */ - DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0)); - local_irq_save(flags); - rstat = info->ioport[REG_STATUS]; - DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat)); - e100_disable_serial_tx_ready_irq(info); - if (info->port.tty->stopped) - rs_stop(info->port.tty); - /* Enable the DMA channel and tell it to continue */ - e100_enable_txdma_channel(info); - /* Wait 12 cycles before doing the DMA command */ - for(i = 6; i > 0; i--) - nop(); - - *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue); - local_irq_restore(flags); - return; - } - /* Normal char-by-char interrupt */ - if (info->xmit.head == info->xmit.tail - || info->port.tty->stopped) { - DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n", - info->port.tty->stopped)); - e100_disable_serial_tx_ready_irq(info); - info->tr_running = 0; - return; - } - DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail])); - /* Send a byte, rs485 timing is critical so turn of ints */ - local_irq_save(flags); - info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail]; - info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1); - info->icount.tx++; - if (info->xmit.head == info->xmit.tail) { -#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER) - if (info->rs485.flags & SER_RS485_ENABLED) { - /* Set a short timer to toggle RTS */ - start_one_shot_timer(&fast_timers_rs485[info->line], - rs485_toggle_rts_timer_function, - (unsigned long)info, - info->char_time_usec*2, - "RS-485"); - } -#endif /* RS485 */ - info->last_tx_active_usec = GET_JIFFIES_USEC(); - info->last_tx_active = jiffies; - e100_disable_serial_tx_ready_irq(info); - info->tr_running = 0; - DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0)); - } else { - /* We must enable since it is disabled in ser_interrupt */ - e100_enable_serial_tx_ready_irq(info); - } - local_irq_restore(flags); - - if (CIRC_CNT(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE) < WAKEUP_CHARS) - rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); - -} /* handle_ser_tx_interrupt */ - -/* result of time measurements: - * RX duration 54-60 us when doing something, otherwise 6-9 us - * ser_int duration: just sending: 8-15 us normally, up to 73 us - */ -static irqreturn_t -ser_interrupt(int irq, void *dev_id) -{ - static volatile int tx_started = 0; - struct e100_serial *info; - int i; - unsigned long flags; - unsigned long irq_mask1_rd; - unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */ - int handled = 0; - static volatile unsigned long reentered_ready_mask = 0; - - local_irq_save(flags); - irq_mask1_rd = *R_IRQ_MASK1_RD; - /* First handle all rx interrupts with ints disabled */ - info = rs_table; - irq_mask1_rd &= e100_ser_int_mask; - for (i = 0; i < NR_PORTS; i++) { - /* Which line caused the data irq? */ - if (irq_mask1_rd & data_mask) { - handled = 1; - handle_ser_rx_interrupt(info); - } - info += 1; - data_mask <<= 2; - } - /* Handle tx interrupts with interrupts enabled so we - * can take care of new data interrupts while transmitting - * We protect the tx part with the tx_started flag. - * We disable the tr_ready interrupts we are about to handle and - * unblock the serial interrupt so new serial interrupts may come. - * - * If we get a new interrupt: - * - it migth be due to synchronous serial ports. - * - serial irq will be blocked by general irq handler. - * - async data will be handled above (sync will be ignored). - * - tx_started flag will prevent us from trying to send again and - * we will exit fast - no need to unblock serial irq. - * - Next (sync) serial interrupt handler will be runned with - * disabled interrupt due to restore_flags() at end of function, - * so sync handler will not be preempted or reentered. - */ - if (!tx_started) { - unsigned long ready_mask; - unsigned long - tx_started = 1; - /* Only the tr_ready interrupts left */ - irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) | - IO_MASK(R_IRQ_MASK1_RD, ser1_ready) | - IO_MASK(R_IRQ_MASK1_RD, ser2_ready) | - IO_MASK(R_IRQ_MASK1_RD, ser3_ready)); - while (irq_mask1_rd) { - /* Disable those we are about to handle */ - *R_IRQ_MASK1_CLR = irq_mask1_rd; - /* Unblock the serial interrupt */ - *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); - - local_irq_enable(); - ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */ - info = rs_table; - for (i = 0; i < NR_PORTS; i++) { - /* Which line caused the ready irq? */ - if (irq_mask1_rd & ready_mask) { - handled = 1; - handle_ser_tx_interrupt(info); - } - info += 1; - ready_mask <<= 2; - } - /* handle_ser_tx_interrupt enables tr_ready interrupts */ - local_irq_disable(); - /* Handle reentered TX interrupt */ - irq_mask1_rd = reentered_ready_mask; - } - local_irq_disable(); - tx_started = 0; - } else { - unsigned long ready_mask; - ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) | - IO_MASK(R_IRQ_MASK1_RD, ser1_ready) | - IO_MASK(R_IRQ_MASK1_RD, ser2_ready) | - IO_MASK(R_IRQ_MASK1_RD, ser3_ready)); - if (ready_mask) { - reentered_ready_mask |= ready_mask; - /* Disable those we are about to handle */ - *R_IRQ_MASK1_CLR = ready_mask; - DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask)); - } - } - - local_irq_restore(flags); - return IRQ_RETVAL(handled); -} /* ser_interrupt */ -#endif - -/* - * ------------------------------------------------------------------- - * Here ends the serial interrupt routines. - * ------------------------------------------------------------------- - */ - -/* - * This routine is used to handle the "bottom half" processing for the - * serial driver, known also the "software interrupt" processing. - * This processing is done at the kernel interrupt level, after the - * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This - * is where time-consuming activities which can not be done in the - * interrupt driver proper are done; the interrupt driver schedules - * them using rs_sched_event(), and they get done here. - */ -static void -do_softint(struct work_struct *work) -{ - struct e100_serial *info; - struct tty_struct *tty; - - info = container_of(work, struct e100_serial, work); - - tty = info->port.tty; - if (!tty) - return; - - if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) - tty_wakeup(tty); -} - -static int -startup(struct e100_serial * info) -{ - unsigned long flags; - unsigned long xmit_page; - int i; - - xmit_page = get_zeroed_page(GFP_KERNEL); - if (!xmit_page) - return -ENOMEM; - - local_irq_save(flags); - - /* if it was already initialized, skip this */ - - if (tty_port_initialized(&info->port)) { - local_irq_restore(flags); - free_page(xmit_page); - return 0; - } - - if (info->xmit.buf) - free_page(xmit_page); - else - info->xmit.buf = (unsigned char *) xmit_page; - -#ifdef SERIAL_DEBUG_OPEN - printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf); -#endif - - /* - * Clear the FIFO buffers and disable them - * (they will be reenabled in change_speed()) - */ - - /* - * Reset the DMA channels and make sure their interrupts are cleared - */ - - if (info->dma_in_enabled) { - info->uses_dma_in = 1; - e100_enable_rxdma_channel(info); - - *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - - /* Wait until reset cycle is complete */ - while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) == - IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); - - /* Make sure the irqs are cleared */ - *info->iclrintradr = - IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | - IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); - } else { - e100_disable_rxdma_channel(info); - } - - if (info->dma_out_enabled) { - info->uses_dma_out = 1; - e100_enable_txdma_channel(info); - *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - - while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) == - IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); - - /* Make sure the irqs are cleared */ - *info->oclrintradr = - IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | - IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); - } else { - e100_disable_txdma_channel(info); - } - - if (info->port.tty) - clear_bit(TTY_IO_ERROR, &info->port.tty->flags); - - info->xmit.head = info->xmit.tail = 0; - info->first_recv_buffer = info->last_recv_buffer = NULL; - info->recv_cnt = info->max_recv_cnt = 0; - - for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) - info->rec_descr[i].buf = 0; - - /* - * and set the speed and other flags of the serial port - * this will start the rx/tx as well - */ -#ifdef SERIAL_HANDLE_EARLY_ERRORS - e100_enable_serial_data_irq(info); -#endif - change_speed(info); - - /* dummy read to reset any serial errors */ - - (void)info->ioport[REG_DATA]; - - /* enable the interrupts */ - if (info->uses_dma_out) - e100_enable_txdma_irq(info); - - e100_enable_rx_irq(info); - - info->tr_running = 0; /* to be sure we don't lock up the transmitter */ - - /* setup the dma input descriptor and start dma */ - - start_receive(info); - - /* for safety, make sure the descriptors last result is 0 bytes written */ - - info->tr_descr.sw_len = 0; - info->tr_descr.hw_len = 0; - info->tr_descr.status = 0; - - /* enable RTS/DTR last */ - - e100_rts(info, 1); - e100_dtr(info, 1); - - tty_port_set_initialized(&info->port, 1); - - local_irq_restore(flags); - return 0; -} - -/* - * This routine will shutdown a serial port; interrupts are disabled, and - * DTR is dropped if the hangup on close termio flag is on. - */ -static void -shutdown(struct e100_serial * info) -{ - unsigned long flags; - struct etrax_dma_descr *descr = info->rec_descr; - struct etrax_recv_buffer *buffer; - int i; - - /* shut down the transmitter and receiver */ - DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line)); - e100_disable_rx(info); - info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40); - - /* disable interrupts, reset dma channels */ - if (info->uses_dma_in) { - e100_disable_rxdma_irq(info); - *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - info->uses_dma_in = 0; - } else { - e100_disable_serial_data_irq(info); - } - - if (info->uses_dma_out) { - e100_disable_txdma_irq(info); - info->tr_running = 0; - *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); - info->uses_dma_out = 0; - } else { - e100_disable_serial_tx_ready_irq(info); - info->tr_running = 0; - } - - if (!tty_port_initialized(&info->port)) - return; - -#ifdef SERIAL_DEBUG_OPEN - printk("Shutting down serial port %d (irq %d)....\n", info->line, - info->irq); -#endif - - local_irq_save(flags); - - if (info->xmit.buf) { - free_page((unsigned long)info->xmit.buf); - info->xmit.buf = NULL; - } - - for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) - if (descr[i].buf) { - buffer = phys_to_virt(descr[i].buf) - sizeof *buffer; - kfree(buffer); - descr[i].buf = 0; - } - - if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) { - /* hang up DTR and RTS if HUPCL is enabled */ - e100_dtr(info, 0); - e100_rts(info, 0); /* could check CRTSCTS before doing this */ - } - - if (info->port.tty) - set_bit(TTY_IO_ERROR, &info->port.tty->flags); - - tty_port_set_initialized(&info->port, 0); - local_irq_restore(flags); -} - - -/* change baud rate and other assorted parameters */ - -static void -change_speed(struct e100_serial *info) -{ - unsigned int cflag; - unsigned long xoff; - unsigned long flags; - /* first some safety checks */ - - if (!info->port.tty) - return; - if (!info->ioport) - return; - - cflag = info->port.tty->termios.c_cflag; - - /* possibly, the tx/rx should be disabled first to do this safely */ - - /* change baud-rate and write it to the hardware */ - if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) { - /* Special baudrate */ - u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */ - unsigned long alt_source = - IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) | - IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal); - /* R_ALT_SER_BAUDRATE selects the source */ - DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n", - (unsigned long)info->baud_base, info->custom_divisor)); - if (info->baud_base == SERIAL_PRESCALE_BASE) { - /* 0, 2-65535 (0=65536) */ - u16 divisor = info->custom_divisor; - /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */ - /* baudrate is 3.125MHz/custom_divisor */ - alt_source = - IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) | - IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale); - alt_source = 0x11; - DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor)); - *R_SERIAL_PRESCALE = divisor; - info->baud = SERIAL_PRESCALE_BASE/divisor; - } - else - { - /* Bad baudbase, we don't support using timer0 - * for baudrate. - */ - printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n", - (unsigned long)info->baud_base, info->custom_divisor); - } - r_alt_ser_baudrate_shadow &= ~mask; - r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8)); - *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow; - } else { - /* Normal baudrate */ - /* Make sure we use normal baudrate */ - u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */ - unsigned long alt_source = - IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) | - IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal); - r_alt_ser_baudrate_shadow &= ~mask; - r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8)); - *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow; - - info->baud = cflag_to_baud(cflag); - info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag); - } - - /* start with default settings and then fill in changes */ - local_irq_save(flags); - /* 8 bit, no/even parity */ - info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) | - IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) | - IO_MASK(R_SERIAL0_REC_CTRL, rec_par)); - - /* 8 bit, no/even parity, 1 stop bit, no cts */ - info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) | - IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) | - IO_MASK(R_SERIAL0_TR_CTRL, tr_par) | - IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) | - IO_MASK(R_SERIAL0_TR_CTRL, auto_cts)); - - if ((cflag & CSIZE) == CS7) { - /* set 7 bit mode */ - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); - info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); - } - - if (cflag & CSTOPB) { - /* set 2 stop bit mode */ - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits); - } - - if (cflag & PARENB) { - /* enable parity */ - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); - info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); - } - - if (cflag & CMSPAR) { - /* enable stick parity, PARODD mean Mark which matches ETRAX */ - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick); - info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick); - } - if (cflag & PARODD) { - /* set odd parity (or Mark if CMSPAR) */ - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd); - info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd); - } - - if (cflag & CRTSCTS) { - /* enable automatic CTS handling */ - DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0)); - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active); - } - - /* make sure the tx and rx are enabled */ - - info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable); - info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); - - /* actually write the control regs to the hardware */ - - info->ioport[REG_TR_CTRL] = info->tx_ctrl; - info->ioport[REG_REC_CTRL] = info->rx_ctrl; - xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty)); - xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); - if (info->port.tty->termios.c_iflag & IXON ) { - DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n", - STOP_CHAR(info->port.tty))); - xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); - } - - *((unsigned long *)&info->ioport[REG_XOFF]) = xoff; - local_irq_restore(flags); - - update_char_time(info); - -} /* change_speed */ - -/* start transmitting chars NOW */ - -static void -rs_flush_chars(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - - if (info->tr_running || - info->xmit.head == info->xmit.tail || - tty->stopped || - !info->xmit.buf) - return; - -#ifdef SERIAL_DEBUG_FLOW - printk("rs_flush_chars\n"); -#endif - - /* this protection might not exactly be necessary here */ - - local_irq_save(flags); - start_transmit(info); - local_irq_restore(flags); -} - -static int rs_raw_write(struct tty_struct *tty, - const unsigned char *buf, int count) -{ - int c, ret = 0; - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - - /* first some sanity checks */ - - if (!info->xmit.buf) - return 0; - -#ifdef SERIAL_DEBUG_DATA - if (info->line == SERIAL_DEBUG_LINE) - printk("rs_raw_write (%d), status %d\n", - count, info->ioport[REG_STATUS]); -#endif - - local_save_flags(flags); - DFLOW(DEBUG_LOG(info->line, "write count %i ", count)); - DFLOW(DEBUG_LOG(info->line, "ldisc\n")); - - - /* The local_irq_disable/restore_flags pairs below are needed - * because the DMA interrupt handler moves the info->xmit values. - * the memcpy needs to be in the critical region unfortunately, - * because we need to read xmit values, memcpy, write xmit values - * in one atomic operation... this could perhaps be avoided by - * more clever design. - */ - local_irq_disable(); - while (count) { - c = CIRC_SPACE_TO_END(info->xmit.head, - info->xmit.tail, - SERIAL_XMIT_SIZE); - - if (count < c) - c = count; - if (c <= 0) - break; - - memcpy(info->xmit.buf + info->xmit.head, buf, c); - info->xmit.head = (info->xmit.head + c) & - (SERIAL_XMIT_SIZE-1); - buf += c; - count -= c; - ret += c; - } - local_irq_restore(flags); - - /* enable transmitter if not running, unless the tty is stopped - * this does not need IRQ protection since if tr_running == 0 - * the IRQ's are not running anyway for this port. - */ - DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret)); - - if (info->xmit.head != info->xmit.tail && - !tty->stopped && - !info->tr_running) { - start_transmit(info); - } - - return ret; -} /* raw_raw_write() */ - -static int -rs_write(struct tty_struct *tty, - const unsigned char *buf, int count) -{ -#if defined(CONFIG_ETRAX_RS485) - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - - if (info->rs485.flags & SER_RS485_ENABLED) - { - /* If we are in RS-485 mode, we need to toggle RTS and disable - * the receiver before initiating a DMA transfer - */ -#ifdef CONFIG_ETRAX_FAST_TIMER - /* Abort any started timer */ - fast_timers_rs485[info->line].function = NULL; - del_fast_timer(&fast_timers_rs485[info->line]); -#endif - e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND)); -#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) - e100_disable_rx(info); - e100_enable_rx_irq(info); -#endif - if (info->rs485.delay_rts_before_send > 0) - msleep(info->rs485.delay_rts_before_send); - } -#endif /* CONFIG_ETRAX_RS485 */ - - count = rs_raw_write(tty, buf, count); - -#if defined(CONFIG_ETRAX_RS485) - if (info->rs485.flags & SER_RS485_ENABLED) - { - unsigned int val; - /* If we are in RS-485 mode the following has to be done: - * wait until DMA is ready - * wait on transmit shift register - * toggle RTS - * enable the receiver - */ - - /* Sleep until all sent */ - tty_wait_until_sent(tty, 0); -#ifdef CONFIG_ETRAX_FAST_TIMER - /* Now sleep a little more so that shift register is empty */ - schedule_usleep(info->char_time_usec * 2); -#endif - /* wait on transmit shift register */ - do{ - get_lsr_info(info, &val); - }while (!(val & TIOCSER_TEMT)); - - e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND)); - -#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) - e100_enable_rx(info); - e100_enable_rxdma_irq(info); -#endif - } -#endif /* CONFIG_ETRAX_RS485 */ - - return count; -} /* rs_write */ - - -/* how much space is available in the xmit buffer? */ - -static int -rs_write_room(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - - return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); -} - -/* How many chars are in the xmit buffer? - * This does not include any chars in the transmitter FIFO. - * Use wait_until_sent for waiting for FIFO drain. - */ - -static int -rs_chars_in_buffer(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - - return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); -} - -/* discard everything in the xmit buffer */ - -static void -rs_flush_buffer(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - - local_irq_save(flags); - info->xmit.head = info->xmit.tail = 0; - local_irq_restore(flags); - - tty_wakeup(tty); -} - -/* - * This function is used to send a high-priority XON/XOFF character to - * the device - * - * Since we use DMA we don't check for info->x_char in transmit_chars_dma(), - * but we do it in handle_ser_tx_interrupt(). - * We disable DMA channel and enable tx ready interrupt and write the - * character when possible. - */ -static void rs_send_xchar(struct tty_struct *tty, char ch) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - local_irq_save(flags); - if (info->uses_dma_out) { - /* Put the DMA on hold and disable the channel */ - *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold); - while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) != - IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold)); - e100_disable_txdma_channel(info); - } - - /* Must make sure transmitter is not stopped before we can transmit */ - if (tty->stopped) - rs_start(tty); - - /* Enable manual transmit interrupt and send from there */ - DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch)); - info->x_char = ch; - e100_enable_serial_tx_ready_irq(info); - local_irq_restore(flags); -} - -/* - * ------------------------------------------------------------ - * rs_throttle() - * - * This routine is called by the upper-layer tty layer to signal that - * incoming characters should be throttled. - * ------------------------------------------------------------ - */ -static void -rs_throttle(struct tty_struct * tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; -#ifdef SERIAL_DEBUG_THROTTLE - printk("throttle %s ....\n", tty_name(tty)); -#endif - DFLOW(DEBUG_LOG(info->line,"rs_throttle\n")); - - /* Do RTS before XOFF since XOFF might take some time */ - if (C_CRTSCTS(tty)) { - /* Turn off RTS line */ - e100_rts(info, 0); - } - if (I_IXOFF(tty)) - rs_send_xchar(tty, STOP_CHAR(tty)); - -} - -static void -rs_unthrottle(struct tty_struct * tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; -#ifdef SERIAL_DEBUG_THROTTLE - printk("unthrottle %s ....\n", tty_name(tty)); -#endif - DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc\n")); - DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count)); - /* Do RTS before XOFF since XOFF might take some time */ - if (C_CRTSCTS(tty)) { - /* Assert RTS line */ - e100_rts(info, 1); - } - - if (I_IXOFF(tty)) { - if (info->x_char) - info->x_char = 0; - else - rs_send_xchar(tty, START_CHAR(tty)); - } - -} - -/* - * ------------------------------------------------------------ - * rs_ioctl() and friends - * ------------------------------------------------------------ - */ - -static int -get_serial_info(struct e100_serial * info, - struct serial_struct * retinfo) -{ - struct serial_struct tmp; - - /* this is all probably wrong, there are a lot of fields - * here that we don't have in e100_serial and maybe we - * should set them to something else than 0. - */ - - memset(&tmp, 0, sizeof(tmp)); - tmp.type = info->type; - tmp.line = info->line; - tmp.port = (int)info->ioport; - tmp.irq = info->irq; - tmp.flags = info->port.flags; - tmp.baud_base = info->baud_base; - tmp.close_delay = info->port.close_delay; - tmp.closing_wait = info->port.closing_wait; - tmp.custom_divisor = info->custom_divisor; - if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) - return -EFAULT; - return 0; -} - -static int -set_serial_info(struct e100_serial *info, - struct serial_struct *new_info) -{ - struct serial_struct new_serial; - struct e100_serial old_info; - int retval = 0; - - if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) - return -EFAULT; - - old_info = *info; - - if (!capable(CAP_SYS_ADMIN)) { - if ((new_serial.type != info->type) || - (new_serial.close_delay != info->port.close_delay) || - ((new_serial.flags & ~ASYNC_USR_MASK) != - (info->port.flags & ~ASYNC_USR_MASK))) - return -EPERM; - info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) | - (new_serial.flags & ASYNC_USR_MASK)); - goto check_and_exit; - } - - if (info->port.count > 1) - return -EBUSY; - - /* - * OK, past this point, all the error checking has been done. - * At this point, we start making changes..... - */ - - info->baud_base = new_serial.baud_base; - info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) | - (new_serial.flags & ASYNC_FLAGS)); - info->custom_divisor = new_serial.custom_divisor; - info->type = new_serial.type; - info->port.close_delay = new_serial.close_delay; - info->port.closing_wait = new_serial.closing_wait; - info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; - - check_and_exit: - if (tty_port_initialized(&info->port)) - change_speed(info); - else - retval = startup(info); - return retval; -} - -/* - * get_lsr_info - get line status register info - * - * Purpose: Let user call ioctl() to get info when the UART physically - * is emptied. On bus types like RS485, the transmitter must - * release the bus after transmitting. This must be done when - * the transmit shift register is empty, not be done when the - * transmit holding register is empty. This functionality - * allows an RS485 driver to be written in user space. - */ -static int -get_lsr_info(struct e100_serial * info, unsigned int *value) -{ - unsigned int result = TIOCSER_TEMT; - unsigned long curr_time = jiffies; - unsigned long curr_time_usec = GET_JIFFIES_USEC(); - unsigned long elapsed_usec = - (curr_time - info->last_tx_active) * 1000000/HZ + - curr_time_usec - info->last_tx_active_usec; - - if (info->xmit.head != info->xmit.tail || - elapsed_usec < 2*info->char_time_usec) { - result = 0; - } - - if (copy_to_user(value, &result, sizeof(int))) - return -EFAULT; - return 0; -} - -#ifdef SERIAL_DEBUG_IO -struct state_str -{ - int state; - const char *str; -}; - -const struct state_str control_state_str[] = { - {TIOCM_DTR, "DTR" }, - {TIOCM_RTS, "RTS"}, - {TIOCM_ST, "ST?" }, - {TIOCM_SR, "SR?" }, - {TIOCM_CTS, "CTS" }, - {TIOCM_CD, "CD" }, - {TIOCM_RI, "RI" }, - {TIOCM_DSR, "DSR" }, - {0, NULL } -}; - -char *get_control_state_str(int MLines, char *s) -{ - int i = 0; - - s[0]='\0'; - while (control_state_str[i].str != NULL) { - if (MLines & control_state_str[i].state) { - if (s[0] != '\0') { - strcat(s, ", "); - } - strcat(s, control_state_str[i].str); - } - i++; - } - return s; -} -#endif - -static int -rs_break(struct tty_struct *tty, int break_state) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - - if (!info->ioport) - return -EIO; - - local_irq_save(flags); - if (break_state == -1) { - /* Go to manual mode and set the txd pin to 0 */ - /* Clear bit 7 (txd) and 6 (tr_enable) */ - info->tx_ctrl &= 0x3F; - } else { - /* Set bit 7 (txd) and 6 (tr_enable) */ - info->tx_ctrl |= (0x80 | 0x40); - } - info->ioport[REG_TR_CTRL] = info->tx_ctrl; - local_irq_restore(flags); - return 0; -} - -static int -rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - - local_irq_save(flags); - - if (clear & TIOCM_RTS) - e100_rts(info, 0); - if (clear & TIOCM_DTR) - e100_dtr(info, 0); - /* Handle FEMALE behaviour */ - if (clear & TIOCM_RI) - e100_ri_out(info, 0); - if (clear & TIOCM_CD) - e100_cd_out(info, 0); - - if (set & TIOCM_RTS) - e100_rts(info, 1); - if (set & TIOCM_DTR) - e100_dtr(info, 1); - /* Handle FEMALE behaviour */ - if (set & TIOCM_RI) - e100_ri_out(info, 1); - if (set & TIOCM_CD) - e100_cd_out(info, 1); - - local_irq_restore(flags); - return 0; -} - -static int -rs_tiocmget(struct tty_struct *tty) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned int result; - unsigned long flags; - - local_irq_save(flags); - - result = - (!E100_RTS_GET(info) ? TIOCM_RTS : 0) - | (!E100_DTR_GET(info) ? TIOCM_DTR : 0) - | (!E100_RI_GET(info) ? TIOCM_RNG : 0) - | (!E100_DSR_GET(info) ? TIOCM_DSR : 0) - | (!E100_CD_GET(info) ? TIOCM_CAR : 0) - | (!E100_CTS_GET(info) ? TIOCM_CTS : 0); - - local_irq_restore(flags); - -#ifdef SERIAL_DEBUG_IO - printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n", - info->line, result, result); - { - char s[100]; - - get_control_state_str(result, s); - printk(KERN_DEBUG "state: %s\n", s); - } -#endif - return result; - -} - - -static int -rs_ioctl(struct tty_struct *tty, - unsigned int cmd, unsigned long arg) -{ - struct e100_serial * info = (struct e100_serial *)tty->driver_data; - - if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && - (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) && - (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) { - if (tty_io_error(tty)) - return -EIO; - } - - switch (cmd) { - case TIOCGSERIAL: - return get_serial_info(info, - (struct serial_struct *) arg); - case TIOCSSERIAL: - return set_serial_info(info, - (struct serial_struct *) arg); - case TIOCSERGETLSR: /* Get line status register */ - return get_lsr_info(info, (unsigned int *) arg); - - case TIOCSERGSTRUCT: - if (copy_to_user((struct e100_serial *) arg, - info, sizeof(struct e100_serial))) - return -EFAULT; - return 0; - -#if defined(CONFIG_ETRAX_RS485) - case TIOCSERSETRS485: - { - /* In this ioctl we still use the old structure - * rs485_control for backward compatibility - * (if we use serial_rs485, then old user-level code - * wouldn't work anymore...). - * The use of this ioctl is deprecated: use TIOCSRS485 - * instead.*/ - struct rs485_control rs485ctrl; - struct serial_rs485 rs485data; - printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n"); - if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg, - sizeof(rs485ctrl))) - return -EFAULT; - - rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send; - rs485data.flags = 0; - - if (rs485ctrl.enabled) - rs485data.flags |= SER_RS485_ENABLED; - else - rs485data.flags &= ~(SER_RS485_ENABLED); - - if (rs485ctrl.rts_on_send) - rs485data.flags |= SER_RS485_RTS_ON_SEND; - else - rs485data.flags &= ~(SER_RS485_RTS_ON_SEND); - - if (rs485ctrl.rts_after_sent) - rs485data.flags |= SER_RS485_RTS_AFTER_SEND; - else - rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND); - - return e100_enable_rs485(tty, &rs485data); - } - - case TIOCSRS485: - { - /* This is the new version of TIOCSRS485, with new - * data structure serial_rs485 */ - struct serial_rs485 rs485data; - if (copy_from_user(&rs485data, (struct rs485_control *)arg, - sizeof(rs485data))) - return -EFAULT; - - return e100_enable_rs485(tty, &rs485data); - } - - case TIOCGRS485: - { - struct serial_rs485 *rs485data = - &(((struct e100_serial *)tty->driver_data)->rs485); - /* This is the ioctl to get RS485 data from user-space */ - if (copy_to_user((struct serial_rs485 *) arg, - rs485data, - sizeof(struct serial_rs485))) - return -EFAULT; - break; - } - - case TIOCSERWRRS485: - { - struct rs485_write rs485wr; - if (copy_from_user(&rs485wr, (struct rs485_write *)arg, - sizeof(rs485wr))) - return -EFAULT; - - return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size); - } -#endif - - default: - return -ENOIOCTLCMD; - } - return 0; -} - -static void -rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios) -{ - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - - change_speed(info); - - /* Handle turning off CRTSCTS */ - if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) - rs_start(tty); - -} - -/* - * ------------------------------------------------------------ - * rs_close() - * - * This routine is called when the serial port gets closed. First, we - * wait for the last remaining data to be sent. Then, we unlink its - * S structure from the interrupt chain if necessary, and we free - * that IRQ if nothing is left in the chain. - * ------------------------------------------------------------ - */ -static void -rs_close(struct tty_struct *tty, struct file * filp) -{ - struct e100_serial * info = (struct e100_serial *)tty->driver_data; - unsigned long flags; - - if (!info) - return; - - /* interrupts are disabled for this entire function */ - - local_irq_save(flags); - - if (tty_hung_up_p(filp)) { - local_irq_restore(flags); - return; - } - -#ifdef SERIAL_DEBUG_OPEN - printk("[%d] rs_close ttyS%d, count = %d\n", current->pid, - info->line, info->count); -#endif - if ((tty->count == 1) && (info->port.count != 1)) { - /* - * Uh, oh. tty->count is 1, which means that the tty - * structure will be freed. Info->count should always - * be one in these conditions. If it's greater than - * one, we've got real problems, since it means the - * serial port won't be shutdown. - */ - printk(KERN_ERR - "rs_close: bad serial port count; tty->count is 1, " - "info->count is %d\n", info->port.count); - info->port.count = 1; - } - if (--info->port.count < 0) { - printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n", - info->line, info->port.count); - info->port.count = 0; - } - if (info->port.count) { - local_irq_restore(flags); - return; - } - /* - * Now we wait for the transmit buffer to clear; and we notify - * the line discipline to only process XON/XOFF characters. - */ - tty->closing = 1; - if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) - tty_wait_until_sent(tty, info->port.closing_wait); - /* - * At this point we stop accepting input. To do this, we - * disable the serial receiver and the DMA receive interrupt. - */ -#ifdef SERIAL_HANDLE_EARLY_ERRORS - e100_disable_serial_data_irq(info); -#endif - - e100_disable_rx(info); - e100_disable_rx_irq(info); - - if (tty_port_initialized(&info->port)) { - /* - * Before we drop DTR, make sure the UART transmitter - * has completely drained; this is especially - * important as we have a transmit FIFO! - */ - rs_wait_until_sent(tty, HZ); - } - - shutdown(info); - rs_flush_buffer(tty); - tty_ldisc_flush(tty); - tty->closing = 0; - info->event = 0; - info->port.tty = NULL; - if (info->port.blocked_open) { - if (info->port.close_delay) - schedule_timeout_interruptible(info->port.close_delay); - wake_up_interruptible(&info->port.open_wait); - } - local_irq_restore(flags); - tty_port_set_active(&info->port, 0); - - /* port closed */ - -#if defined(CONFIG_ETRAX_RS485) - if (info->rs485.flags & SER_RS485_ENABLED) { - info->rs485.flags &= ~(SER_RS485_ENABLED); -#if defined(CONFIG_ETRAX_RS485_ON_PA) - *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit); -#endif - } -#endif - - /* - * Release any allocated DMA irq's. - */ - if (info->dma_in_enabled) { - free_irq(info->dma_in_irq_nbr, info); - cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description); - info->uses_dma_in = 0; -#ifdef SERIAL_DEBUG_OPEN - printk(KERN_DEBUG "DMA irq '%s' freed\n", - info->dma_in_irq_description); -#endif - } - if (info->dma_out_enabled) { - free_irq(info->dma_out_irq_nbr, info); - cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description); - info->uses_dma_out = 0; -#ifdef SERIAL_DEBUG_OPEN - printk(KERN_DEBUG "DMA irq '%s' freed\n", - info->dma_out_irq_description); -#endif - } -} - -/* - * rs_wait_until_sent() --- wait until the transmitter is empty - */ -static void rs_wait_until_sent(struct tty_struct *tty, int timeout) -{ - unsigned long orig_jiffies; - struct e100_serial *info = (struct e100_serial *)tty->driver_data; - unsigned long curr_time = jiffies; - unsigned long curr_time_usec = GET_JIFFIES_USEC(); - long elapsed_usec = - (curr_time - info->last_tx_active) * (1000000/HZ) + - curr_time_usec - info->last_tx_active_usec; - - /* - * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO - * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k) - */ - orig_jiffies = jiffies; - while (info->xmit.head != info->xmit.tail || /* More in send queue */ - (*info->ostatusadr & 0x007f) || /* more in FIFO */ - (elapsed_usec < 2*info->char_time_usec)) { - schedule_timeout_interruptible(1); - if (signal_pending(current)) - break; - if (timeout && time_after(jiffies, orig_jiffies + timeout)) - break; - curr_time = jiffies; - curr_time_usec = GET_JIFFIES_USEC(); - elapsed_usec = - (curr_time - info->last_tx_active) * (1000000/HZ) + - curr_time_usec - info->last_tx_active_usec; - } - set_current_state(TASK_RUNNING); -} - -/* - * rs_hangup() --- called by tty_hangup() when a hangup is signaled. - */ -void -rs_hangup(struct tty_struct *tty) -{ - struct e100_serial * info = (struct e100_serial *)tty->driver_data; - - rs_flush_buffer(tty); - shutdown(info); - info->event = 0; - info->port.count = 0; - tty_port_set_active(&info->port, 0); - info->port.tty = NULL; - wake_up_interruptible(&info->port.open_wait); -} - -/* - * ------------------------------------------------------------ - * rs_open() and friends - * ------------------------------------------------------------ - */ -static int -block_til_ready(struct tty_struct *tty, struct file * filp, - struct e100_serial *info) -{ - DECLARE_WAITQUEUE(wait, current); - unsigned long flags; - int retval; - int do_clocal = 0; - - /* - * If non-blocking mode is set, or the port is not enabled, - * then make the check up front and then exit. - */ - if ((filp->f_flags & O_NONBLOCK) || tty_io_error(tty)) { - tty_port_set_active(&info->port, 1); - return 0; - } - - if (C_CLOCAL(tty)) - do_clocal = 1; - - /* - * Block waiting for the carrier detect and the line to become - * free (i.e., not in use by the callout). While we are in - * this loop, info->port.count is dropped by one, so that - * rs_close() knows when to free things. We restore it upon - * exit, either normal or abnormal. - */ - retval = 0; - add_wait_queue(&info->port.open_wait, &wait); -#ifdef SERIAL_DEBUG_OPEN - printk("block_til_ready before block: ttyS%d, count = %d\n", - info->line, info->port.count); -#endif - local_irq_save(flags); - info->port.count--; - local_irq_restore(flags); - info->port.blocked_open++; - while (1) { - local_irq_save(flags); - /* assert RTS and DTR */ - e100_rts(info, 1); - e100_dtr(info, 1); - local_irq_restore(flags); - set_current_state(TASK_INTERRUPTIBLE); - if (tty_hung_up_p(filp) || !tty_port_initialized(&info->port)) { -#ifdef SERIAL_DO_RESTART - if (info->port.flags & ASYNC_HUP_NOTIFY) - retval = -EAGAIN; - else - retval = -ERESTARTSYS; -#else - retval = -EAGAIN; -#endif - break; - } - if (do_clocal) - /* && (do_clocal || DCD_IS_ASSERTED) */ - break; - if (signal_pending(current)) { - retval = -ERESTARTSYS; - break; - } -#ifdef SERIAL_DEBUG_OPEN - printk("block_til_ready blocking: ttyS%d, count = %d\n", - info->line, info->port.count); -#endif - tty_unlock(tty); - schedule(); - tty_lock(tty); - } - set_current_state(TASK_RUNNING); - remove_wait_queue(&info->port.open_wait, &wait); - if (!tty_hung_up_p(filp)) - info->port.count++; - info->port.blocked_open--; -#ifdef SERIAL_DEBUG_OPEN - printk("block_til_ready after blocking: ttyS%d, count = %d\n", - info->line, info->port.count); -#endif - if (retval) - return retval; - tty_port_set_active(&info->port, 1); - return 0; -} - -static void -deinit_port(struct e100_serial *info) -{ - if (info->dma_out_enabled) { - cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description); - free_irq(info->dma_out_irq_nbr, info); - } - if (info->dma_in_enabled) { - cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description); - free_irq(info->dma_in_irq_nbr, info); - } -} - -/* - * This routine is called whenever a serial port is opened. - * It performs the serial-specific initialization for the tty structure. - */ -static int -rs_open(struct tty_struct *tty, struct file * filp) -{ - struct e100_serial *info; - int retval; - int allocated_resources = 0; - - info = rs_table + tty->index; - if (!info->enabled) - return -ENODEV; - -#ifdef SERIAL_DEBUG_OPEN - printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name, - info->port.count); -#endif - - info->port.count++; - tty->driver_data = info; - info->port.tty = tty; - - info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY); - - /* - * If DMA is enabled try to allocate the irq's. - */ - if (info->port.count == 1) { - allocated_resources = 1; - if (info->dma_in_enabled) { - if (request_irq(info->dma_in_irq_nbr, - rec_interrupt, - info->dma_in_irq_flags, - info->dma_in_irq_description, - info)) { - printk(KERN_WARNING "DMA irq '%s' busy; " - "falling back to non-DMA mode\n", - info->dma_in_irq_description); - /* Make sure we never try to use DMA in */ - /* for the port again. */ - info->dma_in_enabled = 0; - } else if (cris_request_dma(info->dma_in_nbr, - info->dma_in_irq_description, - DMA_VERBOSE_ON_ERROR, - info->dma_owner)) { - free_irq(info->dma_in_irq_nbr, info); - printk(KERN_WARNING "DMA '%s' busy; " - "falling back to non-DMA mode\n", - info->dma_in_irq_description); - /* Make sure we never try to use DMA in */ - /* for the port again. */ - info->dma_in_enabled = 0; - } -#ifdef SERIAL_DEBUG_OPEN - else - printk(KERN_DEBUG "DMA irq '%s' allocated\n", - info->dma_in_irq_description); -#endif - } - if (info->dma_out_enabled) { - if (request_irq(info->dma_out_irq_nbr, - tr_interrupt, - info->dma_out_irq_flags, - info->dma_out_irq_description, - info)) { - printk(KERN_WARNING "DMA irq '%s' busy; " - "falling back to non-DMA mode\n", - info->dma_out_irq_description); - /* Make sure we never try to use DMA out */ - /* for the port again. */ - info->dma_out_enabled = 0; - } else if (cris_request_dma(info->dma_out_nbr, - info->dma_out_irq_description, - DMA_VERBOSE_ON_ERROR, - info->dma_owner)) { - free_irq(info->dma_out_irq_nbr, info); - printk(KERN_WARNING "DMA '%s' busy; " - "falling back to non-DMA mode\n", - info->dma_out_irq_description); - /* Make sure we never try to use DMA out */ - /* for the port again. */ - info->dma_out_enabled = 0; - } -#ifdef SERIAL_DEBUG_OPEN - else - printk(KERN_DEBUG "DMA irq '%s' allocated\n", - info->dma_out_irq_description); -#endif - } - } - - /* - * Start up the serial port - */ - - retval = startup(info); - if (retval) { - if (allocated_resources) - deinit_port(info); - - /* FIXME Decrease count info->port.count here too? */ - return retval; - } - - - retval = block_til_ready(tty, filp, info); - if (retval) { -#ifdef SERIAL_DEBUG_OPEN - printk("rs_open returning after block_til_ready with %d\n", - retval); -#endif - if (allocated_resources) - deinit_port(info); - - return retval; - } - -#ifdef SERIAL_DEBUG_OPEN - printk("rs_open ttyS%d successful...\n", info->line); -#endif - DLOG_INT_TRIG( log_int_pos = 0); - - DFLIP( if (info->line == SERIAL_DEBUG_LINE) { - info->icount.rx = 0; - } ); - - return 0; -} - -#ifdef CONFIG_PROC_FS -/* - * /proc fs routines.... - */ - -static void seq_line_info(struct seq_file *m, struct e100_serial *info) -{ - unsigned long tmp; - - seq_printf(m, "%d: uart:E100 port:%lX irq:%d", - info->line, (unsigned long)info->ioport, info->irq); - - if (!info->ioport || (info->type == PORT_UNKNOWN)) { - seq_printf(m, "\n"); - return; - } - - seq_printf(m, " baud:%d", info->baud); - seq_printf(m, " tx:%lu rx:%lu", - (unsigned long)info->icount.tx, - (unsigned long)info->icount.rx); - tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); - if (tmp) - seq_printf(m, " tx_pend:%lu/%lu", - (unsigned long)tmp, - (unsigned long)SERIAL_XMIT_SIZE); - - seq_printf(m, " rx_pend:%lu/%lu", - (unsigned long)info->recv_cnt, - (unsigned long)info->max_recv_cnt); - -#if 1 - if (info->port.tty) { - if (info->port.tty->stopped) - seq_printf(m, " stopped:%i", - (int)info->port.tty->stopped); - } - - { - unsigned char rstat = info->ioport[REG_STATUS]; - if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect)) - seq_printf(m, " xoff_detect:1"); - } - -#endif - - if (info->icount.frame) - seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame); - - if (info->icount.parity) - seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity); - - if (info->icount.brk) - seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk); - - if (info->icount.overrun) - seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun); - - /* - * Last thing is the RS-232 status lines - */ - if (!E100_RTS_GET(info)) - seq_puts(m, "|RTS"); - if (!E100_CTS_GET(info)) - seq_puts(m, "|CTS"); - if (!E100_DTR_GET(info)) - seq_puts(m, "|DTR"); - if (!E100_DSR_GET(info)) - seq_puts(m, "|DSR"); - if (!E100_CD_GET(info)) - seq_puts(m, "|CD"); - if (!E100_RI_GET(info)) - seq_puts(m, "|RI"); - seq_puts(m, "\n"); -} - - -static int crisv10_proc_show(struct seq_file *m, void *v) -{ - int i; - - seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version); - - for (i = 0; i < NR_PORTS; i++) { - if (!rs_table[i].enabled) - continue; - seq_line_info(m, &rs_table[i]); - } -#ifdef DEBUG_LOG_INCLUDED - for (i = 0; i < debug_log_pos; i++) { - seq_printf(m, "%-4i %lu.%lu ", - i, debug_log[i].time, - timer_data_to_ns(debug_log[i].timer_data)); - seq_printf(m, debug_log[i].string, debug_log[i].value); - } - seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE); - debug_log_pos = 0; -#endif - return 0; -} - -static int crisv10_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, crisv10_proc_show, NULL); -} - -static const struct file_operations crisv10_proc_fops = { - .owner = THIS_MODULE, - .open = crisv10_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - - -/* Finally, routines used to initialize the serial driver. */ - -static void show_serial_version(void) -{ - printk(KERN_INFO - "ETRAX 100LX serial-driver %s, " - "(c) 2000-2004 Axis Communications AB\r\n", - &serial_version[11]); /* "$Revision: x.yy" */ -} - -/* rs_init inits the driver at boot (using the initcall chain) */ - -static const struct tty_operations rs_ops = { - .open = rs_open, - .close = rs_close, - .write = rs_write, - .flush_chars = rs_flush_chars, - .write_room = rs_write_room, - .chars_in_buffer = rs_chars_in_buffer, - .flush_buffer = rs_flush_buffer, - .ioctl = rs_ioctl, - .throttle = rs_throttle, - .unthrottle = rs_unthrottle, - .set_termios = rs_set_termios, - .stop = rs_stop, - .start = rs_start, - .hangup = rs_hangup, - .break_ctl = rs_break, - .send_xchar = rs_send_xchar, - .wait_until_sent = rs_wait_until_sent, - .tiocmget = rs_tiocmget, - .tiocmset = rs_tiocmset, -#ifdef CONFIG_PROC_FS - .proc_fops = &crisv10_proc_fops, -#endif -}; - -static int __init rs_init(void) -{ - int i; - struct e100_serial *info; - struct tty_driver *driver = alloc_tty_driver(NR_PORTS); - - if (!driver) - return -ENOMEM; - - show_serial_version(); - - /* Setup the timed flush handler system */ - -#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER) - timer_setup(&flush_timer, timed_flush_handler, 0); - mod_timer(&flush_timer, jiffies + 5); -#endif - -#if defined(CONFIG_ETRAX_RS485) -#if defined(CONFIG_ETRAX_RS485_ON_PA) - if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit, - rs485_pa_bit)) { - printk(KERN_ERR "ETRAX100LX serial: Could not allocate " - "RS485 pin\n"); - put_tty_driver(driver); - return -EBUSY; - } -#endif -#endif - - /* Initialize the tty_driver structure */ - - driver->driver_name = "serial"; - driver->name = "ttyS"; - driver->major = TTY_MAJOR; - driver->minor_start = 64; - driver->type = TTY_DRIVER_TYPE_SERIAL; - driver->subtype = SERIAL_TYPE_NORMAL; - driver->init_termios = tty_std_termios; - driver->init_termios.c_cflag = - B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */ - driver->init_termios.c_ispeed = 115200; - driver->init_termios.c_ospeed = 115200; - driver->flags = TTY_DRIVER_REAL_RAW; - - tty_set_operations(driver, &rs_ops); - serial_driver = driver; - - /* do some initializing for the separate ports */ - for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) { - if (info->enabled) { - if (cris_request_io_interface(info->io_if, - info->io_if_description)) { - printk(KERN_ERR "ETRAX100LX async serial: " - "Could not allocate IO pins for " - "%s, port %d\n", - info->io_if_description, i); - info->enabled = 0; - } - } - tty_port_init(&info->port); - info->uses_dma_in = 0; - info->uses_dma_out = 0; - info->line = i; - info->port.tty = NULL; - info->type = PORT_ETRAX; - info->tr_running = 0; - info->forced_eop = 0; - info->baud_base = DEF_BAUD_BASE; - info->custom_divisor = 0; - info->x_char = 0; - info->event = 0; - info->xmit.buf = NULL; - info->xmit.tail = info->xmit.head = 0; - info->first_recv_buffer = info->last_recv_buffer = NULL; - info->recv_cnt = info->max_recv_cnt = 0; - info->last_tx_active_usec = 0; - info->last_tx_active = 0; - -#if defined(CONFIG_ETRAX_RS485) - /* Set sane defaults */ - info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND); - info->rs485.flags |= SER_RS485_RTS_AFTER_SEND; - info->rs485.delay_rts_before_send = 0; - info->rs485.flags &= ~(SER_RS485_ENABLED); -#endif - INIT_WORK(&info->work, do_softint); - - if (info->enabled) { - printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n", - serial_driver->name, info->line, info->ioport); - } - tty_port_link_device(&info->port, driver, i); - } - - if (tty_register_driver(driver)) - panic("Couldn't register serial driver\n"); - -#ifdef CONFIG_ETRAX_FAST_TIMER -#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER - memset(fast_timers, 0, sizeof(fast_timers)); -#endif -#ifdef CONFIG_ETRAX_RS485 - memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485)); -#endif - fast_timer_init(); -#endif - -#ifndef CONFIG_ETRAX_KGDB - /* Not needed in simulator. May only complicate stuff. */ - /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */ - - if (request_irq(SERIAL_IRQ_NBR, ser_interrupt, - IRQF_SHARED, "serial ", driver)) - panic("%s: Failed to request irq8", __func__); - -#endif - - return 0; -} - -/* this makes sure that rs_init is called during kernel boot */ -device_initcall(rs_init); diff --git a/drivers/tty/serial/crisv10.h b/drivers/tty/serial/crisv10.h deleted file mode 100644 index 79ba2bc95d3d..000000000000 --- a/drivers/tty/serial/crisv10.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * serial.h: Arch-dep definitions for the Etrax100 serial driver. - * - * Copyright (C) 1998-2007 Axis Communications AB - */ - -#ifndef _ETRAX_SERIAL_H -#define _ETRAX_SERIAL_H - -#include -#include -#include -#include - -/* Software state per channel */ - -#ifdef __KERNEL__ -/* - * This is our internal structure for each serial port's state. - * - * Many fields are paralleled by the structure used by the serial_struct - * structure. - * - * For definitions of the flags field, see tty.h - */ - -#define SERIAL_RECV_DESCRIPTORS 8 - -struct etrax_recv_buffer { - struct etrax_recv_buffer *next; - unsigned short length; - unsigned char error; - unsigned char pad; - - unsigned char buffer[0]; -}; - -struct e100_serial { - struct tty_port port; - int baud; - volatile u8 *ioport; /* R_SERIALx_CTRL */ - u32 irq; /* bitnr in R_IRQ_MASK2 for dmaX_descr */ - - /* Output registers */ - volatile u8 *oclrintradr; /* adr to R_DMA_CHx_CLR_INTR */ - volatile u32 *ofirstadr; /* adr to R_DMA_CHx_FIRST */ - volatile u8 *ocmdadr; /* adr to R_DMA_CHx_CMD */ - const volatile u8 *ostatusadr; /* adr to R_DMA_CHx_STATUS */ - - /* Input registers */ - volatile u8 *iclrintradr; /* adr to R_DMA_CHx_CLR_INTR */ - volatile u32 *ifirstadr; /* adr to R_DMA_CHx_FIRST */ - volatile u8 *icmdadr; /* adr to R_DMA_CHx_CMD */ - volatile u32 *idescradr; /* adr to R_DMA_CHx_DESCR */ - - u8 rx_ctrl; /* shadow for R_SERIALx_REC_CTRL */ - u8 tx_ctrl; /* shadow for R_SERIALx_TR_CTRL */ - u8 iseteop; /* bit number for R_SET_EOP for the input dma */ - int enabled; /* Set to 1 if the port is enabled in HW config */ - - u8 dma_out_enabled; /* Set to 1 if DMA should be used */ - u8 dma_in_enabled; /* Set to 1 if DMA should be used */ - - /* end of fields defined in rs_table[] in .c-file */ - int dma_owner; - unsigned int dma_in_nbr; - unsigned int dma_out_nbr; - unsigned int dma_in_irq_nbr; - unsigned int dma_out_irq_nbr; - unsigned long dma_in_irq_flags; - unsigned long dma_out_irq_flags; - char *dma_in_irq_description; - char *dma_out_irq_description; - - enum cris_io_interface io_if; - char *io_if_description; - - u8 uses_dma_in; /* Set to 1 if DMA is used */ - u8 uses_dma_out; /* Set to 1 if DMA is used */ - u8 forced_eop; /* a fifo eop has been forced */ - int baud_base; /* For special baudrates */ - int custom_divisor; /* For special baudrates */ - struct etrax_dma_descr tr_descr; - struct etrax_dma_descr rec_descr[SERIAL_RECV_DESCRIPTORS]; - int cur_rec_descr; - - volatile int tr_running; /* 1 if output is running */ - - int x_char; /* xon/xoff character */ - unsigned long event; - int line; - int type; /* PORT_ETRAX */ - struct circ_buf xmit; - struct etrax_recv_buffer *first_recv_buffer; - struct etrax_recv_buffer *last_recv_buffer; - unsigned int recv_cnt; - unsigned int max_recv_cnt; - - struct work_struct work; - struct async_icount icount; /* error-statistics etc.*/ - - unsigned long char_time_usec; /* The time for 1 char, in usecs */ - unsigned long flush_time_usec; /* How often we should flush */ - unsigned long last_tx_active_usec; /* Last tx usec in the jiffies */ - unsigned long last_tx_active; /* Last tx time in jiffies */ - unsigned long last_rx_active_usec; /* Last rx usec in the jiffies */ - unsigned long last_rx_active; /* Last rx time in jiffies */ - - int break_detected_cnt; - int errorcode; - -#ifdef CONFIG_ETRAX_RS485 - struct serial_rs485 rs485; /* RS-485 support */ -#endif -}; - -/* this PORT is not in the standard serial.h. it's not actually used for - * anything since we only have one type of async serial-port anyway in this - * system. - */ - -#define PORT_ETRAX 1 - -/* - * Events are used to schedule things to happen at timer-interrupt - * time, instead of at rs interrupt time. - */ -#define RS_EVENT_WRITE_WAKEUP 0 - -#endif /* __KERNEL__ */ - -#endif /* !_ETRAX_SERIAL_H */ diff --git a/drivers/tty/serial/etraxfs-uart.c b/drivers/tty/serial/etraxfs-uart.c deleted file mode 100644 index 24bf6bfb29b4..000000000000 --- a/drivers/tty/serial/etraxfs-uart.c +++ /dev/null @@ -1,960 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "serial_mctrl_gpio.h" - -#define DRV_NAME "etraxfs-uart" -#define UART_NR CONFIG_ETRAX_SERIAL_PORTS - -#define MODIFY_REG(instance, reg, var) \ - do { \ - if (REG_RD_INT(ser, instance, reg) != \ - REG_TYPE_CONV(int, reg_ser_##reg, var)) \ - REG_WR(ser, instance, reg, var); \ - } while (0) - -struct uart_cris_port { - struct uart_port port; - - int initialized; - int irq; - - void __iomem *regi_ser; - - struct mctrl_gpios *gpios; - - int write_ongoing; -}; - -static struct uart_driver etraxfs_uart_driver; -static struct uart_port *console_port; -static int console_baud = 115200; -static struct uart_cris_port *etraxfs_uart_ports[UART_NR]; - -static void cris_serial_port_init(struct uart_port *port, int line); -static void etraxfs_uart_stop_rx(struct uart_port *port); -static inline void etraxfs_uart_start_tx_bottom(struct uart_port *port); - -#ifdef CONFIG_SERIAL_ETRAXFS_CONSOLE -static void -cris_console_write(struct console *co, const char *s, unsigned int count) -{ - struct uart_cris_port *up; - int i; - reg_ser_r_stat_din stat; - reg_ser_rw_tr_dma_en tr_dma_en, old; - - up = etraxfs_uart_ports[co->index]; - - if (!up) - return; - - /* Switch to manual mode. */ - tr_dma_en = old = REG_RD(ser, up->regi_ser, rw_tr_dma_en); - if (tr_dma_en.en == regk_ser_yes) { - tr_dma_en.en = regk_ser_no; - REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en); - } - - /* Send data. */ - for (i = 0; i < count; i++) { - /* LF -> CRLF */ - if (s[i] == '\n') { - do { - stat = REG_RD(ser, up->regi_ser, r_stat_din); - } while (!stat.tr_rdy); - REG_WR_INT(ser, up->regi_ser, rw_dout, '\r'); - } - /* Wait until transmitter is ready and send. */ - do { - stat = REG_RD(ser, up->regi_ser, r_stat_din); - } while (!stat.tr_rdy); - REG_WR_INT(ser, up->regi_ser, rw_dout, s[i]); - } - - /* Restore mode. */ - if (tr_dma_en.en != old.en) - REG_WR(ser, up->regi_ser, rw_tr_dma_en, old); -} - -static int __init -cris_console_setup(struct console *co, char *options) -{ - struct uart_port *port; - int baud = 115200; - int bits = 8; - int parity = 'n'; - int flow = 'n'; - - if (co->index < 0 || co->index >= UART_NR) - co->index = 0; - port = &etraxfs_uart_ports[co->index]->port; - console_port = port; - - co->flags |= CON_CONSDEV; - - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); - console_baud = baud; - cris_serial_port_init(port, co->index); - uart_set_options(port, co, baud, parity, bits, flow); - - return 0; -} - -static struct console cris_console = { - .name = "ttyS", - .write = cris_console_write, - .device = uart_console_device, - .setup = cris_console_setup, - .flags = CON_PRINTBUFFER, - .index = -1, - .data = &etraxfs_uart_driver, -}; -#endif /* CONFIG_SERIAL_ETRAXFS_CONSOLE */ - -static struct uart_driver etraxfs_uart_driver = { - .owner = THIS_MODULE, - .driver_name = "serial", - .dev_name = "ttyS", - .major = TTY_MAJOR, - .minor = 64, - .nr = UART_NR, -#ifdef CONFIG_SERIAL_ETRAXFS_CONSOLE - .cons = &cris_console, -#endif /* CONFIG_SERIAL_ETRAXFS_CONSOLE */ -}; - -static inline int crisv32_serial_get_rts(struct uart_cris_port *up) -{ - void __iomem *regi_ser = up->regi_ser; - /* - * Return what the user has controlled rts to or - * what the pin is? (if auto_rts is used it differs during tx) - */ - reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din); - - return !(rstat.rts_n == regk_ser_active); -} - -/* - * A set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive - * 0=0V , 1=3.3V - */ -static inline void crisv32_serial_set_rts(struct uart_cris_port *up, - int set, int force) -{ - void __iomem *regi_ser = up->regi_ser; - - unsigned long flags; - reg_ser_rw_rec_ctrl rec_ctrl; - - local_irq_save(flags); - rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); - - if (set) - rec_ctrl.rts_n = regk_ser_active; - else - rec_ctrl.rts_n = regk_ser_inactive; - REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); - local_irq_restore(flags); -} - -static inline int crisv32_serial_get_cts(struct uart_cris_port *up) -{ - void __iomem *regi_ser = up->regi_ser; - reg_ser_r_stat_din rstat = REG_RD(ser, regi_ser, r_stat_din); - - return (rstat.cts_n == regk_ser_active); -} - -/* - * Send a single character for XON/XOFF purposes. We do it in this separate - * function instead of the alternative support port.x_char, in the ...start_tx - * function, so we don't mix up this case with possibly enabling transmission - * of queued-up data (in case that's disabled after *receiving* an XOFF or - * negative CTS). This function is used for both DMA and non-DMA case; see HW - * docs specifically blessing sending characters manually when DMA for - * transmission is enabled and running. We may be asked to transmit despite - * the transmitter being disabled by a ..._stop_tx call so we need to enable - * it temporarily but restore the state afterwards. - */ -static void etraxfs_uart_send_xchar(struct uart_port *port, char ch) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - reg_ser_rw_dout dout = { .data = ch }; - reg_ser_rw_ack_intr ack_intr = { .tr_rdy = regk_ser_yes }; - reg_ser_r_stat_din rstat; - reg_ser_rw_tr_ctrl prev_tr_ctrl, tr_ctrl; - void __iomem *regi_ser = up->regi_ser; - unsigned long flags; - - /* - * Wait for tr_rdy in case a character is already being output. Make - * sure we have integrity between the register reads and the writes - * below, but don't busy-wait with interrupts off and the port lock - * taken. - */ - spin_lock_irqsave(&port->lock, flags); - do { - spin_unlock_irqrestore(&port->lock, flags); - spin_lock_irqsave(&port->lock, flags); - prev_tr_ctrl = tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); - rstat = REG_RD(ser, regi_ser, r_stat_din); - } while (!rstat.tr_rdy); - - /* - * Ack an interrupt if one was just issued for the previous character - * that was output. This is required for non-DMA as the interrupt is - * used as the only indicator that the transmitter is ready and it - * isn't while this x_char is being transmitted. - */ - REG_WR(ser, regi_ser, rw_ack_intr, ack_intr); - - /* Enable the transmitter in case it was disabled. */ - tr_ctrl.stop = 0; - REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); - - /* - * Finally, send the blessed character; nothing should stop it now, - * except for an xoff-detected state, which we'll handle below. - */ - REG_WR(ser, regi_ser, rw_dout, dout); - up->port.icount.tx++; - - /* There might be an xoff state to clear. */ - rstat = REG_RD(ser, up->regi_ser, r_stat_din); - - /* - * Clear any xoff state that *may* have been there to - * inhibit transmission of the character. - */ - if (rstat.xoff_detect) { - reg_ser_rw_xoff_clr xoff_clr = { .clr = 1 }; - reg_ser_rw_tr_dma_en tr_dma_en; - - REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr); - tr_dma_en = REG_RD(ser, regi_ser, rw_tr_dma_en); - - /* - * If we had an xoff state but cleared it, instead sneak in a - * disabled state for the transmitter, after the character we - * sent. Thus we keep the port disabled, just as if the xoff - * state was still in effect (or actually, as if stop_tx had - * been called, as we stop DMA too). - */ - prev_tr_ctrl.stop = 1; - - tr_dma_en.en = 0; - REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en); - } - - /* Restore "previous" enabled/disabled state of the transmitter. */ - REG_WR(ser, regi_ser, rw_tr_ctrl, prev_tr_ctrl); - - spin_unlock_irqrestore(&port->lock, flags); -} - -/* - * Do not spin_lock_irqsave or disable interrupts by other means here; it's - * already done by the caller. - */ -static void etraxfs_uart_start_tx(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - - /* we have already done below if a write is ongoing */ - if (up->write_ongoing) - return; - - /* Signal that write is ongoing */ - up->write_ongoing = 1; - - etraxfs_uart_start_tx_bottom(port); -} - -static inline void etraxfs_uart_start_tx_bottom(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - void __iomem *regi_ser = up->regi_ser; - reg_ser_rw_tr_ctrl tr_ctrl; - reg_ser_rw_intr_mask intr_mask; - - tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); - tr_ctrl.stop = regk_ser_no; - REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); - intr_mask = REG_RD(ser, regi_ser, rw_intr_mask); - intr_mask.tr_rdy = regk_ser_yes; - REG_WR(ser, regi_ser, rw_intr_mask, intr_mask); -} - -/* - * This function handles both the DMA and non-DMA case by ordering the - * transmitter to stop of after the current character. We don't need to wait - * for any such character to be completely transmitted; we do that where it - * matters, like in etraxfs_uart_set_termios. Don't busy-wait here; see - * Documentation/serial/driver: this function is called within - * spin_lock_irq{,save} and thus separate ones would be disastrous (when SMP). - * There's no documented need to set the txd pin to any particular value; - * break setting is controlled solely by etraxfs_uart_break_ctl. - */ -static void etraxfs_uart_stop_tx(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - void __iomem *regi_ser = up->regi_ser; - reg_ser_rw_tr_ctrl tr_ctrl; - reg_ser_rw_intr_mask intr_mask; - reg_ser_rw_tr_dma_en tr_dma_en = {0}; - reg_ser_rw_xoff_clr xoff_clr = {0}; - - /* - * For the non-DMA case, we'd get a tr_rdy interrupt that we're not - * interested in as we're not transmitting any characters. For the - * DMA case, that interrupt is already turned off, but no reason to - * waste code on conditionals here. - */ - intr_mask = REG_RD(ser, regi_ser, rw_intr_mask); - intr_mask.tr_rdy = regk_ser_no; - REG_WR(ser, regi_ser, rw_intr_mask, intr_mask); - - tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl); - tr_ctrl.stop = 1; - REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); - - /* - * Always clear possible hardware xoff-detected state here, no need to - * unnecessary consider mctrl settings and when they change. We clear - * it here rather than in start_tx: both functions are called as the - * effect of XOFF processing, but start_tx is also called when upper - * levels tell the driver that there are more characters to send, so - * avoid adding code there. - */ - xoff_clr.clr = 1; - REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr); - - /* - * Disable transmitter DMA, so that if we're in XON/XOFF, we can send - * those single characters without also giving go-ahead for queued up - * DMA data. - */ - tr_dma_en.en = 0; - REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en); - - /* - * Make sure that write_ongoing is reset when stopping tx. - */ - up->write_ongoing = 0; -} - -static void etraxfs_uart_stop_rx(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - void __iomem *regi_ser = up->regi_ser; - reg_ser_rw_rec_ctrl rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl); - - rec_ctrl.en = regk_ser_no; - REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); -} - -static unsigned int etraxfs_uart_tx_empty(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - unsigned long flags; - unsigned int ret; - reg_ser_r_stat_din rstat = {0}; - - spin_lock_irqsave(&up->port.lock, flags); - - rstat = REG_RD(ser, up->regi_ser, r_stat_din); - ret = rstat.tr_empty ? TIOCSER_TEMT : 0; - - spin_unlock_irqrestore(&up->port.lock, flags); - return ret; -} -static unsigned int etraxfs_uart_get_mctrl(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - unsigned int ret; - - ret = 0; - if (crisv32_serial_get_rts(up)) - ret |= TIOCM_RTS; - if (crisv32_serial_get_cts(up)) - ret |= TIOCM_CTS; - return mctrl_gpio_get(up->gpios, &ret); -} - -static void etraxfs_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - - crisv32_serial_set_rts(up, mctrl & TIOCM_RTS ? 1 : 0, 0); - mctrl_gpio_set(up->gpios, mctrl); -} - -static void etraxfs_uart_break_ctl(struct uart_port *port, int break_state) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - unsigned long flags; - reg_ser_rw_tr_ctrl tr_ctrl; - reg_ser_rw_tr_dma_en tr_dma_en; - reg_ser_rw_intr_mask intr_mask; - - spin_lock_irqsave(&up->port.lock, flags); - tr_ctrl = REG_RD(ser, up->regi_ser, rw_tr_ctrl); - tr_dma_en = REG_RD(ser, up->regi_ser, rw_tr_dma_en); - intr_mask = REG_RD(ser, up->regi_ser, rw_intr_mask); - - if (break_state != 0) { /* Send break */ - /* - * We need to disable DMA (if used) or tr_rdy interrupts if no - * DMA. No need to make this conditional on use of DMA; - * disabling will be a no-op for the other mode. - */ - intr_mask.tr_rdy = regk_ser_no; - tr_dma_en.en = 0; - - /* - * Stop transmission and set the txd pin to 0 after the - * current character. The txd setting will take effect after - * any current transmission has completed. - */ - tr_ctrl.stop = 1; - tr_ctrl.txd = 0; - } else { - /* Re-enable the serial interrupt. */ - intr_mask.tr_rdy = regk_ser_yes; - - tr_ctrl.stop = 0; - tr_ctrl.txd = 1; - } - REG_WR(ser, up->regi_ser, rw_tr_ctrl, tr_ctrl); - REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en); - REG_WR(ser, up->regi_ser, rw_intr_mask, intr_mask); - - spin_unlock_irqrestore(&up->port.lock, flags); -} - -static void -transmit_chars_no_dma(struct uart_cris_port *up) -{ - int max_count; - struct circ_buf *xmit = &up->port.state->xmit; - - void __iomem *regi_ser = up->regi_ser; - reg_ser_r_stat_din rstat; - reg_ser_rw_ack_intr ack_intr = { .tr_rdy = regk_ser_yes }; - - if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { - /* No more to send, so disable the interrupt. */ - reg_ser_rw_intr_mask intr_mask; - - intr_mask = REG_RD(ser, regi_ser, rw_intr_mask); - intr_mask.tr_rdy = 0; - intr_mask.tr_empty = 0; - REG_WR(ser, regi_ser, rw_intr_mask, intr_mask); - up->write_ongoing = 0; - return; - } - - /* If the serport is fast, we send up to max_count bytes before - exiting the loop. */ - max_count = 64; - do { - reg_ser_rw_dout dout = { .data = xmit->buf[xmit->tail] }; - - REG_WR(ser, regi_ser, rw_dout, dout); - REG_WR(ser, regi_ser, rw_ack_intr, ack_intr); - xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); - up->port.icount.tx++; - if (xmit->head == xmit->tail) - break; - rstat = REG_RD(ser, regi_ser, r_stat_din); - } while ((--max_count > 0) && rstat.tr_rdy); - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(&up->port); -} - -static void receive_chars_no_dma(struct uart_cris_port *up) -{ - reg_ser_rs_stat_din stat_din; - reg_ser_r_stat_din rstat; - struct tty_port *port; - struct uart_icount *icount; - int max_count = 16; - char flag; - reg_ser_rw_ack_intr ack_intr = { 0 }; - - rstat = REG_RD(ser, up->regi_ser, r_stat_din); - icount = &up->port.icount; - port = &up->port.state->port; - - do { - stat_din = REG_RD(ser, up->regi_ser, rs_stat_din); - - flag = TTY_NORMAL; - ack_intr.dav = 1; - REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr); - icount->rx++; - - if (stat_din.framing_err | stat_din.par_err | stat_din.orun) { - if (stat_din.data == 0x00 && - stat_din.framing_err) { - /* Most likely a break. */ - flag = TTY_BREAK; - icount->brk++; - } else if (stat_din.par_err) { - flag = TTY_PARITY; - icount->parity++; - } else if (stat_din.orun) { - flag = TTY_OVERRUN; - icount->overrun++; - } else if (stat_din.framing_err) { - flag = TTY_FRAME; - icount->frame++; - } - } - - /* - * If this becomes important, we probably *could* handle this - * gracefully by keeping track of the unhandled character. - */ - if (!tty_insert_flip_char(port, stat_din.data, flag)) - panic("%s: No tty buffer space", __func__); - rstat = REG_RD(ser, up->regi_ser, r_stat_din); - } while (rstat.dav && (max_count-- > 0)); - spin_unlock(&up->port.lock); - tty_flip_buffer_push(port); - spin_lock(&up->port.lock); -} - -static irqreturn_t -ser_interrupt(int irq, void *dev_id) -{ - struct uart_cris_port *up = (struct uart_cris_port *)dev_id; - void __iomem *regi_ser; - int handled = 0; - - spin_lock(&up->port.lock); - - regi_ser = up->regi_ser; - - if (regi_ser) { - reg_ser_r_masked_intr masked_intr; - - masked_intr = REG_RD(ser, regi_ser, r_masked_intr); - /* - * Check what interrupts are active before taking - * actions. If DMA is used the interrupt shouldn't - * be enabled. - */ - if (masked_intr.dav) { - receive_chars_no_dma(up); - handled = 1; - } - - if (masked_intr.tr_rdy) { - transmit_chars_no_dma(up); - handled = 1; - } - } - spin_unlock(&up->port.lock); - return IRQ_RETVAL(handled); -} - -#ifdef CONFIG_CONSOLE_POLL -static int etraxfs_uart_get_poll_char(struct uart_port *port) -{ - reg_ser_rs_stat_din stat; - reg_ser_rw_ack_intr ack_intr = { 0 }; - struct uart_cris_port *up = (struct uart_cris_port *)port; - - do { - stat = REG_RD(ser, up->regi_ser, rs_stat_din); - } while (!stat.dav); - - /* Ack the data_avail interrupt. */ - ack_intr.dav = 1; - REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr); - - return stat.data; -} - -static void etraxfs_uart_put_poll_char(struct uart_port *port, - unsigned char c) -{ - reg_ser_r_stat_din stat; - struct uart_cris_port *up = (struct uart_cris_port *)port; - - do { - stat = REG_RD(ser, up->regi_ser, r_stat_din); - } while (!stat.tr_rdy); - REG_WR_INT(ser, up->regi_ser, rw_dout, c); -} -#endif /* CONFIG_CONSOLE_POLL */ - -static int etraxfs_uart_startup(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - unsigned long flags; - reg_ser_rw_intr_mask ser_intr_mask = {0}; - - ser_intr_mask.dav = regk_ser_yes; - - if (request_irq(etraxfs_uart_ports[port->line]->irq, ser_interrupt, - 0, DRV_NAME, etraxfs_uart_ports[port->line])) - panic("irq ser%d", port->line); - - spin_lock_irqsave(&up->port.lock, flags); - - REG_WR(ser, up->regi_ser, rw_intr_mask, ser_intr_mask); - - etraxfs_uart_set_mctrl(&up->port, up->port.mctrl); - - spin_unlock_irqrestore(&up->port.lock, flags); - - return 0; -} - -static void etraxfs_uart_shutdown(struct uart_port *port) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - unsigned long flags; - - spin_lock_irqsave(&up->port.lock, flags); - - etraxfs_uart_stop_tx(port); - etraxfs_uart_stop_rx(port); - - free_irq(etraxfs_uart_ports[port->line]->irq, - etraxfs_uart_ports[port->line]); - - etraxfs_uart_set_mctrl(&up->port, up->port.mctrl); - - spin_unlock_irqrestore(&up->port.lock, flags); - -} - -static void -etraxfs_uart_set_termios(struct uart_port *port, struct ktermios *termios, - struct ktermios *old) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - unsigned long flags; - reg_ser_rw_xoff xoff; - reg_ser_rw_xoff_clr xoff_clr = {0}; - reg_ser_rw_tr_ctrl tx_ctrl = {0}; - reg_ser_rw_tr_dma_en tx_dma_en = {0}; - reg_ser_rw_rec_ctrl rx_ctrl = {0}; - reg_ser_rw_tr_baud_div tx_baud_div = {0}; - reg_ser_rw_rec_baud_div rx_baud_div = {0}; - int baud; - - if (old && - termios->c_cflag == old->c_cflag && - termios->c_iflag == old->c_iflag) - return; - - /* Tx: 8 bit, no/even parity, 1 stop bit, no cts. */ - tx_ctrl.base_freq = regk_ser_f29_493; - tx_ctrl.en = 0; - tx_ctrl.stop = 0; - tx_ctrl.auto_rts = regk_ser_no; - tx_ctrl.txd = 1; - tx_ctrl.auto_cts = 0; - /* Rx: 8 bit, no/even parity. */ - rx_ctrl.dma_err = regk_ser_stop; - rx_ctrl.sampling = regk_ser_majority; - rx_ctrl.timeout = 1; - - rx_ctrl.rts_n = regk_ser_inactive; - - /* Common for tx and rx: 8N1. */ - tx_ctrl.data_bits = regk_ser_bits8; - rx_ctrl.data_bits = regk_ser_bits8; - tx_ctrl.par = regk_ser_even; - rx_ctrl.par = regk_ser_even; - tx_ctrl.par_en = regk_ser_no; - rx_ctrl.par_en = regk_ser_no; - - tx_ctrl.stop_bits = regk_ser_bits1; - - /* - * Change baud-rate and write it to the hardware. - * - * baud_clock = base_freq / (divisor*8) - * divisor = base_freq / (baud_clock * 8) - * base_freq is either: - * off, ext, 29.493MHz, 32.000 MHz, 32.768 MHz or 100 MHz - * 20.493MHz is used for standard baudrates - */ - - /* - * For the console port we keep the original baudrate here. Not very - * beautiful. - */ - if ((port != console_port) || old) - baud = uart_get_baud_rate(port, termios, old, 0, - port->uartclk / 8); - else - baud = console_baud; - - tx_baud_div.div = 29493000 / (8 * baud); - /* Rx uses same as tx. */ - rx_baud_div.div = tx_baud_div.div; - rx_ctrl.base_freq = tx_ctrl.base_freq; - - if ((termios->c_cflag & CSIZE) == CS7) { - /* Set 7 bit mode. */ - tx_ctrl.data_bits = regk_ser_bits7; - rx_ctrl.data_bits = regk_ser_bits7; - } - - if (termios->c_cflag & CSTOPB) { - /* Set 2 stop bit mode. */ - tx_ctrl.stop_bits = regk_ser_bits2; - } - - if (termios->c_cflag & PARENB) { - /* Enable parity. */ - tx_ctrl.par_en = regk_ser_yes; - rx_ctrl.par_en = regk_ser_yes; - } - - if (termios->c_cflag & CMSPAR) { - if (termios->c_cflag & PARODD) { - /* Set mark parity if PARODD and CMSPAR. */ - tx_ctrl.par = regk_ser_mark; - rx_ctrl.par = regk_ser_mark; - } else { - tx_ctrl.par = regk_ser_space; - rx_ctrl.par = regk_ser_space; - } - } else { - if (termios->c_cflag & PARODD) { - /* Set odd parity. */ - tx_ctrl.par = regk_ser_odd; - rx_ctrl.par = regk_ser_odd; - } - } - - if (termios->c_cflag & CRTSCTS) { - /* Enable automatic CTS handling. */ - tx_ctrl.auto_cts = regk_ser_yes; - } - - /* Make sure the tx and rx are enabled. */ - tx_ctrl.en = regk_ser_yes; - rx_ctrl.en = regk_ser_yes; - - spin_lock_irqsave(&port->lock, flags); - - tx_dma_en.en = 0; - REG_WR(ser, up->regi_ser, rw_tr_dma_en, tx_dma_en); - - /* Actually write the control regs (if modified) to the hardware. */ - uart_update_timeout(port, termios->c_cflag, port->uartclk/8); - MODIFY_REG(up->regi_ser, rw_rec_baud_div, rx_baud_div); - MODIFY_REG(up->regi_ser, rw_rec_ctrl, rx_ctrl); - - MODIFY_REG(up->regi_ser, rw_tr_baud_div, tx_baud_div); - MODIFY_REG(up->regi_ser, rw_tr_ctrl, tx_ctrl); - - tx_dma_en.en = 0; - REG_WR(ser, up->regi_ser, rw_tr_dma_en, tx_dma_en); - - xoff = REG_RD(ser, up->regi_ser, rw_xoff); - - if (up->port.state && up->port.state->port.tty && - (up->port.state->port.tty->termios.c_iflag & IXON)) { - xoff.chr = STOP_CHAR(up->port.state->port.tty); - xoff.automatic = regk_ser_yes; - } else - xoff.automatic = regk_ser_no; - - MODIFY_REG(up->regi_ser, rw_xoff, xoff); - - /* - * Make sure we don't start in an automatically shut-off state due to - * a previous early exit. - */ - xoff_clr.clr = 1; - REG_WR(ser, up->regi_ser, rw_xoff_clr, xoff_clr); - - etraxfs_uart_set_mctrl(&up->port, up->port.mctrl); - spin_unlock_irqrestore(&up->port.lock, flags); -} - -static const char * -etraxfs_uart_type(struct uart_port *port) -{ - return "CRISv32"; -} - -static void etraxfs_uart_release_port(struct uart_port *port) -{ -} - -static int etraxfs_uart_request_port(struct uart_port *port) -{ - return 0; -} - -static void etraxfs_uart_config_port(struct uart_port *port, int flags) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - - up->port.type = PORT_CRIS; -} - -static const struct uart_ops etraxfs_uart_pops = { - .tx_empty = etraxfs_uart_tx_empty, - .set_mctrl = etraxfs_uart_set_mctrl, - .get_mctrl = etraxfs_uart_get_mctrl, - .stop_tx = etraxfs_uart_stop_tx, - .start_tx = etraxfs_uart_start_tx, - .send_xchar = etraxfs_uart_send_xchar, - .stop_rx = etraxfs_uart_stop_rx, - .break_ctl = etraxfs_uart_break_ctl, - .startup = etraxfs_uart_startup, - .shutdown = etraxfs_uart_shutdown, - .set_termios = etraxfs_uart_set_termios, - .type = etraxfs_uart_type, - .release_port = etraxfs_uart_release_port, - .request_port = etraxfs_uart_request_port, - .config_port = etraxfs_uart_config_port, -#ifdef CONFIG_CONSOLE_POLL - .poll_get_char = etraxfs_uart_get_poll_char, - .poll_put_char = etraxfs_uart_put_poll_char, -#endif -}; - -static void cris_serial_port_init(struct uart_port *port, int line) -{ - struct uart_cris_port *up = (struct uart_cris_port *)port; - - if (up->initialized) - return; - up->initialized = 1; - port->line = line; - spin_lock_init(&port->lock); - port->ops = &etraxfs_uart_pops; - port->irq = up->irq; - port->iobase = (unsigned long) up->regi_ser; - port->uartclk = 29493000; - - /* - * We can't fit any more than 255 here (unsigned char), though - * actually UART_XMIT_SIZE characters could be pending output. - * At time of this writing, the definition of "fifosize" is here the - * amount of characters that can be pending output after a start_tx call - * until tx_empty returns 1: see serial_core.c:uart_wait_until_sent. - * This matters for timeout calculations unfortunately, but keeping - * larger amounts at the DMA wouldn't win much so let's just play nice. - */ - port->fifosize = 255; - port->flags = UPF_BOOT_AUTOCONF; -} - -static int etraxfs_uart_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct uart_cris_port *up; - int dev_id; - - if (!np) - return -ENODEV; - - dev_id = of_alias_get_id(np, "serial"); - if (dev_id < 0) - dev_id = 0; - - if (dev_id >= UART_NR) - return -EINVAL; - - if (etraxfs_uart_ports[dev_id]) - return -EBUSY; - - up = devm_kzalloc(&pdev->dev, sizeof(struct uart_cris_port), - GFP_KERNEL); - if (!up) - return -ENOMEM; - - up->irq = irq_of_parse_and_map(np, 0); - up->regi_ser = of_iomap(np, 0); - up->port.dev = &pdev->dev; - - up->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0); - if (IS_ERR(up->gpios)) - return PTR_ERR(up->gpios); - - cris_serial_port_init(&up->port, dev_id); - - etraxfs_uart_ports[dev_id] = up; - platform_set_drvdata(pdev, &up->port); - uart_add_one_port(&etraxfs_uart_driver, &up->port); - - return 0; -} - -static int etraxfs_uart_remove(struct platform_device *pdev) -{ - struct uart_port *port; - - port = platform_get_drvdata(pdev); - uart_remove_one_port(&etraxfs_uart_driver, port); - etraxfs_uart_ports[port->line] = NULL; - - return 0; -} - -static const struct of_device_id etraxfs_uart_dt_ids[] = { - { .compatible = "axis,etraxfs-uart" }, - { /* sentinel */ } -}; - -MODULE_DEVICE_TABLE(of, etraxfs_uart_dt_ids); - -static struct platform_driver etraxfs_uart_platform_driver = { - .driver = { - .name = DRV_NAME, - .of_match_table = of_match_ptr(etraxfs_uart_dt_ids), - }, - .probe = etraxfs_uart_probe, - .remove = etraxfs_uart_remove, -}; - -static int __init etraxfs_uart_init(void) -{ - int ret; - - ret = uart_register_driver(&etraxfs_uart_driver); - if (ret) - return ret; - - ret = platform_driver_register(&etraxfs_uart_platform_driver); - if (ret) - uart_unregister_driver(&etraxfs_uart_driver); - - return ret; -} - -static void __exit etraxfs_uart_exit(void) -{ - platform_driver_unregister(&etraxfs_uart_platform_driver); - uart_unregister_driver(&etraxfs_uart_driver); -} - -module_init(etraxfs_uart_init); -module_exit(etraxfs_uart_exit); -- cgit v1.2.3 From f0f56716fc3e5d547fd7811eb218a30ed0695605 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 23 Mar 2018 10:30:53 +0900 Subject: ata: ahci-platform: add reset control support Add support to get and control a list of resets for the device as optional and shared. These resets must be kept de-asserted until the device is enabled. This is specified as shared because some SoCs like UniPhier series have common reset controls with all ahci controller instances. Signed-off-by: Kunihiko Hayashi Reviewed-by: Hans de Goede Signed-off-by: Tejun Heo --- .../devicetree/bindings/ata/ahci-platform.txt | 1 + drivers/ata/ahci.h | 1 + drivers/ata/libahci_platform.c | 24 +++++++++++++++++++--- 3 files changed, 23 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index c760ecb81381..f4006d3c9fdf 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -30,6 +30,7 @@ compatible: Optional properties: - dma-coherent : Present if dma operations are coherent - clocks : a list of phandle + clock specifier pairs +- resets : a list of phandle + reset specifier pairs - target-supply : regulator for SATA target power - phys : reference to the SATA PHY node - phy-names : must be "sata-phy" diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index a9d996e17d75..4356ef1d28a8 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -350,6 +350,7 @@ struct ahci_host_priv { u32 em_msg_type; /* EM message type */ bool got_runtime_pm; /* Did we do pm_runtime_get? */ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ + struct reset_control *rsts; /* Optional */ struct regulator **target_pwrs; /* Optional */ /* * If platform uses PHYs. There is a 1:1 relation between the port number and diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 30cc8f1a31e1..46a762442dc5 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ahci.h" static void ahci_host_stop(struct ata_host *host); @@ -195,7 +196,8 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_regulators); * following order: * 1) Regulator * 2) Clocks (through ahci_platform_enable_clks) - * 3) Phys + * 3) Resets + * 4) Phys * * If resource enabling fails at any point the previous enabled resources * are disabled in reverse order. @@ -215,12 +217,19 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv) if (rc) goto disable_regulator; - rc = ahci_platform_enable_phys(hpriv); + rc = reset_control_deassert(hpriv->rsts); if (rc) goto disable_clks; + rc = ahci_platform_enable_phys(hpriv); + if (rc) + goto disable_resets; + return 0; +disable_resets: + reset_control_assert(hpriv->rsts); + disable_clks: ahci_platform_disable_clks(hpriv); @@ -239,12 +248,15 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_resources); * following order: * 1) Phys * 2) Clocks (through ahci_platform_disable_clks) - * 3) Regulator + * 3) Resets + * 4) Regulator */ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv) { ahci_platform_disable_phys(hpriv); + reset_control_assert(hpriv->rsts); + ahci_platform_disable_clks(hpriv); ahci_platform_disable_regulators(hpriv); @@ -393,6 +405,12 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev) hpriv->clks[i] = clk; } + hpriv->rsts = devm_reset_control_array_get_optional_shared(dev); + if (IS_ERR(hpriv->rsts)) { + rc = PTR_ERR(hpriv->rsts); + goto err_out; + } + hpriv->nports = child_nodes = of_get_child_count(dev->of_node); /* -- cgit v1.2.3 From 8396764154c6365bfeb9cc851b9746511a151255 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Fri, 23 Mar 2018 21:30:36 +0900 Subject: dt-bindings: net: ave: add PXs3 support Add a compatible string for ethernet controller on UniPhier PXs3 SoC. Signed-off-by: Kunihiko Hayashi Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt index 270ea4efff13..96398cc2982f 100644 --- a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt @@ -9,6 +9,7 @@ Required properties: - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC - "socionext,uniphier-ld11-ave4" : for LD11 SoC - "socionext,uniphier-ld20-ave4" : for LD20 SoC + - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC - reg: Address where registers are mapped and size of region. - interrupts: Should contain the MAC interrupt. - phy-mode: See ethernet.txt in the same directory. Allow to choose -- cgit v1.2.3 From ee9c64307b6203151a20ec33e6f51ae1cac1bb6e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 26 Mar 2018 13:20:43 -0300 Subject: Revert "dt-bindings: ifc: Fix the unit address format in the examples" This reverts commit 4e017f1419397473cf3db6e9fa020013998b1aa4. As explained by Rob Herring: "This "fix" is wrong. Memory controllers with chip selects should have the chip select in the unit-address. The correct fix here is you should drop "simple-bus"." Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt index a4d4b6a2ff0d..89427b018ba7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt @@ -43,7 +43,7 @@ Example: 0x1 0x0 0x0 0xffa00000 0x00010000 0x3 0x0 0x0 0xffb00000 0x00020000>; - flash@0 { + flash@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; @@ -58,7 +58,7 @@ Example: }; }; - flash@100000000 { + flash@1,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,ifc-nand"; @@ -73,7 +73,7 @@ Example: }; }; - cpld@@300000000 { + cpld@3,0 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,p1010rdb-cpld"; -- cgit v1.2.3 From dae5af9762c8f03233b68401ecc4fab4befae11c Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 19 Mar 2018 08:25:50 +0100 Subject: dt-bindings: reset: add STM32MP1 resets This patch adds the reset binding entry for STM32MP1 Signed-off-by: Gabriel Fernandez Reviewed-by: Rob Herring Signed-off-by: Philipp Zabel --- .../devicetree/bindings/reset/st,stm32mp1-rcc.txt | 6 ++ include/dt-bindings/reset/stm32mp1-resets.h | 108 +++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt create mode 100644 include/dt-bindings/reset/stm32mp1-resets.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt new file mode 100644 index 000000000000..b4edaf7c7ff3 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt @@ -0,0 +1,6 @@ +STMicroelectronics STM32MP1 Peripheral Reset Controller +======================================================= + +The RCC IP is both a reset and a clock controller. + +Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h new file mode 100644 index 000000000000..f0c3aaef67a0 --- /dev/null +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ +/* + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ +#define _DT_BINDINGS_STM32MP1_RESET_H_ + +#define LTDC_R 3072 +#define DSI_R 3076 +#define DDRPERFM_R 3080 +#define USBPHY_R 3088 +#define SPI6_R 3136 +#define I2C4_R 3138 +#define I2C6_R 3139 +#define USART1_R 3140 +#define STGEN_R 3156 +#define GPIOZ_R 3200 +#define CRYP1_R 3204 +#define HASH1_R 3205 +#define RNG1_R 3206 +#define AXIM_R 3216 +#define GPU_R 3269 +#define ETHMAC_R 3274 +#define FMC_R 3276 +#define QSPI_R 3278 +#define SDMMC1_R 3280 +#define SDMMC2_R 3281 +#define CRC1_R 3284 +#define USBH_R 3288 +#define MDMA_R 3328 +#define MCU_R 8225 +#define TIM2_R 19456 +#define TIM3_R 19457 +#define TIM4_R 19458 +#define TIM5_R 19459 +#define TIM6_R 19460 +#define TIM7_R 19461 +#define TIM12_R 16462 +#define TIM13_R 16463 +#define TIM14_R 16464 +#define LPTIM1_R 19465 +#define SPI2_R 19467 +#define SPI3_R 19468 +#define USART2_R 19470 +#define USART3_R 19471 +#define UART4_R 19472 +#define UART5_R 19473 +#define UART7_R 19474 +#define UART8_R 19475 +#define I2C1_R 19477 +#define I2C2_R 19478 +#define I2C3_R 19479 +#define I2C5_R 19480 +#define SPDIF_R 19482 +#define CEC_R 19483 +#define DAC12_R 19485 +#define MDIO_R 19847 +#define TIM1_R 19520 +#define TIM8_R 19521 +#define TIM15_R 19522 +#define TIM16_R 19523 +#define TIM17_R 19524 +#define SPI1_R 19528 +#define SPI4_R 19529 +#define SPI5_R 19530 +#define USART6_R 19533 +#define SAI1_R 19536 +#define SAI2_R 19537 +#define SAI3_R 19538 +#define DFSDM_R 19540 +#define FDCAN_R 19544 +#define LPTIM2_R 19584 +#define LPTIM3_R 19585 +#define LPTIM4_R 19586 +#define LPTIM5_R 19587 +#define SAI4_R 19592 +#define SYSCFG_R 19595 +#define VREF_R 19597 +#define TMPSENS_R 19600 +#define PMBCTRL_R 19601 +#define DMA1_R 19648 +#define DMA2_R 19649 +#define DMAMUX_R 19650 +#define ADC12_R 19653 +#define USBO_R 19656 +#define SDMMC3_R 19664 +#define CAMITF_R 19712 +#define CRYP2_R 19716 +#define HASH2_R 19717 +#define RNG2_R 19718 +#define CRC2_R 19719 +#define HSEM_R 19723 +#define MBOX_R 19724 +#define GPIOA_R 19776 +#define GPIOB_R 19777 +#define GPIOC_R 19778 +#define GPIOD_R 19779 +#define GPIOE_R 19780 +#define GPIOF_R 19781 +#define GPIOG_R 19782 +#define GPIOH_R 19783 +#define GPIOI_R 19784 +#define GPIOJ_R 19785 +#define GPIOK_R 19786 + +#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ -- cgit v1.2.3 From 33f32c0e1eb710fb9bca647e0e9b439d88961ea9 Mon Sep 17 00:00:00 2001 From: Sean Wang Date: Thu, 15 Mar 2018 15:40:35 +0800 Subject: dt-bindings: dmaengine: Add MediaTek High-Speed DMA controller bindings Document the devicetree bindings for MediaTek High-Speed DMA controller which could be found on MT7623 SoC or other similar Mediatek SoCs. Signed-off-by: Sean Wang Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/mtk-hsdma.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mtk-hsdma.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/mtk-hsdma.txt b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt new file mode 100644 index 000000000000..4bb317359dc6 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt @@ -0,0 +1,33 @@ +MediaTek High-Speed DMA Controller +================================== + +This device follows the generic DMA bindings defined in dma/dma.txt. + +Required properties: + +- compatible: Must be one of + "mediatek,mt7622-hsdma": for MT7622 SoC + "mediatek,mt7623-hsdma": for MT7623 SoC +- reg: Should contain the register's base address and length. +- interrupts: Should contain a reference to the interrupt used by this + device. +- clocks: Should be the clock specifiers corresponding to the entry in + clock-names property. +- clock-names: Should contain "hsdma" entries. +- power-domains: Phandle to the power domain that the device is part of +- #dma-cells: The length of the DMA specifier, must be <1>. This one cell + in dmas property of a client device represents the channel + number. +Example: + + hsdma: dma-controller@1b007000 { + compatible = "mediatek,mt7623-hsdma"; + reg = <0 0x1b007000 0 0x1000>; + interrupts = ; + clocks = <ðsys CLK_ETHSYS_HSDMA>; + clock-names = "hsdma"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; + #dma-cells = <1>; + }; + +DMA clients must use the format described in dma/dma.txt file. -- cgit v1.2.3 From c8a830904991931106c96ff1ee0588d1ca9ea5f0 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 16 Mar 2018 22:02:10 +0800 Subject: pinctrl: sunxi: add support for the Allwinner H6 main pin controller The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring Reviewed-by: Andre Przywara Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 614 +++++++++++++++++++++ 4 files changed, 620 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index 09789fdfa749..ed5eb547afc8 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -27,6 +27,7 @@ Required properties: "allwinner,sun50i-a64-pinctrl" "allwinner,sun50i-a64-r-pinctrl" "allwinner,sun50i-h5-pinctrl" + "allwinner,sun50i-h6-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index bfce99d86dfc..5de1f63b07bb 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -77,4 +77,8 @@ config PINCTRL_SUN50I_H5 def_bool ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_H6 + def_bool ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index 12a752e836ef..3c4aec6611e9 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o +obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c new file mode 100644 index 000000000000..aa8b58125568 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Allwinner H6 SoC pinctrl driver. + * + * Copyright (C) 2017 Icenowy Zheng + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin h6_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), + SUNXI_FUNCTION(0x2, "emac")), /* ERXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), + SUNXI_FUNCTION(0x2, "emac")), /* ERXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), + SUNXI_FUNCTION(0x2, "emac")), /* ECRS_DV */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), + SUNXI_FUNCTION(0x2, "emac")), /* ERXERR */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), + SUNXI_FUNCTION(0x2, "emac")), /* ETXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), + SUNXI_FUNCTION(0x2, "emac")), /* ETXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), + SUNXI_FUNCTION(0x2, "emac")), /* ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), + SUNXI_FUNCTION(0x2, "emac")), /* ETXEN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), + SUNXI_FUNCTION(0x2, "emac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), + SUNXI_FUNCTION(0x2, "emac")), /* EMDIO */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x2, "ccir"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x2, "ccir"), /* DE */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x2, "ccir"), /* HSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x2, "ccir"), /* VSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x2, "ccir"), /* DO0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x2, "ccir"), /* DO1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x2, "ccir"), /* DO2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x2, "ccir"), /* DO3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x2, "ccir"), /* DO4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x2, "ccir"), /* DO5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x2, "ccir"), /* DO6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), + SUNXI_FUNCTION(0x2, "ccir"), /* DO7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), + SUNXI_FUNCTION(0x2, "i2s3"), /* SYNC */ + SUNXI_FUNCTION(0x4, "h_i2s3"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), + SUNXI_FUNCTION(0x2, "i2s3"), /* CLK */ + SUNXI_FUNCTION(0x4, "h_i2s3"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), + SUNXI_FUNCTION(0x2, "i2s3"), /* DOUT */ + SUNXI_FUNCTION(0x4, "h_i2s3"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), + SUNXI_FUNCTION(0x2, "i2s3"), /* DIN */ + SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), + SUNXI_FUNCTION(0x2, "i2s3"), /* MCLK */ + SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), + SUNXI_FUNCTION(0x2, "pwm1"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x4, "spi0")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* DS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ + SUNXI_FUNCTION(0x4, "spi0")), /* CS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ + SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ + SUNXI_FUNCTION(0x4, "spi0")), /* WP */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ + SUNXI_FUNCTION(0x4, "csi"), /* PCLK */ + SUNXI_FUNCTION(0x5, "emac")), /* ERXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ + SUNXI_FUNCTION(0x4, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x5, "emac")), /* ERXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ + SUNXI_FUNCTION(0x4, "csi"), /* HSYNC */ + SUNXI_FUNCTION(0x5, "emac")), /* ERXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "ts0"), /* DVLD */ + SUNXI_FUNCTION(0x4, "csi"), /* VSYNC */ + SUNXI_FUNCTION(0x5, "emac")), /* ERXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ + SUNXI_FUNCTION(0x4, "csi"), /* D0 */ + SUNXI_FUNCTION(0x5, "emac")), /* ERXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ + SUNXI_FUNCTION(0x4, "csi"), /* D1 */ + SUNXI_FUNCTION(0x5, "emac")), /* ERXCTL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ + SUNXI_FUNCTION(0x4, "csi"), /* D2 */ + SUNXI_FUNCTION(0x5, "emac")), /* ENULL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ + SUNXI_FUNCTION(0x4, "csi"), /* D3 */ + SUNXI_FUNCTION(0x5, "emac")), /* ETXD3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ + SUNXI_FUNCTION(0x4, "csi"), /* D4 */ + SUNXI_FUNCTION(0x5, "emac")), /* ETXD2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ + SUNXI_FUNCTION(0x4, "csi"), /* D5 */ + SUNXI_FUNCTION(0x5, "emac")), /* ETXD1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ + SUNXI_FUNCTION(0x4, "csi"), /* D6 */ + SUNXI_FUNCTION(0x5, "emac")), /* ETXD0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ + SUNXI_FUNCTION(0x4, "csi"), /* D7 */ + SUNXI_FUNCTION(0x5, "emac")), /* ETXCK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "ts1"), /* CLK */ + SUNXI_FUNCTION(0x4, "csi"), /* SCK */ + SUNXI_FUNCTION(0x5, "emac")), /* ETXCTL */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "ts1"), /* ERR */ + SUNXI_FUNCTION(0x4, "csi"), /* SDA */ + SUNXI_FUNCTION(0x5, "emac")), /* ECLKIN */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x3, "ts1"), /* SYNC */ + SUNXI_FUNCTION(0x4, "dmic"), /* CLK */ + SUNXI_FUNCTION(0x5, "csi")), /* D8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x3, "ts1"), /* DVLD */ + SUNXI_FUNCTION(0x4, "dmic"), /* DATA0 */ + SUNXI_FUNCTION(0x5, "csi")), /* D9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x3, "ts1"), /* D0 */ + SUNXI_FUNCTION(0x4, "dmic")), /* DATA1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x3, "ts2"), /* CLK */ + SUNXI_FUNCTION(0x4, "dmic")), /* DATA2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x3, "ts2"), /* ERR */ + SUNXI_FUNCTION(0x4, "dmic")), /* DATA3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x3, "ts2"), /* SYNC */ + SUNXI_FUNCTION(0x4, "uart2"), /* TX */ + SUNXI_FUNCTION(0x5, "emac")), /* EMDC */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "ts2"), /* DVLD */ + SUNXI_FUNCTION(0x4, "uart2"), /* RX */ + SUNXI_FUNCTION(0x5, "emac")), /* EMDIO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "ts2"), /* D0 */ + SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ + SUNXI_FUNCTION(0x3, "ts3"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ + SUNXI_FUNCTION(0x3, "ts3"), /* ERR */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION(0x5, "jtag")), /* MS */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ + SUNXI_FUNCTION(0x3, "ts3"), /* SYNC */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION(0x5, "jtag")), /* CK */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x3, "ts3"), /* DVLD */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x5, "jtag")), /* DO */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x3, "ts3"), /* D0 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x5, "jtag")), /* DI */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s2"), /* SYNC */ + SUNXI_FUNCTION(0x3, "h_i2s2"), /* SYNC */ + SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s2"), /* CLK */ + SUNXI_FUNCTION(0x3, "h_i2s2"), /* CLK */ + SUNXI_FUNCTION(0x4, "sim0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s2"), /* DOUT */ + SUNXI_FUNCTION(0x3, "h_i2s2"), /* DOUT */ + SUNXI_FUNCTION(0x4, "sim0"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s2"), /* DIN */ + SUNXI_FUNCTION(0x3, "h_i2s2"), /* DIN */ + SUNXI_FUNCTION(0x4, "sim0"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */ + SUNXI_FUNCTION(0x3, "h_i2s2"), /* MCLK */ + SUNXI_FUNCTION(0x4, "sim0"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x4, "h_i2s0"), /* SYNC */ + SUNXI_FUNCTION(0x5, "sim1"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "i2s0"), /* CLK */ + SUNXI_FUNCTION(0x4, "h_i2s0"), /* CLK */ + SUNXI_FUNCTION(0x5, "sim1"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ir_tx"), + SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT */ + SUNXI_FUNCTION(0x5, "sim1"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CS */ + SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */ + SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN */ + SUNXI_FUNCTION(0x5, "sim1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "h_i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x5, "sim1"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x3, "spdif"), /* MCLK */ + SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x5, "sim1"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x3, "spdif"), /* IN */ + SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x5, "sim1"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */ +}; + +static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 }; + +static const struct sunxi_pinctrl_desc h6_pinctrl_data = { + .pins = h6_pins, + .npins = ARRAY_SIZE(h6_pins), + .irq_banks = 3, + .irq_bank_map = h6_irq_bank_map, + .irq_read_needs_mux = true, +}; + +static int h6_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &h6_pinctrl_data); +} + +static const struct of_device_id h6_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-h6-pinctrl", }, + {} +}; + +static struct platform_driver h6_pinctrl_driver = { + .probe = h6_pinctrl_probe, + .driver = { + .name = "sun50i-h6-pinctrl", + .of_match_table = h6_pinctrl_match, + }, +}; +builtin_platform_driver(h6_pinctrl_driver); -- cgit v1.2.3 From 3a711e0dd4e68f6b202db3f9e2c0086a8780da25 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 10 Mar 2018 12:00:01 +0100 Subject: gpio: pca953x: add compatibility for pcal6524 and pcal9555a The Pyra-Handheld originally used the tca6424 but recently we have replaced it by the pin and package compatible pcal6524. So let's add this to the bindings and the driver. And while we are at it, the pcal9555a does not have a compatible entry either but is already supported by the device id table. Signed-off-by: H. Nikolaus Schaller Reviewed-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | 2 ++ drivers/gpio/gpio-pca953x.c | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt index 0d0158728f89..d2a937682836 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt @@ -16,6 +16,8 @@ Required properties: nxp,pca9574 nxp,pca9575 nxp,pca9698 + nxp,pcal6524 + nxp,pcal9555a maxim,max7310 maxim,max7312 maxim,max7313 diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index a0a5f9730aa7..d2ead4b1cf61 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -70,6 +70,7 @@ static const struct i2c_device_id pca953x_id[] = { { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, { "pca9698", 40 | PCA953X_TYPE, }, + { "pcal6524", 24 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, { "max7310", 8 | PCA953X_TYPE, }, @@ -935,6 +936,9 @@ static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, + { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_INT), }, + { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_INT), }, + { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, -- cgit v1.2.3 From b9c725ed73b7cecc7c9bc4b752ab3eb975ef9330 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 23 Mar 2018 09:34:49 -0700 Subject: dt-bindings: gpio: Add a gpio-reserved-ranges property Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues. Introduce a DT property to describe the set of GPIOs that are available for use so that higher level OSes are able to know what pins to avoid reading/writing. Cc: Grant Likely Cc: Signed-off-by: Stephen Boyd Signed-off-by: Stephen Boyd Reviewed-by: Rob Herring Tested-by: Timur Tabi Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index b5de08e3b1a2..a7c31de29362 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using first 18 GPIOs, at local offset 0 .. 17, are in use. If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an -additional bitmask is needed to specify which GPIOs are actually in use, -and which are dummies. The bindings for this case has not yet been -specified, but should be specified if/when such hardware appears. +additional set of tuples is needed to specify which GPIOs are unusable, with +the gpio-reserved-ranges binding. This property indicates the start and size +of the GPIOs that can't be used. Optionally, a GPIO controller may have a "gpio-line-names" property. This is an array of strings defining the names of the GPIO lines going out of the @@ -178,6 +178,7 @@ gpio-controller@00000000 { gpio-controller; #gpio-cells = <2>; ngpios = <18>; + gpio-reserved-ranges = <0 4>, <12 2>; gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", "Row A", "Row B", "Row C", "Row D", "NMI button", -- cgit v1.2.3 From be520cbc8513ea796c00825e8189d98d67ead33f Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Mon, 5 Mar 2018 10:56:50 +0800 Subject: dt-bindings: gpio: Add Spreadtrum EIC controller documentation This patch adds the device tree bindings for the Spreadtrum EIC controller. The EIC can be seen as a special type of GPIO, which can only be used as input mode. Signed-off-by: Baolin Wang Reviewed-by: Rob Herring Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-eic-sprd.txt | 97 ++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt new file mode 100644 index 000000000000..93d98d09d92b --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-eic-sprd.txt @@ -0,0 +1,97 @@ +Spreadtrum EIC controller bindings + +The EIC is the abbreviation of external interrupt controller, which can +be used only in input mode. The Spreadtrum platform has 2 EIC controllers, +one is in digital chip, and another one is in PMIC. The digital chip EIC +controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and +EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub- +module. + +The EIC-debounce sub-module provides up to 8 source input signal +connections. A debounce mechanism is used to capture the input signals' +stable status (millisecond resolution) and a single-trigger mechanism +is introduced into this sub-module to enhance the input event detection +reliability. In addition, this sub-module's clock can be shut off +automatically to reduce power dissipation. Moreover the debounce range +is from 1ms to 4s with a step size of 1ms. The input signal will be +ignored if it is asserted for less than 1 ms. + +The EIC-latch sub-module is used to latch some special power down signals +and generate interrupts, since the EIC-latch does not depend on the APB +clock to capture signals. + +The EIC-async sub-module uses a 32kHz clock to capture the short signals +(microsecond resolution) to generate interrupts by level or edge trigger. + +The EIC-sync is similar with GPIO's input function, which is a synchronized +signal input register. It can generate interrupts by level or edge trigger +when detecting input signals. + +Required properties: +- compatible: Should be one of the following: + "sprd,sc9860-eic-debounce", + "sprd,sc9860-eic-latch", + "sprd,sc9860-eic-async", + "sprd,sc9860-eic-sync", + "sprd,sc27xx-eic". +- reg: Define the base and range of the I/O address space containing + the GPIO controller registers. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be <2>. The first cell is the gpio number and + the second cell is used to specify optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be <2>. Specifies the number of cells needed + to encode interrupt source. +- interrupts: Should be the port interrupt shared by all the gpios. + +Example: + eic_debounce: gpio@40210000 { + compatible = "sprd,sc9860-eic-debounce"; + reg = <0 0x40210000 0 0x80>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + eic_latch: gpio@40210080 { + compatible = "sprd,sc9860-eic-latch"; + reg = <0 0x40210080 0 0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + eic_async: gpio@402100a0 { + compatible = "sprd,sc9860-eic-async"; + reg = <0 0x402100a0 0 0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + eic_sync: gpio@402100c0 { + compatible = "sprd,sc9860-eic-sync"; + reg = <0 0x402100c0 0 0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + pmic_eic: gpio@300 { + compatible = "sprd,sc27xx-eic"; + reg = <0x300>; + interrupt-parent = <&sc2731_pmic>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; -- cgit v1.2.3 From 3ba111a0182265b65e303c969294b8033ce9d122 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 19 Dec 2017 13:34:59 +0000 Subject: dt-bindings: pwm: renesas-tpu: Document r8a774[35] support Document r8a774[35] specific compatible strings. No driver change is needed as the fallback compatible string "renesas,tpu" activates the right code in the driver. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt index 1aadc804dae4..16e574821668 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt @@ -5,8 +5,10 @@ Required Properties: - compatible: should be one of the following. - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller. - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller. + - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller. + - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller. - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller. - - "renesas,tpu": for generic R-Car TPU PWM controller. + - "renesas,tpu": for generic R-Car and RZ/G1 TPU PWM controller. - reg: Base address and length of each memory resource used by the PWM controller hardware module. -- cgit v1.2.3 From 9d7e72858d9d84abbbb49e98e2dafeee2f7fd9b6 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 20 Dec 2017 11:15:43 +0000 Subject: dt-bindings: pwm: rcar: Document r8a774[35] PWM bindings This patch adds compatible strings specific to r8a774[35], no driver change is needed as the fallback compatible string will activate the right code. Also, this patch replaces the example with a DT snippet used for adding PWM0 support to an r8a7743 based platform as the r8a7743 is now the first platform fully compatible with this driver and its PWM DT nodes refer to up-to-date code. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index 74c118015980..f3bba592d419 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -2,6 +2,8 @@ Required Properties: - compatible: should be "renesas,pwm-rcar" and one of the following. + - "renesas,pwm-r8a7743": for RZ/G1M + - "renesas,pwm-r8a7745": for RZ/G1E - "renesas,pwm-r8a7778": for R-Car M1A - "renesas,pwm-r8a7779": for R-Car H1 - "renesas,pwm-r8a7790": for R-Car H2 @@ -17,13 +19,15 @@ Required Properties: - pinctrl-0: phandle, referring to a default pin configuration node. - pinctrl-names: Set to "default". -Example: R8A7790 (R-Car H2) PWM Timer node +Example: R8A7743 (RZ/G1M) PWM Timer node pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 523>; #pwm-cells = <2>; - clocks = <&mstp5_clks R8A7790_CLK_PWM>; pinctrl-0 = <&pwm0_pins>; pinctrl-names = "default"; }; -- cgit v1.2.3 From 3b8ad2c1effedf2fed4ad989612386b5cff11289 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Dec 2017 17:02:06 +0100 Subject: dt-bindings: pwm: renesas-tpu: Correct example TPU register block size The Timer Pulse Unit on R-Mobile A1 has registers that lie outside the declared register block. Enlarge the register block size to fix this. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt index 16e574821668..d52e30ed8072 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt @@ -24,6 +24,6 @@ Example: R8A7740 (R-Car A1) TPU controller node tpu: pwm@e6600000 { compatible = "renesas,tpu-r8a7740", "renesas,tpu"; - reg = <0xe6600000 0x100>; + reg = <0xe6600000 0x148>; #pwm-cells = <3>; }; -- cgit v1.2.3 From 204e17baa6fd2ec02deca08cdcb60aad77cbd043 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 2 Mar 2018 15:39:45 +0100 Subject: dt-bindings: pwm: renesas-tpu: Correct SoC part numbers and family names R8A73A4 (not R8A77A4) is R-Mobile APE6, R8A7740 is R-Mobile (not R-Car) A1. Signed-off-by: Geert Uytterhoeven Acked-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt index d52e30ed8072..d53a16715da6 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt @@ -3,7 +3,7 @@ Required Properties: - compatible: should be one of the following. - - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller. + - "renesas,tpu-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible PWM controller. - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller. - "renesas,tpu-r8a7743": for R8A7743 (RZ/G1M) compatible PWM controller. - "renesas,tpu-r8a7745": for R8A7745 (RZ/G1E) compatible PWM controller. @@ -20,7 +20,7 @@ Required Properties: Please refer to pwm.txt in this directory for details of the common PWM bindings used by client devices. -Example: R8A7740 (R-Car A1) TPU controller node +Example: R8A7740 (R-Mobile A1) TPU controller node tpu: pwm@e6600000 { compatible = "renesas,tpu-r8a7740", "renesas,tpu"; -- cgit v1.2.3 From cc20173304e4f54c0ccabe0c0636b05c2410a4be Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 6 Jan 2018 17:58:42 +0100 Subject: pwm: jz4740: Add support for devicetree Add support for probing the pwm-jz4740 directly from devicetree. Signed-off-by: Paul Cercueil Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt | 25 ++++++++++++++++++++++ drivers/pwm/pwm-jz4740.c | 14 ++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt new file mode 100644 index 000000000000..7d9d3f90641b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/ingenic,jz47xx-pwm.txt @@ -0,0 +1,25 @@ +Ingenic JZ47xx PWM Controller +============================= + +Required properties: +- compatible: One of: + * "ingenic,jz4740-pwm" + * "ingenic,jz4770-pwm" + * "ingenic,jz4780-pwm" +- #pwm-cells: Should be 3. See pwm.txt in this directory for a description + of the cells format. +- clocks : phandle to the external clock. +- clock-names : Should be "ext". + + +Example: + + pwm: pwm@10002000 { + compatible = "ingenic,jz4740-pwm"; + reg = <0x10002000 0x1000>; + + #pwm-cells = <3>; + + clocks = <&ext>; + clock-names = "ext"; + }; diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index 6539c001fe32..a7b134af5e04 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -174,6 +175,8 @@ static int jz4740_pwm_probe(struct platform_device *pdev) jz4740->chip.ops = &jz4740_pwm_ops; jz4740->chip.npwm = NUM_PWM; jz4740->chip.base = -1; + jz4740->chip.of_xlate = of_pwm_xlate_with_flags; + jz4740->chip.of_pwm_n_cells = 3; platform_set_drvdata(pdev, jz4740); @@ -187,9 +190,20 @@ static int jz4740_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&jz4740->chip); } +#ifdef CONFIG_OF +static const struct of_device_id jz4740_pwm_dt_ids[] = { + { .compatible = "ingenic,jz4740-pwm", }, + { .compatible = "ingenic,jz4770-pwm", }, + { .compatible = "ingenic,jz4780-pwm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); +#endif + static struct platform_driver jz4740_pwm_driver = { .driver = { .name = "jz4740-pwm", + .of_match_table = of_match_ptr(jz4740_pwm_dt_ids), }, .probe = jz4740_pwm_probe, .remove = jz4740_pwm_remove, -- cgit v1.2.3 From e7c4b02c2642a5ff3704bd86ff23a6a7a0f4e279 Mon Sep 17 00:00:00 2001 From: Gerald Baeza Date: Fri, 23 Feb 2018 14:36:03 +0100 Subject: dt-bindings: pwm-stm32-lp: Add #pwm-cells STM32 Low-Power Timer supports generic 3 cells PWM to encode PWM number, period and polarity. Signed-off-by: Gerald Baeza Signed-off-by: Fabrice Gasnier Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt index f8338d11fd2b..bd23302e84be 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt @@ -7,6 +7,8 @@ See ../mfd/stm32-lptimer.txt for details about the parent node. Required parameters: - compatible: Must be "st,stm32-pwm-lp". +- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells + bindings defined in pwm.txt. Optional properties: - pinctrl-names: Set to "default". @@ -18,6 +20,7 @@ Example: ... pwm { compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; pinctrl-names = "default"; pinctrl-0 = <&lppwm1_pins>; }; -- cgit v1.2.3 From 8422c7439ea9c4e08198cec7edd5faf3890c4dd7 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 18 Mar 2018 23:28:46 +0000 Subject: dt-bindings: pwm: sunxi: Add new compatible strings The PWM controllers found in the Allwinner A64 and H5 SoCs are fully compatible to the PWM controllers found in the A13 and H3. Add new compatible strings for those SoCs to the binding document, so that they can be safely used, together with a fallback string (preferably "allwinner,sun5i-a13-pwm"). Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-sun4i.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt index 51ff54c8b8ef..2a1affbff45e 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt @@ -7,6 +7,8 @@ Required properties: - "allwinner,sun5i-a13-pwm" - "allwinner,sun7i-a20-pwm" - "allwinner,sun8i-h3-pwm" + - "allwinner,sun50i-a64-pwm", "allwinner,sun5i-a13-pwm" + - "allwinner,sun50i-h5-pwm", "allwinner,sun5i-a13-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. -- cgit v1.2.3 From aa7c49328bd84cda3c4674b70eb10db0a94f89ab Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 9 Mar 2018 20:53:17 +0900 Subject: dt-bindings: pwm: rcar: Add bindings for R-Car M3N support This patch adds bindings for R-Car M3N. No driver update is needed. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index f3bba592d419..35a3b9761ee5 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -11,6 +11,7 @@ Required Properties: - "renesas,pwm-r8a7794": for R-Car E2 - "renesas,pwm-r8a7795": for R-Car H3 - "renesas,pwm-r8a7796": for R-Car M3-W + - "renesas,pwm-r8a77965": for R-Car M3-N - "renesas,pwm-r8a77995": for R-Car D3 - reg: base address and length of the registers block for the PWM. - #pwm-cells: should be 2. See pwm.txt in this directory for a description of -- cgit v1.2.3 From 3cdb741efa02c5053a738d5816b70de11c4d6364 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 27 Mar 2018 08:53:01 -0700 Subject: regulator: qcom: smd: Add pm8998 and pmi8998 regulators Add the pm8998 and pmi8998 regulators as used in the MSM8998 platform. Signed-off-by: Bjorn Andersson Signed-off-by: Mark Brown --- .../bindings/regulator/qcom,smd-rpm-regulator.txt | 48 ++++++++ drivers/regulator/qcom_smd-regulator.c | 121 +++++++++++++++++++++ include/linux/soc/qcom/smd-rpm.h | 1 + 3 files changed, 170 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt index 4e3dfb5b5f16..58a1d97972f5 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt @@ -23,7 +23,9 @@ Regulator nodes are identified by their compatible: "qcom,rpm-pm8916-regulators" "qcom,rpm-pm8941-regulators" "qcom,rpm-pm8994-regulators" + "qcom,rpm-pm8998-regulators" "qcom,rpm-pma8084-regulators" + "qcom,rpm-pmi8998-regulators" - vdd_s1-supply: - vdd_s2-supply: @@ -119,6 +121,38 @@ Regulator nodes are identified by their compatible: Definition: reference to regulator supplying the input pin, as described in the data sheet +- vdd_s1-supply: +- vdd_s2-supply: +- vdd_s3-supply: +- vdd_s4-supply: +- vdd_s5-supply: +- vdd_s6-supply: +- vdd_s7-supply: +- vdd_s8-supply: +- vdd_s9-supply: +- vdd_s10-supply: +- vdd_s11-supply: +- vdd_s12-supply: +- vdd_s13-supply: +- vdd_l1_l27-supply: +- vdd_l20_l24-supply: +- vdd_l26-supply: +- vdd_l2_l8_l17-supply: +- vdd_l3_l11-supply: +- vdd_l4_l5-supply: +- vdd_l6-supply: +- vdd_l7_l12_l14_l15-supply: +- vdd_l9-supply: +- vdd_l10_l23_l25-supply: +- vdd_l13_l19_l21-supply: +- vdd_l16_l28-supply: +- vdd_l18_l22-supply: +- vdd_lvs1_lvs2-supply: + Usage: optional (pmi8998 only) + Value type: + Definition: reference to regulator supplying the input pin, as + described in the data sheet + - vdd_s1-supply: - vdd_s2-supply: - vdd_s3-supply: @@ -148,6 +182,12 @@ Regulator nodes are identified by their compatible: Definition: reference to regulator supplying the input pin, as described in the data sheet +- vdd_bob-supply: + Usage: optional (pmi8998 only) + Value type: + Definition: reference to regulator supplying the input pin, as + described in the data sheet + The regulator node houses sub-nodes for each regulator within the device. Each sub-node is identified using the node's name, with valid values listed for each of the pmics below. @@ -169,11 +209,19 @@ pm8994: l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2 +pm8998: + s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4, + l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, + l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2 + pma8084: s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1 +pmi8998: + bob + The content of each sub-node is defined by the standard binding for regulators - see regulator.txt. diff --git a/drivers/regulator/qcom_smd-regulator.c b/drivers/regulator/qcom_smd-regulator.c index 940fe1b78411..ef51db5f0d9b 100644 --- a/drivers/regulator/qcom_smd-regulator.c +++ b/drivers/regulator/qcom_smd-regulator.c @@ -165,6 +165,15 @@ static const struct regulator_ops rpm_switch_ops = { .is_enabled = rpm_reg_is_enabled, }; +static const struct regulator_ops rpm_bob_ops = { + .enable = rpm_reg_enable, + .disable = rpm_reg_disable, + .is_enabled = rpm_reg_is_enabled, + + .get_voltage = rpm_reg_get_voltage, + .set_voltage = rpm_reg_set_voltage, +}; + static const struct regulator_desc pma8084_hfsmps = { .linear_ranges = (struct regulator_linear_range[]) { REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500), @@ -355,6 +364,64 @@ static const struct regulator_desc pm8994_lnldo = { .ops = &rpm_smps_ldo_ops_fixed, }; +static const struct regulator_desc pm8998_ftsmps = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000), + }, + .n_linear_ranges = 1, + .n_voltages = 259, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_hfsmps = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 216, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_nldo = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_pldo = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 256, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_pldo_lv = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000), + }, + .n_linear_ranges = 1, + .n_voltages = 128, + .ops = &rpm_smps_ldo_ops, +}; + +static const struct regulator_desc pm8998_switch = { + .ops = &rpm_switch_ops, +}; + +static const struct regulator_desc pmi8998_bob = { + .linear_ranges = (struct regulator_linear_range[]) { + REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000), + }, + .n_linear_ranges = 1, + .n_voltages = 84, + .ops = &rpm_bob_ops, +}; + struct rpm_regulator_data { const char *name; u32 type; @@ -544,12 +611,66 @@ static const struct rpm_regulator_data rpm_pm8994_regulators[] = { {} }; +static const struct rpm_regulator_data rpm_pm8998_regulators[] = { + { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" }, + { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" }, + { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" }, + { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" }, + { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" }, + { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" }, + { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" }, + { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" }, + { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" }, + { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" }, + { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" }, + { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" }, + { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" }, + { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" }, + { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" }, + { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" }, + { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" }, + { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" }, + { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" }, + { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" }, + { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" }, + { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" }, + { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" }, + { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" }, + { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" }, + { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" }, + { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" }, + { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" }, + { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" }, + { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" }, + { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" }, + { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" }, + { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" }, + { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" }, + { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" }, + { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" }, + { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" }, + { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" }, + { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" }, + {} +}; + +static const struct rpm_regulator_data rpm_pmi8998_regulators[] = { + { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" }, + {} +}; + static const struct of_device_id rpm_of_match[] = { { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators }, { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators }, { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators }, { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators }, + { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators }, { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators }, + { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators }, {} }; MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 9f5c6e53f3a5..9e4fdd861a51 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -10,6 +10,7 @@ struct qcom_smd_rpm; /* * Constants used for addressing resources in the RPM. */ +#define QCOM_SMD_RPM_BOBB 0x62626f62 #define QCOM_SMD_RPM_BOOST 0x61747362 #define QCOM_SMD_RPM_BUS_CLK 0x316b6c63 #define QCOM_SMD_RPM_BUS_MASTER 0x73616d62 -- cgit v1.2.3 From 7bb5e54515dbcef7c390506c1339bff6bf220b1c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 27 Mar 2018 15:04:25 +0200 Subject: spi: sh-msiof: Document R-Car M3-N support Document support for the MSIOF module in the Renesas M3-N (r8a77965) SoC. No driver update is needed. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index 80710f0f0448..39806329c193 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -10,6 +10,7 @@ Required properties: "renesas,msiof-r8a7794" (R-Car E2) "renesas,msiof-r8a7795" (R-Car H3) "renesas,msiof-r8a7796" (R-Car M3-W) + "renesas,msiof-r8a77965" (R-Car M3-N) "renesas,msiof-sh73a0" (SH-Mobile AG5) "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device) "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device) -- cgit v1.2.3 From de2404701469a7e8d557b8d7b4d35bda5b262cac Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Tue, 27 Mar 2018 09:32:25 +0800 Subject: ASoC: mediatek: remove "simple-mfd" in the example Remove compatible string "simple-mfd" in the example as we have already added devm_of_platform_populate() in the parent driver. Signed-off-by: Ryder Lee Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt index 6df87b97f7cb..e2f7f4951215 100644 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt @@ -53,7 +53,7 @@ See ../arm/mediatek/mediatek,audsys.txt for details about the parent node. Example: audsys: audio-subsystem@11220000 { - compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd"; + compatible = "mediatek,mt2701-audsys", "syscon"; ... afe: audio-controller { -- cgit v1.2.3 From 147395ea40b36b8652b6df3e50a1cb745be75c93 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 28 Mar 2018 11:14:43 +0530 Subject: dt-bindings: mtd-physmap: Add endianness supports Provide a way to specify the endianness to use when accessing a memory-mapped flash. Signed-off-by: Prabhakar Kushwaha Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon --- Documentation/devicetree/bindings/mtd/mtd-physmap.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt index 4a0a48bf4ecb..232fa12e90ef 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt @@ -41,6 +41,13 @@ additional (optional) property is defined: - erase-size : The chip's physical erase block size in bytes. + The device tree may optionally contain endianness property. + little-endian or big-endian : It Represents the endianness that should be used + by the controller to properly read/write data + from/to the flash. If this property is missing, + the endianness is chosen by the system + (potentially based on extra configuration options). + The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. -- cgit v1.2.3 From 961ba15c48dd465fdbef1b9379bd8031c374d62e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 13 Mar 2018 11:30:16 +0100 Subject: mtd: rawnand: marvell: Fix clock resource by adding a register clock On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The binding documentation is updated accordingly. Signed-off-by: Gregory CLEMENT Signed-off-by: Boris Brezillon --- .../devicetree/bindings/mtd/marvell-nand.txt | 5 +++- drivers/mtd/nand/raw/marvell_nand.c | 34 ++++++++++++++++++---- 2 files changed, 32 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt index c08fb477b3c6..e0c790706b9b 100644 --- a/Documentation/devicetree/bindings/mtd/marvell-nand.txt +++ b/Documentation/devicetree/bindings/mtd/marvell-nand.txt @@ -14,7 +14,10 @@ Required properties: - #address-cells: shall be set to 1. Encode the NAND CS. - #size-cells: shall be set to 0. - interrupts: shall define the NAND controller interrupt. -- clocks: shall reference the NAND controller clock. +- clocks: shall reference the NAND controller clocks, the second one is + is only needed for the Armada 7K/8K SoCs +- clock-names: mandatory if there is a second clock, in this case there + should be one clock named "core" and another one named "reg" - marvell,system-controller: Set to retrieve the syscon node that handles NAND controller related registers (only required with the "marvell,armada-8k-nand[-controller]" compatibles). diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index 528a8e0342bd..3d84f4252af4 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -308,6 +308,7 @@ struct marvell_nfc_caps { * @dev: Parent device (used to print error messages) * @regs: NAND controller registers * @ecc_clk: ECC block clock, two times the NAND controller clock + * @reg_clk: Regiters clock * @complete: Completion object to wait for NAND controller events * @assigned_cs: Bitmask describing already assigned CS lines * @chips: List containing all the NAND chips attached to @@ -321,6 +322,7 @@ struct marvell_nfc { struct device *dev; void __iomem *regs; struct clk *ecc_clk; + struct clk *reg_clk; struct completion complete; unsigned long assigned_cs; struct list_head chips; @@ -2757,7 +2759,12 @@ static int marvell_nfc_probe(struct platform_device *pdev) return irq; } - nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL); + nfc->ecc_clk = devm_clk_get(&pdev->dev, "core"); + + /* Managed the legacy case (when the first clock was not named) */ + if (nfc->ecc_clk == ERR_PTR(-ENOENT)) + nfc->ecc_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(nfc->ecc_clk)) return PTR_ERR(nfc->ecc_clk); @@ -2765,12 +2772,24 @@ static int marvell_nfc_probe(struct platform_device *pdev) if (ret) return ret; + nfc->reg_clk = devm_clk_get(&pdev->dev, "reg"); + if (PTR_ERR(nfc->reg_clk) != -ENOENT) { + if (!IS_ERR(nfc->reg_clk)) { + ret = clk_prepare_enable(nfc->reg_clk); + if (ret) + goto unprepare_ecc_clk; + } else { + ret = PTR_ERR(nfc->reg_clk); + goto unprepare_ecc_clk; + } + } + marvell_nfc_disable_int(nfc, NDCR_ALL_INT); marvell_nfc_clear_int(nfc, NDCR_ALL_INT); ret = devm_request_irq(dev, irq, marvell_nfc_isr, 0, "marvell-nfc", nfc); if (ret) - goto unprepare_clk; + goto unprepare_reg_clk; /* Get NAND controller capabilities */ if (pdev->id_entry) @@ -2781,23 +2800,25 @@ static int marvell_nfc_probe(struct platform_device *pdev) if (!nfc->caps) { dev_err(dev, "Could not retrieve NFC caps\n"); ret = -EINVAL; - goto unprepare_clk; + goto unprepare_reg_clk; } /* Init the controller and then probe the chips */ ret = marvell_nfc_init(nfc); if (ret) - goto unprepare_clk; + goto unprepare_reg_clk; platform_set_drvdata(pdev, nfc); ret = marvell_nand_chips_init(dev, nfc); if (ret) - goto unprepare_clk; + goto unprepare_reg_clk; return 0; -unprepare_clk: +unprepare_reg_clk: + clk_disable_unprepare(nfc->reg_clk); +unprepare_ecc_clk: clk_disable_unprepare(nfc->ecc_clk); return ret; @@ -2814,6 +2835,7 @@ static int marvell_nfc_remove(struct platform_device *pdev) dma_release_channel(nfc->dma_chan); } + clk_disable_unprepare(nfc->reg_clk); clk_disable_unprepare(nfc->ecc_clk); return 0; -- cgit v1.2.3 From 15d6f118285f2ffc73fc8de75ecf7c36c3c6fe18 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 21 Mar 2018 09:36:18 +0100 Subject: mtd: rawnand: sunxi: Stop supporting ECC_HW_SYNDROME mode This mode is not used by any existing setup and should not be used because it overwrites the BBMs. Let's just remove it before someone starts using it. Signed-off-by: Boris Brezillon Acked-by: Maxime Ripard Tested-by: Miquel Raynal --- .../devicetree/bindings/mtd/sunxi-nand.txt | 4 +- drivers/mtd/nand/raw/sunxi_nand.c | 155 +++------------------ 2 files changed, 22 insertions(+), 137 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt index 5e13a5cdff03..0734f03bf3d3 100644 --- a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt @@ -24,8 +24,8 @@ Optional properties: - allwinner,rb : shall contain the native Ready/Busy ids. or - rb-gpios : shall contain the gpios used as R/B pins. -- nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft", - "soft_bch" or "none") +- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or + "none") see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings. diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index f5a55c63935c..aad42812a353 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1475,92 +1475,18 @@ pio_fallback: return sunxi_nfc_hw_ecc_write_page(mtd, chip, buf, oob_required, page); } -static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd, - struct nand_chip *chip, - uint8_t *buf, int oob_required, - int page) -{ - struct nand_ecc_ctrl *ecc = &chip->ecc; - unsigned int max_bitflips = 0; - int ret, i, cur_off = 0; - bool raw_mode = false; - - nand_read_page_op(chip, page, 0, NULL, 0); - - sunxi_nfc_hw_ecc_enable(mtd); - - for (i = 0; i < ecc->steps; i++) { - int data_off = i * (ecc->size + ecc->bytes + 4); - int oob_off = data_off + ecc->size; - u8 *data = buf + (i * ecc->size); - u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4)); - - ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob, - oob_off, &cur_off, - &max_bitflips, !i, - oob_required, - page); - if (ret < 0) - return ret; - else if (ret) - raw_mode = true; - } - - if (oob_required) - sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off, - !raw_mode, page); - - sunxi_nfc_hw_ecc_disable(mtd); - - return max_bitflips; -} - -static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd, - struct nand_chip *chip, - const uint8_t *buf, - int oob_required, int page) -{ - struct nand_ecc_ctrl *ecc = &chip->ecc; - int ret, i, cur_off = 0; - - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - - sunxi_nfc_hw_ecc_enable(mtd); - - for (i = 0; i < ecc->steps; i++) { - int data_off = i * (ecc->size + ecc->bytes + 4); - int oob_off = data_off + ecc->size; - const u8 *data = buf + (i * ecc->size); - const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4)); - - ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, - oob, oob_off, &cur_off, - false, page); - if (ret) - return ret; - } - - if (oob_required || (chip->options & NAND_NEED_SCRAMBLING)) - sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, - &cur_off, page); - - sunxi_nfc_hw_ecc_disable(mtd); - - return nand_prog_page_end_op(chip); -} - -static int sunxi_nfc_hw_common_ecc_read_oob(struct mtd_info *mtd, - struct nand_chip *chip, - int page) +static int sunxi_nfc_hw_ecc_read_oob(struct mtd_info *mtd, + struct nand_chip *chip, + int page) { chip->pagebuf = -1; return chip->ecc.read_page(mtd, chip, chip->data_buf, 1, page); } -static int sunxi_nfc_hw_common_ecc_write_oob(struct mtd_info *mtd, - struct nand_chip *chip, - int page) +static int sunxi_nfc_hw_ecc_write_oob(struct mtd_info *mtd, + struct nand_chip *chip, + int page) { int ret; @@ -1801,9 +1727,14 @@ static const struct mtd_ooblayout_ops sunxi_nand_ooblayout_ops = { .free = sunxi_nand_ooblayout_free, }; -static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, - struct nand_ecc_ctrl *ecc, - struct device_node *np) +static void sunxi_nand_hw_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc) +{ + kfree(ecc->priv); +} + +static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc, + struct device_node *np) { static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; struct nand_chip *nand = mtd_to_nand(mtd); @@ -1889,37 +1820,11 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, goto err; } - ecc->read_oob = sunxi_nfc_hw_common_ecc_read_oob; - ecc->write_oob = sunxi_nfc_hw_common_ecc_write_oob; + ecc->read_oob = sunxi_nfc_hw_ecc_read_oob; + ecc->write_oob = sunxi_nfc_hw_ecc_write_oob; mtd_set_ooblayout(mtd, &sunxi_nand_ooblayout_ops); ecc->priv = data; - return 0; - -err: - kfree(data); - - return ret; -} - -static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc) -{ - kfree(ecc->priv); -} - -static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, - struct nand_ecc_ctrl *ecc, - struct device_node *np) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); - struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); - int ret; - - ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np); - if (ret) - return ret; - if (nfc->dmac) { ecc->read_page = sunxi_nfc_hw_ecc_read_page_dma; ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage_dma; @@ -1937,33 +1842,18 @@ static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, ecc->write_oob_raw = nand_write_oob_std; return 0; -} - -static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd, - struct nand_ecc_ctrl *ecc, - struct device_node *np) -{ - int ret; - - ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np); - if (ret) - return ret; - ecc->prepad = 4; - ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page; - ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page; - ecc->read_oob_raw = nand_read_oob_syndrome; - ecc->write_oob_raw = nand_write_oob_syndrome; +err: + kfree(data); - return 0; + return ret; } static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc) { switch (ecc->mode) { case NAND_ECC_HW: - case NAND_ECC_HW_SYNDROME: - sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc); + sunxi_nand_hw_ecc_ctrl_cleanup(ecc); break; case NAND_ECC_NONE: default: @@ -1991,11 +1881,6 @@ static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc, if (ret) return ret; break; - case NAND_ECC_HW_SYNDROME: - ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np); - if (ret) - return ret; - break; case NAND_ECC_NONE: case NAND_ECC_SOFT: break; -- cgit v1.2.3 From 8fa9eb39c614acbabaecefd5507a426b45fa4704 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Fri, 23 Mar 2018 15:38:09 +0800 Subject: dt-bindings: iommu/rockchip: Add clock property Add clock property, since we are going to control clocks in rockchip iommu driver. Signed-off-by: Jeffy Chen Reviewed-by: Robin Murphy Reviewed-by: Rob Herring Signed-off-by: Joerg Roedel --- Documentation/devicetree/bindings/iommu/rockchip,iommu.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt index 2098f7732264..6ecefea1c6f9 100644 --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt @@ -14,6 +14,11 @@ Required properties: "single-master" device, and needs no additional information to associate with its master device. See: Documentation/devicetree/bindings/iommu/iommu.txt +- clocks : A list of clocks required for the IOMMU to be accessible by + the host CPU. +- clock-names : Should contain the following: + "iface" - Main peripheral bus clock (PCLK/HCL) (required) + "aclk" - AXI bus clock (required) Optional properties: - rockchip,disable-mmu-reset : Don't use the mmu reset operation. @@ -27,5 +32,7 @@ Example: reg = <0xff940300 0x100>; interrupts = ; interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; }; -- cgit v1.2.3 From 75530a78de21267f0dc76fbc67d2253e89233d54 Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Tue, 27 Mar 2018 14:43:14 -0700 Subject: dt-bindings: net: Add bindings for National Instruments XGE netdev This adds bindings for the NI XGE 1G/10G network device. Reviewed-by: Rob Herring Signed-off-by: Moritz Fischer Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/nixge.txt | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nixge.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/nixge.txt b/Documentation/devicetree/bindings/net/nixge.txt new file mode 100644 index 000000000000..e55af7f0881a --- /dev/null +++ b/Documentation/devicetree/bindings/net/nixge.txt @@ -0,0 +1,32 @@ +* NI XGE Ethernet controller + +Required properties: +- compatible: Should be "ni,xge-enet-2.00" +- reg: Address and length of the register set for the device +- interrupts: Should contain tx and rx interrupt +- interrupt-names: Should be "rx" and "tx" +- phy-mode: See ethernet.txt file in the same directory. +- phy-handle: See ethernet.txt file in the same directory. +- nvmem-cells: Phandle of nvmem cell containing the MAC address +- nvmem-cell-names: Should be "address" + +Examples (10G generic PHY): + nixge0: ethernet@40000000 { + compatible = "ni,xge-enet-2.00"; + reg = <0x40000000 0x6000>; + + nvmem-cells = <ð1_addr>; + nvmem-cell-names = "address"; + + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + interrupt-parent = <&intc>; + + phy-mode = "xgmii"; + phy-handle = <ðernet_phy1>; + + ethernet_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <4>; + }; + }; -- cgit v1.2.3 From e8de85d5a107352ff428f735b0afc8133bcbc3e5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 26 Jan 2018 19:23:25 -0200 Subject: dt-bindings: fsl-quadspi: Add the example of two SPI NOR Improve the bindings example by adding an example of how to represent two SPI NOR devices. Signed-off-by: Fabio Estevam Acked-by: Han Xu Signed-off-by: Cyrille Pitchen Signed-off-by: Boris Brezillon --- .../devicetree/bindings/mtd/fsl-quadspi.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt index 63d4d626fbd5..483e9cfac1b1 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt @@ -39,3 +39,27 @@ qspi0: quadspi@40044000 { .... }; }; + +Example showing the usage of two SPI NOR devices: + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2>; + status = "okay"; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; -- cgit v1.2.3 From 9217e566bdee4583d0a9ea4879c8f5e004886eac Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 29 Mar 2018 07:29:48 +0200 Subject: of_net: Implement of_get_nvmem_mac_address helper It's common practice to store MAC addresses for network interfaces into nvmem devices. However the code to actually do this in the kernel lacks, so this patch adds of_get_nvmem_mac_address() for drivers to obtain the address from an nvmem cell provider. This is particulary useful on devices where the ethernet interface cannot be configured by the bootloader, for example because it's in an FPGA. Signed-off-by: Mike Looijmans Reviewed-by: Florian Fainelli Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/ethernet.txt | 2 ++ drivers/of/of_net.c | 40 ++++++++++++++++++++++ include/linux/of_net.h | 6 ++++ 3 files changed, 48 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt index 2974e63ba311..cfc376bc977a 100644 --- a/Documentation/devicetree/bindings/net/ethernet.txt +++ b/Documentation/devicetree/bindings/net/ethernet.txt @@ -10,6 +10,8 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. the boot program; should be used in cases where the MAC address assigned to the device by the boot program is different from the "local-mac-address" property; +- nvmem-cells: phandle, reference to an nvmem node for the MAC address; +- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used; - max-speed: number, specifies maximum speed in Mbit/s supported by the device; - max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than the maximum frame size (there's contradiction in the Devicetree diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c index d820f3edd431..53189d4022a6 100644 --- a/drivers/of/of_net.c +++ b/drivers/of/of_net.c @@ -7,6 +7,7 @@ */ #include #include +#include #include #include #include @@ -80,3 +81,42 @@ const void *of_get_mac_address(struct device_node *np) return of_get_mac_addr(np, "address"); } EXPORT_SYMBOL(of_get_mac_address); + +/** + * Obtain the MAC address from an nvmem provider named 'mac-address' through + * device tree. + * On success, copies the new address into memory pointed to by addr and + * returns 0. Returns a negative error code otherwise. + * @np: Device tree node containing the nvmem-cells phandle + * @addr: Pointer to receive the MAC address using ether_addr_copy() + */ +int of_get_nvmem_mac_address(struct device_node *np, void *addr) +{ + struct nvmem_cell *cell; + const void *mac; + size_t len; + int ret; + + cell = of_nvmem_cell_get(np, "mac-address"); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + mac = nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(mac)) + return PTR_ERR(mac); + + if (len < ETH_ALEN || !is_valid_ether_addr(mac)) { + ret = -EINVAL; + } else { + ether_addr_copy(addr, mac); + ret = 0; + } + + kfree(mac); + + return ret; +} +EXPORT_SYMBOL(of_get_nvmem_mac_address); diff --git a/include/linux/of_net.h b/include/linux/of_net.h index 9cd72aab76fe..90d81ee9e6a0 100644 --- a/include/linux/of_net.h +++ b/include/linux/of_net.h @@ -13,6 +13,7 @@ struct net_device; extern int of_get_phy_mode(struct device_node *np); extern const void *of_get_mac_address(struct device_node *np); +extern int of_get_nvmem_mac_address(struct device_node *np, void *addr); extern struct net_device *of_find_net_device_by_node(struct device_node *np); #else static inline int of_get_phy_mode(struct device_node *np) @@ -25,6 +26,11 @@ static inline const void *of_get_mac_address(struct device_node *np) return NULL; } +static inline int of_get_nvmem_mac_address(struct device_node *np, void *addr) +{ + return -ENODEV; +} + static inline struct net_device *of_find_net_device_by_node(struct device_node *np) { return NULL; -- cgit v1.2.3 From 9b85756341c53fd13b4b5e25104c22849274cd0d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 29 Mar 2018 11:02:55 +0100 Subject: dt-bindings: net: renesas-ravb: Add support for r8a77470 SoC Add a new compatible string for the RZ/G1C (R8A77470) SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Acked-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt index b4dc455eb155..c306f55d335b 100644 --- a/Documentation/devicetree/bindings/net/renesas,ravb.txt +++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt @@ -7,6 +7,7 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,etheravb-r8a7743" for the R8A7743 SoC. - "renesas,etheravb-r8a7745" for the R8A7745 SoC. + - "renesas,etheravb-r8a77470" for the R8A77470 SoC. - "renesas,etheravb-r8a7790" for the R8A7790 SoC. - "renesas,etheravb-r8a7791" for the R8A7791 SoC. - "renesas,etheravb-r8a7792" for the R8A7792 SoC. -- cgit v1.2.3 From ff2969c479d97c6221a9835ee0ab4c44513badc6 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Thu, 8 Mar 2018 17:24:57 +0200 Subject: dt-binding: timer: document NPCM7xx timer DT bindings Added device tree binding documentation for Nuvoton NPCM7xx timer. Signed-off-by: Tomer Maimon Acked-by: Rob Herring Reviewed-by: Brendan Higgins Signed-off-by: Daniel Lezcano --- .../bindings/timer/nuvoton,npcm7xx-timer.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt new file mode 100644 index 000000000000..ea22dfe485be --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt @@ -0,0 +1,21 @@ +Nuvoton NPCM7xx timer + +Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit +timer counters. + +Required properties: +- compatible : "nuvoton,npcm750-timer" for Poleg NPCM750. +- reg : Offset and length of the register set for the device. +- interrupts : Contain the timer interrupt with flags for + falling edge. +- clocks : phandle of timer reference clock (usually a 25 MHz clock). + +Example: + +timer@f0008000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = ; + reg = <0xf0008000 0x50>; + clocks = <&clk NPCM7XX_CLK_TIMER>; +}; + -- cgit v1.2.3 From cc01456a0d9a3cbfec85cf23f2ce53323e8fc973 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 28 Mar 2018 11:22:35 +0800 Subject: dt-bindings: timer: tpm: fix typo of clock name The clock name should be ipg instead of igp. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt index b4aa7ddb5b13..f82087b220f4 100644 --- a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt +++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt @@ -15,7 +15,7 @@ Required properties: - interrupts : Should be the clock event device interrupt. - clocks : The clocks provided by the SoC to drive the timer, must contain an entry for each entry in clock-names. -- clock-names : Must include the following entries: "igp" and "per". +- clock-names : Must include the following entries: "ipg" and "per". Example: tpm5: tpm@40260000 { -- cgit v1.2.3 From a5af1fb94ffcad1aff3bc7f8a78dae7ee266f31c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 30 Mar 2018 01:00:34 +0200 Subject: dt-bindings: net: meson-dwmac: add support for the Meson8m2 SoC The Meson8m2 SoC uses a similar (potentially even identical) register layout for the dwmac glue as Meson8b and GXBB. Unfortunately there is no documentation available. Testing shows that both, RMII and RGMII PHYs are working if they are configured as on Meson8b. Add a new compatible string to the documentation so differences (if there are any) between Meson8m2 and the other SoCs can be taken care of within the driver. Signed-off-by: Martin Blumenstingl Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/meson-dwmac.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt index 354dd9896bb5..61cada22ae6c 100644 --- a/Documentation/devicetree/bindings/net/meson-dwmac.txt +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt @@ -9,6 +9,7 @@ Required properties on all platforms: - compatible: Depending on the platform this should be one of: - "amlogic,meson6-dwmac" - "amlogic,meson8b-dwmac" + - "amlogic,meson8m2-dwmac" - "amlogic,meson-gxbb-dwmac" Additionally "snps,dwmac" and any applicable more detailed version number described in net/stmmac.txt @@ -19,13 +20,13 @@ Required properties on all platforms: configuration (for example the PRG_ETHERNET register range on Meson8b and newer) -Required properties on Meson8b and newer: +Required properties on Meson8b, Meson8m2, GXBB and newer: - clock-names: Should contain the following: - "stmmaceth" - see stmmac.txt - "clkin0" - first parent clock of the internal mux - "clkin1" - second parent clock of the internal mux -Optional properties on Meson8b and newer: +Optional properties on Meson8b, Meson8m2, GXBB and newer: - amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided by this driver) in nanoseconds. Allowed values are: 0ns, 2ns, 4ns, 6ns. -- cgit v1.2.3 From a0b007e1ef1cb5b7f8d4be296beeb0a097af57ac Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 29 Mar 2018 11:11:06 +0100 Subject: dt-bindings: rcar-dmac: Document r8a77470 support Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers. Document RZ/G1C (also known as R8A77470) SoC bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 2f5167da1afc..aadfb236d53a 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -18,6 +18,7 @@ Required Properties: Examples with soctypes are: - "renesas,dmac-r8a7743" (RZ/G1M) - "renesas,dmac-r8a7745" (RZ/G1E) + - "renesas,dmac-r8a77470" (RZ/G1C) - "renesas,dmac-r8a7790" (R-Car H2) - "renesas,dmac-r8a7791" (R-Car M2-W) - "renesas,dmac-r8a7792" (R-Car V2H) -- cgit v1.2.3 From 7c7055c7c5c7a7e66395777b72e6693a81831a54 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Tue, 13 Mar 2018 17:42:00 +0100 Subject: dt-bindings: stm32-dma: introduce DMA features bitfield This bitfield intends to address features to be activated within the driver. Initially the mask was only meant for FIFO Threshold management. Backward compatibility is preserved but the meaning of this field has been extended to features instead of only threshold. Signed-off-by: Pierre-Yves MORDRET Reviewed-by: Rob Herring Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/stm32-dma.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt index 0b55718bf889..c5f519097204 100644 --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt @@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells: 0x1: medium 0x2: high 0x3: very high -4. A 32bit mask specifying the DMA FIFO threshold configuration which are device - dependent: - -bit 0-1: Fifo threshold +4. A 32bit bitfield value specifying DMA features which are device dependent: + -bit 0-1: DMA FIFO threshold selection 0x0: 1/4 full FIFO 0x1: 1/2 full FIFO 0x2: 3/4 full FIFO 0x3: full FIFO + Example: usart1: serial@40011000 { -- cgit v1.2.3 From adf38bb0b5956ab5469acb1ca981a9287c7ad1d8 Mon Sep 17 00:00:00 2001 From: Zhichang Yuan Date: Wed, 21 Mar 2018 17:23:02 -0500 Subject: HISI LPC: Support the LPC host on Hip06/Hip07 with DT bindings The low-pin-count (LPC) interface of Hip06/Hip07 accesses I/O port space of peripherals. Implement the LPC host controller driver which performs the I/O operations on the underlying hardware. We don't want to touch existing drivers such as ipmi-bt, so this driver applies the indirect-IO introduced in the previous patch after registering an indirect-IO node to the indirect-IO devices list which will be searched by the I/O accessors to retrieve the host-local I/O port. The driver config is set as a bool instead of a tristate. The reason here is that, by the very nature of the driver providing a logical PIO range, it does not make sense to have this driver as a loadable module. Another more specific reason is that the Huawei D03 board which includes Hip06 SoC requires the LPC bus for UART console, so should be built in. Tested-by: dann frazier Signed-off-by: Zou Rongrong Signed-off-by: Zhichang Yuan Signed-off-by: John Garry Signed-off-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko Acked-by: Rob Herring # dts part --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ++ drivers/bus/Kconfig | 8 + drivers/bus/Makefile | 1 + drivers/bus/hisi_lpc.c | 415 +++++++++++++++++++++ 4 files changed, 457 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 drivers/bus/hisi_lpc.c (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt new file mode 100644 index 000000000000..10bd35f9207f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt @@ -0,0 +1,33 @@ +Hisilicon Hip06 Low Pin Count device + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + Hip06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +Required properties: +- compatible: value should be as follows: + (a) "hisilicon,hip06-lpc" + (b) "hisilicon,hip07-lpc" +- #address-cells: must be 2 which stick to the ISA/EISA binding doc. +- #size-cells: must be 1 which stick to the ISA/EISA binding doc. +- reg: base memory range where the LPC register set is mapped. + +Note: + The node name before '@' must be "isa" to represent the binding stick to the + ISA/EISA binding specification. + +Example: + +isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0xa01b0000 0x0 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; +}; diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 57e011d36a79..a3fad0f0292f 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -65,6 +65,14 @@ config BRCMSTB_GISB_ARB arbiter. This driver provides timeout and target abort error handling and internal bus master decoding. +config HISILICON_LPC + bool "Support for ISA I/O space on HiSilicon Hip06/7" + depends on ARM64 && (ARCH_HISI || COMPILE_TEST) + select INDIRECT_PIO + help + Driver to enable I/O access to devices attached to the Low Pin + Count bus on the HiSilicon Hip06/7 SoC. + config IMX_WEIM bool "Freescale EIM DRIVER" depends on ARCH_MXC diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 9bcd0bf3954b..50bb12a971a0 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_ARM_CCI) += arm-cci.o obj-$(CONFIG_ARM_CCN) += arm-ccn.o +obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_MIPS_CDMM) += mips_cdmm.o diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c new file mode 100644 index 000000000000..6123bff3215f --- /dev/null +++ b/drivers/bus/hisi_lpc.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan + * Author: Zou Rongrong + * Author: John Garry + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "hisi-lpc" + +/* + * Setting this bit means each IO operation will target a different port + * address; 0 means repeated IO operations will use the same port, + * such as BT. + */ +#define FG_INCRADDR_LPC 0x02 + +struct lpc_cycle_para { + unsigned int opflags; + unsigned int csize; /* data length of each operation */ +}; + +struct hisi_lpc_dev { + spinlock_t cycle_lock; + void __iomem *membase; + struct logic_pio_hwaddr *io_host; +}; + +/* The max IO cycle counts supported is four per operation at maximum */ +#define LPC_MAX_DWIDTH 4 + +#define LPC_REG_STARTUP_SIGNAL 0x00 +#define LPC_REG_STARTUP_SIGNAL_START BIT(0) +#define LPC_REG_OP_STATUS 0x04 +#define LPC_REG_OP_STATUS_IDLE BIT(0) +#define LPC_REG_OP_STATUS_FINISHED BIT(1) +#define LPC_REG_OP_LEN 0x10 /* LPC cycles count per start */ +#define LPC_REG_CMD 0x14 +#define LPC_REG_CMD_OP BIT(0) /* 0: read, 1: write */ +#define LPC_REG_CMD_SAMEADDR BIT(3) +#define LPC_REG_ADDR 0x20 /* target address */ +#define LPC_REG_WDATA 0x24 /* write FIFO */ +#define LPC_REG_RDATA 0x28 /* read FIFO */ + +/* The minimal nanosecond interval for each query on LPC cycle status */ +#define LPC_NSEC_PERWAIT 100 + +/* + * The maximum waiting time is about 128us. It is specific for stream I/O, + * such as ins. + * + * The fastest IO cycle time is about 390ns, but the worst case will wait + * for extra 256 lpc clocks, so (256 + 13) * 30ns = 8 us. The maximum burst + * cycles is 16. So, the maximum waiting time is about 128us under worst + * case. + * + * Choose 1300 as the maximum. + */ +#define LPC_MAX_WAITCNT 1300 + +/* About 10us. This is specific for single IO operations, such as inb */ +#define LPC_PEROP_WAITCNT 100 + +static int wait_lpc_idle(unsigned char *mbase, unsigned int waitcnt) +{ + u32 status; + + do { + status = readl(mbase + LPC_REG_OP_STATUS); + if (status & LPC_REG_OP_STATUS_IDLE) + return (status & LPC_REG_OP_STATUS_FINISHED) ? 0 : -EIO; + ndelay(LPC_NSEC_PERWAIT); + } while (--waitcnt); + + return -ETIME; +} + +/* + * hisi_lpc_target_in - trigger a series of LPC cycles for read operation + * @lpcdev: pointer to hisi lpc device + * @para: some parameters used to control the lpc I/O operations + * @addr: the lpc I/O target port address + * @buf: where the read back data is stored + * @opcnt: how many I/O operations required, i.e. data width + * + * Returns 0 on success, non-zero on fail. + */ +static int hisi_lpc_target_in(struct hisi_lpc_dev *lpcdev, + struct lpc_cycle_para *para, unsigned long addr, + unsigned char *buf, unsigned long opcnt) +{ + unsigned int cmd_word; + unsigned int waitcnt; + unsigned long flags; + int ret; + + if (!buf || !opcnt || !para || !para->csize || !lpcdev) + return -EINVAL; + + cmd_word = 0; /* IO mode, Read */ + waitcnt = LPC_PEROP_WAITCNT; + if (!(para->opflags & FG_INCRADDR_LPC)) { + cmd_word |= LPC_REG_CMD_SAMEADDR; + waitcnt = LPC_MAX_WAITCNT; + } + + /* whole operation must be atomic */ + spin_lock_irqsave(&lpcdev->cycle_lock, flags); + + writel_relaxed(opcnt, lpcdev->membase + LPC_REG_OP_LEN); + writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD); + writel_relaxed(addr, lpcdev->membase + LPC_REG_ADDR); + + writel(LPC_REG_STARTUP_SIGNAL_START, + lpcdev->membase + LPC_REG_STARTUP_SIGNAL); + + /* whether the operation is finished */ + ret = wait_lpc_idle(lpcdev->membase, waitcnt); + if (ret) { + spin_unlock_irqrestore(&lpcdev->cycle_lock, flags); + return ret; + } + + readsb(lpcdev->membase + LPC_REG_RDATA, buf, opcnt); + + spin_unlock_irqrestore(&lpcdev->cycle_lock, flags); + + return 0; +} + +/* + * hisi_lpc_target_out - trigger a series of LPC cycles for write operation + * @lpcdev: pointer to hisi lpc device + * @para: some parameters used to control the lpc I/O operations + * @addr: the lpc I/O target port address + * @buf: where the data to be written is stored + * @opcnt: how many I/O operations required, i.e. data width + * + * Returns 0 on success, non-zero on fail. + */ +static int hisi_lpc_target_out(struct hisi_lpc_dev *lpcdev, + struct lpc_cycle_para *para, unsigned long addr, + const unsigned char *buf, unsigned long opcnt) +{ + unsigned int waitcnt; + unsigned long flags; + u32 cmd_word; + int ret; + + if (!buf || !opcnt || !para || !lpcdev) + return -EINVAL; + + /* default is increasing address */ + cmd_word = LPC_REG_CMD_OP; /* IO mode, write */ + waitcnt = LPC_PEROP_WAITCNT; + if (!(para->opflags & FG_INCRADDR_LPC)) { + cmd_word |= LPC_REG_CMD_SAMEADDR; + waitcnt = LPC_MAX_WAITCNT; + } + + spin_lock_irqsave(&lpcdev->cycle_lock, flags); + + writel_relaxed(opcnt, lpcdev->membase + LPC_REG_OP_LEN); + writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD); + writel_relaxed(addr, lpcdev->membase + LPC_REG_ADDR); + + writesb(lpcdev->membase + LPC_REG_WDATA, buf, opcnt); + + writel(LPC_REG_STARTUP_SIGNAL_START, + lpcdev->membase + LPC_REG_STARTUP_SIGNAL); + + /* whether the operation is finished */ + ret = wait_lpc_idle(lpcdev->membase, waitcnt); + + spin_unlock_irqrestore(&lpcdev->cycle_lock, flags); + + return ret; +} + +static unsigned long hisi_lpc_pio_to_addr(struct hisi_lpc_dev *lpcdev, + unsigned long pio) +{ + return pio - lpcdev->io_host->io_start + lpcdev->io_host->hw_start; +} + +/* + * hisi_lpc_comm_in - input the data in a single operation + * @hostdata: pointer to the device information relevant to LPC controller + * @pio: the target I/O port address + * @dwidth: the data length required to read from the target I/O port + * + * When success, data is returned. Otherwise, ~0 is returned. + */ +static u32 hisi_lpc_comm_in(void *hostdata, unsigned long pio, size_t dwidth) +{ + struct hisi_lpc_dev *lpcdev = hostdata; + struct lpc_cycle_para iopara; + unsigned long addr; + u32 rd_data = 0; + int ret; + + if (!lpcdev || !dwidth || dwidth > LPC_MAX_DWIDTH) + return ~0; + + addr = hisi_lpc_pio_to_addr(lpcdev, pio); + + iopara.opflags = FG_INCRADDR_LPC; + iopara.csize = dwidth; + + ret = hisi_lpc_target_in(lpcdev, &iopara, addr, + (unsigned char *)&rd_data, dwidth); + if (ret) + return ~0; + + return le32_to_cpu(rd_data); +} + +/* + * hisi_lpc_comm_out - output the data in a single operation + * @hostdata: pointer to the device information relevant to LPC controller + * @pio: the target I/O port address + * @val: a value to be output from caller, maximum is four bytes + * @dwidth: the data width required writing to the target I/O port + * + * This function corresponds to out(b,w,l) only. + */ +static void hisi_lpc_comm_out(void *hostdata, unsigned long pio, + u32 val, size_t dwidth) +{ + struct hisi_lpc_dev *lpcdev = hostdata; + struct lpc_cycle_para iopara; + const unsigned char *buf; + unsigned long addr; + + if (!lpcdev || !dwidth || dwidth > LPC_MAX_DWIDTH) + return; + + val = cpu_to_le32(val); + + buf = (const unsigned char *)&val; + addr = hisi_lpc_pio_to_addr(lpcdev, pio); + + iopara.opflags = FG_INCRADDR_LPC; + iopara.csize = dwidth; + + hisi_lpc_target_out(lpcdev, &iopara, addr, buf, dwidth); +} + +/* + * hisi_lpc_comm_ins - input the data in the buffer in multiple operations + * @hostdata: pointer to the device information relevant to LPC controller + * @pio: the target I/O port address + * @buffer: a buffer where read/input data bytes are stored + * @dwidth: the data width required writing to the target I/O port + * @count: how many data units whose length is dwidth will be read + * + * When success, the data read back is stored in buffer pointed by buffer. + * Returns 0 on success, -errno otherwise. + */ +static u32 hisi_lpc_comm_ins(void *hostdata, unsigned long pio, void *buffer, + size_t dwidth, unsigned int count) +{ + struct hisi_lpc_dev *lpcdev = hostdata; + unsigned char *buf = buffer; + struct lpc_cycle_para iopara; + unsigned long addr; + + if (!lpcdev || !buf || !count || !dwidth || dwidth > LPC_MAX_DWIDTH) + return -EINVAL; + + iopara.opflags = 0; + if (dwidth > 1) + iopara.opflags |= FG_INCRADDR_LPC; + iopara.csize = dwidth; + + addr = hisi_lpc_pio_to_addr(lpcdev, pio); + + do { + int ret; + + ret = hisi_lpc_target_in(lpcdev, &iopara, addr, buf, dwidth); + if (ret) + return ret; + buf += dwidth; + } while (--count); + + return 0; +} + +/* + * hisi_lpc_comm_outs - output the data in the buffer in multiple operations + * @hostdata: pointer to the device information relevant to LPC controller + * @pio: the target I/O port address + * @buffer: a buffer where write/output data bytes are stored + * @dwidth: the data width required writing to the target I/O port + * @count: how many data units whose length is dwidth will be written + */ +static void hisi_lpc_comm_outs(void *hostdata, unsigned long pio, + const void *buffer, size_t dwidth, + unsigned int count) +{ + struct hisi_lpc_dev *lpcdev = hostdata; + struct lpc_cycle_para iopara; + const unsigned char *buf = buffer; + unsigned long addr; + + if (!lpcdev || !buf || !count || !dwidth || dwidth > LPC_MAX_DWIDTH) + return; + + iopara.opflags = 0; + if (dwidth > 1) + iopara.opflags |= FG_INCRADDR_LPC; + iopara.csize = dwidth; + + addr = hisi_lpc_pio_to_addr(lpcdev, pio); + do { + if (hisi_lpc_target_out(lpcdev, &iopara, addr, buf, dwidth)) + break; + buf += dwidth; + } while (--count); +} + +static const struct logic_pio_host_ops hisi_lpc_ops = { + .in = hisi_lpc_comm_in, + .out = hisi_lpc_comm_out, + .ins = hisi_lpc_comm_ins, + .outs = hisi_lpc_comm_outs, +}; + +/* + * hisi_lpc_probe - the probe callback function for hisi lpc host, + * will finish all the initialization. + * @pdev: the platform device corresponding to hisi lpc host + * + * Returns 0 on success, non-zero on fail. + */ +static int hisi_lpc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct acpi_device *acpi_device = ACPI_COMPANION(dev); + struct logic_pio_hwaddr *range; + struct hisi_lpc_dev *lpcdev; + resource_size_t io_end; + struct resource *res; + int ret; + + lpcdev = devm_kzalloc(dev, sizeof(*lpcdev), GFP_KERNEL); + if (!lpcdev) + return -ENOMEM; + + spin_lock_init(&lpcdev->cycle_lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + lpcdev->membase = devm_ioremap_resource(dev, res); + if (IS_ERR(lpcdev->membase)) + return PTR_ERR(lpcdev->membase); + + range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL); + if (!range) + return -ENOMEM; + + range->fwnode = dev->fwnode; + range->flags = LOGIC_PIO_INDIRECT; + range->size = PIO_INDIRECT_SIZE; + + ret = logic_pio_register_range(range); + if (ret) { + dev_err(dev, "register IO range failed (%d)!\n", ret); + return ret; + } + lpcdev->io_host = range; + + /* register the LPC host PIO resources */ + if (!acpi_device) { + ret = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (ret) + return ret; + } + + lpcdev->io_host->hostdata = lpcdev; + lpcdev->io_host->ops = &hisi_lpc_ops; + + io_end = lpcdev->io_host->io_start + lpcdev->io_host->size; + dev_info(dev, "registered range [%pa - %pa]\n", + &lpcdev->io_host->io_start, &io_end); + + return ret; +} + +static const struct of_device_id hisi_lpc_of_match[] = { + { .compatible = "hisilicon,hip06-lpc", }, + { .compatible = "hisilicon,hip07-lpc", }, + {} +}; + +static struct platform_driver hisi_lpc_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = hisi_lpc_of_match, + }, + .probe = hisi_lpc_probe, +}; +builtin_platform_driver(hisi_lpc_driver); -- cgit v1.2.3 From 730b35e08c5721dece9e624a33481d78cde221df Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Tue, 3 Apr 2018 21:11:48 +0200 Subject: dt-bindings: i2c: add binding for Socionext SynQuacer I2C Add a binding for the I2C controller that can be found in the Socionext SynQuacer SoC. Signed-off-by: Ard Biesheuvel Reviewed-by: Rob Herring Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-synquacer.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-synquacer.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt new file mode 100644 index 000000000000..72f4a2f0fedc --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-synquacer.txt @@ -0,0 +1,29 @@ +Socionext SynQuacer I2C + +Required properties: +- compatible : Must be "socionext,synquacer-i2c" +- reg : Offset and length of the register set for the device +- interrupts : A single interrupt specifier +- #address-cells : Must be <1>; +- #size-cells : Must be <0>; +- clock-names : Must contain "pclk". +- clocks : Must contain an entry for each name in clock-names. + (See the common clock bindings.) + +Optional properties: +- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and + Fast modes are supported, possible values are 100000 and + 400000. + +Example : + + i2c@51210000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x51210000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "pclk"; + clocks = <&clk_i2c>; + clock-frequency = <400000>; + }; -- cgit v1.2.3 From 89727949ea1e5f8ec481cba4d5c71c32d8bff3bc Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 21 Mar 2018 09:20:10 -0500 Subject: dt-bindings: documentation: add clock bindings information for Stratix10 Document that Stratix10 clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Stratix10 platform. Signed-off-by: Dinh Nguyen Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/intc_stratix10.txt | 20 ++++++ include/dt-bindings/clock/stratix10-clock.h | 84 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/intc_stratix10.txt create mode 100644 include/dt-bindings/clock/stratix10-clock.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt new file mode 100644 index 000000000000..9f4ec5cb5c6b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intc_stratix10.txt @@ -0,0 +1,20 @@ +Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be + "intel,stratix10-clkmgr" + +- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. + +- #clock-cells : from common clock binding, shall be set to 1. + +Example: + clkmgr: clock-controller@ffd10000 { + compatible = "intel,stratix10-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/stratix10-clock.h b/include/dt-bindings/clock/stratix10-clock.h new file mode 100644 index 000000000000..0ac1c90a18bf --- /dev/null +++ b/include/dt-bindings/clock/stratix10-clock.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017, Intel Corporation + */ + +#ifndef __STRATIX10_CLOCK_H +#define __STRATIX10_CLOCK_H + +/* fixed rate clocks */ +#define STRATIX10_OSC1 0 +#define STRATIX10_CB_INTOSC_HS_DIV2_CLK 1 +#define STRATIX10_CB_INTOSC_LS_CLK 2 +#define STRATIX10_F2S_FREE_CLK 3 + +/* fixed factor clocks */ +#define STRATIX10_L4_SYS_FREE_CLK 4 +#define STRATIX10_MPU_PERIPH_CLK 5 +#define STRATIX10_MPU_L2RAM_CLK 6 +#define STRATIX10_SDMMC_CIU_CLK 7 + +/* PLL clocks */ +#define STRATIX10_MAIN_PLL_CLK 8 +#define STRATIX10_PERIPH_PLL_CLK 9 +#define STRATIX10_BOOT_CLK 10 + +/* Periph clocks */ +#define STRATIX10_MAIN_MPU_BASE_CLK 11 +#define STRATIX10_MAIN_NOC_BASE_CLK 12 +#define STRATIX10_MAIN_EMACA_CLK 13 +#define STRATIX10_MAIN_EMACB_CLK 14 +#define STRATIX10_MAIN_EMAC_PTP_CLK 15 +#define STRATIX10_MAIN_GPIO_DB_CLK 16 +#define STRATIX10_MAIN_SDMMC_CLK 17 +#define STRATIX10_MAIN_S2F_USR0_CLK 18 +#define STRATIX10_MAIN_S2F_USR1_CLK 19 +#define STRATIX10_MAIN_PSI_REF_CLK 20 + +#define STRATIX10_PERI_MPU_BASE_CLK 21 +#define STRATIX10_PERI_NOC_BASE_CLK 22 +#define STRATIX10_PERI_EMACA_CLK 23 +#define STRATIX10_PERI_EMACB_CLK 24 +#define STRATIX10_PERI_EMAC_PTP_CLK 25 +#define STRATIX10_PERI_GPIO_DB_CLK 26 +#define STRATIX10_PERI_SDMMC_CLK 27 +#define STRATIX10_PERI_S2F_USR0_CLK 28 +#define STRATIX10_PERI_S2F_USR1_CLK 29 +#define STRATIX10_PERI_PSI_REF_CLK 30 + +#define STRATIX10_MPU_FREE_CLK 31 +#define STRATIX10_NOC_FREE_CLK 32 +#define STRATIX10_S2F_USR0_CLK 33 +#define STRATIX10_NOC_CLK 34 +#define STRATIX10_EMAC_A_FREE_CLK 35 +#define STRATIX10_EMAC_B_FREE_CLK 36 +#define STRATIX10_EMAC_PTP_FREE_CLK 37 +#define STRATIX10_GPIO_DB_FREE_CLK 38 +#define STRATIX10_SDMMC_FREE_CLK 39 +#define STRATIX10_S2F_USER1_FREE_CLK 40 +#define STRATIX10_PSI_REF_FREE_CLK 41 + +/* Gate clocks */ +#define STRATIX10_MPU_CLK 42 +#define STRATIX10_L4_MAIN_CLK 43 +#define STRATIX10_L4_MP_CLK 44 +#define STRATIX10_L4_SP_CLK 45 +#define STRATIX10_CS_AT_CLK 46 +#define STRATIX10_CS_TRACE_CLK 47 +#define STRATIX10_CS_PDBG_CLK 48 +#define STRATIX10_CS_TIMER_CLK 49 +#define STRATIX10_S2F_USER0_CLK 50 +#define STRATIX10_S2F_USER1_CLK 51 +#define STRATIX10_EMAC0_CLK 52 +#define STRATIX10_EMAC1_CLK 53 +#define STRATIX10_EMAC2_CLK 54 +#define STRATIX10_EMAC_PTP_CLK 55 +#define STRATIX10_GPIO_DB_CLK 56 +#define STRATIX10_SDMMC_CLK 57 +#define STRATIX10_PSI_REF_CLK 58 +#define STRATIX10_USB_CLK 59 +#define STRATIX10_SPI_M_CLK 60 +#define STRATIX10_NAND_CLK 61 +#define STRATIX10_NUM_CLKS 62 + +#endif /* __STRATIX10_CLOCK_H */ -- cgit v1.2.3 From 0c123a4fbbf4672fb8c357158eb9368f3d3660f2 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Tue, 20 Mar 2018 10:24:03 +0800 Subject: dt-bindings: imx: update clock doc for imx6sll Add clock binding doc update for imx6sll. Signed-off-by: Bai Ping Acked-by: Dong Aisheng Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/imx6sll-clock.txt | 36 ++++ include/dt-bindings/clock/imx6sll-clock.h | 202 +++++++++++++++++++++ 2 files changed, 238 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx6sll-clock.txt create mode 100644 include/dt-bindings/clock/imx6sll-clock.h (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/clock/imx6sll-clock.txt b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt new file mode 100644 index 000000000000..fee849d5fdd1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6sll-clock.txt @@ -0,0 +1,36 @@ +* Clock bindings for Freescale i.MX6 SLL + +Required properties: +- compatible: Should be "fsl,imx6sll-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h +for the full list of i.MX6 SLL clock IDs. + +Examples: + +#include + +clks: clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; +}; + +uart1: serial@2020000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; +}; diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h new file mode 100644 index 000000000000..151111e68f4f --- /dev/null +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H +#define __DT_BINDINGS_CLOCK_IMX6SLL_H + +#define IMX6SLL_CLK_DUMMY 0 +#define IMX6SLL_CLK_CKIL 1 +#define IMX6SLL_CLK_OSC 2 +#define IMX6SLL_PLL1_BYPASS_SRC 3 +#define IMX6SLL_PLL2_BYPASS_SRC 4 +#define IMX6SLL_PLL3_BYPASS_SRC 5 +#define IMX6SLL_PLL4_BYPASS_SRC 6 +#define IMX6SLL_PLL5_BYPASS_SRC 7 +#define IMX6SLL_PLL6_BYPASS_SRC 8 +#define IMX6SLL_PLL7_BYPASS_SRC 9 +#define IMX6SLL_CLK_PLL1 10 +#define IMX6SLL_CLK_PLL2 11 +#define IMX6SLL_CLK_PLL3 12 +#define IMX6SLL_CLK_PLL4 13 +#define IMX6SLL_CLK_PLL5 14 +#define IMX6SLL_CLK_PLL6 15 +#define IMX6SLL_CLK_PLL7 16 +#define IMX6SLL_PLL1_BYPASS 17 +#define IMX6SLL_PLL2_BYPASS 18 +#define IMX6SLL_PLL3_BYPASS 19 +#define IMX6SLL_PLL4_BYPASS 20 +#define IMX6SLL_PLL5_BYPASS 21 +#define IMX6SLL_PLL6_BYPASS 22 +#define IMX6SLL_PLL7_BYPASS 23 +#define IMX6SLL_CLK_PLL1_SYS 24 +#define IMX6SLL_CLK_PLL2_BUS 25 +#define IMX6SLL_CLK_PLL3_USB_OTG 26 +#define IMX6SLL_CLK_PLL4_AUDIO 27 +#define IMX6SLL_CLK_PLL5_VIDEO 28 +#define IMX6SLL_CLK_PLL6_ENET 29 +#define IMX6SLL_CLK_PLL7_USB_HOST 30 +#define IMX6SLL_CLK_USBPHY1 31 +#define IMX6SLL_CLK_USBPHY2 32 +#define IMX6SLL_CLK_USBPHY1_GATE 33 +#define IMX6SLL_CLK_USBPHY2_GATE 34 +#define IMX6SLL_CLK_PLL2_PFD0 35 +#define IMX6SLL_CLK_PLL2_PFD1 36 +#define IMX6SLL_CLK_PLL2_PFD2 37 +#define IMX6SLL_CLK_PLL2_PFD3 38 +#define IMX6SLL_CLK_PLL3_PFD0 39 +#define IMX6SLL_CLK_PLL3_PFD1 40 +#define IMX6SLL_CLK_PLL3_PFD2 41 +#define IMX6SLL_CLK_PLL3_PFD3 42 +#define IMX6SLL_CLK_PLL4_POST_DIV 43 +#define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 +#define IMX6SLL_CLK_PLL5_POST_DIV 45 +#define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 +#define IMX6SLL_CLK_PLL2_198M 47 +#define IMX6SLL_CLK_PLL3_120M 48 +#define IMX6SLL_CLK_PLL3_80M 49 +#define IMX6SLL_CLK_PLL3_60M 50 +#define IMX6SLL_CLK_STEP 51 +#define IMX6SLL_CLK_PLL1_SW 52 +#define IMX6SLL_CLK_AXI_ALT_SEL 53 +#define IMX6SLL_CLK_AXI_SEL 54 +#define IMX6SLL_CLK_PERIPH_PRE 55 +#define IMX6SLL_CLK_PERIPH2_PRE 56 +#define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 +#define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 +#define IMX6SLL_CLK_PERCLK_SEL 59 +#define IMX6SLL_CLK_USDHC1_SEL 60 +#define IMX6SLL_CLK_USDHC2_SEL 61 +#define IMX6SLL_CLK_USDHC3_SEL 62 +#define IMX6SLL_CLK_SSI1_SEL 63 +#define IMX6SLL_CLK_SSI2_SEL 64 +#define IMX6SLL_CLK_SSI3_SEL 65 +#define IMX6SLL_CLK_PXP_SEL 66 +#define IMX6SLL_CLK_LCDIF_PRE_SEL 67 +#define IMX6SLL_CLK_LCDIF_SEL 68 +#define IMX6SLL_CLK_EPDC_PRE_SEL 69 +#define IMX6SLL_CLK_SPDIF_SEL 70 +#define IMX6SLL_CLK_ECSPI_SEL 71 +#define IMX6SLL_CLK_UART_SEL 72 +#define IMX6SLL_CLK_ARM 73 +#define IMX6SLL_CLK_PERIPH 74 +#define IMX6SLL_CLK_PERIPH2 75 +#define IMX6SLL_CLK_PERIPH2_CLK2 76 +#define IMX6SLL_CLK_PERIPH_CLK2 77 +#define IMX6SLL_CLK_MMDC_PODF 78 +#define IMX6SLL_CLK_AXI_PODF 79 +#define IMX6SLL_CLK_AHB 80 +#define IMX6SLL_CLK_IPG 81 +#define IMX6SLL_CLK_PERCLK 82 +#define IMX6SLL_CLK_USDHC1_PODF 83 +#define IMX6SLL_CLK_USDHC2_PODF 84 +#define IMX6SLL_CLK_USDHC3_PODF 85 +#define IMX6SLL_CLK_SSI1_PRED 86 +#define IMX6SLL_CLK_SSI2_PRED 87 +#define IMX6SLL_CLK_SSI3_PRED 88 +#define IMX6SLL_CLK_SSI1_PODF 89 +#define IMX6SLL_CLK_SSI2_PODF 90 +#define IMX6SLL_CLK_SSI3_PODF 91 +#define IMX6SLL_CLK_PXP_PODF 92 +#define IMX6SLL_CLK_LCDIF_PRED 93 +#define IMX6SLL_CLK_LCDIF_PODF 94 +#define IMX6SLL_CLK_EPDC_SEL 95 +#define IMX6SLL_CLK_EPDC_PODF 96 +#define IMX6SLL_CLK_SPDIF_PRED 97 +#define IMX6SLL_CLK_SPDIF_PODF 98 +#define IMX6SLL_CLK_ECSPI_PODF 99 +#define IMX6SLL_CLK_UART_PODF 100 + +/* CCGR 0 */ +#define IMX6SLL_CLK_AIPSTZ1 101 +#define IMX6SLL_CLK_AIPSTZ2 102 +#define IMX6SLL_CLK_DCP 103 +#define IMX6SLL_CLK_UART2_IPG 104 +#define IMX6SLL_CLK_UART2_SERIAL 105 + +/* CCGR 1 */ +#define IMX6SLL_CLK_ECSPI1 106 +#define IMX6SLL_CLK_ECSPI2 107 +#define IMX6SLL_CLK_ECSPI3 108 +#define IMX6SLL_CLK_ECSPI4 109 +#define IMX6SLL_CLK_UART3_IPG 110 +#define IMX6SLL_CLK_UART3_SERIAL 111 +#define IMX6SLL_CLK_UART4_IPG 112 +#define IMX6SLL_CLK_UART4_SERIAL 113 +#define IMX6SLL_CLK_EPIT1 114 +#define IMX6SLL_CLK_EPIT2 115 +#define IMX6SLL_CLK_GPT_BUS 116 +#define IMX6SLL_CLK_GPT_SERIAL 117 + +/* CCGR2 */ +#define IMX6SLL_CLK_CSI 118 +#define IMX6SLL_CLK_I2C1 119 +#define IMX6SLL_CLK_I2C2 120 +#define IMX6SLL_CLK_I2C3 121 +#define IMX6SLL_CLK_OCOTP 122 +#define IMX6SLL_CLK_LCDIF_APB 123 +#define IMX6SLL_CLK_PXP 124 + +/* CCGR3 */ +#define IMX6SLL_CLK_UART5_IPG 125 +#define IMX6SLL_CLK_UART5_SERIAL 126 +#define IMX6SLL_CLK_EPDC_AXI 127 +#define IMX6SLL_CLK_EPDC_PIX 128 +#define IMX6SLL_CLK_LCDIF_PIX 129 +#define IMX6SLL_CLK_WDOG1 130 +#define IMX6SLL_CLK_MMDC_P0_FAST 131 +#define IMX6SLL_CLK_MMDC_P0_IPG 132 +#define IMX6SLL_CLK_OCRAM 133 + +/* CCGR4 */ +#define IMX6SLL_CLK_PWM1 134 +#define IMX6SLL_CLK_PWM2 135 +#define IMX6SLL_CLK_PWM3 136 +#define IMX6SLL_CLK_PWM4 137 + +/* CCGR 5 */ +#define IMX6SLL_CLK_ROM 138 +#define IMX6SLL_CLK_SDMA 139 +#define IMX6SLL_CLK_KPP 140 +#define IMX6SLL_CLK_WDOG2 141 +#define IMX6SLL_CLK_SPBA 142 +#define IMX6SLL_CLK_SPDIF 143 +#define IMX6SLL_CLK_SPDIF_GCLK 144 +#define IMX6SLL_CLK_SSI1 145 +#define IMX6SLL_CLK_SSI1_IPG 146 +#define IMX6SLL_CLK_SSI2 147 +#define IMX6SLL_CLK_SSI2_IPG 148 +#define IMX6SLL_CLK_SSI3 149 +#define IMX6SLL_CLK_SSI3_IPG 150 +#define IMX6SLL_CLK_UART1_IPG 151 +#define IMX6SLL_CLK_UART1_SERIAL 152 + +/* CCGR 6 */ +#define IMX6SLL_CLK_USBOH3 153 +#define IMX6SLL_CLK_USDHC1 154 +#define IMX6SLL_CLK_USDHC2 155 +#define IMX6SLL_CLK_USDHC3 156 + +#define IMX6SLL_CLK_IPP_DI0 157 +#define IMX6SLL_CLK_IPP_DI1 158 +#define IMX6SLL_CLK_LDB_DI0_SEL 159 +#define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 +#define IMX6SLL_CLK_LDB_DI0_DIV_7 161 +#define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 +#define IMX6SLL_CLK_LDB_DI0 163 +#define IMX6SLL_CLK_LDB_DI1_SEL 164 +#define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 +#define IMX6SLL_CLK_LDB_DI1_DIV_7 166 +#define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 +#define IMX6SLL_CLK_LDB_DI1 168 +#define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 +#define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 +#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 +#define IMX6SLL_CLK_EXTERN_AUDIO 172 + +#define IMX6SLL_CLK_END 173 + +#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ -- cgit v1.2.3 From ddc141e5c6be3c5f3f900ba306fe7c7fdb4258cc Mon Sep 17 00:00:00 2001 From: Oliver O'Halloran Date: Fri, 6 Apr 2018 15:21:15 +1000 Subject: doc/devicetree: Persistent memory region bindings Add device-tree binding documentation for the nvdimm region driver. Cc: devicetree@vger.kernel.org Signed-off-by: Oliver O'Halloran Acked-by: Michael Ellerman Signed-off-by: Dan Williams --- .../devicetree/bindings/pmem/pmem-region.txt | 65 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/pmem/pmem-region.txt (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/pmem/pmem-region.txt b/Documentation/devicetree/bindings/pmem/pmem-region.txt new file mode 100644 index 000000000000..5cfa4f016a00 --- /dev/null +++ b/Documentation/devicetree/bindings/pmem/pmem-region.txt @@ -0,0 +1,65 @@ +Device-tree bindings for persistent memory regions +----------------------------------------------------- + +Persistent memory refers to a class of memory devices that are: + + a) Usable as main system memory (i.e. cacheable), and + b) Retain their contents across power failure. + +Given b) it is best to think of persistent memory as a kind of memory mapped +storage device. To ensure data integrity the operating system needs to manage +persistent regions separately to the normal memory pool. To aid with that this +binding provides a standardised interface for discovering where persistent +memory regions exist inside the physical address space. + +Bindings for the region nodes: +----------------------------- + +Required properties: + - compatible = "pmem-region" + + - reg = ; + The reg property should specificy an address range that is + translatable to a system physical address range. This address + range should be mappable as normal system memory would be + (i.e cacheable). + + If the reg property contains multiple address ranges + each address range will be treated as though it was specified + in a separate device node. Having multiple address ranges in a + node implies no special relationship between the two ranges. + +Optional properties: + - Any relevant NUMA assocativity properties for the target platform. + + - volatile; This property indicates that this region is actually + backed by non-persistent memory. This lets the OS know that it + may skip the cache flushes required to ensure data is made + persistent after a write. + + If this property is absent then the OS must assume that the region + is backed by non-volatile memory. + +Examples: +-------------------- + + /* + * This node specifies one 4KB region spanning from + * 0x5000 to 0x5fff that is backed by non-volatile memory. + */ + pmem@5000 { + compatible = "pmem-region"; + reg = <0x00005000 0x00001000>; + }; + + /* + * This node specifies two 4KB regions that are backed by + * volatile (normal) memory. + */ + pmem@6000 { + compatible = "pmem-region"; + reg = < 0x00006000 0x00001000 + 0x00008000 0x00001000 >; + volatile; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index 06230c06a071..662a71da42c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -8041,6 +8041,7 @@ L: linux-nvdimm@lists.01.org Q: https://patchwork.kernel.org/project/linux-nvdimm/list/ S: Supported F: drivers/nvdimm/of_pmem.c +F: Documentation/devicetree/bindings/pmem/pmem-region.txt LIBNVDIMM: NON-VOLATILE MEMORY DEVICE SUBSYSTEM M: Dan Williams -- cgit v1.2.3 From 21481189e8ffa4016e398d46ac6d66fb0f23acc3 Mon Sep 17 00:00:00 2001 From: Esben Haabendal Date: Fri, 6 Apr 2018 14:38:34 +0200 Subject: net/fsl_pq_mdio: Allow explicit speficition of TBIPA address This introduces a simpler and generic method for for finding (and mapping) the TBIPA register. Instead of relying of complicated logic for finding the TBIPA register address based on the MDIO or MII register block base address, which even in some cases relies on undocumented shadow registers, a second "reg" entry for the mdio bus devicetree node specifies the TBIPA register. Backwards compatibility is kept, as the existing logic is applied when only a single "reg" mapping is specified. Signed-off-by: Esben Haabendal Signed-off-by: David S. Miller --- .../devicetree/bindings/net/fsl-tsec-phy.txt | 6 ++- drivers/net/ethernet/freescale/fsl_pq_mdio.c | 50 +++++++++++++++------- 2 files changed, 39 insertions(+), 17 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt index 594982c6b9f9..79bf352e659c 100644 --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt @@ -6,7 +6,11 @@ the definition of the PHY node in booting-without-of.txt for an example of how to define a PHY. Required properties: - - reg : Offset and length of the register set for the device + - reg : Offset and length of the register set for the device, and optionally + the offset and length of the TBIPA register (TBI PHY address + register). If TBIPA register is not specified, the driver will + attempt to infer it from the register set specified (your mileage may + vary). - compatible : Should define the compatible device type for the mdio. Currently supported strings/devices are: - "fsl,gianfar-tbi" diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.c b/drivers/net/ethernet/freescale/fsl_pq_mdio.c index 80ad16acf0f1..ac2c3f6a12bc 100644 --- a/drivers/net/ethernet/freescale/fsl_pq_mdio.c +++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.c @@ -377,6 +377,38 @@ static const struct of_device_id fsl_pq_mdio_match[] = { }; MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match); +static void set_tbipa(const u32 tbipa_val, struct platform_device *pdev, + uint32_t __iomem * (*get_tbipa)(void __iomem *), + void __iomem *reg_map, struct resource *reg_res) +{ + struct device_node *np = pdev->dev.of_node; + uint32_t __iomem *tbipa; + bool tbipa_mapped; + + tbipa = of_iomap(np, 1); + if (tbipa) { + tbipa_mapped = true; + } else { + tbipa_mapped = false; + tbipa = (*get_tbipa)(reg_map); + + /* + * Add consistency check to make sure TBI is contained within + * the mapped range (not because we would get a segfault, + * rather to catch bugs in computing TBI address). Print error + * message but continue anyway. + */ + if ((void *)tbipa > reg_map + resource_size(reg_res) - 4) + dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n", + ((void *)tbipa - reg_map) + 4); + } + + iowrite32be(be32_to_cpu(tbipa_val), tbipa); + + if (tbipa_mapped) + iounmap(tbipa); +} + static int fsl_pq_mdio_probe(struct platform_device *pdev) { const struct of_device_id *id = @@ -450,8 +482,6 @@ static int fsl_pq_mdio_probe(struct platform_device *pdev) if (tbi) { const u32 *prop = of_get_property(tbi, "reg", NULL); - uint32_t __iomem *tbipa; - if (!prop) { dev_err(&pdev->dev, "missing 'reg' property in node %pOF\n", @@ -459,20 +489,8 @@ static int fsl_pq_mdio_probe(struct platform_device *pdev) err = -EBUSY; goto error; } - - tbipa = data->get_tbipa(priv->map); - - /* - * Add consistency check to make sure TBI is contained - * within the mapped range (not because we would get a - * segfault, rather to catch bugs in computing TBI - * address). Print error message but continue anyway. - */ - if ((void *)tbipa > priv->map + resource_size(&res) - 4) - dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n", - ((void *)tbipa - priv->map) + 4); - - iowrite32be(be32_to_cpup(prop), tbipa); + set_tbipa(*prop, pdev, + data->get_tbipa, priv->map, &res); } } -- cgit v1.2.3 From 8b8b5903d50d6e4c5fd06272022b25a11c3214cf Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Tue, 6 Mar 2018 15:43:54 +0100 Subject: dt-bindings: thermal: remove no longer needed samsung thermal properties Remove documentation for longer needed samsung thermal properties. Signed-off-by: Bartlomiej Zolnierkiewicz Reviewed-by: Rob Herring Signed-off-by: Eduardo Valentin --- .../devicetree/bindings/thermal/exynos-thermal.txt | 23 +++++----------------- 1 file changed, 5 insertions(+), 18 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 1b596fd38dc4..b957acff57aa 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -49,19 +49,6 @@ on the SoC (only first trip points defined in DT will be configured): - samsung,exynos5433-tmu: 8 - samsung,exynos7-tmu: 8 -Following properties are mandatory (depending on SoC): -- samsung,tmu_gain: Gain value for internal TMU operation. -- samsung,tmu_reference_voltage: Value of TMU IP block's reference voltage -- samsung,tmu_noise_cancel_mode: Mode for noise cancellation -- samsung,tmu_efuse_value: Default level of temperature - it is needed when - in factory fusing produced wrong value -- samsung,tmu_min_efuse_value: Minimum temperature fused value -- samsung,tmu_max_efuse_value: Maximum temperature fused value -- samsung,tmu_first_point_trim: First point trimming value -- samsung,tmu_second_point_trim: Second point trimming value -- samsung,tmu_default_temp_offset: Default temperature offset -- samsung,tmu_cal_type: Callibration type - ** Optional properties: - vtmu-supply: This entry is optional and provides the regulator node supplying @@ -78,7 +65,7 @@ Example 1): clocks = <&clock 383>; clock-names = "tmu_apbif"; vtmu-supply = <&tmu_regulator_node>; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; Example 2): @@ -89,7 +76,7 @@ Example 2): interrupts = <0 58 0>; clocks = <&clock 21>; clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register") @@ -99,7 +86,7 @@ Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register") interrupts = <0 184 0>; clocks = <&clock 318>, <&clock 318>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_cpu3: tmu@1006c000 { @@ -108,7 +95,7 @@ Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register") interrupts = <0 185 0>; clocks = <&clock 318>, <&clock 319>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; tmu_gpu: tmu@100a0000 { @@ -117,7 +104,7 @@ Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register") interrupts = <0 215 0>; clocks = <&clock 319>, <&clock 318>; clock-names = "tmu_apbif", "tmu_triminfo_apbif"; - #include "exynos4412-tmu-sensor-conf.dtsi" + #thermal-sensor-cells = <0>; }; Note: For multi-instance tmu each instance should have an alias correctly -- cgit v1.2.3 From e04907dbc25930b88ee2328fe692c776f63ddf2c Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 9 Feb 2018 14:28:10 +0530 Subject: dt-bindings: thermal: Remove "cooling-{min|max}-level" properties The "cooling-min-level" and "cooling-max-level" properties are not parsed by any part of kernel currently and the max cooling state of a CPU cooling device is found by referring to the cpufreq table instead. Remove the unused bindings. Signed-off-by: Viresh Kumar Reviewed-by: Rob Herring Signed-off-by: Eduardo Valentin --- Documentation/devicetree/bindings/thermal/thermal.txt | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt b/Documentation/devicetree/bindings/thermal/thermal.txt index 1719d47a5e2f..cc553f0952c5 100644 --- a/Documentation/devicetree/bindings/thermal/thermal.txt +++ b/Documentation/devicetree/bindings/thermal/thermal.txt @@ -55,8 +55,7 @@ of heat dissipation). For example a fan's cooling states correspond to the different fan speeds possible. Cooling states are referred to by single unsigned integers, where larger numbers mean greater heat dissipation. The precise set of cooling states associated with a device -(as referred to by the cooling-min-level and cooling-max-level -properties) should be defined in a particular device's binding. +should be defined in a particular device's binding. For more examples of cooling devices, refer to the example sections below. Required properties: @@ -69,15 +68,6 @@ Required properties: See Cooling device maps section below for more details on how consumers refer to cooling devices. -Optional properties: -- cooling-min-level: An integer indicating the smallest - Type: unsigned cooling state accepted. Typically 0. - Size: one cell - -- cooling-max-level: An integer indicating the largest - Type: unsigned cooling state accepted. - Size: one cell - * Trip points The trip node is a node to describe a point in the temperature domain @@ -226,8 +216,6 @@ cpus { 396000 950000 198000 850000 >; - cooling-min-level = <0>; - cooling-max-level = <3>; #cooling-cells = <2>; /* min followed by max */ }; ... @@ -241,8 +229,6 @@ cpus { */ fan0: fan@48 { ... - cooling-min-level = <0>; - cooling-max-level = <9>; #cooling-cells = <2>; /* min followed by max */ }; }; -- cgit v1.2.3 From 3ae2da7b28b393d4f6faef3d384cc725ef39716b Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 20 Apr 2018 16:52:52 +0300 Subject: usb: host: xhci-plat: Fix clock resource by adding a register clock On Armada 7K/8K we need to explicitly enable the register clock. This clock is optional because not all the SoCs using this IP need it but at least for Armada 7K/8K it is actually mandatory. The change was done at xhci-plat level and not at a xhci-mvebu.c because, it is expected that other SoC would have this kind of constraint. The binding documentation is updating accordingly. Signed-off-by: Gregory CLEMENT Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/usb/usb-xhci.txt | 5 ++++- drivers/usb/host/xhci-plat.c | 25 ++++++++++++++++++---- drivers/usb/host/xhci.h | 3 ++- 3 files changed, 27 insertions(+), 6 deletions(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index c4c00dff4b56..bd1dd316fb23 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -28,7 +28,10 @@ Required properties: - interrupts: one XHCI interrupt should be described here. Optional properties: - - clocks: reference to a clock + - clocks: reference to the clocks + - clock-names: mandatory if there is a second clock, in this case + the name must be "core" for the first clock and "reg" for the + second one - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM - usb3-lpm-capable: determines if platform is USB3 LPM capable - quirk-broken-port-ped: set if the controller has broken port disable mechanism diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index f0231fea524e..596e7a71b666 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -157,6 +157,7 @@ static int xhci_plat_probe(struct platform_device *pdev) struct resource *res; struct usb_hcd *hcd; struct clk *clk; + struct clk *reg_clk; int ret; int irq; @@ -226,17 +227,27 @@ static int xhci_plat_probe(struct platform_device *pdev) hcd->rsrc_len = resource_size(res); /* - * Not all platforms have a clk so it is not an error if the - * clock does not exists. + * Not all platforms have clks so it is not an error if the + * clock do not exist. */ + reg_clk = devm_clk_get(&pdev->dev, "reg"); + if (!IS_ERR(reg_clk)) { + ret = clk_prepare_enable(reg_clk); + if (ret) + goto put_hcd; + } else if (PTR_ERR(reg_clk) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto put_hcd; + } + clk = devm_clk_get(&pdev->dev, NULL); if (!IS_ERR(clk)) { ret = clk_prepare_enable(clk); if (ret) - goto put_hcd; + goto disable_reg_clk; } else if (PTR_ERR(clk) == -EPROBE_DEFER) { ret = -EPROBE_DEFER; - goto put_hcd; + goto disable_reg_clk; } xhci = hcd_to_xhci(hcd); @@ -252,6 +263,7 @@ static int xhci_plat_probe(struct platform_device *pdev) device_wakeup_enable(hcd->self.controller); xhci->clk = clk; + xhci->reg_clk = reg_clk; xhci->main_hcd = hcd; xhci->shared_hcd = __usb_create_hcd(driver, sysdev, &pdev->dev, dev_name(&pdev->dev), hcd); @@ -322,6 +334,9 @@ put_usb3_hcd: disable_clk: clk_disable_unprepare(clk); +disable_reg_clk: + clk_disable_unprepare(reg_clk); + put_hcd: usb_put_hcd(hcd); @@ -337,6 +352,7 @@ static int xhci_plat_remove(struct platform_device *dev) struct usb_hcd *hcd = platform_get_drvdata(dev); struct xhci_hcd *xhci = hcd_to_xhci(hcd); struct clk *clk = xhci->clk; + struct clk *reg_clk = xhci->reg_clk; xhci->xhc_state |= XHCI_STATE_REMOVING; @@ -347,6 +363,7 @@ static int xhci_plat_remove(struct platform_device *dev) usb_put_hcd(xhci->shared_hcd); clk_disable_unprepare(clk); + clk_disable_unprepare(reg_clk); usb_put_hcd(hcd); pm_runtime_set_suspended(&dev->dev); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 05c909b04f14..6dfc4867dbcf 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1729,8 +1729,9 @@ struct xhci_hcd { int page_shift; /* msi-x vectors */ int msix_count; - /* optional clock */ + /* optional clocks */ struct clk *clk; + struct clk *reg_clk; /* data structures */ struct xhci_device_context_array *dcbaa; struct xhci_ring *cmd_ring; -- cgit v1.2.3 From 34df2466b48dfe258e14fe2a7bc4641416575ade Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 23 Apr 2018 09:32:40 +0200 Subject: dt-bindings: meson-uart: DT fix s/clocks-names/clock-names/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt index 8ff65fa632fd..c06c045126fc 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt @@ -21,7 +21,7 @@ Required properties: - interrupts : identifier to the device interrupt - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock names. -- clocks-names : +- clock-names : * "xtal" for external xtal clock identifier * "pclk" for the bus core clock, either the clk81 clock or the gate clock * "baud" for the source of the baudrate generator, can be either the xtal -- cgit v1.2.3 From ef9604b622ce3b77e0ec6b566a016ddd64c5deb0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 9 Apr 2018 13:20:00 +0100 Subject: serial: sh-sci: Document r8a77470 bindings RZ/G1C (R8A77470) SoC also has the R-Car gen2 compatible SCIF and HSCIF ports, so document the SoC specific bindings. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index ad962f4ec3aa..a006ea4d065f 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -17,6 +17,8 @@ Required properties: - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART. - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART. - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART. + - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART. + - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART. - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART. - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART. - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. -- cgit v1.2.3 From 17a16542b88e753cc3bd54cf30b74df3d547421e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 23 Apr 2018 09:35:16 +0200 Subject: dt-bindings: mvebu-uart: DT fix s/interrupts-names/interrupt-names/ Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/mvebu-uart.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree') diff --git a/Documentation/devicetree/bindings/serial/mvebu-uart.txt b/Documentation/devicetree/bindings/serial/mvebu-uart.txt index 2ae2fee7e023..b7e0e32b9ac6 100644 --- a/Documentation/devicetree/bindings/serial/mvebu-uart.txt +++ b/Documentation/devicetree/bindings/serial/mvebu-uart.txt @@ -24,7 +24,7 @@ Required properties: - Must contain two elements for the extended variant of the IP (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx", respectively the UART TX interrupt and the UART RX interrupt. A - corresponding interrupts-names property must be defined. + corresponding interrupt-names property must be defined. - For backward compatibility reasons, a single element interrupts property is also supported for the standard variant of the IP, containing only the UART sum interrupt. This form is deprecated -- cgit v1.2.3