From 74273035c7e486fa046ee7f80fbdb9c19169ef19 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Mar 2022 15:27:16 +0000 Subject: dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220315152717.20045-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml') diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 9ccf54870aa4..52df1b146174 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Lad Prabhakar description: - The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO - controller. + The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and + GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function (port mode) or in alternate function mode. @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - items: -- cgit v1.2.3