From eeee8b340d54d06b6115b53251aecadff0b69a1e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Sat, 14 Sep 2013 00:41:07 +0200 Subject: DTS: ARM: OMAP3-N900: Add SSI support Add SSI device tree data for OMAP3 and Nokia N900. Signed-off-by: Sebastian Reichel --- arch/arm/boot/dts/omap3-n900.dts | 24 ++++++++++++++++++ arch/arm/boot/dts/omap3.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap34xx.dtsi | 11 ++++++++ arch/arm/boot/dts/omap36xx.dtsi | 11 ++++++++ 4 files changed, 101 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 0bf40c90faba..5bccd8c3367f 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -145,6 +145,19 @@ 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ >; }; + + ssi_pins: pinmux_ssi { + pinctrl-single,pins = < + 0x150 (PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ + 0x14e (PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ + 0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + 0x14c (PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ + 0x154 (PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ + 0x156 (PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ + 0x158 (PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ + 0x15a (PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ + >; + }; }; &i2c1 { @@ -490,6 +503,17 @@ power = <50>; }; +&ssi_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&ssi_pins>; + + ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ +}; + +&ssi_port2 { + status = "disabled"; +}; + &uart1 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index a5fc83b9c835..cb00ce6cc292 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -669,6 +669,61 @@ num-eps = <16>; ram-bits = <12>; }; + + ssi: ssi-controller@48058000 { + compatible = "ti,omap3-ssi"; + ti,hwmods = "ssi"; + + status = "disabled"; + + reg = <0x48058000 0x1000>, + <0x48059000 0x1000>; + reg-names = "sys", + "gdd"; + + interrupts = <71>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ssi_port1: ssi-port@0 { + compatible = "ti,omap3-ssi-port"; + + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x4805a000 0x800>, + <0x4805a800 0x800>; + reg-names = "tx", + "rx"; + + interrupt-parent = <&intc>; + interrupts = <67>, + <68>; + interrupt-names = "mpu_irq0", + "mpu_irq1"; + }; + + ssi_port2: ssi-port@1 { + compatible = "ti,omap3-ssi-port"; + + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x4805b000 0x800>, + <0x4805b800 0x800>; + reg-names = "tx", + "rx"; + + interrupt-parent = <&intc>; + interrupts = <69>, + <70>; + interrupt-names = "mpu_irq0", + "mpu_irq1"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 2e92360da1f3..3819c1e91591 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -40,6 +40,17 @@ }; }; +&ssi { + status = "ok"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 7e8dee9175d6..a63496189b54 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -52,6 +52,17 @@ }; }; +&ssi { + status = "ok"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + /include/ "omap36xx-clocks.dtsi" /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" -- cgit v1.2.3