From cb2a782eb8087d1bed61f58aa38fe06a693031d7 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 17 Jun 2019 13:05:00 +0800 Subject: drm/amd/powerplay: add feature check in unforce_dpm_levels function (v2) if not check dpm feature is enabled, it will cause show smc send message failed log in dmesg log. eg: echo "auto" > power_dpm_force_performance_level v2: whitespace fix (Alex) Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Reviewed-by: Rui Teng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 953209b7c3eb..d1246981e3ac 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -815,14 +815,21 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu) { uint32_t min_freq, max_freq; enum smu_clk_type clk_type; - enum smu_clk_type clks[] = { - SMU_GFXCLK, - SMU_MCLK, - SMU_SOCCLK, + struct clk_feature_map { + enum smu_clk_type clk_type; + uint32_t feature; + } clk_feature_map[] = { + {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT}, + {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT}, + {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT}, }; - for (i = 0; i < ARRAY_SIZE(clks); i++) { - clk_type = clks[i]; + for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) { + if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature)) + continue; + + clk_type = clk_feature_map[i].clk_type; + ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq); if (ret) return ret; -- cgit v1.2.3