From 56d32c51dffac8a431b472a4c31efb8563b048d1 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 6 Dec 2022 23:57:36 +0100 Subject: arch: arm64: apple: t8103: Use standard "iommu" node name The PCIe iommu nodes use "dart" as node names. Replace it with the the standard "iommu" node name as all other iommu nodes. Fixes: 3c866bb79577 ("arm64: dts: apple: t8103: Add PCIe DARTs") Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 6f5a2334e5b1..daf46f7b8a6e 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -670,7 +670,7 @@ resets = <&ps_ans2>; }; - pcie0_dart_0: dart@681008000 { + pcie0_dart_0: iommu@681008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x81008000 0x0 0x4000>; #iommu-cells = <1>; @@ -679,7 +679,7 @@ power-domains = <&ps_apcie_gp>; }; - pcie0_dart_1: dart@682008000 { + pcie0_dart_1: iommu@682008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x82008000 0x0 0x4000>; #iommu-cells = <1>; @@ -688,7 +688,7 @@ power-domains = <&ps_apcie_gp>; }; - pcie0_dart_2: dart@683008000 { + pcie0_dart_2: iommu@683008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x83008000 0x0 0x4000>; #iommu-cells = <1>; -- cgit v1.2.3 From 9742350931df69f8aad7a764ff6286ac069305f5 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 6 Dec 2022 23:57:37 +0100 Subject: arch: arm64: apple: t600x: Use standard "iommu" node name The PCIe iommu nodes use "dart" as node names. Replace it with the the standard "iommu" node name as all other iommu nodes. Fixes: 7b0b0191a2c7 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 0b8958a8db77..f006f990a8e2 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -208,7 +208,7 @@ #sound-dai-cells = <1>; }; - pcie0_dart_0: dart@581008000 { + pcie0_dart_0: iommu@581008000 { compatible = "apple,t6000-dart"; reg = <0x5 0x81008000 0x0 0x4000>; #iommu-cells = <1>; @@ -217,7 +217,7 @@ power-domains = <&ps_apcie_gp_sys>; }; - pcie0_dart_1: dart@582008000 { + pcie0_dart_1: iommu@582008000 { compatible = "apple,t6000-dart"; reg = <0x5 0x82008000 0x0 0x4000>; #iommu-cells = <1>; @@ -226,7 +226,7 @@ power-domains = <&ps_apcie_gp_sys>; }; - pcie0_dart_2: dart@583008000 { + pcie0_dart_2: iommu@583008000 { compatible = "apple,t6000-dart"; reg = <0x5 0x83008000 0x0 0x4000>; #iommu-cells = <1>; @@ -235,7 +235,7 @@ power-domains = <&ps_apcie_gp_sys>; }; - pcie0_dart_3: dart@584008000 { + pcie0_dart_3: iommu@584008000 { compatible = "apple,t6000-dart"; reg = <0x5 0x84008000 0x0 0x4000>; #iommu-cells = <1>; -- cgit v1.2.3 From 63bf0b66ddfa6761dd47350b8d1f7161a06e9954 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 5 Dec 2022 19:02:11 +0900 Subject: arm64: dts: apple: Rename dart-sio* to sio-dart* All the other DARTs are named foo-dart, so let's keep things consistent. Fixes: 51979fbb7fb8 ("arm64: dts: apple: t600x: Add MCA and its support") Fixes: 8a3df85ad87d ("arm64: dts: apple: t8103: Add MCA and its support") Reviewed-by: Sven Peter Reviewed-by: Mark Kettenis Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 6 +++--- arch/arm64/boot/dts/apple/t8103.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index f006f990a8e2..1c41954e3899 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -53,7 +53,7 @@ interrupts = ; }; - dart_sio_0: iommu@39b004000 { + sio_dart_0: iommu@39b004000 { compatible = "apple,t6000-dart"; reg = <0x3 0x9b004000 0x0 0x4000>; interrupt-parent = <&aic>; @@ -62,7 +62,7 @@ power-domains = <&ps_sio_cpu>; }; - dart_sio_1: iommu@39b008000 { + sio_dart_1: iommu@39b008000 { compatible = "apple,t6000-dart"; reg = <0x3 0x9b008000 0x0 0x8000>; interrupt-parent = <&aic>; @@ -179,7 +179,7 @@ <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>, <0>, <0>; - iommus = <&dart_sio_0 2>, <&dart_sio_1 2>; + iommus = <&sio_dart_0 2>, <&sio_dart_1 2>; power-domains = <&ps_sio_adma>; resets = <&ps_audio_p>; }; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index daf46f7b8a6e..264bd0bae567 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -318,7 +318,7 @@ #performance-domain-cells = <0>; }; - dart_sio: iommu@235004000 { + sio_dart: iommu@235004000 { compatible = "apple,t8103-dart"; reg = <0x2 0x35004000 0x0 0x4000>; interrupt-parent = <&aic>; @@ -431,7 +431,7 @@ <0>, <0>; #dma-cells = <1>; - iommus = <&dart_sio 2>; + iommus = <&sio_dart 2>; power-domains = <&ps_sio_adma>; resets = <&ps_audio_p>; }; -- cgit v1.2.3 From 9ecb7a4b8ac67c1a73fefd17bc00e943d7f74378 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 6 Dec 2022 23:38:46 +0100 Subject: arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes The t8103 CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions. The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described. Based on Rob Herring's patch adding cache properties and nodes for t600x. Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/ Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103.dtsi | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 264bd0bae567..9859219699f4 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -63,6 +63,9 @@ operating-points-v2 = <&ecluster_opp>; capacity-dmips-mhz = <714>; performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_e1: cpu@1 { @@ -74,6 +77,9 @@ operating-points-v2 = <&ecluster_opp>; capacity-dmips-mhz = <714>; performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_e2: cpu@2 { @@ -85,6 +91,9 @@ operating-points-v2 = <&ecluster_opp>; capacity-dmips-mhz = <714>; performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_e3: cpu@3 { @@ -96,6 +105,9 @@ operating-points-v2 = <&ecluster_opp>; capacity-dmips-mhz = <714>; performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; }; cpu_p0: cpu@10100 { @@ -107,6 +119,9 @@ operating-points-v2 = <&pcluster_opp>; capacity-dmips-mhz = <1024>; performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p1: cpu@10101 { @@ -118,6 +133,9 @@ operating-points-v2 = <&pcluster_opp>; capacity-dmips-mhz = <1024>; performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p2: cpu@10102 { @@ -129,6 +147,9 @@ operating-points-v2 = <&pcluster_opp>; capacity-dmips-mhz = <1024>; performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; }; cpu_p3: cpu@10103 { @@ -140,6 +161,23 @@ operating-points-v2 = <&pcluster_opp>; capacity-dmips-mhz = <1024>; performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; }; }; -- cgit v1.2.3 From 2aa48e294622f7204d02de9758795171c0bd937a Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Wed, 7 Dec 2022 10:43:05 +0900 Subject: arm64: dts: apple: t600x-pmgr: Fix search & replace typo It looks like the search-and-replace that happened to add die IDs to the t600x PMGR tree was a little bit too eager on a comment, and nobody noticed! Let's fix that. Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Asahi Lina Reviewed-by: Janne Grunau Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t600x-pmgr.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi index b8daeb0368d5..0bd44753b76a 100644 --- a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi @@ -225,7 +225,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = DIE_LABEL(afr); - /* Apple Fabric, media DIE_NODE(stuff): this can power down */ + /* Apple Fabric, media stuff: this can power down */ }; DIE_NODE(ps_afnc1_ioa): power-controller@1f0 { -- cgit v1.2.3 From 67327f125801f98aec9e2cf5e1df16cf493a065f Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Wed, 7 Dec 2022 10:43:04 +0900 Subject: arm64: dts: apple: t6002: Fix GPU power domains On t6002 (M1 Ultra), each die contains a self-contained GPU block. However, only the coprocessor and global management circuitry of the first die are used. This is what is represented by the "gpu" PS (the one in die1 is disabled). Nonetheless, this shared component drives the processing blocks in both dies, and therefore depends on the AFR fabric being powered up on both dies. Add an explicit dependency from the GPU block on die0 to AFR on die1, next to the existing die0 AFR dependency. Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Asahi Lina Reviewed-by: Janne Grunau Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t6002.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index 15da2c7eb1fe..a963a5011799 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -294,3 +294,8 @@ }; }; }; + +&ps_gfx { + // On t6002, the die0 GPU power domain needs both AFR power domains + power-domains = <&ps_afr>, <&ps_afr_die1>; +}; -- cgit v1.2.3