From 77977b800451ea7f438bf0398c76e56ef92379fa Mon Sep 17 00:00:00 2001 From: Michał Mirosław Date: Tue, 18 Dec 2018 12:20:48 +0100 Subject: clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Datasheet for SAMA5D2x mentions 6 sources for PCKx, the last being AUDIOPLL. Signed-off-by: Michał Mirosław Acked-by: Alexandre Belloni Signed-off-by: Stephen Boyd --- drivers/clk/at91/sama5d2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index d69ad96fe988..ade063622531 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -241,13 +241,14 @@ static void __init sama5d2_pmc_setup(struct device_node *np) parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "mck"; + parent_names[5] = "audiopll_pmcck"; for (i = 0; i < 3; i++) { char name[6]; snprintf(name, sizeof(name), "prog%d", i); hw = at91_clk_register_programmable(regmap, name, - parent_names, 5, i, + parent_names, 6, i, &at91sam9x5_programmable_layout); if (IS_ERR(hw)) goto err_free; -- cgit v1.2.3 From bb631af3d55fa89a612a5f09f3a3dda76121385a Mon Sep 17 00:00:00 2001 From: Michał Mirosław Date: Tue, 18 Dec 2018 12:20:48 +0100 Subject: clk: at91: optimize clk_round_rate() for AUDIO_PLL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop the search for parent rate when exact match is found. This makes for 3 clk_round_rate() calls instead of 64 of them on SAMA5D2-based board when searching for 12.288MHz clock. Signed-off-by: Michał Mirosław Reviewed-by: Nicolas Ferre Signed-off-by: Stephen Boyd --- drivers/clk/at91/clk-audio-pll.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c index 36d77146a3bd..3cc4a82f4e9f 100644 --- a/drivers/clk/at91/clk-audio-pll.c +++ b/drivers/clk/at91/clk-audio-pll.c @@ -340,7 +340,12 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, *parent_rate); - for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) { + if (!rate) + return 0; + + best_parent_rate = clk_round_rate(pclk->clk, 1); + div = max(best_parent_rate / rate, 1UL); + for (; div <= AUDIO_PLL_QDPMC_MAX; div++) { best_parent_rate = clk_round_rate(pclk->clk, rate * div); tmp_rate = best_parent_rate / div; tmp_diff = abs(rate - tmp_rate); @@ -350,6 +355,8 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, best_rate = tmp_rate; best_diff = tmp_diff; tmp_qd = div; + if (!best_diff) + break; /* got exact match */ } } -- cgit v1.2.3 From 97d010dc420469fbdfcf0b335578f19a0b25e17b Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Sat, 23 Feb 2019 01:08:58 +0100 Subject: clk: at91: programmable: remove unneeded register read This register read is a leftover of a previous read/modify/write. We now use regmap_update_bits(), so we don't need it anymore. Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni Signed-off-by: Stephen Boyd --- drivers/clk/at91/clk-programmable.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c index 5bc68b9c5498..89d6f3736dbf 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -132,11 +132,8 @@ static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate, struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; unsigned long div = parent_rate / rate; - unsigned int pckr; int shift = 0; - regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); - if (!div) return -EINVAL; -- cgit v1.2.3