From a2aa578fec8c29436bce5e6c15e1e31729d539a3 Mon Sep 17 00:00:00 2001 From: David Wang Date: Thu, 3 May 2018 10:32:46 +0800 Subject: x86/Centaur: Report correct CPU/cache topology Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the function is unused so for. The Centaur init code also misses to initialize x86_info::max_cores, so the CPU topology can't be described correctly. Initialize x86_info::max_cores and invoke init_cacheinfo() to make CPU and cache topology information available and correct. Signed-off-by: David Wang Signed-off-by: Thomas Gleixner Cc: lukelin@viacpu.com Cc: qiyuanwang@zhaoxin.com Cc: gregkh@linuxfoundation.org Cc: brucechang@via-alliance.com Cc: timguo@zhaoxin.com Cc: cooperyan@zhaoxin.com Cc: hpa@zytor.com Cc: benjaminpan@viatech.com Link: https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidwang@zhaoxin.com --- arch/x86/kernel/cpu/centaur.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 80d5110481ec..c265494234e6 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c) clear_cpu_cap(c, 0*32+31); #endif early_init_centaur(c); + init_intel_cacheinfo(c); + c->x86_max_cores = detect_num_cpu_cores(c); +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); -- cgit v1.2.3