From 9d7370a56d1871e924377872985a13f6cd104e82 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 23 Mar 2022 10:19:32 +0100 Subject: soc: mediatek: mmsys: Add sw0_rst_offset for MT8192 MT8192 has the same sw0 reset offset as MT8186: add the parameter to be able to use mmsys as a reset controller for managing at least the DSI reset line. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Link: https://lore.kernel.org/r/20220323091932.10648-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 4fc4c2c9ea20..893cec3c9651 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -70,6 +70,7 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), + .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { -- cgit v1.2.3