From 99fa80c3de159a612f5f5d36bc0e6aae3d42fd2f Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 27 Jan 2021 21:23:26 +0300 Subject: ARM: dts: aspeed: amd-ethanolx: Enable secondary LPC snooping address AMD EthanolX CRB uses 2-byte POST codes which are sent to ports 0x80/0x81. Currently ASPEED controller snoops only 0x80 port and therefore captures only the lower byte of each POST code. Enable secondary LPC snooping address to capture the higher byte of POST codes. Signed-off-by: Konstantin Aladyshev Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210127182326.424-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 96ff0aea64e5..ac2d04cfaf2f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -218,7 +218,7 @@ &lpc_snoop { status = "okay"; - snoop-ports = <0x80>; + snoop-ports = <0x80>, <0x81>; }; &lpc_ctrl { -- cgit v1.2.3