From 9ce18f6f0b0c7463fcdce70c35db17a891adc90d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:23 +0800 Subject: irqchip/sunxi-nmi: Convert magic numbers to defines The sunxi-nmi driver has a bunch of raw register offsets and bit values. Convert them into define macros for better readability. Signed-off-by: Chen-Yu Tsai Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-sunxi-nmi.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index 668730c5cb66..177efb473c7d 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -25,6 +25,20 @@ #define SUNXI_NMI_SRC_TYPE_MASK 0x00000003 +#define SUNXI_NMI_IRQ_BIT BIT(0) + +#define SUN6I_NMI_CTRL 0x00 +#define SUN6I_NMI_PENDING 0x04 +#define SUN6I_NMI_ENABLE 0x34 + +#define SUN7I_NMI_CTRL 0x00 +#define SUN7I_NMI_PENDING 0x04 +#define SUN7I_NMI_ENABLE 0x08 + +#define SUN9I_NMI_CTRL 0x00 +#define SUN9I_NMI_ENABLE 0x04 +#define SUN9I_NMI_PENDING 0x08 + enum { SUNXI_SRC_TYPE_LEVEL_LOW = 0, SUNXI_SRC_TYPE_EDGE_FALLING, @@ -39,21 +53,21 @@ struct sunxi_sc_nmi_reg_offs { }; static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = { - .ctrl = 0x00, - .pend = 0x04, - .enable = 0x08, + .ctrl = SUN7I_NMI_CTRL, + .pend = SUN7I_NMI_PENDING, + .enable = SUN7I_NMI_ENABLE, }; static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = { - .ctrl = 0x00, - .pend = 0x04, - .enable = 0x34, + .ctrl = SUN6I_NMI_CTRL, + .pend = SUN6I_NMI_PENDING, + .enable = SUN6I_NMI_ENABLE, }; static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = { - .ctrl = 0x00, - .pend = 0x08, - .enable = 0x04, + .ctrl = SUN9I_NMI_CTRL, + .pend = SUN9I_NMI_PENDING, + .enable = SUN9I_NMI_ENABLE, }; static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, @@ -188,7 +202,7 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node, gc->chip_types[1].handler = handle_edge_irq; sunxi_sc_nmi_write(gc, reg_offs->enable, 0); - sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1); + sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT); irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain); -- cgit v1.2.3 From e3ece0d5a31a588ced938d09f30c870ed9b2a2a6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:24 +0800 Subject: irqchip/sunxi-nmi: Document interrupt disabling and clearing at probe time The sunxi-nmi disables all its interrupts and clears any pending interrupts at probe time. Add comments documenting it, just to make it clear. Signed-off-by: Chen-Yu Tsai Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-sunxi-nmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index 177efb473c7d..9a7f6971cc3a 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -201,7 +201,10 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node, gc->chip_types[1].regs.type = reg_offs->ctrl; gc->chip_types[1].handler = handle_edge_irq; + /* Disable any active interrupts */ sunxi_sc_nmi_write(gc, reg_offs->enable, 0); + + /* Clear any pending NMI interrupts */ sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT); irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain); -- cgit v1.2.3 From c81a248069cd2f48f6326c35e2cdbd181cbc403c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:25 +0800 Subject: irqchip/sunxi-nmi: Reorder sunxi_sc_nmi_reg_offs' in ascending order This is a pure code move to reorder the various sunxi_sc_nmi_reg_offs' by family and alphabetical order. No functionality changes. Signed-off-by: Chen-Yu Tsai Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-sunxi-nmi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index 9a7f6971cc3a..76f2431b6b7b 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -52,18 +52,18 @@ struct sunxi_sc_nmi_reg_offs { u32 enable; }; -static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = { - .ctrl = SUN7I_NMI_CTRL, - .pend = SUN7I_NMI_PENDING, - .enable = SUN7I_NMI_ENABLE, -}; - static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = { .ctrl = SUN6I_NMI_CTRL, .pend = SUN6I_NMI_PENDING, .enable = SUN6I_NMI_ENABLE, }; +static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = { + .ctrl = SUN7I_NMI_CTRL, + .pend = SUN7I_NMI_PENDING, + .enable = SUN7I_NMI_ENABLE, +}; + static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = { .ctrl = SUN9I_NMI_CTRL, .pend = SUN9I_NMI_PENDING, -- cgit v1.2.3 From 11b345ab79a1986fd9da365f646621d9ced9dcfb Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:26 +0800 Subject: irqchip/sunxi-nmi: Const-ify sunxi_sc_nmi_reg_offs structures The sunxi_sc_nmi_reg_offs, which hold the register offsets for the various variants, is never modified, and only used at init time within the init functions referenced by IRQCHIP_DECLARE, which themselves are tagged __init. Const-ify the sunxi_sc_nmi_reg_offs structures, and tag them as __initconst. Signed-off-by: Chen-Yu Tsai Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-sunxi-nmi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index 76f2431b6b7b..e713ec66322b 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -52,19 +52,19 @@ struct sunxi_sc_nmi_reg_offs { u32 enable; }; -static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = { +static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { .ctrl = SUN6I_NMI_CTRL, .pend = SUN6I_NMI_PENDING, .enable = SUN6I_NMI_ENABLE, }; -static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = { +static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = { .ctrl = SUN7I_NMI_CTRL, .pend = SUN7I_NMI_PENDING, .enable = SUN7I_NMI_ENABLE, }; -static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = { +static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = { .ctrl = SUN9I_NMI_CTRL, .pend = SUN9I_NMI_PENDING, .enable = SUN9I_NMI_ENABLE, @@ -142,7 +142,7 @@ static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type) } static int __init sunxi_sc_nmi_irq_init(struct device_node *node, - struct sunxi_sc_nmi_reg_offs *reg_offs) + const struct sunxi_sc_nmi_reg_offs *reg_offs) { struct irq_domain *domain; struct irq_chip_generic *gc; -- cgit v1.2.3 From cd647575ac2f0c72dfded033f1d8c36c4cf13aa6 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:27 +0800 Subject: dt-bindings/interrupt-controller: sunxi-nmi: Add compatible for A31 R_INTC The A31 and later have an R_INTC block which handles the NMI interrupt pin on the SoC. This interrupt pin is used by the external PMIC to signal interrupts to the SoC. While this hardware block is undocumented, the interrupt offsets combined with the register regions for the existing "sun6i-a31-sc-nmi" compatible line up with the old interrupt controller found on the A10. Experiments show that only the first 32 interrupt lines can be enabled, and only the first (NMI) interrupt is actually connected. This patch adds a new, properly named compatible for the A31 R_INTC block, which requires the register region to be properly aligned to the block boundary. For comparison, the old "sun6i-a31-sc-nmi" compatible had its register region aligned with the first used register. This didn't match up with the memory map in the SoC's datasheet/user manual. Since the new compatible supercedes the old one, deprecate the old one. Signed-off-by: Chen-Yu Tsai Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/allwinner,sunxi-nmi.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt index 81cd3692405e..4ae553eb333d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt @@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller Required properties: -- compatible : should be "allwinner,sun7i-a20-sc-nmi" or - "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi" +- compatible : should be one of the following: + - "allwinner,sun7i-a20-sc-nmi" + - "allwinner,sun6i-a31-sc-nmi" (deprecated) + - "allwinner,sun6i-a31-r-intc" + - "allwinner,sun9i-a80-nmi" - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an -- cgit v1.2.3 From 173bda53b3403d7278d74c4dabedf3d4325a2f89 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 6 Jun 2017 13:59:28 +0800 Subject: irqchip/sunxi-nmi: Support sun6i-a31-r-intc compatible The R_INTC on the A31 is undocumented. It was previously supported by the sun6i-a31-sc-nmi compatible. This compatible however required the register region to start at the first used register, rather than the boundaries laid out in the SoC's memory map. The new compatible fixes the alignment, while also naming it properly. Since the only difference between the old and new compatibles are a fixed offset for the registers, and since the old one is deprecated, this patch adds a set of register defines for the new compatible, while modifying the old set to reference the new set minus a fixed offset. Signed-off-by: Chen-Yu Tsai Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-sunxi-nmi.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c index e713ec66322b..a412b5d5d0fa 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -27,9 +27,18 @@ #define SUNXI_NMI_IRQ_BIT BIT(0) -#define SUN6I_NMI_CTRL 0x00 -#define SUN6I_NMI_PENDING 0x04 -#define SUN6I_NMI_ENABLE 0x34 +#define SUN6I_R_INTC_CTRL 0x0c +#define SUN6I_R_INTC_PENDING 0x10 +#define SUN6I_R_INTC_ENABLE 0x40 + +/* + * For deprecated sun6i-a31-sc-nmi compatible. + * Registers are offset by 0x0c. + */ +#define SUN6I_R_INTC_NMI_OFFSET 0x0c +#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET) +#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET) +#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET) #define SUN7I_NMI_CTRL 0x00 #define SUN7I_NMI_PENDING 0x04 @@ -52,6 +61,12 @@ struct sunxi_sc_nmi_reg_offs { u32 enable; }; +static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = { + .ctrl = SUN6I_R_INTC_CTRL, + .pend = SUN6I_R_INTC_PENDING, + .enable = SUN6I_R_INTC_ENABLE, +}; + static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = { .ctrl = SUN6I_NMI_CTRL, .pend = SUN6I_NMI_PENDING, @@ -217,6 +232,14 @@ fail_irqd_remove: return ret; } +static int __init sun6i_r_intc_irq_init(struct device_node *node, + struct device_node *parent) +{ + return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs); +} +IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", + sun6i_r_intc_irq_init); + static int __init sun6i_sc_nmi_irq_init(struct device_node *node, struct device_node *parent) { -- cgit v1.2.3 From 53ccf3310d271facca17a2766bd4020811ada6a4 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:53 +0200 Subject: irqchip/i8259: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-i8259.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c index 1aec12c6d9ac..7aafbb091b67 100644 --- a/drivers/irqchip/irq-i8259.c +++ b/drivers/irqchip/irq-i8259.c @@ -307,7 +307,7 @@ static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq, return 0; } -static struct irq_domain_ops i8259A_ops = { +static const struct irq_domain_ops i8259A_ops = { .map = i8259A_irq_domain_map, .xlate = irq_domain_xlate_onecell, }; -- cgit v1.2.3 From dcbbefceb27d53379be96979480a7e7d5de59ab8 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:54 +0200 Subject: irqchip/irq-imx-gpcv2: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-imx-gpcv2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index 9463f3557e82..bb36f572e322 100644 --- a/drivers/irqchip/irq-imx-gpcv2.c +++ b/drivers/irqchip/irq-imx-gpcv2.c @@ -200,7 +200,7 @@ static int imx_gpcv2_domain_alloc(struct irq_domain *domain, &parent_fwspec); } -static struct irq_domain_ops gpcv2_irqchip_data_domain_ops = { +static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = { .translate = imx_gpcv2_domain_translate, .alloc = imx_gpcv2_domain_alloc, .free = irq_domain_free_irqs_common, -- cgit v1.2.3 From e183c2a3ea1996932fef7d5867df387793b1941f Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:55 +0200 Subject: irqchip/irq-mbigen: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-mbigen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index 31d6b5a582d2..567b29c47608 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -228,7 +228,7 @@ static int mbigen_irq_domain_alloc(struct irq_domain *domain, return 0; } -static struct irq_domain_ops mbigen_domain_ops = { +static const struct irq_domain_ops mbigen_domain_ops = { .translate = mbigen_domain_translate, .alloc = mbigen_irq_domain_alloc, .free = irq_domain_free_irqs_common, -- cgit v1.2.3 From 0b7e815aaa3bb7c89b05a4f092835a7391c0724c Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:56 +0200 Subject: irqchip/irq-mips-gic: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-mips-gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index eb7fbe159963..65642a78b8a3 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -874,7 +874,7 @@ int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, } } -static struct irq_domain_ops gic_ipi_domain_ops = { +static const struct irq_domain_ops gic_ipi_domain_ops = { .xlate = gic_ipi_domain_xlate, .alloc = gic_ipi_domain_alloc, .free = gic_ipi_domain_free, -- cgit v1.2.3 From 580393cc10f9a05a4f3b2e09fb066456f97d5b8d Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:57 +0200 Subject: irqchip/irq-renesas-h8300h: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Cc: Yoshinori Sato Cc: uclinux-h8-devel@lists.sourceforge.jp Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-renesas-h8300h.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-h8300h.c b/drivers/irqchip/irq-renesas-h8300h.c index c378768d75b3..b8327590ae52 100644 --- a/drivers/irqchip/irq-renesas-h8300h.c +++ b/drivers/irqchip/irq-renesas-h8300h.c @@ -67,7 +67,7 @@ static int irq_map(struct irq_domain *h, unsigned int virq, return 0; } -static struct irq_domain_ops irq_ops = { +static const struct irq_domain_ops irq_ops = { .map = irq_map, .xlate = irq_domain_xlate_onecell, }; -- cgit v1.2.3 From c9262475fa592c1f7777edbc2689589a5ce7266e Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:58 +0200 Subject: irqchip/irq-renesas-h8s: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Cc: Yoshinori Sato Cc: uclinux-h8-devel@lists.sourceforge.jp Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-renesas-h8s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-h8s.c b/drivers/irqchip/irq-renesas-h8s.c index af8c6c61c824..71d8139be26c 100644 --- a/drivers/irqchip/irq-renesas-h8s.c +++ b/drivers/irqchip/irq-renesas-h8s.c @@ -73,7 +73,7 @@ static __init int irq_map(struct irq_domain *h, unsigned int virq, return 0; } -static struct irq_domain_ops irq_ops = { +static const struct irq_domain_ops irq_ops = { .map = irq_map, .xlate = irq_domain_xlate_onecell, }; -- cgit v1.2.3 From 3403b0259d152c3ca67b32bb710f826bc17c0d16 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Wed, 31 May 2017 18:52:27 +0100 Subject: irqchip/gic-v3-its: Fix MSI alias accounting The call to pci_for_each_dma_alias() in the ITS PCI code has aroused suspicion in the past, and upon closer inspection does turn out to be completely backwards. Rather than iterating through each RID alias of the given device, what we actually want to be doing here is iterating through all the *other* devices which may also alias the same RID, in order to size the table for the worst case. Do the right thing by ignoring the initial DMA aliases themselves and just using that walk to detect an aliasing bridge, then walking back down the bus topology as necessary to actually count everything else. Our alias handling still isn't perfect, since we don't account for the cases of certain bridges only taking ownership of transactions under particular circumstances, but without completely reworking the ITS code to cope with the notion of multiple DevIDs per device, it'll have to do. Signed-off-by: Robin Murphy Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 35 ++++++++++++++++---------------- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c index aee1c60d7ab5..77931214d954 100644 --- a/drivers/irqchip/irq-gic-v3-its-pci-msi.c +++ b/drivers/irqchip/irq-gic-v3-its-pci-msi.c @@ -41,27 +41,22 @@ static struct irq_chip its_msi_irq_chip = { .irq_write_msi_msg = pci_msi_domain_write_msg, }; -struct its_pci_alias { - struct pci_dev *pdev; - u32 count; -}; - -static int its_pci_msi_vec_count(struct pci_dev *pdev) +static int its_pci_msi_vec_count(struct pci_dev *pdev, void *data) { - int msi, msix; + int msi, msix, *count = data; msi = max(pci_msi_vec_count(pdev), 0); msix = max(pci_msix_vec_count(pdev), 0); + *count += max(msi, msix); - return max(msi, msix); + return 0; } static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data) { - struct its_pci_alias *dev_alias = data; + struct pci_dev **alias_dev = data; - if (pdev != dev_alias->pdev) - dev_alias->count += its_pci_msi_vec_count(pdev); + *alias_dev = pdev; return 0; } @@ -69,9 +64,9 @@ static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data) static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *info) { - struct pci_dev *pdev; - struct its_pci_alias dev_alias; + struct pci_dev *pdev, *alias_dev; struct msi_domain_info *msi_info; + int alias_count = 0; if (!dev_is_pci(dev)) return -EINVAL; @@ -79,16 +74,20 @@ static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev, msi_info = msi_get_domain_info(domain->parent); pdev = to_pci_dev(dev); - dev_alias.pdev = pdev; - dev_alias.count = nvec; - - pci_for_each_dma_alias(pdev, its_get_pci_alias, &dev_alias); + /* + * If pdev is downstream of any aliasing bridges, take an upper + * bound of how many other vectors could map to the same DevID. + */ + pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev); + if (alias_dev != pdev && alias_dev->subordinate) + pci_walk_bus(alias_dev->subordinate, its_pci_msi_vec_count, + &alias_count); /* ITS specific DeviceID, as the core ITS ignores dev. */ info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev); return msi_info->ops->msi_prepare(domain->parent, - dev, dev_alias.count, info); + dev, max(nvec, alias_count), info); } static struct msi_domain_ops its_pci_msi_ops = { -- cgit v1.2.3 From 8b8d94a72fd4e773320173efbc745ed8fe677ac5 Mon Sep 17 00:00:00 2001 From: MaJun Date: Thu, 18 May 2017 16:19:13 +0800 Subject: irqchip/gicv3-its: Skip irq affinity setting when target cpu is the same as current setting Just skip the irq affinity setting when the target cpu is the same as current setting. This is a small optimization for irq affinity setting logic. Signed-off-by: MaJun Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 45ea193325d2..b33528026c5c 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -644,9 +644,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, if (cpu >= nr_cpu_ids) return -EINVAL; - target_col = &its_dev->its->collections[cpu]; - its_send_movi(its_dev, target_col, id); - its_dev->event_map.col_map[id] = cpu; + /* don't set the affinity when the target cpu is same as current one */ + if (cpu != its_dev->event_map.col_map[id]) { + target_col = &its_dev->its->collections[cpu]; + its_send_movi(its_dev, target_col, id); + its_dev->event_map.col_map[id] = cpu; + } return IRQ_SET_MASK_OK_DONE; } -- cgit v1.2.3 From 9a234c9c0a8de4245d5db788bcbbbaa35dcbe0a6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 May 2017 10:07:37 +0200 Subject: irqchip/armada-370-xp: Re-order register definitions In order to clarify to which register base the various register definitions apply, this commit re-orders them, and adds a comment that clearly indicate which registers are relative to "main_int_base" and which registers are relative to "per_cpu_int_base". Acked-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-armada-370-xp.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index eb0d4d41b156..76147dfdfccd 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -34,25 +34,24 @@ #include #include -/* Interrupt Controller Registers Map */ -#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) -#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) -#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) -#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) - +/* Registers relative to main_int_base */ #define ARMADA_370_XP_INT_CONTROL (0x00) +#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04) #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) -#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) +/* Registers relative to per_cpu_int_base */ +#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08) +#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c) #define ARMADA_375_PPI_CAUSE (0x10) - -#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) -#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) -#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8) +#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) +#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) +#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) +#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54) +#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu) #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) -- cgit v1.2.3 From 054ea4ce0016bcb560a25e6e94de95538954a4a8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 May 2017 10:07:38 +0200 Subject: irqchip/armada-370-xp: Document the overall driver logic Since the overall logic of the driver to handle the global and per-CPU masking of the interrupts is far from trivial, this commit adds a long comment detailing how the hardware operates and what strategy the driver implements on top of that. Acked-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-armada-370-xp.c | 80 +++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 76147dfdfccd..1f7dea613d15 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -34,6 +34,86 @@ #include #include +/* + * Overall diagram of the Armada XP interrupt controller: + * + * To CPU 0 To CPU 1 + * + * /\ /\ + * || || + * +---------------+ +---------------+ + * | | | | + * | per-CPU | | per-CPU | + * | mask/unmask | | mask/unmask | + * | CPU0 | | CPU1 | + * | | | | + * +---------------+ +---------------+ + * /\ /\ + * || || + * \\_______________________// + * || + * +-------------------+ + * | | + * | Global interrupt | + * | mask/unmask | + * | | + * +-------------------+ + * /\ + * || + * interrupt from + * device + * + * The "global interrupt mask/unmask" is modified using the + * ARMADA_370_XP_INT_SET_ENABLE_OFFS and + * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative + * to "main_int_base". + * + * The "per-CPU mask/unmask" is modified using the + * ARMADA_370_XP_INT_SET_MASK_OFFS and + * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to + * "per_cpu_int_base". This base address points to a special address, + * which automatically accesses the registers of the current CPU. + * + * The per-CPU mask/unmask can also be adjusted using the global + * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use + * to configure interrupt affinity. + * + * Due to this model, all interrupts need to be mask/unmasked at two + * different levels: at the global level and at the per-CPU level. + * + * This driver takes the following approach to deal with this: + * + * - For global interrupts: + * + * At ->map() time, a global interrupt is unmasked at the per-CPU + * mask/unmask level. It is therefore unmasked at this level for + * the current CPU, running the ->map() code. This allows to have + * the interrupt unmasked at this level in non-SMP + * configurations. In SMP configurations, the ->set_affinity() + * callback is called, which using the + * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask + * for the interrupt. + * + * The ->mask() and ->unmask() operations only mask/unmask the + * interrupt at the "global" level. + * + * So, a global interrupt is enabled at the per-CPU level as soon + * as it is mapped. At run time, the masking/unmasking takes place + * at the global level. + * + * - For per-CPU interrupts + * + * At ->map() time, a per-CPU interrupt is unmasked at the global + * mask/unmask level. + * + * The ->mask() and ->unmask() operations mask/unmask the interrupt + * at the per-CPU level. + * + * So, a per-CPU interrupt is enabled at the global level as soon + * as it is mapped. At run time, the masking/unmasking takes place + * at the per-CPU level. + */ + /* Registers relative to main_int_base */ #define ARMADA_370_XP_INT_CONTROL (0x00) #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04) -- cgit v1.2.3 From 0fa4ce746d1d8c8aa3d09fbc675497fa4c4a5475 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 May 2017 10:07:39 +0200 Subject: irqchip/armada-370-xp: Re-enable per-CPU interrupts at resume time Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to irq_set_probe(). While the commit log seems to imply that there are no functional changes, there are indeed functional changes introduced by this commit: the IRQ_NOAUTOEN flag is no longer cleared. This functional change caused a regression on Armada XP, which no longer works properly after suspend/resume because per-CPU interrupts remain disabled. This regression was temporarly worked around in commit 353d6d6c82e5d ("irqchip/armada-370-xp: Fix regression by clearing IRQ_NOAUTOEN"), but it is not the most satisfying solution. This commit implements the solution that was initially discussed with Thomas Gleixner. Due to how the hardware registers work, the irq-armada-370-xp cannot simply save/restore a bunch of registers at suspend/resume to make sure that the interrupts remain in the same state after resuming. Therefore, it relies on the kernel to say whether the interrupt is disabled or not, using the irqd_irq_disabled() function. This was all working fine while the IRQ_NOAUTOEN flag was cleared. With the change introduced by Rob Herring in d17cab4451df1, the IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled() returns false for per-CPU interrupts, and therefore our per-CPU interrupts are no longer re-enabled after resume. This commit fixes that by using irqd_irq_disabled() only for global interrupts, and using the newly introduced irq_percpu_is_enabled() for per-CPU interrupts. Also, it fixes a related problems that per-CPU interrupts were only re-enabled on the boot CPU and not other CPUs. Until now this wasn't a problem since on this platform, only the local timers are using per-CPU interrupts and the local timers of secondary CPUs are turned off/on during CPU hotplug before suspend, after after resume. However, since Linux 4.4, we are also be using per-CPU interrupts for the network controller, so we need to properly restore the per-CPU interrupts on secondary CPUs as well. Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-armada-370-xp.c | 46 ++++++++++++++++++++++++++++++++----- 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 1f7dea613d15..1d4de6e73d5d 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -360,7 +360,6 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_percpu_devid_irq); - } else { irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, handle_level_irq); @@ -424,16 +423,40 @@ static void armada_mpic_send_doorbell(const struct cpumask *mask, ARMADA_370_XP_SW_TRIG_INT_OFFS); } +static void armada_xp_mpic_reenable_percpu(void) +{ + unsigned int irq; + + /* Re-enable per-CPU interrupts that were enabled before suspend */ + for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) { + struct irq_data *data; + int virq; + + virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq); + if (virq == 0) + continue; + + data = irq_get_irq_data(virq); + + if (!irq_percpu_is_enabled(virq)) + continue; + + armada_370_xp_irq_unmask(data); + } +} + static int armada_xp_mpic_starting_cpu(unsigned int cpu) { armada_xp_mpic_perf_init(); armada_xp_mpic_smp_cpu_init(); + armada_xp_mpic_reenable_percpu(); return 0; } static int mpic_cascaded_starting_cpu(unsigned int cpu) { armada_xp_mpic_perf_init(); + armada_xp_mpic_reenable_percpu(); enable_percpu_irq(parent_irq, IRQ_TYPE_NONE); return 0; } @@ -581,16 +604,27 @@ static void armada_370_xp_mpic_resume(void) if (virq == 0) continue; - if (!is_percpu_irq(irq)) + data = irq_get_irq_data(virq); + + if (!is_percpu_irq(irq)) { + /* Non per-CPU interrupts */ writel(irq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - else + if (!irqd_irq_disabled(data)) + armada_370_xp_irq_unmask(data); + } else { + /* Per-CPU interrupts */ writel(irq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); - data = irq_get_irq_data(virq); - if (!irqd_irq_disabled(data)) - armada_370_xp_irq_unmask(data); + /* + * Re-enable on the current CPU, + * armada_xp_mpic_reenable_percpu() will take + * care of secondary CPUs when they come up. + */ + if (irq_percpu_is_enabled(virq)) + armada_370_xp_irq_unmask(data); + } } /* Reconfigure doorbells for IPIs and MSIs */ -- cgit v1.2.3 From 1957b7bfa65893ee282e9901b2132d87c2720e07 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 May 2017 10:07:40 +0200 Subject: Revert "irqchip/armada-370-xp: Fix regression by clearing IRQ_NOAUTOEN" This reverts commit 353d6d6c82e5d2533ba22e7f9fb081582bf50dc2, which is no longer needed, now that the irq-armada-370-xp driver properly re-enables per-CPU interrupt on both the boot CPU and secondary CPUs after resume. Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-armada-370-xp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 1d4de6e73d5d..577b42831de8 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -365,7 +365,6 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, handle_level_irq); } irq_set_probe(virq); - irq_clear_status_flags(virq, IRQ_NOAUTOEN); return 0; } -- cgit v1.2.3 From 13dcf12bf877b9ed8845c7a68390702e368ec622 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 2 Jun 2017 10:20:52 +0200 Subject: irqchip/aspeed-vic: Constify irq_domain_ops struct irq_domain_ops is not modified, so it can be made const. Cc: Joel Stanley Signed-off-by: Tobias Klauser Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-aspeed-vic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-aspeed-vic.c b/drivers/irqchip/irq-aspeed-vic.c index d24451d5bf8a..88e139e4c1f9 100644 --- a/drivers/irqchip/irq-aspeed-vic.c +++ b/drivers/irqchip/irq-aspeed-vic.c @@ -186,7 +186,7 @@ static int avic_map(struct irq_domain *d, unsigned int irq, return 0; } -static struct irq_domain_ops avic_dom_ops = { +static const struct irq_domain_ops avic_dom_ops = { .map = avic_map, .xlate = irq_domain_xlate_onetwocell, }; -- cgit v1.2.3 From fa776a3f2b1b62970179bcefc55fae85e5700746 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 16 May 2017 15:57:47 +0800 Subject: irqchip/aspeed-vic: Add AST2500 compatible string In addition to introducing the new compatible string the bindings description is reworked to be more generic. Acked-by: Rob Herring Signed-off-by: Andrew Jeffery Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/aspeed,ast2400-vic.txt | 9 +++++---- drivers/irqchip/irq-aspeed-vic.c | 3 ++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt index 6c6e85324b9d..e3fea0758d25 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt @@ -1,12 +1,13 @@ Aspeed Vectored Interrupt Controller -These bindings are for the Aspeed AST2400 interrupt controller register layout. -The SoC has an legacy register layout, but this driver does not support that -mode of operation. +These bindings are for the Aspeed interrupt controller. The AST2400 and +AST2500 SoC families include a legacy register layout before a re-designed +layout, but the bindings do not prescribe the use of one or the other. Required properties: -- compatible : should be "aspeed,ast2400-vic". +- compatible : "aspeed,ast2400-vic" + "aspeed,ast2500-vic" - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an diff --git a/drivers/irqchip/irq-aspeed-vic.c b/drivers/irqchip/irq-aspeed-vic.c index 88e139e4c1f9..03ba477ea0d0 100644 --- a/drivers/irqchip/irq-aspeed-vic.c +++ b/drivers/irqchip/irq-aspeed-vic.c @@ -227,4 +227,5 @@ static int __init avic_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(aspeed_new_vic, "aspeed,ast2400-vic", avic_of_init); +IRQCHIP_DECLARE(ast2400_vic, "aspeed,ast2400-vic", avic_of_init); +IRQCHIP_DECLARE(ast2500_vic, "aspeed,ast2500-vic", avic_of_init); -- cgit v1.2.3 From 0a56f9eebe6320980b68c60c852436cbf2a14b61 Mon Sep 17 00:00:00 2001 From: Brendan Higgins Date: Fri, 2 Jun 2017 18:29:48 -0700 Subject: irqchip/aspeed-i2c-ic: Add binding docs for Aspeed I2C Interrupt Controller Added device tree binding documentation for Aspeed I2C Interrupt Controller. Signed-off-by: Brendan Higgins Acked-by: Rob Herring Signed-off-by: Marc Zyngier --- .../interrupt-controller/aspeed,ast2400-i2c-ic.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt new file mode 100644 index 000000000000..033cc82e5684 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt @@ -0,0 +1,25 @@ +Device tree configuration for the I2C Interrupt Controller on the AST24XX and +AST25XX SoCs. + +Required Properties: +- #address-cells : should be 1 +- #size-cells : should be 1 +- #interrupt-cells : should be 1 +- compatible : should be "aspeed,ast2400-i2c-ic" + or "aspeed,ast2500-i2c-ic" +- reg : address start and range of controller +- interrupts : interrupt number +- interrupt-controller : denotes that the controller receives and fires + new interrupts for child busses + +Example: + +i2c_ic: interrupt-controller@0 { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + compatible = "aspeed,ast2400-i2c-ic"; + reg = <0x0 0x40>; + interrupts = <12>; + interrupt-controller; +}; -- cgit v1.2.3 From f48e699ddf7056f83bb8e2dbe3c2ae8d1ff1a31a Mon Sep 17 00:00:00 2001 From: Brendan Higgins Date: Fri, 2 Jun 2017 18:29:49 -0700 Subject: irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 separate I2C busses. This adds a dummy irqchip which maps the single hardware interrupt to software interrupts for each of the busses. Signed-off-by: Brendan Higgins Signed-off-by: Marc Zyngier --- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-aspeed-i2c-ic.c | 115 ++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-aspeed-i2c-ic.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index b64c59b838a0..e067f9839b33 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -73,6 +73,6 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o -obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o +obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o diff --git a/drivers/irqchip/irq-aspeed-i2c-ic.c b/drivers/irqchip/irq-aspeed-i2c-ic.c new file mode 100644 index 000000000000..815b88dd18f2 --- /dev/null +++ b/drivers/irqchip/irq-aspeed-i2c-ic.c @@ -0,0 +1,115 @@ +/* + * Aspeed 24XX/25XX I2C Interrupt Controller. + * + * Copyright (C) 2012-2017 ASPEED Technology Inc. + * Copyright 2017 IBM Corporation + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + + +#define ASPEED_I2C_IC_NUM_BUS 14 + +struct aspeed_i2c_ic { + void __iomem *base; + int parent_irq; + struct irq_domain *irq_domain; +}; + +/* + * The aspeed chip provides a single hardware interrupt for all of the I2C + * busses, so we use a dummy interrupt chip to translate this single interrupt + * into multiple interrupts, each associated with a single I2C bus. + */ +static void aspeed_i2c_ic_irq_handler(struct irq_desc *desc) +{ + struct aspeed_i2c_ic *i2c_ic = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long bit, status; + unsigned int bus_irq; + + chained_irq_enter(chip, desc); + status = readl(i2c_ic->base); + for_each_set_bit(bit, &status, ASPEED_I2C_IC_NUM_BUS) { + bus_irq = irq_find_mapping(i2c_ic->irq_domain, bit); + generic_handle_irq(bus_irq); + } + chained_irq_exit(chip, desc); +} + +/* + * Set simple handler and mark IRQ as valid. Nothing interesting to do here + * since we are using a dummy interrupt chip. + */ +static int aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain, + unsigned int irq, irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops aspeed_i2c_ic_irq_domain_ops = { + .map = aspeed_i2c_ic_map_irq_domain, +}; + +static int __init aspeed_i2c_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_i2c_ic *i2c_ic; + int ret = 0; + + i2c_ic = kzalloc(sizeof(*i2c_ic), GFP_KERNEL); + if (!i2c_ic) + return -ENOMEM; + + i2c_ic->base = of_iomap(node, 0); + if (IS_ERR(i2c_ic->base)) { + ret = PTR_ERR(i2c_ic->base); + goto err_free_ic; + } + + i2c_ic->parent_irq = irq_of_parse_and_map(node, 0); + if (i2c_ic->parent_irq < 0) { + ret = i2c_ic->parent_irq; + goto err_iounmap; + } + + i2c_ic->irq_domain = irq_domain_add_linear(node, ASPEED_I2C_IC_NUM_BUS, + &aspeed_i2c_ic_irq_domain_ops, + NULL); + if (!i2c_ic->irq_domain) { + ret = -ENOMEM; + goto err_iounmap; + } + + i2c_ic->irq_domain->name = "aspeed-i2c-domain"; + + irq_set_chained_handler_and_data(i2c_ic->parent_irq, + aspeed_i2c_ic_irq_handler, i2c_ic); + + pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq); + + return 0; + +err_iounmap: + iounmap(i2c_ic->base); +err_free_ic: + kfree(i2c_ic); + return ret; +} + +IRQCHIP_DECLARE(ast2400_i2c_ic, "aspeed,ast2400-i2c-ic", aspeed_i2c_ic_of_init); +IRQCHIP_DECLARE(ast2500_i2c_ic, "aspeed,ast2500-i2c-ic", aspeed_i2c_ic_of_init); -- cgit v1.2.3 From a1628366227aff3433f646cec2beb36d1f018f86 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Tue, 25 Apr 2017 16:12:23 +0000 Subject: irqchip/qcom: Use builtin_platform_driver to simplify the code Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun Signed-off-by: Marc Zyngier --- drivers/irqchip/qcom-irq-combiner.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/irqchip/qcom-irq-combiner.c b/drivers/irqchip/qcom-irq-combiner.c index 226558698344..6aa3ea479214 100644 --- a/drivers/irqchip/qcom-irq-combiner.c +++ b/drivers/irqchip/qcom-irq-combiner.c @@ -288,9 +288,4 @@ static struct platform_driver qcom_irq_combiner_probe = { }, .probe = combiner_probe, }; - -static int __init register_qcom_irq_combiner(void) -{ - return platform_driver_register(&qcom_irq_combiner_probe); -} -device_initcall(register_qcom_irq_combiner); +builtin_platform_driver(qcom_irq_combiner_probe); -- cgit v1.2.3 From 11f69da0dada3e4472b5b1319fae9b1df194e3d6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Jun 2017 15:29:12 +0200 Subject: dt-bindings/interrupt-controller: Add DT binding for the Marvell GICP This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC level in the AP. Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/marvell,gicp.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt new file mode 100644 index 000000000000..64a00ceb7da4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt @@ -0,0 +1,27 @@ +Marvell GICP Controller +----------------------- + +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI +interrupts by doing a memory transaction. It is used by the ICU +located in the Marvell CP110 to turn wired interrupts inside the CP +into GIC SPI interrupts. + +Required properties: + +- compatible: Must be "marvell,ap806-gicp" + +- reg: Must be the address and size of the GICP SPI registers + +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available + for this GICP + +- msi-controller: indicates that this is an MSI controller + +Example: + +gicp_spi: gicp-spi@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; + msi-controller; +}; -- cgit v1.2.3 From f39a29bb5ca3f1c54fa677d9de17a09079b7e898 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Jun 2017 15:29:13 +0200 Subject: dt-bindings/interrupt-controller: Add DT binding for the Marvell ICU This commit adds the Device Tree binding documentation for the Marvell ICU interrupt controller, which collects wired interrupts from the devices located into the CP110 hardware block of Marvell Armada 7K/8K, and converts them into SPI interrupts in the GIC located in the AP hardware block, using the GICP extension. Acked-by: Rob Herring Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- .../bindings/interrupt-controller/marvell,icu.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt new file mode 100644 index 000000000000..aa8bf2ec8905 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt @@ -0,0 +1,51 @@ +Marvell ICU Interrupt Controller +-------------------------------- + +The Marvell ICU (Interrupt Consolidation Unit) controller is +responsible for collecting all wired-interrupt sources in the CP and +communicating them to the GIC in the AP, the unit translates interrupt +requests on input wires to MSG memory mapped transactions to the GIC. + +Required properties: + +- compatible: Should be "marvell,cp110-icu" + +- reg: Should contain ICU registers location and length. + +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value shall be 3. + + The 1st cell is the group type of the ICU interrupt. Possible group + types are: + + ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure + ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure + ICU_GRP_SEI (0x4) : System error interrupt + ICU_GRP_REI (0x5) : RAM error interrupt + + The 2nd cell is the index of the interrupt in the ICU unit. + + The 3rd cell is the type of the interrupt. See arm,gic.txt for + details. + +- interrupt-controller: Identifies the node as an interrupt + controller. + +- msi-parent: Should point to the GICP controller, the GIC extension + that allows to trigger interrupts using MSG memory mapped + transactions. + +Example: + +icu: interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x10>; + #interrupt-cells = <3>; + interrupt-controller; + msi-parent = <&gicp>; +}; + +usb3h0: usb3@500000 { + interrupt-parent = <&icu>; + interrupts = ; +}; -- cgit v1.2.3 From a68a63cb4dfc30e8a79b444aabc7747bb7621acf Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Jun 2017 15:29:14 +0200 Subject: irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP This commit adds a simple driver for the Marvell GICP, a hardware unit that converts memory writes into GIC SPI interrupts. The driver provides a number of functions to the ICU driver to allocate GICP interrupts, and get the physical addresses that the ICUs should write to to set/clear interrupts. Signed-off-by: Thomas Petazzoni Reviewed-by: Marc Zyngier Signed-off-by: Marc Zyngier --- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mvebu-gicp.c | 279 +++++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-mvebu-gicp.h | 11 ++ 4 files changed, 294 insertions(+) create mode 100644 drivers/irqchip/irq-mvebu-gicp.c create mode 100644 drivers/irqchip/irq-mvebu-gicp.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 478f8ace2664..e527ee596d54 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -268,6 +268,9 @@ config IRQ_MXS select IRQ_DOMAIN select STMP_DEVICE +config MVEBU_GICP + bool + config MVEBU_ODMI bool select GENERIC_MSI_IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e067f9839b33..f214f4573307 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o +obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c new file mode 100644 index 000000000000..45358ac9bb1d --- /dev/null +++ b/drivers/irqchip/irq-mvebu-gicp.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2017 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "irq-mvebu-gicp.h" + +#define GICP_SETSPI_NSR_OFFSET 0x0 +#define GICP_CLRSPI_NSR_OFFSET 0x8 + +struct mvebu_gicp_spi_range { + unsigned int start; + unsigned int count; +}; + +struct mvebu_gicp { + struct mvebu_gicp_spi_range *spi_ranges; + unsigned int spi_ranges_cnt; + unsigned int spi_cnt; + unsigned long *spi_bitmap; + spinlock_t spi_lock; + struct resource *res; + struct device *dev; +}; + +static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx) +{ + int i; + + for (i = 0; i < gicp->spi_ranges_cnt; i++) { + struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i]; + + if (idx < r->count) + return r->start + idx; + + idx -= r->count; + } + + return -EINVAL; +} + +int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi, + phys_addr_t *clrspi) +{ + struct platform_device *pdev; + struct mvebu_gicp *gicp; + + pdev = of_find_device_by_node(dn); + if (!pdev) + return -ENODEV; + + gicp = platform_get_drvdata(pdev); + if (!gicp) + return -ENODEV; + + *setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET; + *clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET; + + return 0; +} + +static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct mvebu_gicp *gicp = data->chip_data; + phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET; + + msg->data = data->hwirq; + msg->address_lo = lower_32_bits(setspi); + msg->address_hi = upper_32_bits(setspi); +} + +static struct irq_chip gicp_irq_chip = { + .name = "GICP", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_compose_msi_msg = gicp_compose_msi_msg, +}; + +static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct mvebu_gicp *gicp = domain->host_data; + struct irq_fwspec fwspec; + unsigned int hwirq; + int ret; + + spin_lock(&gicp->spi_lock); + hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt); + if (hwirq == gicp->spi_cnt) { + spin_unlock(&gicp->spi_lock); + return -ENOSPC; + } + __set_bit(hwirq, gicp->spi_bitmap); + spin_unlock(&gicp->spi_lock); + + fwspec.fwnode = domain->parent->fwnode; + fwspec.param_count = 3; + fwspec.param[0] = GIC_SPI; + fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32; + /* + * Assume edge rising for now, it will be properly set when + * ->set_type() is called + */ + fwspec.param[2] = IRQ_TYPE_EDGE_RISING; + + ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); + if (ret) { + dev_err(gicp->dev, "Cannot allocate parent IRQ\n"); + goto free_hwirq; + } + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &gicp_irq_chip, gicp); + if (ret) + goto free_irqs_parent; + + return 0; + +free_irqs_parent: + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +free_hwirq: + spin_lock(&gicp->spi_lock); + __clear_bit(hwirq, gicp->spi_bitmap); + spin_unlock(&gicp->spi_lock); + return ret; +} + +static void gicp_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct mvebu_gicp *gicp = domain->host_data; + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + + if (d->hwirq >= gicp->spi_cnt) { + dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq); + return; + } + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + + spin_lock(&gicp->spi_lock); + __clear_bit(d->hwirq, gicp->spi_bitmap); + spin_unlock(&gicp->spi_lock); +} + +static const struct irq_domain_ops gicp_domain_ops = { + .alloc = gicp_irq_domain_alloc, + .free = gicp_irq_domain_free, +}; + +static struct irq_chip gicp_msi_irq_chip = { + .name = "GICP", + .irq_set_type = irq_chip_set_type_parent, +}; + +static struct msi_domain_ops gicp_msi_ops = { +}; + +static struct msi_domain_info gicp_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops = &gicp_msi_ops, + .chip = &gicp_msi_irq_chip, +}; + +static int mvebu_gicp_probe(struct platform_device *pdev) +{ + struct mvebu_gicp *gicp; + struct irq_domain *inner_domain, *plat_domain, *parent_domain; + struct device_node *node = pdev->dev.of_node; + struct device_node *irq_parent_dn; + int ret, i; + + gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL); + if (!gicp) + return -ENOMEM; + + gicp->dev = &pdev->dev; + + gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!gicp->res) + return -ENODEV; + + ret = of_property_count_u32_elems(node, "marvell,spi-ranges"); + if (ret < 0) + return ret; + + gicp->spi_ranges_cnt = ret / 2; + + gicp->spi_ranges = + devm_kzalloc(&pdev->dev, + gicp->spi_ranges_cnt * + sizeof(struct mvebu_gicp_spi_range), + GFP_KERNEL); + if (!gicp->spi_ranges) + return -ENOMEM; + + for (i = 0; i < gicp->spi_ranges_cnt; i++) { + of_property_read_u32_index(node, "marvell,spi-ranges", + i * 2, + &gicp->spi_ranges[i].start); + + of_property_read_u32_index(node, "marvell,spi-ranges", + i * 2 + 1, + &gicp->spi_ranges[i].count); + + gicp->spi_cnt += gicp->spi_ranges[i].count; + } + + gicp->spi_bitmap = devm_kzalloc(&pdev->dev, + BITS_TO_LONGS(gicp->spi_cnt), + GFP_KERNEL); + if (!gicp->spi_bitmap) + return -ENOMEM; + + irq_parent_dn = of_irq_find_parent(node); + if (!irq_parent_dn) { + dev_err(&pdev->dev, "failed to find parent IRQ node\n"); + return -ENODEV; + } + + parent_domain = irq_find_host(irq_parent_dn); + if (!parent_domain) { + dev_err(&pdev->dev, "failed to find parent IRQ domain\n"); + return -ENODEV; + } + + inner_domain = irq_domain_create_hierarchy(parent_domain, 0, + gicp->spi_cnt, + of_node_to_fwnode(node), + &gicp_domain_ops, gicp); + if (!inner_domain) + return -ENOMEM; + + + plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node), + &gicp_msi_domain_info, + inner_domain); + if (!plat_domain) { + irq_domain_remove(inner_domain); + return -ENOMEM; + } + + platform_set_drvdata(pdev, gicp); + + return 0; +} + +static const struct of_device_id mvebu_gicp_of_match[] = { + { .compatible = "marvell,ap806-gicp", }, + {}, +}; + +static struct platform_driver mvebu_gicp_driver = { + .probe = mvebu_gicp_probe, + .driver = { + .name = "mvebu-gicp", + .of_match_table = mvebu_gicp_of_match, + }, +}; +builtin_platform_driver(mvebu_gicp_driver); diff --git a/drivers/irqchip/irq-mvebu-gicp.h b/drivers/irqchip/irq-mvebu-gicp.h new file mode 100644 index 000000000000..98535e886ea5 --- /dev/null +++ b/drivers/irqchip/irq-mvebu-gicp.h @@ -0,0 +1,11 @@ +#ifndef __MVEBU_GICP_H__ +#define __MVEBU_GICP_H__ + +#include + +struct device_node; + +int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi, + phys_addr_t *clrspi); + +#endif /* __MVEBU_GICP_H__ */ -- cgit v1.2.3 From e0de91a977bfe4c199138fa256a211a648ef6999 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Jun 2017 15:29:15 +0200 Subject: irqchip/irq-mvebu-icu: Add new driver for Marvell ICU The Marvell ICU unit is found in the CP110 block of the Marvell Armada 7K and 8K SoCs. It collects the wired interrupts of the devices located in the CP110 and turns them into SPI interrupts in the GIC located in the AP806 side of the SoC, by using a memory transaction. Until now, the ICU was configured in a static fashion by the firmware, and Linux was relying on this static configuration. By having Linux configure the ICU, we are more flexible, and we can allocate dynamically the GIC SPI interrupts only for devices that are actually in use. The driver was initially written by Hanna Hawa . Reviewed-by: Marc Zyngier Signed-off-by: Thomas Petazzoni Signed-off-by: Marc Zyngier --- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mvebu-icu.c | 289 +++++++++++++++++++++ .../dt-bindings/interrupt-controller/mvebu-icu.h | 15 ++ 4 files changed, 308 insertions(+) create mode 100644 drivers/irqchip/irq-mvebu-icu.c create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index e527ee596d54..676232a94f9f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -271,6 +271,9 @@ config IRQ_MXS config MVEBU_GICP bool +config MVEBU_ICU + bool + config MVEBU_ODMI bool select GENERIC_MSI_IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index f214f4573307..e88d856cc09c 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o +obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c new file mode 100644 index 000000000000..e18c48d3a92e --- /dev/null +++ b/drivers/irqchip/irq-mvebu-icu.c @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2017 Marvell + * + * Hanna Hawa + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "irq-mvebu-gicp.h" + +/* ICU registers */ +#define ICU_SETSPI_NSR_AL 0x10 +#define ICU_SETSPI_NSR_AH 0x14 +#define ICU_CLRSPI_NSR_AL 0x18 +#define ICU_CLRSPI_NSR_AH 0x1c +#define ICU_INT_CFG(x) (0x100 + 4 * (x)) +#define ICU_INT_ENABLE BIT(24) +#define ICU_IS_EDGE BIT(28) +#define ICU_GROUP_SHIFT 29 + +/* ICU definitions */ +#define ICU_MAX_IRQS 207 +#define ICU_SATA0_ICU_ID 109 +#define ICU_SATA1_ICU_ID 107 + +struct mvebu_icu { + struct irq_chip irq_chip; + void __iomem *base; + struct irq_domain *domain; + struct device *dev; +}; + +struct mvebu_icu_irq_data { + struct mvebu_icu *icu; + unsigned int icu_group; + unsigned int type; +}; + +static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct irq_data *d = irq_get_irq_data(desc->irq); + struct mvebu_icu_irq_data *icu_irqd = d->chip_data; + struct mvebu_icu *icu = icu_irqd->icu; + unsigned int icu_int; + + if (msg->address_lo || msg->address_hi) { + /* Configure the ICU with irq number & type */ + icu_int = msg->data | ICU_INT_ENABLE; + if (icu_irqd->type & IRQ_TYPE_EDGE_RISING) + icu_int |= ICU_IS_EDGE; + icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT; + } else { + /* De-configure the ICU */ + icu_int = 0; + } + + writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); + + /* + * The SATA unit has 2 ports, and a dedicated ICU entry per + * port. The ahci sata driver supports only one irq interrupt + * per SATA unit. To solve this conflict, we configure the 2 + * SATA wired interrupts in the south bridge into 1 GIC + * interrupt in the north bridge. Even if only a single port + * is enabled, if sata node is enabled, both interrupts are + * configured (regardless of which port is actually in use). + */ + if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) { + writel_relaxed(icu_int, + icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); + writel_relaxed(icu_int, + icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); + } +} + +static int +mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, + unsigned long *hwirq, unsigned int *type) +{ + struct mvebu_icu *icu = d->host_data; + unsigned int icu_group; + + /* Check the count of the parameters in dt */ + if (WARN_ON(fwspec->param_count < 3)) { + dev_err(icu->dev, "wrong ICU parameter count %d\n", + fwspec->param_count); + return -EINVAL; + } + + /* Only ICU group type is handled */ + icu_group = fwspec->param[0]; + if (icu_group != ICU_GRP_NSR && icu_group != ICU_GRP_SR && + icu_group != ICU_GRP_SEI && icu_group != ICU_GRP_REI) { + dev_err(icu->dev, "wrong ICU group type %x\n", icu_group); + return -EINVAL; + } + + *hwirq = fwspec->param[1]; + if (*hwirq >= ICU_MAX_IRQS) { + dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq); + return -EINVAL; + } + + /* Mask the type to prevent wrong DT configuration */ + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static int +mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + int err; + unsigned long hwirq; + struct irq_fwspec *fwspec = args; + struct mvebu_icu *icu = platform_msi_get_host_data(domain); + struct mvebu_icu_irq_data *icu_irqd; + + icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL); + if (!icu_irqd) + return -ENOMEM; + + err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq, + &icu_irqd->type); + if (err) { + dev_err(icu->dev, "failed to translate ICU parameters\n"); + goto free_irqd; + } + + icu_irqd->icu_group = fwspec->param[0]; + icu_irqd->icu = icu; + + err = platform_msi_domain_alloc(domain, virq, nr_irqs); + if (err) { + dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n"); + goto free_irqd; + } + + /* Make sure there is no interrupt left pending by the firmware */ + err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false); + if (err) + goto free_msi; + + err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &icu->irq_chip, icu_irqd); + if (err) { + dev_err(icu->dev, "failed to set the data to IRQ domain\n"); + goto free_msi; + } + + return 0; + +free_msi: + platform_msi_domain_free(domain, virq, nr_irqs); +free_irqd: + kfree(icu_irqd); + return err; +} + +static void +mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d = irq_get_irq_data(virq); + struct mvebu_icu_irq_data *icu_irqd = d->chip_data; + + kfree(icu_irqd); + + platform_msi_domain_free(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops mvebu_icu_domain_ops = { + .translate = mvebu_icu_irq_domain_translate, + .alloc = mvebu_icu_irq_domain_alloc, + .free = mvebu_icu_irq_domain_free, +}; + +static int mvebu_icu_probe(struct platform_device *pdev) +{ + struct mvebu_icu *icu; + struct device_node *node = pdev->dev.of_node; + struct device_node *gicp_dn; + struct resource *res; + phys_addr_t setspi, clrspi; + u32 i, icu_int; + int ret; + + icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu), + GFP_KERNEL); + if (!icu) + return -ENOMEM; + + icu->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + icu->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(icu->base)) { + dev_err(&pdev->dev, "Failed to map icu base address.\n"); + return PTR_ERR(icu->base); + } + + icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "ICU.%x", + (unsigned int)res->start); + if (!icu->irq_chip.name) + return -ENOMEM; + + icu->irq_chip.irq_mask = irq_chip_mask_parent; + icu->irq_chip.irq_unmask = irq_chip_unmask_parent; + icu->irq_chip.irq_eoi = irq_chip_eoi_parent; + icu->irq_chip.irq_set_type = irq_chip_set_type_parent; +#ifdef CONFIG_SMP + icu->irq_chip.irq_set_affinity = irq_chip_set_affinity_parent; +#endif + + /* + * We're probed after MSI domains have been resolved, so force + * resolution here. + */ + pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, node, + DOMAIN_BUS_PLATFORM_MSI); + if (!pdev->dev.msi_domain) + return -EPROBE_DEFER; + + gicp_dn = irq_domain_get_of_node(pdev->dev.msi_domain); + if (!gicp_dn) + return -ENODEV; + + ret = mvebu_gicp_get_doorbells(gicp_dn, &setspi, &clrspi); + if (ret) + return ret; + + /* Set Clear/Set ICU SPI message address in AP */ + writel_relaxed(upper_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AH); + writel_relaxed(lower_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AL); + writel_relaxed(upper_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AH); + writel_relaxed(lower_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AL); + + /* + * Clean all ICU interrupts with type SPI_NSR, required to + * avoid unpredictable SPI assignments done by firmware. + */ + for (i = 0 ; i < ICU_MAX_IRQS ; i++) { + icu_int = readl(icu->base + ICU_INT_CFG(i)); + if ((icu_int >> ICU_GROUP_SHIFT) == ICU_GRP_NSR) + writel_relaxed(0x0, icu->base + ICU_INT_CFG(i)); + } + + icu->domain = + platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS, + mvebu_icu_write_msg, + &mvebu_icu_domain_ops, icu); + if (!icu->domain) { + dev_err(&pdev->dev, "Failed to create ICU domain\n"); + return -ENOMEM; + } + + return 0; +} + +static const struct of_device_id mvebu_icu_of_match[] = { + { .compatible = "marvell,cp110-icu", }, + {}, +}; + +static struct platform_driver mvebu_icu_driver = { + .probe = mvebu_icu_probe, + .driver = { + .name = "mvebu-icu", + .of_match_table = mvebu_icu_of_match, + }, +}; +builtin_platform_driver(mvebu_icu_driver); diff --git a/include/dt-bindings/interrupt-controller/mvebu-icu.h b/include/dt-bindings/interrupt-controller/mvebu-icu.h new file mode 100644 index 000000000000..8249558545c7 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/mvebu-icu.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for the MVEBU ICU driver. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H + +/* interrupt specifier cell 0 */ + +#define ICU_GRP_NSR 0x0 +#define ICU_GRP_SR 0x1 +#define ICU_GRP_SEI 0x4 +#define ICU_GRP_REI 0x5 + +#endif -- cgit v1.2.3 From 935bba7ccf0246fae8247aa8dab7aa85c43de2d8 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Thu, 22 Jun 2017 16:05:30 +0530 Subject: irqchip/gic-v3-its: Make of_device_ids const of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index b33528026c5c..fee7d13a5587 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1804,7 +1804,7 @@ int its_cpu_init(void) return 0; } -static struct of_device_id its_device_id[] = { +static const struct of_device_id its_device_id[] = { { .compatible = "arm,gic-v3-its", }, {}, }; -- cgit v1.2.3 From 5b8670612d4014f33d9f130693bfba5327726411 Mon Sep 17 00:00:00 2001 From: Arvind Yadav Date: Thu, 22 Jun 2017 16:11:13 +0530 Subject: irqchip/gic-v3-its-platform-msi: Make of_device_ids const of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its-platform-msi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its-platform-msi.c b/drivers/irqchip/irq-gic-v3-its-platform-msi.c index 9e9dda33eb17..249240d9a425 100644 --- a/drivers/irqchip/irq-gic-v3-its-platform-msi.c +++ b/drivers/irqchip/irq-gic-v3-its-platform-msi.c @@ -86,7 +86,7 @@ static struct msi_domain_info its_pmsi_domain_info = { .chip = &its_pmsi_irq_chip, }; -static struct of_device_id its_device_id[] = { +static const struct of_device_id its_device_id[] = { { .compatible = "arm,gic-v3-its", }, {}, }; -- cgit v1.2.3 From dbd2b826723319eb6e4bee5214f8901e336c06be Mon Sep 17 00:00:00 2001 From: Ganapatrao Kulkarni Date: Thu, 22 Jun 2017 11:40:12 +0530 Subject: irqchip/gic-v3-its: Add ACPI NUMA node mapping Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2. Later in per device probe, ITS devices are mapped to numa node using ITS Id to proximity domain mapping. [maz: fix dependency on ACPICA, fixed structure name, minor cleanups] Reviewed-by: Lorenzo Pieralisi Signed-off-by: Ganapatrao Kulkarni Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 76 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index fee7d13a5587..63cd0f2b8707 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1836,6 +1836,78 @@ static int __init its_of_probe(struct device_node *node) #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) +#if defined(CONFIG_ACPI_NUMA) && (ACPI_CA_VERSION >= 0x20170531) +struct its_srat_map { + /* numa node id */ + u32 numa_node; + /* GIC ITS ID */ + u32 its_id; +}; + +static struct its_srat_map its_srat_maps[MAX_NUMNODES] __initdata; +static int its_in_srat __initdata; + +static int __init acpi_get_its_numa_node(u32 its_id) +{ + int i; + + for (i = 0; i < its_in_srat; i++) { + if (its_id == its_srat_maps[i].its_id) + return its_srat_maps[i].numa_node; + } + return NUMA_NO_NODE; +} + +static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header, + const unsigned long end) +{ + int node; + struct acpi_srat_gic_its_affinity *its_affinity; + + its_affinity = (struct acpi_srat_gic_its_affinity *)header; + if (!its_affinity) + return -EINVAL; + + if (its_affinity->header.length < sizeof(*its_affinity)) { + pr_err("SRAT: Invalid header length %d in ITS affinity\n", + its_affinity->header.length); + return -EINVAL; + } + + if (its_in_srat >= MAX_NUMNODES) { + pr_err("SRAT: ITS affinity exceeding max count[%d]\n", + MAX_NUMNODES); + return -EINVAL; + } + + node = acpi_map_pxm_to_node(its_affinity->proximity_domain); + + if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { + pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); + return 0; + } + + its_srat_maps[its_in_srat].numa_node = node; + its_srat_maps[its_in_srat].its_id = its_affinity->its_id; + its_in_srat++; + pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", + its_affinity->proximity_domain, its_affinity->its_id, node); + + return 0; +} + +static void __init acpi_table_parse_srat_its(void) +{ + acpi_table_parse_entries(ACPI_SIG_SRAT, + sizeof(struct acpi_table_srat), + ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, + gic_acpi_parse_srat_its, 0); +} +#else +static void __init acpi_table_parse_srat_its(void) { } +static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } +#endif + static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, const unsigned long end) { @@ -1864,7 +1936,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, goto dom_err; } - err = its_probe_one(&res, dom_handle, NUMA_NO_NODE); + err = its_probe_one(&res, dom_handle, + acpi_get_its_numa_node(its_entry->translation_id)); if (!err) return 0; @@ -1876,6 +1949,7 @@ dom_err: static void __init its_acpi_probe(void) { + acpi_table_parse_srat_its(); acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, gic_acpi_parse_madt_its, 0); } -- cgit v1.2.3 From 6c31e123dc4c59eeaae6ac1cd08b929e8b6f7651 Mon Sep 17 00:00:00 2001 From: Shanker Donthineni Date: Thu, 22 Jun 2017 18:19:14 -0500 Subject: irqchip/gic-v3-its: Don't assume GICv3 hardware supports 16bit INTID The current ITS driver is assuming every ITS hardware implementation supports minimum of 16bit INTID. But this is not true, as per GICv3 specification, INTID field is IMPLEMENTATION DEFINED in the range of 14-24 bits. We might see an unpredictable system behavior on systems where hardware support less than 16bits and software tries to use 64K LPI interrupts. On Qualcomm Datacenter Technologies QDF2400 platform, boot log shows confusing information about number of LPI chunks as shown below. The QDF2400 ITS hardware supports 24bit INTID. This patch allocates the memory resources for PEND/PROP tables based on discoverable value which is specified in GITS_TYPER.IDbits. Also it fixes the log message that reflects the correct number of LPI chunks were allocated. ITS@0xff7efe0000: allocated 524288 Devices @3c0400000 (indirect, esz 8, psz 64K, shr 1) ITS@0xff7efe0000: allocated 8192 Interrupt Collections @3c0130000 (flat, esz 8, psz 64K, shr 1) ITS@0xff7efe0000: allocated 8192 Virtual CPUs @3c0140000 (flat, esz 8, psz 64K, shr 1) ITS: Allocated 524032 chunks for LPIs PCI/MSI: ITS@0xff7efe0000 domain created Platform MSI: ITS@0xff7efe0000 domain created Signed-off-by: Shanker Donthineni Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 63cd0f2b8707..fed99c55e2f4 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -691,9 +691,11 @@ static struct irq_chip its_irq_chip = { */ #define IRQS_PER_CHUNK_SHIFT 5 #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) +#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ static unsigned long *lpi_bitmap; static u32 lpi_chunks; +static u32 lpi_id_bits; static DEFINE_SPINLOCK(lpi_lock); static int its_lpi_to_chunk(int lpi) @@ -789,17 +791,13 @@ static void its_lpi_free(struct event_lpi_map *map) } /* - * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to + * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to * deal with (one configuration byte per interrupt). PENDBASE has to * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). */ -#define LPI_PROPBASE_SZ SZ_64K -#define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) - -/* - * This is how many bits of ID we need, including the useless ones. - */ -#define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) +#define LPI_NRBITS lpi_id_bits +#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) +#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) #define LPI_PROP_DEFAULT_PRIO 0xa0 @@ -807,6 +805,7 @@ static int __init its_alloc_lpi_tables(void) { phys_addr_t paddr; + lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS); gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, get_order(LPI_PROPBASE_SZ)); if (!gic_rdists->prop_page) { @@ -825,7 +824,7 @@ static int __init its_alloc_lpi_tables(void) /* Make sure the GIC will observe the written configuration */ gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); - return 0; + return its_lpi_init(lpi_id_bits); } static const char *its_base_type_string[] = { @@ -1100,7 +1099,7 @@ static void its_cpu_init_lpis(void) * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. */ pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, - get_order(max(LPI_PENDBASE_SZ, SZ_64K))); + get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); if (!pend_page) { pr_err("Failed to allocate PENDBASE for CPU%d\n", smp_processor_id()); @@ -1975,8 +1974,5 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, } gic_rdists = rdists; - its_alloc_lpi_tables(); - its_lpi_init(rdists->id_bits); - - return 0; + return its_alloc_lpi_tables(); } -- cgit v1.2.3